WO2023202689A1

WO2023202689A1 - Multiphase buck conversion circuit, apparatus and device

Info

Publication number: WO2023202689A1
Application number: PCT/CN2023/089695
Authority: WO
Inventors: 黎永泉
Original assignee: 深圳英集芯科技股份有限公司
Priority date: 2022-04-21
Filing date: 2023-04-21
Publication date: 2023-10-26
Also published as: CN114531026B; CN114531026A; CN116979807A

Abstract

Embodiments of the present application provide a multiphase buck conversion circuit, apparatus and device. The circuit comprises: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first driver, a second driver, a first controller, a second controller, a voltage division module, a first operational amplifier, a reference voltage source, a first inductor L1, a second inductor L2, an output resistor R0, a load resistor RL and an output capacitor C0, wherein a multi-phase signal can be generated, thereby improving the practicability of a buck converter.

Description

Multi-phase buck conversion circuits, devices and equipment

This application claims priority to the Chinese patent application filed with the China Patent Office on April 21, 2022, with application number 202210420753.2 and the application name "Polyphase Buck Conversion Circuit, Device and Equipment", the entire content of which is incorporated by reference. in this application.

Technical field

The present application relates to the field of circuit structure technology, and specifically to a multi-phase buck conversion circuit, device and equipment.

Background technique

There are more and more applications using RBCOT architecture to implement buck converters. Due to its excellent transient load response characteristics and switching frequency close to traditional fixed-frequency converters, it has attracted more users' attention. However, RBCOT itself does not have a frequency generation circuit, which requires a phase generation circuit when adjusting the frequency or in a multi-phase system. Because there is no fixed clock generator, it is impossible to adjust or divide the frequency to generate multiple signals by adjusting or increasing the frequency of the fixed clock generator. If the frequency of the phase signal cannot be adjusted well or a polyphase signal is generated, the practicality of the buck converter will be reduced.

Contents of the invention

Embodiments of the present application provide a multi-phase buck converter circuit, device and equipment that can generate multi-phase signals, thus improving the practicality of the buck converter.

The first aspect of the embodiment of the present application provides a multi-phase buck conversion circuit, the circuit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first driver, a second Driver, first controller, second controller, voltage dividing module, first operational amplifier, reference voltage source, first inductor L1, second inductor L2, output resistor R0, load resistor _RL , output capacitor C0, where ,

The first terminal of the first switch S1 is connected to the first terminal and the signal input terminal of the third switch S3, and the second terminal of the first switch S1 is connected to the first terminal and the signal input terminal of the second switch S2. The first end of the first inductor L1 is connected, the control port of the first switch S1 is connected to the first end of the first driver, the second end of the second switch S2 is connected to ground,

The second end of the first inductor L1 and the second end of the second inductor L2, the first end of the output resistor R0, the first end of the load resistor _RL , and the voltage dividing module The first end is connected, wherein the first end of the load resistor R _L is a signal output port,

The second end of the output resistor R0 is connected to the first end of the output capacitor C0, the second end of the output capacitor C0 is connected to ground, and the second end of the load resistor R _L is connected to ground,

The second end of the first driver is connected to the control port of the second switch S2, the third end of the first driver is connected to the first end of the first controller, and the first control port The second end of the controller is connected to the first end of the second controller, and the third end of the first controller is connected to the output end of the first operational amplifier,

The second end of the second controller is connected to the first end of the second driver, and the second end of the second driver is connected to the control end of the third switch S3. The second driver The third terminal is connected to the control terminal of the fourth switch S4,

The second end of the third switch S3 is connected to the first end of the fourth switch S4 and the first end of the second inductor L2, and the second end of the fourth switch S4 is connected to ground.

The first terminal of the first operational amplifier is connected to the second terminal of the voltage dividing module, and the first operational amplifier The second terminal of the voltage converter is connected to the first terminal of the reference voltage source, and the second terminal of the reference voltage source is grounded.

In conjunction with the first aspect, in a possible implementation, the first controller includes: a second operational amplifier, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, The fifth MOS transistor M5, the first comparator, the second comparator, the third comparator, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fifth switch S5, the sixth switch S6, and the seventh switch S7 , the first resistor R1, where,

The first terminal of the second operational amplifier is connected to the voltage input port, the output terminal of the second operational amplifier is connected to the first terminal of the first MOS transistor M1, and the second terminal of the second operational amplifier The terminal is connected to the second terminal of the first MOS transistor M1 and the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.

The third end of the first MOS tube M1 and the first end of the second MOS tube M2, the second end of the second MOS tube M2, the first end of the third MOS tube M3, and the fourth MOS tube The first end of M4 and the first end of the fifth MOS transistor M5 are connected, and the third end of the second MOS transistor M2 is connected to the power supply.

The second end of the third MOS transistor M3 is connected to the first end of the first capacitor C1, the first end of the fifth switch S5, and the first end of the first comparator. The third end of the three MOS tube M3 is connected to the power supply,

The second end of the first comparator is connected to the signal output port that outputs the K2 proportional output signal, and the output port of the first comparator is connected to the first signal port,

The second end of the first capacitor C1 is connected to the second end of the fifth switch S5 and grounded,

The second end of the fourth MOS transistor M4 is connected to the first end of the second capacitor C2, the first end of the sixth switch S6, and the first end of the second comparator. The third terminal of the four MOS tube M4 is connected to the power supply,

The second end of the second comparator is connected to the signal output port that outputs the K5 proportional output signal, and the output port of the second comparator is connected to the clock signal port,

The second terminal of the second capacitor C2 is connected to the second terminal of the sixth switch S6 and grounded,

The second end of the fifth MOS transistor M5 is connected to the first end of the third capacitor C3, the first end of the seventh switch S7, and the first end of the third comparator. The third terminal of the five MOS tube M5 is connected to the power supply,

The second end of the third comparator is connected to the signal output port that outputs the K2 proportional output signal, and the output port of the third comparator is connected to the second signal port,

The second terminal of the third capacitor C3 is connected to the second terminal of the seventh switch S7 and is grounded.

Combined with the first aspect, in a possible implementation, the second MOS transistor M2 is used to output an output current signal of K2 proportion to the third MOS transistor M3, and the second MOS transistor M2 is used to output an output current signal of K2 proportion to the fourth MOS transistor M3. M4 outputs an output current signal with a K4 ratio, and the second MOS transistor M2 is used to output an output current signal with a K3 ratio to the fifth MOS transistor M5, where the value of K3 is used to indicate the operating frequency of the multi-phase buck conversion circuit.

In conjunction with the first aspect, in a possible implementation, the K2 proportional output signal includes a second phase PWM signal generated by the K2 proportional output signal.

In conjunction with the first aspect, in a possible implementation, the circuit further includes a second resistor R2, a first end of the second resistor R2 is connected to the second end of the first switch S1, and the third The second terminal of the two resistors R2 is connected to the first terminal of the second switch S2.

A second aspect of the embodiment of the present application provides a multi-phase buck conversion device, which includes a circuit board and a multi-phase buck conversion circuit as described in any one of the first aspects.

A third aspect of the embodiments of the present application provides a multi-phase buck conversion device, which includes a housing and a multi-phase buck conversion device as described in the second aspect.

Implementing the embodiments of this application will at least have the following beneficial effects:

The multi-phase buck conversion circuit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first driver, a second driver, a first controller, a second controller, and a voltage dividing module. , the first operational amplifier, the reference voltage source, the first inductor L1, the second inductor L2, the output resistor R0, the load resistor _RL , and the output capacitor C0, wherein the first terminal of the first switch S1 is connected to the third The first end of the switch S3 is connected to the signal input end, and the second end of the first switch S1 is connected to the first end of the second switch S2 and the first end of the first inductor L1. The control port of the first switch S1 is connected to the first terminal of the first driver, the second terminal of the second switch S2 is connected to ground, and the second terminal of the first inductor L1 is connected to the first terminal of the second inductor L2. The second end, the first end of the output resistor R0, the first end of the load resistor _RL , and the first end of the voltage dividing module are connected, wherein the first end of the load resistor _RL is a signal output port, the second end of the output resistor R0 is connected to the first end of the output capacitor C0, the second end of the output capacitor C0 is grounded, and the second end of the load resistor R _L is grounded, The second end of the first driver is connected to the control port of the second switch S2, the third end of the first driver is connected to the first end of the first controller, and the first control port The second end of the second controller is connected to the first end of the second controller, the third end of the first controller is connected to the output end of the first operational amplifier, and the second end of the second controller is connected to the output end of the first operational amplifier. The terminal is connected to the first terminal of the second driver, the second terminal of the second driver is connected to the control terminal of the third switch S3, and the third terminal of the second driver is connected to the fourth terminal of the second driver. The control end of the switch S4 is connected, and the second end of the third switch S3 is connected to the first end of the fourth switch S4 and the first end of the second inductor L2. The second terminal is connected to ground, the first terminal of the first operational amplifier is connected to the second terminal of the voltage dividing module, and the second terminal of the first operational amplifier is connected to the first terminal of the reference voltage source. The second terminal of the reference voltage source is connected to the ground. Therefore, a multi-phase signal can be generated, thereby improving the practicality of the buck converter.

Description of the drawings

Figure 1 is a schematic structural diagram of a multi-phase buck conversion circuit provided by an embodiment of the present application;

Figure 2 provides a schematic structural diagram of a first controller according to an embodiment of the present application;

Figure 3 is a schematic structural diagram of another multi-phase buck conversion circuit provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of the working waveform of a multi-phase buck conversion circuit provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than describing a specific sequence. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

Reference in this application to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

Please refer to Figure 1. Figure 1 provides a schematic structural diagram of a multi-phase buck conversion circuit according to an embodiment of the present application. Figure 1 As shown, the multi-phase buck conversion circuit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first driver 10, a second driver 20, a first controller 30, a second control The device 40, the voltage dividing module 50, the first operational amplifier 60, the reference voltage source 70, the first inductor L1, the second inductor L2, the output resistor R0, the load resistor R _L and the output capacitor C0, where,

The first terminal of the first switch S1 is connected to the first terminal and the signal input terminal of the third switch S3, and the second terminal of the first switch S1 is connected to the first terminal and the signal input terminal of the second switch S2. The first end of the first inductor L1 is connected, the control port of the first switch S1 is connected to the first end of the first driver 10, the second end of the second switch S2 is connected to ground,

The second end of the first inductor L1 and the second end of the second inductor L2, the first end of the output resistor R0, the first end of the load resistor _RL , and the voltage dividing module 50 The first end of the load resistor R _L is connected to the signal output port,

The second end of the first driver 10 is connected to the control port of the second switch S2, and the third end of the first driver 10 is connected to the first end of the first controller 30. The second terminal of the first controller 30 is connected to the first terminal of the second controller 40, and the third terminal of the first controller 30 is connected to the output terminal of the first operational amplifier 60,

The second terminal of the second controller 40 is connected to the first terminal of the second driver 20, and the second terminal of the second driver 20 is connected to the control terminal of the third switch S3. The third terminal of the second driver 20 is connected to the control terminal of the fourth switch S4,

The first terminal of the first operational amplifier 60 is connected to the second terminal of the voltage dividing module 50 , and the second terminal of the first operational amplifier 60 is connected to the first terminal of the reference voltage source 70 , the second terminal of the reference voltage source 70 is grounded.

In this example, the multi-phase buck conversion circuit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first driver, a second driver, a first controller, a second controller, The voltage dividing module, the first operational amplifier, the reference voltage source, the first inductor L1, the second inductor L2, the output resistor R0, the load resistor _RL , and the output capacitor C0, wherein the first terminal of the first switch S1 and The first end of the third switch S3 is connected to the signal input end, and the second end of the first switch S1 is connected to the first end of the second switch S2 and the first end of the first inductor L1. connection, the control port of the first switch S1 is connected to the first terminal of the first driver, the second terminal of the second switch S2 is grounded, and the second terminal of the first inductor L1 is connected to the first terminal of the first driver. The second end of the two inductors L2, the first end of the output resistor R0, the first end of the load resistor R _L , and the first end of the voltage dividing module are connected, wherein the load resistor R _L The first end of is a signal output port, the second end of the output resistor R0 is connected to the first end of the output capacitor C0, the second end of the output capacitor C0 is grounded, and the third end of the load resistor R _L Two ends are grounded, the second end of the first driver is connected to the control port of the second switch S2, and the third end of the first driver is connected to the first end of the first controller, so The second end of the first controller is connected to the first end of the second controller, the third end of the first controller is connected to the output end of the first operational amplifier, and the second control The second end of the second driver is connected to the first end of the second driver, the second end of the second driver is connected to the control end of the third switch S3, and the third end of the second driver is connected to the control end of the third switch S3. The control end of the fourth switch S4 is connected, and the second end of the third switch S3 is connected to the first end of the fourth switch S4 and the first end of the second inductor L2. The second end of the four-switch S4 is connected to ground, the first end of the first operational amplifier is connected to the second end of the voltage dividing module, and the second end of the first operational amplifier is connected to the The first terminal of the reference voltage source is connected, and the second terminal of the reference voltage source is grounded. Therefore, a multi-phase signal can be generated, thereby improving the practicality of the buck converter.

In a possible implementation, the first controller 30 includes: a second operational amplifier 301, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5. , the first comparator CMP1, the second comparator CMP2, the third comparator CMP3, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fifth switch S5, the sixth switch S6, the seventh switch S7, the A resistor R1, where,

The first controller and the second controller in the embodiment of the present application have the same circuit structure.

In a possible implementation, the second MOS transistor M2 is used to output an output current signal of K2 proportion to the third MOS transistor M3, and the second MOS transistor M2 is used to output an output current signal of K4 proportion to the fourth MOS transistor M4. To output a current signal, the second MOS transistor M2 is used to output an output current signal with a ratio of K3 to the fifth MOS transistor M5, where the value of K3 is used to indicate the operating frequency of the multi-phase buck conversion circuit.

In a possible implementation, the K2 proportional output signal includes a second phase PWM signal generated by the K2 proportional output signal.

In a possible implementation, as shown in Figure 3, the circuit further includes a second resistor R2, the first end of the second resistor R2 is connected to the second end of the first switch S1, and the The second terminal of the second resistor R2 is connected to the first terminal of the second switch S2.

In a specific embodiment, the embodiment of the present application provides an example of the working principle of a specific multi-phase buck conversion circuit.

The circuit shown in Figure 2 is a T _ON generating circuit (controller) when the multi-phase system is working. Compared with the single-phase T _ON generating circuit, the structure has two more sets of current proportion and slope generating circuits, as well as two comparators. The current in M2 is proportioned to M4 through K4 , the drain terminal of M4 is connected to the second capacitor C2 of the phase ramp signal, the second capacitor C2 is connected to the switch S6, the switch S6 is controlled by PHASE_CONTROL, the other terminal is connected to the second comparator CMP2, and the positive phase terminal of the second comparator CMP2 is connected to the reference voltage K5* VIN generates a phase output signal. The current in M2 passes through K3 and flows to M5 again. The drain terminal of M5 is connected to a third capacitor C3. Similarly, the third capacitor C3 is connected to the seventh switch S7. The seventh switch S7 is controlled by the PWM2 signal. , the third capacitor C3 is connected to the third comparator CMP3, and the positive phase terminal of CMP3 is connected to the K2*VOUT reference voltage to generate the T _ON signal of the second phase PWM. VIN is the input voltage.

The schematic diagram of the system operating waveform is shown in Figure 4. According to the T _SW period formula of the single-phase operating system, the K3 coefficient can be used to adjust the system operating frequency. Then the combination of the K4 coefficient and the second capacitor C2 capacitance can generate a phase start signal. Taking two phases as an example, the phase difference between the two is 180 degrees, that is, the second phase is delayed by half a period T _DELAY =1*T _SW /2 than the first phase. According to the T _SW formula in single-phase operation, T _SW =K2 *C _TON /(K3/R1), where C _TON is the capacitor connected to the MOS tube. Assuming that the capacitances of C1 and C2 are consistent, the slope time formula of the phase slope is T _DELAY =K5*C2/(K4* K1/R1), assuming C1=C2, and setting K5=K2, K4=2*K3, we can get T _DELAY ={K2*C _TON /(K3*K1/R1)}*(1/2)=1 *T _SW /2, it can be seen that the phase ramp signal realizes a 1/2 period time signal. In the same way, any other phase combination of two phases, three phases and more than four phases can be realized by simply adjusting the ratio of K4 and K3. As shown in Figure 4, assuming that the VOUT voltage is at the lowest point in the cycle, the voltage feedback loop comparator output is high, the PWM_RST signal is set high, the first phase PWM1 signal is set high, and the PHASE_CONTROL signal is set high, and the voltage on the first capacitor C1 Starts to rise, and the voltage of the second capacitor C2 also starts to rise. When the slope voltage of the first phase T _ON reaches the set value, the output of the comparator CMP1 is set to 0, and PWM1 is set to 0. Similarly, when the slope voltage of the second capacitor C2 reaches the set value When , that is, delayed by 1/2*T _SW relative to the PWM_RST of the first phase, the output of the comparator CMP2 is set to 0 and a PHASE2_RST narrow pulse signal is generated. The third capacitor C3 begins to charge, and at the same time the second phase PWM2 signal is set high. , when the slope voltage of the third capacitor C3 arrives, the PWM2 signal is set to 0, waiting for the new cycle start signal. After the PWM2 signal is set to 0, it waits for a period of time before the first phase cycle time T _SW arrives. PWM_RST is set high again, PWM1 is set high again and enters a new cycle. At the same time, the second capacitor C2 also begins to generate a new ramp voltage. When the ramp voltage of the second capacitor C2 arrives, it means that the second cycle start signal relative to the first phase is delayed again. After 1/2*T _SW time, the second phase receives the new PHASE2_RST signal, and the second phase PWM2 is set high again, starting a new cycle.

The multi-phase buck conversion circuit can also perform frequency adjustment. The principle of frequency adjustment is: the current of M2 is equal to the current in M1 and equal to the current in resistor R1. According to the working characteristics of EA, I _R1 =K*VIN/R1, then It can be obtained that the current in M3 is K3*(K1*VIN/R1). According to the reference voltage K2*VOUT of the positive phase terminal of the first comparator CMP1, assuming that the ramp-up time is TON, according to the capacitor voltage charge formula I*T=C*V You can get TON*K3*(K1*VIN/R1)=K2*VOUT*C1, then you can get the TON expression as TON=K2*VOUT*C1/(K3*VIN/R1)={K2*C1/(K3 *K1/R1)}*VOUT/VIN, according to the relationship between the operating frequency of the buck converter and the input and output voltage, we can get T _ON =T _SW *(VOUT/VIN), where T _SW is the converter working cycle time, compare the two Using the TON formula, we can get the system working cycle T _SW =K2*C1/(K3/R1), where K2, C1 and R1 are fixed constants, and K3 is an adjustable variable, so we can get the system working cycle when K3 is fixed. It is fixed, that is, the system operating frequency basically does not change with changes in input or output. At the same time, different frequency setting adjustment functions can be achieved by adjusting the value of K3.

It should be noted that for the sake of simple description, the foregoing method embodiments are expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence. Because in accordance with this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily necessary for this application.

In the above embodiments, each embodiment is described with its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or may be Integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical or other forms.

The embodiments of the present application have been introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and the core idea of the present application; at the same time, for Those of ordinary skill in the art will have changes in the specific implementation and application scope based on the ideas of the present application. In summary, the content of this description should not be understood as a limitation of the present application.

Claims

A multi-phase buck conversion circuit, characterized in that the circuit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first driver, a second driver, and a first controller. , the second controller, the voltage dividing module, the first operational amplifier, the reference voltage source, the first inductor L1, the second inductor L2, the output resistor R0, the load resistor RL , and the output capacitor C0, where,

The first terminal of the first switch S1 is connected to the first terminal and the signal input terminal of the third switch S3, and the second terminal of the first switch S1 is connected to the first terminal and the signal input terminal of the second switch S2. The first end of the first inductor L1 is connected, the control port of the first switch S1 is connected to the first end of the first driver, the second end of the second switch S2 is connected to ground,

The second end of the first inductor L1 and the second end of the second inductor L2, the first end of the output resistor R0, the first end of the load resistor RL , and the voltage dividing module The first end is connected, wherein the first end of the load resistor R L is a signal output port,

The second end of the output resistor R0 is connected to the first end of the output capacitor C0, the second end of the output capacitor C0 is connected to ground, and the second end of the load resistor R L is connected to ground,

The second end of the first driver is connected to the control port of the second switch S2, the third end of the first driver is connected to the first end of the first controller, and the first control port The second end of the controller is connected to the first end of the second controller, and the third end of the first controller is connected to the output end of the first operational amplifier,

The second end of the second controller is connected to the first end of the second driver, and the second end of the second driver is connected to the control end of the third switch S3. The second driver The third terminal is connected to the control terminal of the fourth switch S4,

The second end of the third switch S3 is connected to the first end of the fourth switch S4 and the first end of the second inductor L2, and the second end of the fourth switch S4 is connected to ground.

The first terminal of the first operational amplifier is connected to the second terminal of the voltage dividing module, the second terminal of the first operational amplifier is connected to the first terminal of the reference voltage source, and the reference The second terminal of the voltage source is connected to ground.
The conversion circuit according to claim 1, characterized in that the first controller includes: a second operational amplifier, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4. , the fifth MOS transistor M5, the first comparator, the second comparator, the third comparator, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fifth switch S5, the sixth switch S6, the seventh switch S7, first resistor R1, where,

The first terminal of the second operational amplifier is connected to the voltage input port, the output terminal of the second operational amplifier is connected to the first terminal of the first MOS transistor M1, and the second terminal of the second operational amplifier The terminal is connected to the second terminal of the first MOS transistor M1 and the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded.

The third end of the first MOS tube M1 and the first end of the second MOS tube M2, the second end of the second MOS tube M2, the first end of the third MOS tube M3, and the fourth MOS tube The first end of M4 and the first end of the fifth MOS transistor M5 are connected, and the third end of the second MOS transistor M2 is connected to the power supply.

The second end of the third MOS transistor M3 is connected to the first end of the first capacitor C1, the first end of the fifth switch S5, and the first end of the first comparator. The third end of the three MOS tube M3 is connected to the power supply,

The second end of the first comparator is connected to the signal output port that outputs the K2 proportional output signal, and the output port of the first comparator is connected to the first signal port,

The second end of the first capacitor C1 is connected to the second end of the fifth switch S5 and grounded,

The second terminal of the fourth MOS transistor M4, the first terminal of the second capacitor C2, and the first terminal of the sixth switch S6 terminal is connected to the first terminal of the second comparator, and the third terminal of the fourth MOS transistor M4 is connected to the power supply,

The second end of the second comparator is connected to the signal output port that outputs the K5 proportional output signal, and the output port of the second comparator is connected to the clock signal port,

The second terminal of the second capacitor C2 is connected to the second terminal of the sixth switch S6 and grounded,

The second end of the fifth MOS transistor M5 is connected to the first end of the third capacitor C3, the first end of the seventh switch S7, and the first end of the third comparator. The third terminal of the five MOS tube M5 is connected to the power supply,

The second end of the third comparator is connected to the signal output port that outputs the K2 proportional output signal, and the output port of the third comparator is connected to the second signal port,

The second terminal of the third capacitor C3 is connected to the second terminal of the seventh switch S7 and is grounded.
The conversion circuit according to claim 2, characterized in that the second MOS transistor M2 is used to output an output current signal of K2 proportion to the third MOS transistor M3, and the second MOS transistor M2 is used to output an output current signal of K2 proportion to the fourth MOS transistor M3. The tube M4 outputs an output current signal with a ratio of K4, and the second MOS tube M2 is used to output an output current signal with a ratio of K3 to the fifth MOS tube M5, where the value of K3 is used to indicate the operating frequency of the multi-phase buck conversion circuit. .
The conversion circuit according to claim 3, wherein the K2 proportional output signal includes a second phase PWM signal generated by the K2 proportional output signal.
The conversion circuit according to any one of claims 1 to 4, characterized in that the circuit further includes a second resistor R2, the first end of the second resistor R2 and the second end of the first switch S1 The second terminal of the second resistor R2 is connected to the first terminal of the second switch S2.
A multi-phase buck conversion device, characterized in that the device includes a circuit board and the multi-phase buck conversion circuit according to any one of claims 1 to 5.
A multi-phase buck conversion device, characterized in that the device includes a housing and a multi-phase buck conversion device as claimed in claim 6.