WO2023202242A1 - Instruction word processing circuit and method, and chip - Google Patents

Abstract

An instruction word processing circuit and method, and a chip, which belong to the technical field of artificial intelligence. The instruction word processing circuit comprises: an instruction word generation register, an instruction word sending circuit, an instruction word receiving circuit and an instruction word training state machine, wherein the instruction word generation register is electrically connected to the instruction word sending circuit; the instruction word training state machine is respectively electrically connected to the instruction word generation register, the instruction word sending circuit and the instruction word receiving circuit; and the instruction word sending circuit comprises a plurality of delay control units, which are used for adjusting a transmission delay of an instruction word in the instruction word sending circuit. A plurality of delay control units are added to an instruction word sending circuit, such that a transmission delay of an instruction word in the instruction word sending circuit can be adjusted, and thus the central position of a data window of the instruction word can be aligned with a clock sampling edge, thereby facilitating correct sampling performed by a memory on the instruction word.

Description

Instruction word processing circuit, chip and method

This application claims priority to the Chinese patent application with application number 202210430604.4 and the invention name "Instruction Word Processing Circuit, Chip and Method" submitted on April 22, 2022, the entire content of which is incorporated into this application by reference.

Technical field

This application relates to the field of artificial intelligence technology, and in particular to an instruction word processing circuit, chip and method.

Background technique

During the working process of the high-bandwidth memory (High Bandwidth Memory, HBM) chip, the host of the high-bandwidth memory sends the instruction word (Address Word) to the dynamic random access memory (Dynamic Random Access Memory, DRAM) of the high-bandwidth memory. AWORD) signal to instruct the DRAM to perform corresponding operations through the instruction word corresponding to the instruction word signal.

In the related art, when the center of the high level of the instruction word signal (ie, the data window) is aligned with the rising edge of the sampling clock signal, the DRAM samples the instruction word signal to obtain the correct instruction word. However, in the actual working process of high-bandwidth memory, the instruction word signal transmitted to the DRAM and the sampling clock signal are prone to offset, resulting in instruction word signal sampling errors, which leads to errors in the host's operation of the DRAM, thereby affecting the DRAM. the accuracy of the data stored in it.

Contents of the invention

This application provides an instruction word processing circuit, chip and method. The technical solutions are as follows:

According to one aspect of the embodiment of the present application, an instruction word processing circuit is provided. The instruction word processing circuit includes:

The instruction word processing circuit includes: an instruction word generation register, an instruction word sending circuit, an instruction word receiving circuit and an instruction word training state machine;

The instruction word generation register is electrically connected to the instruction word sending circuit;

The instruction word training state machine is electrically connected to the instruction word generation register, the instruction word sending circuit and the instruction word receiving circuit respectively;

The instruction word sending circuit includes a plurality of delay control units, and the delay control units are used to adjust the transmission delay of the instruction word in the instruction word sending circuit.

According to one aspect of an embodiment of the present application, a chip is provided, and the chip includes: a memory and an instruction word processing circuit as described above.

According to one aspect of the embodiment of the present application, an instruction word processing method is provided. The method is applied in an instruction word processing circuit. The instruction word processing circuit includes an instruction word generation register, an instruction word sending circuit, and an instruction word receiving circuit. and instruction word training state machine; the method includes:

The instruction word generation register generates a test instruction word sequence; wherein the test instruction word sequence includes at least one test instruction word;

The instruction word sending circuit sends the test instruction word to the memory;

The instruction word receiving circuit receives the feedback instruction word corresponding to the test instruction word sent by the memory, and sends the feedback instruction word to the instruction word training state machine. The feedback instruction word is generated by the memory according to The clock signal is obtained by sampling the test instruction word;

The instruction word training state machine adjusts the transmission delay of the transmission sub-circuit corresponding to the test instruction word according to the feedback instruction word, and determines the delay control unit that should be used by the transmission sub-circuit corresponding to the test instruction word. quantity.

According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, and the computer program is loaded and executed by a processor to implement the above instruction word processing method.

According to an aspect of an embodiment of the present application, a computer program product is provided. The computer program product includes a computer program. The computer program is stored in a computer-readable storage medium. A processor reads the computer program from the computer-readable storage medium. The computer program is fetched and executed to implement the above instruction word processing method.

The technical solution provided by this application improves the instruction word sending circuit and adds more than one delay control unit in the instruction word sending circuit, so that the instruction word sending circuit has the ability to change the transmission delay of the instruction word. Based on this ability, the circuit can adjust the relative position between the clock sampling edge and the data window of the instruction word, which helps to align the clock sampling edge with the center position of the data window (such as high level) of the instruction word, and then Improved the sampling accuracy of instruction words.

Description of the drawings

Figure 1 is a schematic structural diagram of a high-bandwidth memory dynamic random access memory provided by an exemplary embodiment of the present application;

Figure 2 is a schematic diagram of the row instruction word transmission process of the high-bandwidth memory provided by an exemplary embodiment of the present application;

Figure 3 is a schematic diagram of the alignment relationship between the rising edge of clock sampling and the data window of the instruction word under normal circumstances provided by an exemplary embodiment of the present application;

Figure 4 is a schematic diagram of the offset between the instruction word and the sampling clock signal provided by an exemplary embodiment of the present application;

Figure 5 is a schematic diagram showing the deviation between the instruction word and the sampling clock signal provided by another exemplary embodiment of the present application;

Figure 6 is a schematic diagram of the structure of an instruction word processing circuit provided by an exemplary embodiment of the present application;

Figure 7 is a schematic diagram of the arrangement of instruction words in the instruction word register in HBM DRAM provided by an exemplary embodiment of the present application;

Figure 8 is a schematic diagram of the arrangement of delay control units in the transmission subcircuit corresponding to the column of instruction words in the instruction word sending circuit provided by an exemplary embodiment of the present application;

Figure 9 is a schematic diagram of the offset step counting unit adjusting the number of delay control units used in the transmission subcircuit provided by an exemplary embodiment of the present application;

Figure 10 is a schematic diagram of the left shift difference and right shift difference determination process provided by an exemplary embodiment of the present application;

Figure 11 is a schematic diagram of a single-step byte training stage provided by an exemplary embodiment of the present application;

Figure 12 is a schematic diagram of the single-step segment training stage provided by an exemplary embodiment of the present application;

Figure 13 is a flow chart of an instruction word processing method provided by an exemplary embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Before introducing the technical solution of this application, the terms involved in this application will be introduced and explained.

A high-bandwidth memory chip is a chip that includes a central processing unit (Central Processing Unit, CPU)/image processor (Graphic Processing Unit, GPU). In some embodiments, the high-bandwidth memory chip includes multiple stacked Double Data Rate (DDR) chips (or DRAM, SDRAM (Synchronous Dynamic Random Access Memory, synchronous dynamic random access memory), etc.), By packaging DDR chips and processors in a stacked relationship, a high-bandwidth memory with a higher memory bus width can be obtained. In the embodiment of this application, high-bandwidth memory may also be called high-bandwidth memory.

High-bandwidth memory and high-performance graphics accelerators, high-performance data centers, Artificial Intelligence (AI), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) and Used in conjunction with network equipment, it can meet some application scenarios that require high bandwidth.

Artificial intelligence is a theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can respond in a similar way to human intelligence. Artificial intelligence is the study of the design principles and implementation methods of various intelligent machines, so that the machines have the functions of perception, reasoning and decision-making.

Artificial intelligence technology is a comprehensive subject that covers a wide range of fields, including both hardware-level technology and software-level technology. Basic artificial intelligence technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, operation/interaction systems, mechatronics and other technologies. Artificial intelligence software technology mainly includes computer vision technology technology, speech processing technology, natural language processing technology, and machine learning/deep learning.

In view of the bandwidth advantage, high-bandwidth memory has more powerful transmission capabilities, which can provide better support for artificial intelligence technology, high-performance computing, games and other application scenarios, especially scenarios that require the processing of large amounts of data.

Before introducing the technical solutions provided by the embodiments of the present application, the background technology involved in the embodiments of the present application will first be described.

The memory of the high-bandwidth memory is used to receive the instruction word sent by the host of the high-bandwidth memory and perform corresponding operations according to the instructions of the instruction word. Optionally, the memory may be a dynamic random access memory or other memory capable of receiving instructions.

Exemplarily, FIG. 1 is a schematic structural diagram of a high-bandwidth memory dynamic random access memory provided by an exemplary embodiment of the present application. Among them, the dynamic random access memory 100 of the high-bandwidth memory can receive the instruction word sequence (ie, instruction word signal) provided by the host of the high-bandwidth memory, and obtain the instruction word by analyzing the received instruction word sequence. The dynamic random access memory 100 may include a multiple input signature register (Multiple Input Signature Register, MISR) unit for storing the above parsed instruction words.

In addition, the dynamic random access memory 100 supports the IEEE (the Institute of Electrical and Electronics Engineers, Institute of Electrical and Electronics Engineers) Std (standard) 1500 interface to support testing, debugging and other functions. Table 1 is about the type and description information of each interface in Figure 1.

Table 1

The instruction word of high-bandwidth memory is the general name for the control signals on the dynamic random access memory interface of high-bandwidth memory. It can be used to instruct the dynamic random access memory to perform related operations on data, such as read, write, refresh, overwrite and other operations. In some examples, the instruction words include: a row (Row, R) instruction word signal, a column (Column, C) instruction word signal, and a clock enable (Clock Enable, CKE) signal.

The following takes the single-channel HBM2e DRAM as an example (HBM2e is the third generation HBM) to introduce the instruction words of high-bandwidth memory. The instruction words of high-bandwidth memory can be divided into two categories: row instruction words and column instruction words. Each row instruction word may include 9 bytes (bits), that is, the bit width of the row instruction word is 9, and each column instruction word may include 7 bytes, that is, the bit width of the column instruction word is 7. Each byte corresponds to a rising edge instruction word and a falling edge instruction word. Referring to Table 2, Table 2 shows the bit width distribution of different types of instruction word signals.

Table 2

Through the instruction words of the high-bandwidth memory, the function of sending instructions to the dynamic random access memory of the high-bandwidth memory can be realized. Only when the instruction words of the high-bandwidth memory are accurately sent can the dynamic random access memory of the high-bandwidth memory be ensured. correctness of operation.

Exemplarily, FIG. 2 is a schematic diagram of a row instruction word transmission process of a high-bandwidth memory provided by an exemplary embodiment of the present application. CK_t (forward clock signal) and CK_c (reverse clock signal) in Figure 2 form a differential clock, where, There is a 180° phase difference between CK_t and CK_c. Optionally, when the rising edge of CK_t (or the falling edge of CK_c) is aligned with the center position of the data window 201 corresponding to the instruction data of the row instruction word, the dynamic random access memory of the high-bandwidth memory can be guaranteed Sample the correct instruction word. Alternatively, the rising edge of CK_t and the falling edge of CK_c may be called clock sampling edges. R0-R6 in Figure 2 are 7 bytes (i.e. bit width) corresponding to a certain row instruction word.

For example, FIG. 3 is a schematic diagram of the alignment relationship between the rising edge of clock sampling and the data window of the instruction word under normal circumstances, provided by an exemplary embodiment of the present application. In Figure 3, the data in the data window 310 of the instruction word is 1 (high level), and the clock sampling edge (clock rising edge) 301 is aligned with the high level center 302 of the instruction word (that is, the center of the data window 310). Optionally, the rising edge of the clock in Figure 3 corresponds to the center position of the data window of the instruction word, which is called sampling alignment.

On the rising edge of CK_t (or the falling edge of CK_c), when the center position of the data window corresponding to the instruction data of the row instruction word is offset, the dynamic random access memory sampling of the high-bandwidth memory cannot be guaranteed. The correctness of the command word. At this time, the high-bandwidth memory is in a metastable state, and the data obtained by sampling the instruction word signal in the dynamic random access memory of the high-bandwidth memory has a certain probability of errors. For example, on the rising edge of CK_t (or the falling edge of CK_c), if the center position of the data window corresponding to the instruction data of the row instruction word is offset, although the data in the data window of the instruction word is 1, Due to a dynamic random access memory sampling error, the data corresponding to the sampled instruction word is 0.

For example, FIG. 4 is a schematic diagram illustrating the deviation between the instruction word and the sampling clock signal provided by an exemplary embodiment of the present application. The clock sampling edge (rising edge of the clock) 401 is offset from the data window 410 of the instruction word, causing the dynamic random access memory of the high-bandwidth memory to erroneously sample the instruction word.

In digital circuits, under ideal conditions, the sampling edge of the clock signal and the data appear at the same time, and the correct data can be collected. In reality, the data signal has a rise time, and the state transition of the logic gate also takes time. Therefore, the data should remain stable before the clock sampling edge appears (that is, before the clock sampling edge appears, the signal's high level or The low level has remained stable). The minimum time the data remains stable before the clock sampling edge occurs is called setup time (set up timing). Since it takes a certain amount of time to collect data, the data should remain stable for a period of time after the clock sampling edge occurs, so that there is sufficient time to sample the data. After the clock sampling edge occurs, the shortest time for the data to remain stable is called the hold time (hold timing). When the clock sampling edge is too close to the data setup edge (or the cancellation edge), a timing violation occurs in the setup time (or sustain time) of the sampling, that is, the time for the data to stabilize before the clock sampling edge appears is less than the setup time, resulting in The data is unstable, and the time the data remains stable after the clock sampling edge appears is less than the hold time, resulting in the dynamic random access memory not having enough time to sample the data, which in turn causes the dynamic random access memory to sample data incorrectly.

For example, FIG. 5 is a schematic diagram of an offset between an instruction word and a sampling clock signal provided by another exemplary embodiment of the present application. In Figure 5, although the clock sampling edge 501 does not shift out of the data window of the instruction word, the distance between the clock sampling edge and the data cancel edge 502 of the instruction word is too close, resulting in a timing violation of the maintenance time, thereby affecting the sampling of the instruction word. Correctness, causing errors in the operations performed by the memory of high-bandwidth memory, causing exceptions in the operations performed by the memory of high-bandwidth memory.

In some embodiments, the reasons that cause the center position of the data window of the instruction word to deviate from the clock sampling edge may include:

1. Because the back-end timing of high-bandwidth memory does not converge, the transmission of instruction words in the transmission line is delayed, resulting in offset;

2. Due to production failures of high-bandwidth memory, the transmission of instruction words in the transmission line is delayed, resulting in offset;

3. During the working process of high-bandwidth memory, due to environmental changes in process, voltage, temperature, etc., the transmission of instruction words in the transmission line is delayed, resulting in offset;

4. During the operation of high-bandwidth memory, the influence of crosstalk between signals causes the instruction word and clock signal to deviate.

Optionally, when the data window of the instruction word and the clock signal are offset, the following problems will occur:

1. If this operation is the loss or sampling error of the Active command, the "read" after the subsequent Active command will Or the "write" command will work when the row is not activated, and HBM DRAM cannot correctly execute the "read" or "write" command, that is, the "read" or "write" command will not be executed normally.

2. If this operation is a loss or sampling error of the "Precharge" or "Precharge All" command, the currently activated row cannot be correctly precharged and exited, which will result in subsequent HBM DRAM , the "read" or "write" instructions will not be executed normally.

3. If this operation is the loss or sampling error of the "Single Bank" or "Refresh" instruction, HBM DRAM will lose the current refresh instruction. If the refresh instruction cannot satisfy the refresh of HBM DRAM demand, it will cause the data stored in HBM DRAM to malfunction or be lost.

4. If this operation is the loss or sampling of the "Power-Down Entry" or "Self Refresh Entry" or "Power-Down&Self Refresh Exit" command If it is wrong, it will cause the mode switching error of HBM DRAM, which will lead to the abnormality of HBM DRAM.

5. If this operation is a loss or sampling error of "read" and "write" instructions, HBM DRAM will have errors in reading and writing data, and may even cause pollution to the data in HBM DRAM.

Embodiments of the present application provide an instruction word processing circuit and method, which can be used to adjust the offset between the data window of the instruction word and the clock signal to achieve sampling alignment, thereby improving the sampling accuracy of the instruction word by the memory of the bandwidth memory. .

Please refer to FIG. 6 , which is a schematic diagram of the structure of an instruction word processing circuit provided by an exemplary embodiment of the present application. The instruction word processing circuit includes: an instruction word generation register 610, an instruction word sending circuit 620, an instruction word receiving circuit 630 and an instruction word training state machine 640;

The instruction word generation register 610 is electrically connected to the instruction word sending circuit 620; the instruction word training state machine 640 is electrically connected to the instruction word generation register 610, the instruction word sending circuit 620 and the instruction word receiving circuit 630 respectively; the instruction word The sending circuit 620 includes a plurality of delay control units 622, and the delay control units 622 are used to adjust the transmission delay of the instruction word in the instruction word sending circuit 620.

The instruction word generation register 610 refers to a synchronous sequential logic circuit used to store and generate binary bit codes. Optionally, the storage circuit corresponding to the instruction word generation register 610 includes several flip-flops (FF) or latches (latches) with memory functions. Take a flip-flop as an example. A flip-flop is used to store k-bit binary codes, and k is a positive integer. By connecting the clock ports of x flip-flops, an instruction generation register that stores x*k-bit binary codes can be formed. x is Positive integer. In some cases, k=1, that is, a flip-flop can store 1 binary bit. Among them, the binary bit code can constitute the instruction word signal. The instruction word signal can only include row instruction words, or only column instruction words, or can also include both row instruction words and column instruction words. In the embodiment of the present application, the instruction word signal The number of instruction words included is not limited.

The command word transmitting circuit 620 refers to a circuit for transmitting command word signals. In some embodiments, the instruction word sending circuit 620 includes at least one transmission sub-circuit. Optionally, the transmission subcircuit is also called an instruction word transmission path. The above-mentioned instruction word processing circuit can be deployed in the above-mentioned high-bandwidth memory, and the instruction word sending circuit 620 is used for the host of the high-bandwidth memory to send instruction words to the memory of the high-bandwidth memory. Optionally, the above-mentioned instruction word processing circuit may be the above-mentioned high-bandwidth memory, and the embodiments of the present application are not limited here.

In some embodiments, the number of transmission sub-circuits in the instruction word sending circuit 620 is related to the total bit width of the instruction words supported in the high-bandwidth memory. For example, the number of transmission sub-circuits in the instruction word sending circuit 620 may be the same as the number of bits of the total bit width of the instruction words supported in the high-bandwidth memory. For example, when the total bit width of the instruction word of the high-bandwidth memory is 17 bits (i.e., 17 bits, the sum of the bit widths of the row instruction word, column instruction word and clock enable signal), the transmission in the instruction word sending circuit 620 The total number of sub-circuits is 17, that is, the transmission sub-circuit has a one-to-one correspondence with the bytes of the instruction word, and one byte of the instruction word corresponds to one transmission sub-circuit. Optionally, the instruction word sending circuit 620 can transmit the bytes corresponding to the instruction words in parallel through at least one transmission subcircuit, thereby improving the transmission efficiency of the instruction words. In addition, the number of transmission sub-circuits is set according to the total bit width of the instruction word, so that the instruction sending circuit 620 can be adjusted for each byte of the instruction word to achieve alignment between the center position of the data window of the instruction word and the clock sampling edge. .

In some embodiments, the transmission sub-circuit in the instruction word sending circuit 620 is arranged in a manner consistent with being arranged within a high bandwidth. It is related to the arrangement of the instruction words in the instruction word register in the stored memory. The memory can be a dynamic random access memory or other types of memory. For example, at least one transmission sub-circuit in the instruction word sending circuit 620 can be arranged sequentially according to the byte arrangement of the instruction words in the instruction word register.

For example, FIG. 7 is a schematic diagram of the arrangement of instruction words in the instruction word register in HBM DRAM provided by an exemplary embodiment of the present application. In Figure 7, the instruction word register 710 is a multi-input feature register, or a linear feedback shift register (Linear Feedback Shift Register, LFSR), which is used to store instruction words. As shown in Figure 7, the instruction word register 710 includes 17 bytes (ie, 34-bit instruction bits). From left to right, they are: bytes corresponding to R5~R0, bytes corresponding to R6, and C7~C4. byte, the byte corresponding to CKE, the byte corresponding to C3 to C0, and the byte corresponding to C8, then the 17 transmission sub-circuits in the instruction word sending circuit 620 can be sorted in the order of R5-C8 in Figure 7.

Among them, the falling edge instruction words (F in Figure 7) and rising edge instruction words (R in Figure 7) in each byte are staggered from left to right. The rising edge instruction word means the signal changes from 0 to 1, and the falling edge instruction word means the signal changes from 1 to 0. For example, the byte corresponding to R5 includes the R5 falling edge instruction word and the R5 rising edge instruction word. The R5 falling edge instruction word is arranged to the left of the R5 rising edge instruction word. C0-C8 are 9 bytes corresponding to the column instruction word.

It should be noted that the arrangement of instruction words in the instruction word register in the embodiment of the present application can be determined according to actual conditions such as relevant standards, and is not limited in the embodiment of the present application.

In some embodiments, by setting the arrangement of the transmission subcircuit in the instruction word sending circuit 620 to be the same as the arrangement of the instruction words in the instruction word register, the memory of the high-bandwidth memory can facilitate the sampling and summarization of instruction words. storage.

The instruction word sending circuit 620 has more than one delay control unit. In some embodiments, the delay control unit is called a delay element (Delay Element, DE). The delay control unit can be used to increase the transmission delay of the instruction word transmitted in the instruction word sending circuit to adjust the transmission delay of the instruction word in the instruction word sending circuit. For example, each delay control unit can correspond to the same or different delay lengths (such as 36ps, 32ps, 28ps, etc.). According to the transmission delay requirements, different numbers of delay control units can be set in the instruction invention circuit 620. To increase the transmission delay of the instruction word transmitted in the instruction word sending circuit. The function implementation of the delay control unit will be described in detail below and will not be repeated here.

In some embodiments, more than one transmission sub-circuit in the instruction word sending circuit 620 shares the delay control unit in the instruction word sending circuit 620, that is, multiple delay control units in the instruction word sending circuit 620, each transmission Sub-circuits can be called as needed. In other embodiments, the transmission sub-circuits each have an independent delay control unit, that is, each transmission sub-circuit is independently provided with at least one delay control unit. The embodiments of the present application are not limited here.

The command word receiving circuit 630 is a circuit capable of receiving digital pulses. In some embodiments, the digital pulses include 0-1 pulses (representing 1) and 1-0 pulses (representing 0). Optionally, the instruction word receiving circuit 630 refers to an interface supported by the host of the high-bandwidth memory, which can be used to receive the instruction word returned by the memory of the high-bandwidth memory. The interface type of the instruction word receiving circuit 630 belongs to the interface supported by the high-bandwidth memory and the memory of the high-bandwidth memory, such as the IEEE 1500 interface.

The instruction word training state machine 640 refers to a circuit responsible for training the transmission delay of the instruction word. In some embodiments, the instruction word training state machine 640 refers to a circuit designed through an integrated circuit (such as an application specific integrated circuit (Application Specific Integrated Circuit, ASIC)) and generated after a chip tape-out process. Optionally, the instruction word training state machine 640 can be deployed in a high-bandwidth memory to train the transmission delay of the instruction word in the high-bandwidth memory so that the center position of the data window of the instruction word is consistent with the clock sampling edge. alignment.

In some embodiments, the instruction word training state machine 640 is electrically connected to the instruction word generation register 610, the instruction word sending circuit 620, and the instruction word receiving circuit 630, including: the instruction word training state machine 640 is connected to the instruction word through an interface. The interface of the word generation register 610, the interface of the instruction word transmitting circuit 620, and the interface of the instruction word receiving circuit 630 are connected. Optionally, the interfaces used by the instruction word training state machine 640 to connect to the instruction word generation register 610, the instruction word sending circuit 620, and the instruction word receiving circuit 630 may be the same interface, or they may be different interfaces.

For example, the instruction word training state machine 640 and the instruction word generation register 610 are connected through interface 1, the instruction word training state machine 640 and the instruction word sending circuit 620 are connected through interface 2, and the instruction word training state machine 640 and the instruction word are connected through interface 2. The receiving circuits 630 are connected through interface 3, where interface 1, interface 2 and interface 3 are three different interfaces.

In some embodiments, referring to FIG. 6 , the instruction word generation register 610 , the instruction word sending circuit 620 , the instruction word receiving circuit 630 and the instruction word training state machine 640 are all disposed in the host 600 of the high-bandwidth memory chip. Among them, the instruction word generation register 610 and the instruction word training state machine 640 are applied to the instruction word training phase of the high-bandwidth memory. The instruction word training (training) phase can be called the control word (Control Word, CA) training phase. The instruction word training phase is different from the high-bandwidth memory working phase. In the working phase, the high-bandwidth memory sends instruction words to the memory through the host to instruct the memory to complete corresponding operations to complete external tasks, while the instruction word training phase is used to adjust the alignment position of the clock sampling edge and the data window of the instruction word. Optionally, the instruction word generation register 610 can be applied to both the instruction word training phase and the working phase. The instruction word sending circuit 620 can be used both in the instruction word training phase and in the working phase. The instruction word training phase will be described in detail below and will not be described again here.

To sum up, by improving the instruction word sending circuit and adding more than one delay control unit in the instruction word sending circuit, the instruction word sending circuit has the ability to change the transmission delay of the instruction word. The instruction word sending circuit is based on This ability can adjust the relative position between the clock sampling edge and the data window of the instruction word, thereby helping to align the clock sampling edge with the center position of the data window (such as high level) of the instruction word, thereby improving Sampling accuracy of instruction words.

In addition, bytes corresponding to the instruction words are transmitted in parallel through at least one transmission subcircuit, thereby improving the transmission efficiency of the instruction words. At the same time, the number of transmission sub-circuits is set according to the total bit width of the instruction word, so that the instruction sending circuit can be adjusted for each byte of the instruction word, and by adjusting the number of delay control units used in the instruction word sending circuit, Changing the transmission delay of the instruction word in the transmission control circuit to adjust the alignment position between the clock sampling edge and the center position of the data window of the instruction word helps to align the clock sampling edge with the center position of the data window of the instruction word , thereby improving the accuracy of the instruction words obtained by memory sampling.

In the instruction word training phase of the high-bandwidth memory, the clock sampling edge is aligned with the center position of the instruction word data window in advance, so that the memory can correctly sample the instruction word without affecting the working phase of the high-bandwidth memory. , that is, the high-bandwidth memory memory can perform correct operations according to the instructions of the high-bandwidth memory host.

Below, the instruction word processing circuit will be further introduced and explained through several embodiments.

In some embodiments, the instruction word sending circuit includes at least one transmission sub-circuit corresponding to the instruction word, and each transmission sub-circuit includes more than one delay control unit.

In some embodiments, the total number of delay control units included in each transmission sub-circuit is equal, that is, in the instruction word sending circuit, there are p delay single control units in all transmission sub-circuits, and p is greater than 1. Positive integer. For example, p=256.

In some embodiments, more than one delay control unit in the transmission subcircuit is arranged in series. Exemplarily, FIG. 8 is a schematic diagram of the arrangement of delay control units in the transmission sub-circuit corresponding to the column of instruction words in the instruction word sending circuit provided by an exemplary embodiment of the present application. As shown in Figure 8, the transmitting circuit 800 corresponding to the column instruction word includes 7 transmission sub-circuits, that is, the transmission sub-circuits corresponding to the C0-C6 bytes of the column instruction word. Each transmission sub-circuit includes p delay control units 801 (ie "DE" in Figure 8).

When the instruction word is transmitted in the transmission sub-circuit, the instruction word passes through the delay control unit in the transmission sub-circuit in sequence until the instruction word is taken out from the transmission sub-circuit. For example, C0 of the instruction word is taken out and sent to the memory of the high-bandwidth memory after passing through some or all delay control units in its corresponding transmission sub-circuit in sequence. Among them, the number of delay control units that the instruction words need to pass through can be set and adjusted according to the results of the instruction word training phase.

For any transmission sub-circuit in the instruction word sending circuit, the total number of delay control units in the transmission sub-circuit determines the ability of the transmission sub-circuit to adjust the transmission delay of the instruction word. Optionally, the ability of the transmission subcircuit to adjust the transmission delay of the instruction word is positively correlated with the total number of delay control units in the transmission subcircuit, that is, the greater the number of delay control units included in the transmission subcircuit. More means that the transmission subcircuit has a wider adjustable range for the transmission delay of the instruction word. Since the adjustment process of the transmission delay of the instruction word (that is, the adjustment process of the number of delay control units required) is at a high The instruction word training phase of the bandwidth memory is carried out. In the actual working process of the high-bandwidth memory, the transmission sub-circuit may not use all the delay control units. Therefore, the number of delay control units cannot be increased infinitely to avoid unnecessary waste.

The specific number of delay control units in the transmission subcircuit can be determined based on the ability of a single delay control unit to increase the transmission delay and the degree of offset between the data window of the instruction word and the clock sampling edge in the high-bandwidth memory. The embodiments of the present application are not limited here.

By setting a delay control unit in any transmission sub-circuit in the instruction transmission circuit, the transmission sub-circuit has the ability to change the transmission delay of the instruction word, so that in the instruction word training phase of the high-bandwidth memory, different The transmission sub-circuit corresponding to the instruction word (such as row instruction word, column instruction word) is independently adjusted. Since the data windows of different instruction words have different offsets from the clock sampling edges, adjusting the transmission delays of different instruction words on the corresponding transmission subcircuit will help ensure that the center position of the data window of each instruction word is consistent with the clock Sampling edge alignment helps reduce sampling errors in any instruction word and improves the accuracy of the memory receiving instructions sent by the host and performing corresponding operations in accordance with the instructions.

In some embodiments, the delay control unit changes the transmission delay of the instruction word by changing the phase of the instruction word. Among them, the phase of the instruction word can be changed through an inverter. For example, the delay control unit may include n inverters. The inverters are used to change the phase of the instruction word transmitted in the transmission subcircuit, and n is a positive integer. Among them, one inverter is used to increase the instruction word In the case of phase, the total number n of inverters included in one delay control unit satisfies: where k is a positive integer. In the case where one inverter is used to increase the phase of the instruction word (2a+1)π (a is a natural number), n is a positive even number. For example, when a=0, one inverter can increase the phase of the command word by π. At this time n=2, 4, 6....

Taking the classic mode as an example, an inverter that can increase the phase of the instruction word by π can increase the transmission delay of the instruction word by approximately 8ps (1ps=10 ^-12 s). When one delay control unit includes four inverters, for each additional delay control unit used in the transmission subcircuit, the transmission delay of the instruction word in the transmission subcircuit increases by 32ps.

The total number of inverters in each delay control unit determines the adjustment granularity of the transmission delay of the instruction word that the delay control unit can change. For example, the greater the total number of inverters in the delay control unit and the use of a delay control unit in the transmission subcircuit, the greater the change in the transmission delay of the instruction word, and the center position of the data window of the instruction word will be The alignment speed of the clock sampling edge is faster, but the alignment accuracy between the center position of the data window of the instruction word and the clock sampling edge may be lower.

On the contrary, the smaller the total number of inverters in the delay control unit, and each additional delay control unit used in the transmission subcircuit, the smaller the change in the transmission delay of the instruction word, the higher the high level of the data window of the instruction word. The alignment to the clock sampling edge is slower. In this case, every time a delay control unit is added (or reduced) in the transmission subcircuit, the increase (or decrease) in the transmission delay of the instruction word is small, so that the clock sampling edge is consistent with the data window of the instruction word. The alignment accuracy of the center position is higher.

Experiments were conducted by changing the number of inverters in the delay control unit. When the delay control unit included 4 inverters that could increase the π phase, the center position of the data window of the instruction word was aligned with the clock sampling edge. The effect is better, and the process of adjusting the center position of the instruction word data window to align with the clock sampling edge is faster. The embodiment of the present application constructs a delay control unit through an inverter, so that the delay control unit not only has the ability to transmit delay, but also has the ability to flexibly adjust the granularity of the transmission delay, so that the high-bandwidth memory has the ability to adjust The ability to align the position between the center position of the data window of the instruction word and the clock sampling edge, and then perform alignment training on the center position of the data window of the instruction word and the clock sampling edge to improve the sampling accuracy of the instruction word.

In some embodiments, the transmission subcircuit includes at least one tap interface, and the tap interface and the delay control unit are staggered in proportion; wherein, the tap interface is used to connect the instruction word transmitted in the transmission subcircuit, so as to transmit the instruction word to memory. In this way, by changing the tap interface used in the transmission circuit, the number of delay control units put into use in the transmission sub-circuit can be adjusted, and then the transmission delay of the instruction word in the instruction word sending circuit can be adjusted, so that the high-bandwidth memory has the ability to adjust instructions The ability to align the position between the center position of the word's data window and the clock sample edge. Optionally, the tap interface has two usage states. For example, "1" indicates that the tap interface is put into use, and "0" indicates that the tap interface is prohibited from use.

In some embodiments, the delay control units and tap interfaces are staggered according to a certain proportion in the transmission subpath, and also That is, there are m delay control units between one tap interface and the nearest adjacent tap interface, and m is a positive integer. For example, tap interface a and tap interface b are the two closest tap interfaces, and there are two delay control units between tap interface a and tap interface b.

In some embodiments, the delay control units and tap interfaces are staggered in the transmission subpath, that is, two adjacent delay control units in the transmission subcircuit are separated by a tap interface, and two adjacent delay control units are separated by a tap interface. There is a delay control unit spaced between tap interfaces. In this case, assuming that the instruction word transmission delay that each delay control unit can increase is the same, by adjusting the tap interface used to receive the instruction word in the transmission subcircuit, change the instruction word used before being taken out from the transmission subcircuit. The number of delay control units is used to change the transmission delay of the instruction word in the transmission sub-circuit.

To sum up, during the process of transmitting instruction words by the transmission subcircuit, when the transmitted instruction words arrive at the tap interface in use, they can be directly taken out of the transmission subcircuit by the tap interface and transmitted to the memory without the need for Then go through the delay control unit after the tap interface. By arranging at least one tap interface in the transmission sub-circuit, the high-bandwidth memory can adjust the transmission delay of the instruction word in the transmission sub-circuit by changing the tap interface used to receive the instruction word in the transmission sub-circuit, so that the high-bandwidth memory can be used at different times. When the structure of the transmission subcircuit is changed, the transmission delay of the instruction word in the transmission subcircuit can be flexibly changed.

Below, several embodiments are used to introduce the working process of the instruction word processing circuit in the instruction word training phase of high-bandwidth memory.

In some embodiments, the instruction word generation register is used to generate a test instruction word sequence; wherein the test instruction word sequence includes at least one test instruction word; the instruction word sending circuit is used to send the test instruction word to the memory; and the instruction word receiving circuit is used to Receive the feedback instruction word corresponding to the test instruction word sent by the memory, and send the feedback instruction word to the instruction word training state machine. The feedback instruction word is obtained by the memory sampling the test instruction word according to the clock signal; the instruction word training state machine is used to Feed back the instruction word, adjust the transmission delay of the transmission sub-circuit corresponding to the test instruction word, and determine the number of delay control units that should be used in the transmission sub-circuit corresponding to the test instruction word.

Among them, the test instruction word refers to the instruction word used to test the transmission delay in the transmission sub-circuit in which it is located. The test instruction word sequence is used to test the transmission delay in the transmission subcircuit corresponding to at least one instruction word. In some embodiments, the test instruction word sequence is called a test pattern sequence. Optionally, the test instruction word sequence in the embodiment of the present application corresponds to the above-mentioned instruction word signal (such as row instruction word, column instruction word), and the test instruction word in the test instruction word sequence corresponds to one word of a certain instruction word. Festival. Optionally, during the working phase of the high-bandwidth memory, the instruction word generation register is used to generate an instruction word signal to instruct the memory of the high-bandwidth memory to perform corresponding operations.

In some embodiments, the test instruction word is a high-level signal on an instruction word bit that lasts for 1 beat; where 1 beat refers to one cycle of the clock signal. In some embodiments, one cycle of the clock signal includes one clock rising edge and one clock falling edge. Optionally, the clock rising edge and the clock falling edge can be called clock sampling edges. In the embodiment of the present application, taking the rising edge of the clock as the clock sampling edge as an example, the offset existing between the data window of the instruction word and the clock sampling edge is adjusted.

In some embodiments, the test instruction word sequence includes a clock signal in addition to at least one test instruction word. At least one test instruction word in the sequence of test instruction words corresponds to the same clock signal. The memory of the high-bandwidth memory samples at least one test instruction word in the test instruction word sequence according to the clock sampling edge of the clock signal. For example, in HBM, the test instruction word sequence can include a total of 17 test instruction words (i.e. 17 bytes), with a total of 34 instruction bits. Each test instruction word includes a rising edge instruction word and a falling edge instruction word of 2-bit instructions. Character. For example, the test instruction word R1 includes the R1 rising instruction word and the R1 falling edge instruction word. In some embodiments, the test instruction word is one of a rising edge instruction word or a falling edge instruction word in the instruction word bits.

After the instruction word generation register generates the instruction word test sequence, it transmits the test instruction word sequence to the instruction word sending circuit, so that the test instruction word is transmitted to the memory of the high-bandwidth memory through the instruction word sending circuit. In some embodiments, the memory in high-bandwidth memory refers to high-bandwidth memory dynamic random access memory, abbreviated as HBM DRAM.

It should be noted that the memory in the high-bandwidth memory can also be stacked to improve data transmission. Other types of memory with transmission bandwidth are not limited in the embodiments of this application.

The instruction word sending circuit transmits the test instruction word to the memory, including: transmitting the test instruction word sequence to the memory, or sending individual test instruction words in the test instruction sequence to the memory. For example, this memory refers to high-bandwidth memory memory, such as HBM DRAM. When the instruction word sending circuit sends a test instruction word individually to the memory, the clock signal corresponding to the instruction word sequence needs to be sent to the memory.

Taking HBM DRAM as an example, the process of receiving and processing test instruction words by the memory is introduced.

In some embodiments, HBM DRAM receives the test instruction word sequence in the instruction word sending circuit through a double-edge instruction word receiving circuit, and samples it through the vector analysis circuit of HBM DRAM to obtain a feedback instruction word sequence; where, the feedback instruction word The sequence includes at least one feedback instruction word, and the feedback instruction word has a one-to-one correspondence with the test instruction word. The feedback instruction word can be the same as its corresponding test instruction word, or it can be opposite to its corresponding test instruction word. After parsing the feedback instruction word sequence, the vector analysis circuit transmits the feedback instruction word sequence to the instruction word register of HBM DRAM. In some embodiments, the instruction word register unit may be a MISR unit.

In some embodiments, the HBM DRAM has an instruction word sending circuit capable of sending feedback instruction words. In some embodiments, the instruction word sending circuit for sending the feedback instruction word refers to an interface that sends digital pulses. Optionally, the above instruction word sending circuit can be implemented through the IEEE1500 interface in HBM DRAM.

In some embodiments, HBM Host obtains the feedback instruction word sequence in the instruction word register through the instruction word receiving circuit. For example, at least one feedback instruction word stored in the instruction word register of the HBM DRAM is obtained through the IEEE1500 interface in the HBM Host. Another example is to obtain the storage feedback instruction word sequence in the instruction word register of HBM DRAM through the IEEE1500 interface in HBM Host. Exemplarily, the instruction word receiving circuit in the HBM Host corresponds to the instruction word sending circuit in the HBM DRAM to realize data transmission through the IEEE1500 interface. For example, the feedback instruction word corresponding to the test instruction word can be sent to the IEEE1500 interface in the HBM Host through the IEEE1500 interface in the HBM DRAM, or the feedback instruction word sequence corresponding to the test instruction word sequence can be sent.

In some embodiments, the IEEE 1500 interface in the HBM DRAM sends a feedback instruction word or a sequence of feedback instruction words to the IEEE 1500 interface in the HBM Host in the form of digital pulses. For the pulse corresponding to any feedback instruction word: 0-1 pulse means that the data corresponding to the feedback instruction word is 1, and 1-0 pulse means that the data corresponding to the feedback instruction word is 0.

In the instruction word training phase of the high-bandwidth memory, the memory samples the test instruction word sent by the instruction word sending circuit to obtain the feedback instruction word, and sends the feedback instruction word to the host of the high-bandwidth memory. According to the feedback instruction word and the test instruction word The change between the two determines the alignment between the center of the data window of the test instruction word and the clock sampling edge, and facilitates adjustment of the alignment relationship between the data window of the test instruction word and the clock sampling edge to improve the sampling accuracy of the instruction word.

Optionally, after receiving the feedback instruction word, the instruction word receiving circuit of HBM Host transmits the feedback instruction word to the instruction word training state machine. The instruction word training state machine adjusts the transmission delay of the transmission sub-circuit corresponding to the test instruction word according to the feedback instruction word, and determines the number of delay control units that should be used in the transmission sub-circuit corresponding to the test instruction word.

In some embodiments, the instruction word training state machine determines the change in the number of delay control units that should be used in the transmission sub-circuit corresponding to the test instruction word by feeding back the value of the instruction word, so as to finally determine the transmission sub-circuit corresponding to the test instruction word. The number of delay control units that should be used. For the specific content of this process, please refer to the embodiment below.

To sum up, by sending the test instruction word to the memory of the high-bandwidth memory, and sampling the test instruction word through the memory of the high-bandwidth memory, the feedback instruction word can be obtained more directly according to the change of the sampling result (feedback instruction word) Feedback the change in alignment position between the data window of the test instruction word and the clock sampling edge, in order to determine the number of delay control units that should be used in the transmission sub-circuit corresponding to the test instruction word, and complete the processing of the test instruction word in the transmission sub-circuit. Transmission delay is adjusted. The instruction word training phase performed by the instruction word processing circuit helps to improve the accuracy of the instruction words read by the memory of the high-bandwidth memory during the operation of the high-bandwidth memory.

Next, the process of determining the number of delay control units that the transmission subcircuit should use by the instruction word training state machine is introduced and explained.

In some embodiments, the instruction word training state machine includes: an offset step counting unit and an offset step determining unit; The shift step size counting unit is used to change the number of delay control units put into use in the transmission subcircuit corresponding to the test instruction word; the offset step size determination unit is used to determine the corresponding test instruction word when the feedback instruction word meets the alignment condition. The difference between the number of delay control units currently used in the transmission sub-circuit and the number of delay control units originally used, and based on the difference, determine the delay control unit that should be used by the transmission sub-circuit corresponding to the test instruction word quantity.

The offset step counting unit may refer to a circuit used to adjust the delay control unit used in the transmission sub-circuit. The offset step counting unit can be called a step counter (Step Counter). For example, the offset step counting unit changes the number of delay control units put into use in the transmission sub-circuit corresponding to the test instruction word by controlling the tap interface used in the transmission sub-circuit corresponding to the test instruction word.

For example, the offset step counting unit changes the usage status of a tap interface in the transmission sub-circuit and replaces the tap interface used to take out the test instruction word from the transmission sub-circuit, so as to change the position of the test instruction word in the transmission sub-circuit. The number of delay control units passed through. Assume that the tap interface in the transmission subcircuit has two states: the allowed use state (such as represented by "1") and the prohibited use state (such as represented by "0"). The state of only one tap interface allowed to exist in the transmission subcircuit at the same time is the allowed use state. The offset step counting unit changes the tap interface in the state of "1" in the transmission subcircuit to the state of "0", and changes the state of the tap interface in the transmission subcircuit to "0". The use status of any tap interface other than this tap interface changes to "1", and the replacement of the tap interface in the transmission subcircuit can be completed.

Exemplarily, FIG. 9 is a schematic diagram of an offset step counting unit adjusting the number of delay control units used in a transmission subcircuit provided by an exemplary embodiment of the present application. The offset step counting unit 910 adjusts the number of delay control units put into use in the transmission sub-circuit 920 by changing the tap interface in the transmission sub-circuit 920 for receiving the test instruction word. For example, when transmitting the test instruction word for the i-th time, the transmission subcircuit 920 uses the tap interface 3 to receive the test instruction word. That is to say, before the test instruction word is received from the transmission sub-circuit 920, the test instruction word needs to pass through three delay control units in the transmission sub-circuit 920. If the offset step counting unit 910 instructs the transmission subcircuit 920 to change to use the tap interface 2 to receive the test instruction word, the test instruction word needs to pass through two delay control units in the transmission subcircuit 920, thereby adjusting the test instruction The transmission delay of the word in the transmission sub-circuit 920.

Since every time the test instruction word passes through a delay control unit, its transmission delay in the transmission subcircuit will increase. Through the offset step counting unit, the tap interface used to receive the test instruction word is adjusted to change the transmission subcircuit of the test instruction word. The number of delay control units in the circuit changes the phase of the test instruction word to adjust the transmission delay of the test instruction word in the transmission subcircuit. When there is an offset between the high-level center position of the test instruction word and the clock sampling edge, changing and adjusting the transmission delay of the test instruction word in the transmission subcircuit is equivalent to changing the clock sampling edge in the data window of the test instruction word. the aligned position.

In some embodiments, the offset step counting unit adjusts a fixed amount of change in the number of delay control units used in the transmission subcircuit each time. That is, the offset step counting unit instructs the transmission subcircuit to increase/decrease the used delay control unit by the same amount each time. For example, when it is necessary to reduce the number of delay control units used in the transmission subcircuit, the offset step counting unit instructs each time to reduce the use of one delay control unit in the transmission subcircuit. For another example, when it is necessary to increase the delay control units put into use in the transmission subcircuit, the offset step counting unit instructs two additional delay control units to be used in the transmission subcircuit each time.

When the delay control units and tap interfaces in the transmission subcircuit are arranged in a staggered manner, if the offset step counting unit instructs the transmission subcircuit to increase the use of one delay control unit each time, the offset step counting unit will indicate The test instruction word is taken out from the q+1th tap interface, q is the position of the currently used tap interface, and q is a positive integer to achieve the purpose of increasing the number of delay control units used in the transmission subcircuit.

Through this method, the offset step counting unit instructs the transmission sub-circuit to change the number of delay control units each time. The control transmission sub-circuit only needs to adjust the tap interface for receiving the test instruction word according to the needs, without the need to adjust the offset The number of delay control units controlled by the step counting unit is adjusted, which reduces the adjustment complexity of the delay control unit.

In some embodiments, each time the offset step counting unit adjusts the number of delay control units used in the transmission subcircuit, the change amount is dynamically changed, that is, each time the offset step counting unit adjusts the number of delay control units used in the transmission subcircuit, The amount of variation of the delay control unit is not fixed. Exemplarily, the offset step counting unit adjusts the number of delay control units used in the transmission subcircuit. The amount of change keeps decreasing. For example, the offset step counting unit instructs a certain transmission subcircuit to increase the use of m and n delay control units for the first and second times respectively, where m is greater than n.

In one example, the offset step counting unit uses the dichotomy principle to adjust the variation of the delay control unit used in the transmission subcircuit, that is, the offset step counting unit adjusts the delay control used in the transmission subcircuit each time. The amount of change in the number of units is half of the amount of change in the last time the offset step counting unit adjusted the number of delay control units used in the transmission subcircuit.

Assume that the total number of delay control units included in a certain transmission sub-circuit is 256, of which the number of delay control units to be used is 129, that is, the transmission sub-circuit passes through the 127th delay control unit The adjacent and subsequent tap interface (i.e., the 127th tap interface) receives the test instruction word, which passes through 127 delay control units in the transmission subcircuit. When it is necessary to increase the delay control unit used in the transmission sub-circuit, the offset step counting unit indicates for the first time that the number of delay control units used in the transmission sub-circuit is increased to 64, and for the second time The change amount indicating the number of delay control units used by the transmission sub-circuit is 32, the third time indicating the change amount of the number of delay control units used by the transmission sub-circuit is 16, and so on.

It should be noted that whether the offset step counting unit needs to adjust the number of delay control units used in the transmission subcircuit for the second, third, ...wth time, and the second and third times ,...the wth adjustment of the number of delay control units used in the transmission subcircuit is to increase the number of delay control units or reduce the number of delay control units, depending on the first increase of the transmission subcircuit. After the number of delay control units used in the test instruction word is transmitted again using the transmission subcircuit, the feedback instruction word obtained satisfies the alignment condition. For details on this process, please refer to the embodiment below.

In some embodiments, the alignment condition includes: the feedback instruction word is opposite to the test instruction word. For example, when the test instruction word has a high level, that is, the data signal of the test instruction word is 1, and the data signal of the feedback instruction word is 0, that is, the alignment condition is met. This can intuitively reflect the deviation between the center position of the data window of the instruction word and the clock sampling edge, which reduces the training complexity of the instruction word.

In some embodiments, in the process of not adjusting the delay control unit in the transmission subcircuit corresponding to the feedback instruction word, the data corresponding to the test instruction word generated by the instruction word generation register is 1 (1-beat high level ), the data corresponding to the feedback instruction word is also 1, that is, in the initial state, the memory of the high-bandwidth memory can correctly sample the test instruction word, but there may be a deviation between the center position of the data window of the instruction word and the clock sampling edge. In order to ensure the sampling accuracy of the instruction words, the delay control unit in the transmission subcircuit corresponding to each test instruction word needs to be optimized.

For example, at the beginning of the instruction word training phase, the operating frequency of the clock needs to be adjusted to ensure that when the test instruction word is sent to the memory of the high-bandwidth memory for the first time, the high-bandwidth memory samples the test instruction word according to the clock signal to obtain the correct result. feedback command word. Although at the beginning of the test, there is an offset between the center position of the high-level window of the test instruction word and the clock sampling edge (rising edge), the offset is not enough to cause a timing violation, so the memory of the high-bandwidth memory can The word sampling is correct, and the obtained feedback command word is the same as the test command word (both corresponding values are 1).

In this case, the offset step counting unit needs to adjust the number of delay control units used in the transmission subcircuit corresponding to the feedback instruction word, and adjust the transmission delay of the test instruction word in the transmission subcircuit so that the clock sampling edge Aligned with the edges of the test instruction word's data window to determine the duration of the high level in the test instruction word's data window.

In some embodiments, the edges of the data window of the test instruction word include: a high-level establishment edge and a high-level withdrawal edge. The offset step counting unit needs to adjust the data amount of the delay control unit used in the transmission subcircuit corresponding to the feedback word multiple times to achieve edge alignment between the clock sampling edge and the high level, and to achieve edge alignment between the clock sampling edge and the high level. Undo edge alignment.

Whether the clock sampling edge is aligned with the high-level edge can be reflected by the feedback instruction word. For example, when the clock sampling edge is edge aligned with the high level, the memory cannot correctly sample the test instruction word during the training phase. At this time, if the test instruction word is 1, the feedback instruction word is 0. And because, in the instruction word training phase, it is necessary to ensure that the memory can correctly sample the test instruction word for the first time, that is, the sampled feedback instruction word is 1. Therefore, after adjusting the number of delay control units used in the transmission subcircuit, if the feedback command word is 0, it means that the clock sampling edge has been aligned with the high-level establishment edge.

Referring to the above introduction, when the alignment position of the clock sampling edge and the data window of the instruction word does not meet the setup time or duration, timing violations will occur. That is to say, when the clock sampling edge is internally aligned with the data window of the test instruction word, there will also be a test instruction word sampling error, causing the feedback instruction word to be 0. However, since the test instruction word needs to be aligned with the high-level edge establishment and the test instruction word with the high-level cancellation edge, the deviations caused by timing violations during the two alignment processes can be ignored or offset each other.

In some embodiments, the difference includes a left shift difference and a right shift difference, and the offset step determination unit is used to: determine the left shift difference and the right shift difference respectively; where the left shift difference refers to the feedback When the instruction word meets the alignment condition, the number of delay control units used in the transmission subcircuit corresponding to the test instruction word is reduced; the right shift difference means that when the feedback instruction word meets the alignment condition, the test instruction word corresponds to Increase the number of delay control units used in the transmission subcircuit; determine the number of delay control units that should be used in the transmission subcircuit corresponding to the test instruction word based on the left shift difference and right shift difference.

Among them, the right shift difference refers to the change amount of the delay control unit used in the transmission subcircuit when the clock sampling edge is aligned with the high-level establishment edge of the test instruction word. Since at the beginning of the instruction word training phase, it is ensured that the memory can correctly sample the test instruction word, that is, the clock sampling edge is aligned with the position within the data window of the test instruction word. Aligning the clock sampling edge with the high level of the test instruction word is equivalent to moving the data window of the test instruction word to the right. This shows that the occurrence time of the data window of the test instruction word is delayed, that is, the transmission delay of the test instruction word in the transmission subcircuit increases, and the number of delay control units put into use in the transmission subcircuit increases.

The left shift difference refers to the change in the delay control unit used in the transmission subcircuit when the clock sampling edge is aligned with the high-level withdrawal edge of the test command word. Since at the beginning of the instruction word training phase, it is ensured that the memory can correctly sample the test instruction word, that is, the clock sampling edge is aligned with the position within the data window of the test instruction word. Aligning the clock sampling edge with the high-level cancel edge of the test instruction word is equivalent to moving the data window of the test instruction word to the left. This shows that the occurrence time of the data window of the test instruction word is advanced, that is, the transmission delay of the test instruction word in the transmission sub-circuit is reduced, and the number of delay control units put into use in the transmission sub-circuit is reduced.

Taking the determination of the right shift difference as an example, the working process of the instruction word adjustment circuit is introduced. In the process of controlling the right shift of the data window of the test instruction word, it may be necessary one or more times to align the clock sampling edge with the high-level cancellation edge of the test instruction word. In the case of only one right shift, the corresponding increase in the delay control unit is determined as the right shift difference corresponding to the test instruction word; in the case of multiple right shifts, the multiple right shifts are The sum of the increasing numbers of the corresponding delay control units is determined as the right shift difference corresponding to the test instruction word.

For example, after the instruction word training state machine receives the feedback instruction word 1, if the feedback instruction word 1 does not meet the alignment condition, the offset step counting unit indicates the transmission subcircuit corresponding to the feedback instruction word 1, and additionally uses a1 Delay control unit, a1 is a positive integer. The value corresponding to the current right shift difference is a1. For example, the transmission subcircuit increases the number of delay control units used in the transmission subcircuit by adjusting the tap interface used to receive the test instruction word. Optionally, the step counting unit can change the number of delay control units used in the transmission subcircuit according to a fixed step size, or can adjust the number of delay control units used in the transmission subcircuit according to a dynamically changing step size. Please refer to the above embodiment for the specific process, which will not be described in detail here.

After the offset step counting unit increases the number of delay control units used in the transmission subcircuit, the instruction word training state machine indicates to the instruction word generation register and sends the test instruction word to the transmission subcircuit again, and the transmission subcircuit will test the instruction word Send to storage the second time. Since the number of delay control units put into use in the transmission subcircuit changes at this time, the number of delay control units that the test instruction word passes through in the transmission subcircuit changes, and the phase of the test instruction word changes, causing the clock sampling The alignment of the edge with the data window of the test instruction word changes.

The memory samples the test instruction word whose phase has changed, obtains the feedback instruction word 2, and sends the feedback instruction word 2 to the instruction word receiving circuit. The feedback instruction word 2 is sent to the instruction word training state machine through the instruction word receiving circuit.

The instruction word training state machine determines whether the feedback instruction word 2 meets the alignment condition. Assuming that feedback instruction word 2 does not meet the alignment condition (that is, the value corresponding to feedback instruction word 2 is 1), the offset step counting unit indicates the transmission subcircuit corresponding to feedback instruction word 2, and a2 delay control units are added, a2 is a positive integer. The value corresponding to the current right shift difference is a1+a2.

Subsequently, the instruction word training state machine instructs the instruction word generation register to send the test instruction word again, and executes the test instruction word The process of sending the command word to the memory and obtaining the feedback command word sent by the memory. The command word state training machine receives the feedback command word 3 obtained by sampling the test command word from the memory this time. After obtaining the feedback instruction word 3, it is judged whether the instruction word 3 meets the alignment condition. Assuming that the feedback instruction word 3 does not meet the alignment condition (that is, the value corresponding to the feedback instruction word 3 is 1), the feedback instruction is indicated through the offset step counting unit. In the word corresponding transmission sub-circuit, a3 delay control units are added. The value corresponding to the current right shift difference is a1+a2+a3. Repeat the steps in which the instruction word training state machine instructs the instruction word generation register to send the test instruction word to the instruction word sending circuit until the feedback instruction word meets the alignment condition (that is, the value corresponding to the feedback instruction word is 0).

In some embodiments, the offset step counting unit adjusts the number of delay control units used in the transmission subcircuit according to the same step size each time. That is, in the above embodiment: a1=a2=a3=ai, where i is the delay control used by the offset step counting unit in the transmission subcircuit corresponding to the feedback instruction word when the feedback instruction word meets the alignment condition The number of times the number of units is adjusted, where i is a positive integer.

In other embodiments, the offset step counting unit adjusts the number of delay control units used in the transmission subcircuit according to steps that are not exactly the same each time. That is, in the above embodiment, a1, a2, a3... are not completely equal. In this case, the resulting right shift difference may exceed the right shift difference if the clock sampling edge is aligned with the high-level cancel edge of the test instruction word (that is, the pointer sampling edge exceeds the data window, and the feedback instruction word is also satisfy the alignment condition), therefore when the feedback instruction word satisfies the alignment condition, the offset step counting unit again adjusts the delay control unit used in the transmission subcircuit corresponding to the feedback instruction word to ensure that the clock sampling edge is aligned with the The high level of the test instruction word cancels the right shift difference under edge alignment, so that the optimal right shift difference can be obtained, thereby improving the training accuracy of the instruction word.

Illustratively, taking the process of determining the right shift difference as an example, when the feedback instruction word satisfies the alignment condition, the offset step counting unit instructs the transmission subcircuit to: reduce the number of delay control units used.

For example, after the offset step counting unit indicates that b1 delay control units are added to the transmission subcircuit, the feedback instruction word sent by the memory meets the alignment condition. The offset step counting unit instructs the transmission subcircuit to reduce the use of b2 delay control units. The purpose of the above process is to determine the minimum number of changes in the delay control unit used in the transmission subcircuit, which can cause sampling errors in the memory's sampling of the test instruction word, that is, the feedback instruction word is 0. If the difference is shifted right, it can be b1-b2.

In some embodiments, the offset step determination unit determines the right shift difference, including: obtaining the first number of delay control units used in the transmission subcircuit corresponding to the feedback instruction word when the feedback instruction word meets the alignment condition ; Obtain the second number of delay control units used in the transmission subcircuit corresponding to the feedback instruction word in the initial stage of instruction word training; calculate the difference between the first number and the second number, and determine the right shift difference.

Optionally, in the initial stage of instruction word training, at least one delay control unit is used in the transmission subcircuit corresponding to each test instruction word. For example, if the total number of delay control units in the transmission subcircuit is A, then the number of delay control units originally used in the transmission subcircuit is not less than 1 and not more than A.

Since the left shift difference and the right shift difference need to be determined in the process of determining the delay control unit that should be used in the transmission subcircuit, the number of delay control units originally used in the transmission subcircuit can be set to Half of the total number of delay control units in order to facilitate the increase or decrease of the number of delay control units that the test instruction words pass through in the transmission sub-circuit, so as to increase or decrease the phase of the test instruction words.

For example, if a certain transmission subcircuit includes 256 delay control units, the original number of delay control units used in the transmission subcircuit is 128.

In other embodiments, the offset step size determination unit determines the right shift difference, including: before obtaining the feedback instruction word to meet the alignment condition, the offset step size calculation unit adjusts the delay control unit used in the transmission subcircuit each time. Quantity; when the feedback instruction word meets the alignment condition, the statistical result is used as the right shift difference.

For example, before the feedback instruction word meets the alignment condition, the offset step counting unit adjusts the number of delay control units used in the transmission subcircuit a total of three times, as follows: the first time the transmission subcircuit increases the delay used The number of time control units is 5, the number of delay control units used for the second increase is 5, and the number of delay control units used for the third time is reduced to 2, then the right shift difference is 8 (5 +5-2).

In the above example, the reason why the delay control unit used in the transmission sub-circuit is reduced for the third time is that the second offset step counting unit adjusts the change of the delay control unit used in the transmission sub-circuit by greater than 1 (increased by 5 ), assuming that the additional use of 8 delay control units in the transmission subcircuit can establish edge alignment between the clock sampling edge and the data window of the test instruction subcircuit, then the additional use of 10 delay control units means that the value corresponding to the feedback instruction word will be certain is 0, but only fewer delay control units are needed to obtain the value of the feedback command word as 0. In order to avoid reducing the error, it is necessary to reduce the number of delay control units used, and determine the minimum delay control unit change amount when a sampling error occurs in the test instruction word as the right shift difference.

After the right shift difference is determined, the transmission subcircuit is reset, that is, the number of delay control units that the test instruction word passes through in the transmission subcircuit is the number of delay control units originally used. In some embodiments, the instruction word training state machine is used to instruct the transmission subcircuit corresponding to the feedback instruction word to restore the original number of delay control units used. For example, the transmission subcircuit is instructed to use the initial tap interface to receive the test instruction word through the offset step counting unit.

After resetting the transmission subcircuit, the process of determining the left shift difference begins. The determination process of the left shift difference is similar to the determination process of the right shift difference. By whether the feedback instruction word meets the alignment condition, it is determined whether it is necessary to continue to reduce the number of delay control units used in the transmission subcircuit corresponding to the feedback instruction word, so as to Reduce the phase of the test instruction word so that the cancel edge of the data window of the test instruction word is aligned with the clock sampling edge. Please refer to the above embodiment for the specific content of this process, which will not be described again here.

It should be noted that there is no sequence between determining the left shift difference and determining the right shift difference. You can determine the left shift difference and then determine the right shift difference, or you can first determine the right shift difference and then Determine the left shift difference.

Exemplarily, FIG. 10 is a schematic diagram of the left shift difference and right shift difference determination process provided by an exemplary embodiment of the present application. In Figure 10, for the test instruction word 1001 transmitted in the transmission subcircuit, the test instruction word 1001 in the initial phase is adjusted to the test instruction word 1001 in phase 1 (increasing the delay control unit used in the transmission subcircuit quantity), so that the establishment edge of the data window of the test instruction word 1001 is aligned with the clock sampling edge. At this time, the right shift difference can be represented by R_CNT. Reset the test instruction word 1001 under phase 1 to obtain the test instruction word 1001 under the initial phase, and then adjust the test instruction word 1001 under the initial phase to the test instruction word 1001 under phase 2 (to reduce the use in the transmission subcircuit (the number of delay control units) so that the withdrawal edge of the data window is aligned with the clock sampling edge. At this time, the left shift difference can be represented by L_CNT. It can be seen from Figure 10 that the sum of R_CNT and L_CNT is equal to the duration of the high level in the data window of the test instruction word.

After determining the left shift difference and right shift difference, the offset step determination unit can determine the number of delay control units that should be used in the transmission subcircuit corresponding to the feedback instruction word based on the left shift difference and right shift difference. . The number of delay control units that should be used refers to the number of delay control units used in the transmission subcircuit corresponding to the feedback instruction word when the test instruction word can be correctly sampled by the memory. This improves the sampling accuracy of the instruction word. sex.

In some embodiments, the offset step determination unit is configured to: calculate a first alignment amount based on the left shift difference value and the right shift difference value; wherein the first alignment amount is used to characterize the high voltage of the transmission signal of the test instruction word. Half of the flat duration; determine the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word based on the number of delay control units originally used and the first alignment amount.

For example, the first alignment amount=(right shift difference value+left shift difference value)*0.5. The first alignment amount can be understood as the number of delay control units corresponding to half of the high-level duration in the data window called the test instruction word.

The number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word is calculated by the originally used number of delay control units and the first alignment amount.

For example, for the number of delay control units originally used in the transmission subcircuit - shift the difference left to obtain the edge alignment amount. When the delay control unit with this edge alignment amount is used in the transmission subcircuit, the data window of the instruction word is tested. The setup edge of can be aligned with the clock sampling edge. Subsequently, only the delay control unit of the first alignment amount needs to be added to the transmission sub-circuit to align the center position of the data window of the test instruction word with the clock sampling edge, that is, the delay that should be used by the transmission sub-circuit corresponding to the test instruction word. The number of time control units T = the original number of delay control units used + 0.5* (right shift difference - left shift difference).

In this way, by adjusting the tap interface used to receive the test command word, so that before the tap interface receives the test command word from the transmission sub-circuit, the number of delay control units that the test command word passes through is T, which can ensure the accuracy of the test command word. data window The center position is aligned with the clock sampling edge to ensure the sampling accuracy of the instruction word.

In some embodiments, the word processing circuit is instructed to perform the above alignment process on all transmission sub-circuits respectively. In some embodiments, the above process may be called a single-step byte training (Per bit training) phase.

For example, Figure 11 is a schematic diagram of a single-step byte training stage provided by an exemplary embodiment of the present application. Among them, the center position of the data window corresponding to byte 1101 of the instruction word, byte 1102 of the instruction word, ..., and byte j of the instruction word respectively is aligned with the clock sampling edge 1; byte i of the instruction word corresponds to The center position of the data window is aligned with clock sampling edge 2 so that each test instruction word is sampled correctly.

In the independent byte training phase of the instruction word training phase, by determining the number of delay control units that should be used in each transmission subcircuit, the center position of the data window of each test instruction word can be aligned with the clock sampling edge, so that The offset from the clock signal is corrected to ensure that the instruction words transmitted in each transmission sub-circuit can be sampled correctly.

In some embodiments, in addition to being controlled by the instruction word processing circuit, the single-step byte training phase can also be executed by program product control, for example, using the program product to configure the offset step calculation unit each time the transmission subcircuit is changed. The variation in the number of delay control units used in the program product is used to instruct the host to send a feedback instruction word transmission instruction to the memory, so that the memory sends a feedback instruction word or a sequence of feedback instruction words to the host.

Optionally, after completing the single-step byte training phase, some transmission sub-circuits can also be adjusted so that the high-level center positions of the data windows of multiple test instruction words are aligned with the same clock sampling edge to reduce instruction The duration of transmission resources occupied during word transmission reduces data transmission pressure. This stage can also be called the single-step segment training stage (Per Slice training).

In some embodiments, the offset step size determination unit is also used to: determine the delay control unit that should be used by the transmission sub-circuit corresponding to the test instruction word based on the number of originally used delay control units and the first alignment amount. After the number, calculate the second alignment amount according to the left shift difference value and the right shift difference value; wherein, the second alignment amount is used to characterize the high-level duration of the transmission signal of the test instruction word; use the second alignment amount to The transmission subcircuit corresponding to the word should be adjusted using the number of delay control units.

Optionally, the second alignment amount=left shift difference value+right shift difference value. In the single-step segment training phase, the instruction word generation sequence generates a test instruction word sequence, and the test instruction word sequence is transmitted to the transmission subcircuit. The transmission subcircuit receives the test instruction word sequence and tests each test instruction word in the test word sequence, and sends it to the memory (such as HBM DRAM) using the corresponding transmission subcircuit. The memory samples all test instruction words in the test instruction word sequence within one clock cycle, generates a feedback instruction word sequence, and transmits the feedback instruction word sequence to the instruction word receiving circuit, which sends the feedback instruction word sequence Train the state machine for the instruction words.

The instruction word training state machine determines whether the feedback instruction word sequence satisfies the second alignment condition. In some embodiments, the second alignment condition means that the value of all feedback instruction words in the feedback instruction word sequence is 1.

When the feedback instruction word sequence satisfies the second alignment condition, it means that the center position of the data window of each test instruction word is aligned with the same clock sampling edge. When the feedback instruction word sequence does not meet the second alignment condition, adjust the number of delay control units used in the target transmission sub-circuit whose value of the feedback instruction word is 0, so as to ensure the transmission of the transmission sub-circuit corresponding to the test instruction word. The delay is the same as the transmission delay of the transmission subcircuit corresponding to at least one other test instruction word.

In some embodiments, adjusting the number of delay control units used in the target transmission subcircuit includes:

Reduce or increase the delay control unit using the second alignment amount in the target transmission subcircuit, and repeat the step of sending the test instruction word sequence to the memory until the feedback instruction word sequence satisfies the second alignment condition.

Exemplarily, FIG. 12 is a schematic diagram of a single-step segment training stage provided by an exemplary embodiment of the present application. In Figure 12, by adjusting the test instruction word 1202 from phase 1 to phase 2 (that is, reducing the number of delay control units used in the transmission sub-circuit corresponding to the test instruction word 1202 (left shift difference + right shift difference) ), so that the test instruction word 1201 and the test instruction word 1202 in phase 2 are aligned with the same clock sampling edge.

In some embodiments, the instruction word processing circuit further includes: a clock phase-locked loop register, which is used to adjust the frequency of the clock signal of the memory.

Change the operating frequency of the high-bandwidth memory by adjusting the clock phase-locked loop register, that is, adjusting the memory to test the instruction word The frequency of the clock signal that is sampled. In some embodiments, the operating frequency of the high-bandwidth memory is 1.8Ghz. The higher the operating frequency of the high-bandwidth memory, the shorter the data window corresponding to the test instruction word. And because the signal conversion process from low level to high level takes time, the conversion from high level to low level also takes time, which makes the high level maintain stable duration lower than the length of the data window. In this case, a slight offset between the clock sampling edge and the high-voltage midpoint of the data window in the test command word will cause an error in the sampling of the test command word. Reducing the operating frequency of high-bandwidth memory through the clock phase-locked loop register helps enable the test instruction words to be sampled correctly.

In some embodiments, when performing the instruction word test phase of the high-bandwidth memory, the clock phase-locked loop register is required to control the operating frequency of the high-bandwidth memory (also called the operating frequency of the clock) below the test frequency. The test frequency refers to It can ensure that any test instruction word can be sampled at the correct working frequency, that is, under the test frequency, the memory can sample correctly when it samples any test instruction word for the first time, that is, the data corresponding to the test instruction word is 1. The data corresponding to the feedback command word is also 1. Among them, the test frequency refers to the clock operating frequency that enables each test instruction word to be correctly sampled by the memory. In some embodiments, the test frequency is process data obtained through experimental testing.

For example, under the 12nm chip manufacturing process, the instruction word processing circuit was tape-out to obtain a high-bandwidth memory. During the test of the high-bandwidth memory, it was found that the operating frequency of the high-bandwidth memory was 300MHz. In either case, any test instruction word can be sampled correctly by the memory. In this case, during the test of high-bandwidth memory, the operating frequency of the high-bandwidth memory chip can be adjusted to 300MHz through the clock phase-locked loop register.

In some cases, for a certain test frequency, there is at least one test instruction word that cannot be sampled correctly. That is, if at least one test instruction word is sampled for the first time and the data corresponding to the feedback instruction word is 0, then you need to pass The clock phase-locked loop register continues to reduce the operating frequency of the clock until all test instruction words are sampled for the first time and the data corresponding to the feedback instruction words are all 1.

By adjusting the operating frequency of the clock during the instruction word test phase, the duration of the high level in the data window of the test instruction word is extended, and the difficulty of aligning the sampling edge of the clock signal with the center position of the high level in the data window of the test instruction word is reduced. , so that the instruction word training phase can be completed quickly, and at the same time, it helps to improve the accuracy of instruction word sampling during the working process of high-bandwidth memory.

In some embodiments, after determining the delay control unit that should be used in each transmission subcircuit, the clock operating frequency may change during the operation of the high-bandwidth memory. For example, if the clock operating frequency is increased to 1.5GHz, at this clock operating frequency, the clock sampling edge may again deviate from the high/low level center of the data window of the instruction word, resulting in possible errors in the sampling of the instruction word. In this case, the operating frequency used during the operation can be used to perform the instruction word training process of the high-bandwidth memory again. For the adjustment process of the transmission delay of the instruction word in the transmission subcircuit, please refer to the above embodiment. This will not be described in detail.

Because at the test frequency, the number of delay control units used in the transmission subpath has been adjusted through the test instruction word, so that the transmission delay of each instruction word in the corresponding transmission subpath can meet the data window of the instruction word. The center position remains aligned with the clock sampling edge. Therefore, at the operating frequency, the offset between the clock sampling edge and the center position of the data window of the instruction word will not be too large, so at the operating frequency, it is easy to adjust the number of delay control units that should be used in the transmission subcircuit. .

In some embodiments, the instruction word processing circuit further includes a training instruction receiving unit, which is configured to receive a training instruction. The training instruction is used to instruct the instruction word processing circuit to start an instruction word training process.

In some embodiments, when the operating environment of the high-bandwidth memory exceeds a threshold, the detection unit on the substrate of the high-bandwidth memory sends a training instruction to the instruction word processing circuit. Optionally, the working environment of high-bandwidth memory includes: process, voltage, temperature, etc.

Through the above method, when the working environment of the high-bandwidth memory changes, re-training the instruction words of the high-bandwidth memory can avoid the deviation of the instruction words in the working phase due to changes in the working environment, resulting in the memory's distortion of the instruction words. Sampling error.

In some embodiments, the instruction word processing circuit includes a cycle control unit; wherein the cycle control unit is used to In the training cycle, the instruction word training phase is performed on the high-bandwidth memory to avoid sampling errors caused by offsets in the instruction words during the working phase of the high-bandwidth memory.

After completing the instruction word training, during the operation of the high-bandwidth memory, the number of delay control units used by each transmission sub-circuit in the instruction word sending circuit is the number of delay control units that should be used in the transmission sub-circuit determined in the instruction word training stage. The number of delay control units allows the center position of the data window of each instruction word to be aligned with the clock sampling edge during the working phase. Furthermore, the center position of these data windows is aligned with the same clock sampling edge, which helps Each instruction word can be sampled correctly.

An exemplary embodiment of the present application provides a chip, which includes a memory and the instruction word processing circuit introduced in the above embodiment.

In some embodiments, the instruction word processing circuit is provided in the host module of the chip, and the host module is used to instruct the memory to perform corresponding operations, such as instructing the memory through instruction words. In some embodiments, the chip further includes a substrate, and inductive sensors, such as temperature sensors and voltage sensors, are provided in the substrate to instruct the host module to perform instruction word training when the operating temperature and operating voltage of the chip change.

In some embodiments, the chip is also provided with an adjustment register. The adjustment register is used to connect with the computer program product and receive instructions from the computer program product to adjust the instruction word training phase. For example, adjust the execution time of the instruction word training phase, adjust the offset step adjustment unit, change the number of delay control units used by the transmission subcircuit, etc.

In some embodiments, the chip may be a high-bandwidth memory chip or other chips in which the clock sampling edge is easily offset from the center position of the data window of the instruction word, which is not limited in the embodiments of the present application. In the above embodiments, only high-bandwidth memory chips are used as examples to introduce the instruction word processing circuit. This does not limit the instruction word processing circuit to only be applied to high-bandwidth memory chips.

The following are method embodiments of the present application. For details not disclosed in the method embodiments of the present application, please refer to the embodiments of the instruction word processing circuit of the present application.

Please refer to Figure 13, which is a flow chart of an instruction word processing method provided by an exemplary embodiment of the present application. For example, the execution subject of this method may be the host 600 of the high-bandwidth memory chip shown in FIG. 6 .

An exemplary embodiment of the present application provides an instruction word processing method. The method is applied in an instruction word processing circuit. The instruction word processing circuit includes an instruction word generation register, an instruction word sending circuit, an instruction word receiving circuit and an instruction word processing circuit. Word training state machine; as shown in Figure 13, this method may include the following steps (1310~1340):

Step 1310: The instruction word generation register generates a test instruction word sequence; wherein the test instruction word sequence includes at least one test instruction word.

Step 1320: The instruction word sending circuit sends the test instruction word to the memory.

Step 1330: The instruction word receiving circuit receives the feedback instruction word corresponding to the test instruction word sent by the memory, and sends the feedback instruction word to the instruction word training state machine. The feedback instruction word is generated by the The memory samples the test instruction word according to the clock signal.

Step 1340: The instruction word training state machine adjusts the transmission delay of the transmission sub-circuit corresponding to the test instruction word according to the feedback instruction word, and determines the delay that should be used by the transmission sub-circuit corresponding to the test instruction word. number of control units.

In some embodiments, the instruction word training state machine includes: an offset step counting unit and an offset step determination unit; the instruction word training state machine performs the test instruction word according to the feedback instruction word. The transmission delay of the corresponding transmission sub-circuit is adjusted to determine the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word, including: the offset step counting unit changes the corresponding value of the test instruction word The number of delay control units put into use in the transmission sub-circuit; the offset step determination unit determines the current used in the transmission sub-circuit corresponding to the test instruction word when the feedback instruction word meets the alignment condition The difference between the number of delay control units and the number of originally used delay control units, and based on the difference, determine the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word.

In some embodiments, the difference includes a left shift difference and a right shift difference; the offset step determination unit determines the offset step size corresponding to the test instruction word when the feedback instruction word satisfies the alignment condition. The difference between the number of delay control units currently used in the transmission sub-circuit and the number of delay control units originally used, and based on the difference, determine the delay that should be used by the transmission sub-circuit corresponding to the test instruction word. The number of time control units includes: the offset step determination unit determines the left shift difference and the right shift difference respectively when the feedback instruction word meets the alignment condition; wherein, the left shift difference The shift difference value refers to the reduction in the number of delay control units used in the transmission sub-circuit corresponding to the test instruction word when the feedback instruction word satisfies the alignment condition. The right shift difference value refers to the When the feedback instruction word satisfies the alignment condition, the number of delay control units used in the transmission subcircuit corresponding to the test instruction word is increased; the offset step determination unit is based on the left shift difference and the right shift difference to determine the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word.

In some embodiments, the offset step size determination unit determines the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word based on the left shift difference value and the right shift difference value, The method includes: the offset step determination unit calculating a first alignment amount according to the left shift difference value and the right shift difference value; wherein the first alignment amount is used to characterize the transmission signal of the test instruction word half of the duration of the high level; the offset step determination unit determines that the transmission sub-circuit corresponding to the test instruction word should be based on the number of originally used delay control units and the first alignment amount. The number of delay control units used.

In some embodiments, the offset step size determination unit determines the delay that should be used by the transmission sub-circuit corresponding to the test instruction word based on the number of originally used delay control units and the first alignment amount. After controlling the number of units, the second alignment amount is calculated according to the left shift difference value and the right shift difference value; wherein the second alignment amount is used to characterize the transmission signal of the test instruction word. The duration of the high level; the offset step determination unit uses the second alignment amount to adjust the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word.

In some embodiments, the method further includes: a sequence generation instruction unit in the instruction word training state machine, instructing the instruction word generation register to send the instruction word to the sequence generation register when the feedback instruction word does not satisfy the alignment condition. The instruction word sending circuit resends the test instruction word.

It should be noted that the method provided by the above embodiments belongs to the same concept as the embodiment of the instruction word processing circuit. For details of its implementation process, please refer to the embodiment of the instruction word processing circuit, which will not be described again here. For the beneficial effects of the above method embodiments, please refer to the description of the instruction word processing circuit embodiment, which will not be described again here.

Embodiments of the present application also provide a computer-readable storage medium, which stores a computer program. The computer program is loaded and executed by a processor to implement the instruction word processing method provided by the above method embodiments.

The computer-readable media may include computer storage media and communication media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media include RAM (Random Access Memory), ROM (Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory, flash memory or other solid-state storage technology, CD-ROM, DVD (Digital Video Disc, high-density digital video disc) or other optical storage, tape cassette, magnetic tape , disk storage or other magnetic storage devices. Of course, those skilled in the art will know that the computer storage medium is not limited to the above types.

Embodiments of the present application also provide a computer program product. The computer program product includes a computer program. The computer program is stored in a computer-readable storage medium. The processor reads and executes the computer program from the computer-readable storage medium. Computer program to implement the instruction word processing method provided by each of the above method embodiments.

It should be noted that the information (including but not limited to subject device information, subject personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application, All are authorized by the subject or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the laws and regulations of relevant countries and regions. Relevant laws, regulations and standards. For example, the instruction words, instruction word processing circuits, etc. involved in this application were obtained with full authorization.

It should be understood that "plurality" mentioned in this article means two or more. "And/or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the related objects are in an "or" relationship.

The above are only optional embodiments of this application and are not intended to limit this application. Any modifications, equivalent switches, improvements, etc. made within the spirit and principles of this application shall be included in the protection of this application. within the range.

Claims (20)

1. An instruction word processing circuit, the instruction word processing circuit includes: an instruction word generation register, an instruction word sending circuit, an instruction word receiving circuit and an instruction word training state machine;

   The instruction word generation register is electrically connected to the instruction word sending circuit;

   The instruction word training state machine is electrically connected to the instruction word generation register, the instruction word sending circuit and the instruction word receiving circuit respectively;

   The instruction word sending circuit includes a plurality of delay control units, and the delay control units are used to adjust the transmission delay of the instruction word in the instruction word sending circuit.
2. The instruction word processing circuit according to claim 1, wherein the instruction word sending circuit includes at least one transmission sub-circuit corresponding to the instruction word, and each transmission sub-circuit includes more than one of the delay control units.
3. The instruction word processing circuit according to claim 2, wherein the delay control unit includes n inverters, the inverters are used to change the phase of the instruction word transmitted in the transmission sub-circuit, the n is a positive integer.
4. The instruction word processing circuit according to claim 2, wherein the transmission subcircuit includes at least one tap interface, and the tap interface and the delay control unit are staggered in proportion; wherein the tap interface is used for The test instruction word transmitted in the transmission sub-circuit is received so as to transmit the test instruction word to the memory.
5. The instruction word processing circuit according to claim 2, wherein,

   The instruction word generation register is used to generate a test instruction word sequence; wherein the test instruction word sequence includes at least one test instruction word;

   The instruction word sending circuit is used to send the test instruction word to the memory;

   The instruction word receiving circuit is used to receive the feedback instruction word corresponding to the test instruction word sent by the memory, and send the feedback instruction word to the instruction word training state machine. The feedback instruction word is generated by the The memory samples the test instruction word according to the clock signal;

   The instruction word training state machine is used to adjust the transmission delay of the transmission sub-circuit corresponding to the test instruction word according to the feedback instruction word, and determine the delay that should be used by the transmission sub-circuit corresponding to the test instruction word. Number of control units.
6. The instruction word processing circuit according to claim 5, wherein the instruction word training state machine includes: an offset step counting unit and an offset step determining unit;

   The offset step counting unit is used to change the number of delay control units put into use in the transmission sub-circuit corresponding to the test instruction word;

   The offset step determination unit is used to determine the number of delay control units currently used in the transmission sub-circuit corresponding to the test instruction word when the feedback instruction word meets the alignment condition, and the number of delay control units originally used. The difference between the number of time control units, and the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word is determined based on the difference.
7. The instruction word processing circuit according to claim 6, wherein the difference value includes a left shift difference value and a right shift difference value, and the offset step size determination unit is used for:

   Determine the left shift difference and the right shift difference respectively; wherein, the left shift difference refers to the transmission subunit corresponding to the test instruction word when the feedback instruction word satisfies the alignment condition. The number of delay control units used in the circuit is reduced; the right shift difference refers to the increase in the delay used in the transmission subcircuit corresponding to the test instruction word when the feedback instruction word satisfies the alignment condition. the number of time control units;

   According to the left shift difference value and the right shift difference value, the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word is determined.
8. The instruction word processing circuit according to claim 7, wherein the offset step size determination unit is used for:

   Calculate a first alignment amount according to the left shift difference value and the right shift difference value; wherein the first alignment amount is used to characterize half of the high level duration of the transmission signal of the test instruction word;

   The number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word is determined based on the originally used number of delay control units and the first alignment amount.
9. The instruction word processing circuit according to claim 8, wherein the offset step size determination unit is also used for:

   After determining the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word based on the number of originally used delay control units and the first alignment amount, according to the left shift difference value and the right shift difference value to calculate a second alignment amount; wherein the second alignment amount is used to characterize the high level duration of the transmission signal of the test instruction word;

   The second alignment amount is used to adjust the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word.
10. The instruction word processing circuit of claim 6, wherein the alignment condition includes the feedback instruction word being opposite to the test instruction word.
11. The instruction word processing circuit according to claim 6, wherein the offset step counting unit is used to control the tap interface used in the transmission subcircuit corresponding to the test instruction word, and change the transmission corresponding to the test instruction word. The number of delay control units in use in the subcircuit.
12. The instruction word processing circuit according to claim 6, wherein the instruction word training state machine further includes:

    A sequence generation instruction unit, configured to instruct the instruction word generation register to resend the test instruction word to the instruction word sending circuit when the feedback instruction word does not satisfy the alignment condition.
13. The instruction word processing circuit according to claim 1, wherein the instruction word processing circuit further includes:

    The clock phase-locked loop register is used to adjust the frequency of the memory clock signal.
14. A chip, which includes a memory and an instruction word processing circuit according to any one of claims 1 to 13.
15. An instruction word processing method, the method is applied in an instruction word processing circuit, the instruction word processing circuit includes an instruction word generation register, an instruction word sending circuit, an instruction word receiving circuit and an instruction word training state machine; the method includes :

    The instruction word generation register generates a test instruction word sequence; wherein the test instruction word sequence includes at least one test instruction word;

    The instruction word sending circuit sends the test instruction word to the memory;

    The instruction word receiving circuit receives the feedback instruction word corresponding to the test instruction word sent by the memory, and sends the feedback instruction word to the instruction word training state machine. The feedback instruction word is generated by the memory according to The clock signal is obtained by sampling the test instruction word;

    The instruction word training state machine adjusts the transmission delay of the transmission sub-circuit corresponding to the test instruction word according to the feedback instruction word, and determines the delay control unit that should be used by the transmission sub-circuit corresponding to the test instruction word. quantity.
16. The method according to claim 15, wherein the instruction word training state machine includes: an offset step counting unit and offset step size determination unit;

    The instruction word training state machine adjusts the transmission delay of the transmission sub-circuit corresponding to the test instruction word according to the feedback instruction word, and determines the delay control unit that should be used by the transmission sub-circuit corresponding to the test instruction word. Quantity, including:

    The offset step counting unit changes the number of delay control units put into use in the transmission sub-circuit corresponding to the test instruction word;

    When the feedback instruction word satisfies the alignment condition, the offset step determination unit determines the number of delay control units currently used in the transmission sub-circuit corresponding to the test instruction word and the originally used delay control unit. The difference between the numbers, and the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word is determined based on the difference.
17. The method of claim 16, wherein the difference includes a left shift difference and a right shift difference;

    When the feedback instruction word satisfies the alignment condition, the offset step determination unit determines the number of delay control units currently used in the transmission sub-circuit corresponding to the test instruction word and the originally used delay control unit. The difference between the numbers, and determine the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word based on the difference, including:

    The offset step size determination unit determines the left shift difference value and the right shift difference value respectively when the feedback instruction word meets the alignment condition; wherein the left shift difference value refers to the left shift difference value when the feedback instruction word satisfies the alignment condition. When the feedback instruction word satisfies the alignment condition, the number of delay control units used in the transmission subcircuit corresponding to the test instruction word is reduced; the right shift difference means that when the feedback instruction word satisfies the In the case of alignment conditions, increase the number of delay control units used in the transmission subcircuit corresponding to the test instruction word;

    The offset step size determination unit determines the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word based on the left shift difference value and the right shift difference value.
18. The method according to claim 17, wherein the offset step size determination unit determines the delay that should be used by the transmission sub-circuit corresponding to the test instruction word based on the left shift difference value and the right shift difference value. Number of control units, including:

    The offset step determination unit calculates a first alignment amount based on the left shift difference value and the right shift difference value; wherein the first alignment amount is used to characterize the high level of the transmission signal of the test instruction word. Half the level duration;

    The offset step size determination unit determines the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word based on the number of originally used delay control units and the first alignment amount.
19. The method of claim 18, wherein the method further includes:

    The offset step size determination unit determines the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word based on the number of originally used delay control units and the first alignment amount. After that, the second alignment amount is calculated according to the left shift difference value and the right shift difference value; wherein the second alignment amount is used to characterize the duration of the high level of the transmission signal of the test instruction word. ;

    The offset step size determination unit uses the second alignment amount to adjust the number of delay control units that should be used by the transmission sub-circuit corresponding to the test instruction word.
20. The method according to claim 16, wherein the instruction word training state machine further includes a sequence generation instruction unit, the method further includes:

    The sequence generation instruction unit instructs the instruction word generation register to resend the test instruction word to the instruction word sending circuit when the feedback instruction word does not satisfy the alignment condition.