CN115113686A

CN115113686A - Timing adjustment method and device, storage medium and electronic equipment

Info

Publication number: CN115113686A
Application number: CN202210439634.1A
Authority: CN
Inventors: 强鹏
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2022-09-27
Also published as: WO2023207376A9; WO2023207376A1

Abstract

The application discloses a time sequence adjusting method and device, a storage medium and electronic equipment. Wherein, the method comprises the following steps: the method comprises the steps of responding to an acquired first reading instruction, generating a sampling signal, sampling data signals transmitted on N transmission circuits on a sampling edge of the sampling signal to obtain first sampling data, determining a transmission circuit with time sequence offset in the N transmission circuits according to values of identical bits in training data and the first sampling data, and adjusting transmission delay on the transmission circuit with the time sequence offset until the center of the data signals transmitted on the transmission circuit with the time sequence offset are aligned with the sampling edge of the sampling signal. The method and the device can be applied to the field of artificial intelligence and the like, and solve the technical problem that in the related technology, data signals cannot be aligned with sampling signals, so that data reading sampling errors are caused.

Description

Timing adjustment method and device, storage medium and electronic equipment

Technical Field

The present disclosure relates to the field of computers, and in particular, to a method and an apparatus for adjusting a timing sequence, a storage medium, and an electronic device.

Background

According to a related protocol of the HBM (High-Bandwidth Memory), the data read-write speed of the HBM device can reach a bit rate of up to 3.6 GHz. At such a high operating frequency, if the data transmission is interfered by noise on the data communication link or crosstalk occurs between data lines, errors in data reading and writing are easily caused. High frequency data reading and data transmission are easily affected by PVT (Process Verification Test) environment changes, and crosstalk between signals causes read data and the sampled RDQS signal to shift, so that a read data sampling error occurs.

For example, when the HBM Host initiates a read operation to the HBM DRAM (Dynamic Random Access Memory), the HBM DRAM returns read data to the HBM Host. At the same time, the HBM DRAM also returns a Read DQ Strobe (RDQS) signal to the HBM Host that matches the Read data. The HBM host will use this signal as a sampling signal for sampling read data, and therefore, when the read data and the sampled RDQS signal are not aligned, a sampling error of the read data may result.

When the data read from the HBM DRAM is wrong, the correct execution of the entire HBM subsystem is affected, and in severe cases, the normal operation of the entire chip is even affected.

In view of the above problems, no effective solution has been proposed.

Disclosure of Invention

The embodiment of the application provides a time sequence adjusting method and device, a storage medium and electronic equipment, so as to at least solve the technical problem that in the related technology, a data signal and a sampling signal cannot be aligned to cause a sampling error of read data.

According to an aspect of an embodiment of the present application, there is provided a timing adjustment method, including: generating a sampling signal in response to an acquired first read instruction, wherein the first read instruction is used for reading training data, the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2; sampling data signals transmitted on N transmission circuits on sampling edges of the sampling signals to obtain first sampling data, wherein the N bits in the training data are transmitted on the N transmission circuits as data signals, and the first sampling data are data represented by the N bits; determining a transmission circuit with time sequence offset in the N transmission circuits according to the values of the same bits in the training data and the first sampling data; adjusting a transmission delay on the timing offset transmission circuit until a center of a data signal transmitted on the timing offset transmission circuit is aligned with a sampling edge of the sampling signal.

According to another aspect of the embodiments of the present application, there is also provided a timing adjustment apparatus, including: the device comprises a generating module, a sampling module and a processing module, wherein the generating module is used for responding to an acquired first read instruction, the first read instruction is used for reading training data, the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2; the sampling module is configured to sample data signals transmitted on N transmission circuits on sampling edges of the sampling signals to obtain first sampling data, where the N bits in the training data are transmitted on the N transmission circuits as data signals, and the first sampling data is data represented by the N bits; a determining module, configured to determine, according to values of the same bit in the training data and the first sampling data, a transmission circuit with a timing offset in the N transmission circuits; and the adjusting module is used for adjusting the transmission delay on the transmission circuit with the timing deviation until the center of the data signal transmitted on the transmission circuit with the timing deviation is aligned with the sampling edge of the sampling signal.

Optionally, the apparatus is configured to determine, according to values of the same bit in the training data and the first sampling data, a transmission circuit with a timing offset in the N transmission circuits, by: determining whether values of the same bits in the training data and the first sampling data are the same; and under the condition that M bits with different values exist in the N bits, determining M transmission circuits in the N transmission circuits as the transmission circuits with the time sequence offset, wherein the M transmission circuits are used for transmitting data signals corresponding to the M bits, and M is greater than or equal to 1 and less than or equal to N.

Optionally, the apparatus is configured to adjust the transmission delay on the timing offset transmission circuit until the center of the data signal transmitted on the timing offset transmission circuit is aligned with the sampling edge of the sampling signal by:

performing a first round of adjustment on the transmission delay on the transmission circuit with the timing offset in the N transmission circuits until the center of the data signal transmitted on each transmission circuit in the N transmission circuits is aligned with a sampling edge of the sampling signal respectively;

and under the condition that a transmission circuit, of which the transmitted data signal is not aligned with a target sampling edge, exists in the N transmission circuits obtained after the first round of adjustment is performed, performing a second round of adjustment on the transmission delay on the transmission circuit, of which the transmitted data signal is not aligned with the target sampling edge, until the center of the data signal transmitted on each transmission circuit in the N transmission circuits is aligned with the target sampling edge, wherein the target sampling edge is the sampling edge aligned with the center of the data signal transmitted on the N transmission circuits for the most times.

Optionally, the apparatus is configured to perform a first round of adjustment on transmission delays of the transmission circuits with timing offset in the N transmission circuits until a center of a data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampling signal respectively, by:

performing the following operations on each of the N transmission circuits with timing offset, wherein each of the transmission circuits with timing offset is a current transmission circuit when the following operations are performed:

determining a first edge of a time window in which the data signal transmitted on the current transmission line is located as a first position and a second edge of the time window in which the data signal is located as a second position under the condition that the data signal transmitted on the current transmission line corresponds to the high level of the sampling signal;

increasing the propagation delay on the current propagation circuit until the first edge moves from the first position to a target position, wherein the target position corresponds to a sampling edge of the sampled signal, and determining a first delay amount of the increased propagation delay on the current propagation circuit;

decreasing the current transfer circuit decrease transfer delay until the second edge moves from the second position to the target position, determining a second delay amount of the decreased transfer delay on the current transfer circuit;

and adjusting a time window where the data signal transmitted on the current transmission circuit is located according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal.

Optionally, the apparatus is configured to, in a case that there is a transmission circuit, in which a transmitted data signal is not aligned with a target sampling edge, in N transmission circuits obtained after performing the first round of adjustment, perform a second round of adjustment on a transmission delay on the transmission circuit, in which the transmitted data signal is not aligned with the target sampling edge, until a center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, by:

repeatedly performing the following operations until a center of a data signal transmitted on each of the N transmit circuits is aligned with the target sampling edge, wherein a current sampling edge is initialized to a sampling edge adjacent to the target sampling edge:

closing a first group of sampling edges except the target sampling edge in the sampling signal through clock gating, and reserving the target sampling edge;

determining whether a first set of data signals transmitted on the N transmission lines that are not aligned with the target sampling edge exist in the data signals transmitted on the N transmission lines according to whether the centers of the data signals transmitted on the N transmission lines are aligned with the target sampling edge;

in the presence of the first set of data signals, turning off a second set of sampling edges, other than a current sampling edge, of the sampling signals by the clock gating, and reserving the current sampling edge, wherein the second set of sampling edges includes the target sampling edge, and the current sampling edge is different from the target sampling edge;

determining whether a second set of data signals is present in the first set of data signals that is not aligned with the second set of sample edges based on whether a center of the first set of data signals is aligned with the current sample edge;

adjusting a transmission delay on a transmission circuit that transmitted a target data signal in the presence of the target data signal in the first set of data signals, wherein a center of the target data signal is aligned with the current sampling edge before adjustment and is aligned with the target sampling edge after adjustment;

in the presence of the second set of data signals, updating the current sampling edge to a sampling edge of the sampling signal that is not retained by the clock gating.

determining a target delay unit in delay control units arranged on the transmission circuits with timing offset, and transmitting the corresponding data signal from the output position of the target delay unit, wherein the center of the data signal transmitted from the output position of the target delay unit is aligned with the sampling edge of the sampling signal, one delay control unit is arranged on each transmission path in the N transmission circuits, the delay control unit comprises a preset number of delay units which are sequentially connected in series, and each delay unit is used for delaying the transmission on the transmission circuit by adjusting the unit time length.

Optionally, the apparatus is further configured to:

obtaining N target transmission circuits after the transmission delay on the transmission circuit with the time sequence offset in the N transmission circuits is adjusted, wherein the center of a data signal transmitted on each target transmission circuit in the N target transmission circuits is aligned with the sampling edge of the sampling signal;

in response to an acquired second read instruction, sampling data signals transmitted on the N target transmission lines on sampling edges of the sampling signals to obtain second sampling data, where the second read instruction is used to read target data, where the target data is unknown data represented by N bits, the N bits in the target data are transmitted as data signals on the N target transmission lines, and the second sampling data is data represented by N bits.

Optionally, the apparatus is further configured to:

sending the second read instruction when the target memory is configured to be in a register read mode, wherein the target memory is divided into a plurality of double-byte registers, and the second read instruction is used for reading the target data in a target double-byte register in the plurality of double-byte registers through the N target transmission circuits.

Optionally, the apparatus is configured to sample, in response to the acquired second read instruction, data signals transmitted on the N target transmission lines on sampling edges of the sampling signal to obtain second sampling data, and includes:

in response to the acquired second read instruction, the 128-bit memory read data bus signals, the 16-bit read data mask signals and the 16-bit data bus inversion signals transmitted on the 160 target transmission lines are sampled on the sampling edges of the sampling signals, so as to obtain second sampling data.

in the case that the sampling edge is a rising edge, adjusting a transmission delay on the transmission circuit with timing offset until the center of a data signal transmitted on the transmission circuit with timing offset is aligned with the rising edge of the sampling signal; or

In the case that the sampling edge is a falling edge, adjusting a transmission delay on the transmission circuit with timing offset until a center of a data signal transmitted on the transmission circuit with timing offset is aligned with the falling edge of the sampling signal.

adjusting the transmission delay on the transmission circuit with the time sequence offset until a central point corresponding to the data signal transmitted on the transmission circuit with the time sequence offset is aligned with a sampling edge of the sampling signal, wherein the central point is a central point of a time window where the data signal is located; or

And adjusting the transmission delay on the transmission circuit with the timing deviation until the sampling edge of the sampling signal is positioned in a time sub-window corresponding to the data signal transmitted on the transmission circuit with the timing deviation, wherein the time sub-window is a sub-window including the central point in the time window.

According to another aspect of the embodiments of the present application, there is also provided a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the above timing adjustment method when running.

According to yet another aspect of embodiments herein, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the timing adjustment method as above.

According to another aspect of the embodiments of the present application, there is also provided an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the timing adjustment method through the computer program.

In the embodiment of the present application, a sampling signal is generated in response to an acquired first read instruction, where the first read instruction is used to read training data, where the training data is known data represented by N bits, N is a positive integer greater than or equal to 2, and data signals transmitted on N transmission circuits are sampled on sampling edges of the sampling signal to obtain first sampling data, where N bits in the training data are transmitted as data signals on the N transmission circuits, the first sampling data is data represented by N bits, a transmission circuit with timing offset in the N transmission circuits is determined according to values of the same bits in the training data and the first sampling data, a transmission delay in the transmission circuit with timing offset is adjusted until a center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edges of the sampling signal, through the pin training of reading data, the offset between the data signal read by the memory device and the sampling signal can be adjusted, and the purpose of ensuring the alignment of the sampling signal to the data signal center of the reading data is achieved, so that the technical effect of improving the accuracy of reading data is realized, and the technical problem that the data signal cannot be aligned with the sampling signal in the related technology to cause the sampling error of the reading data is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a schematic diagram of an application environment of an alternative timing adjustment method according to an embodiment of the present application;

FIG. 2 is a flow chart illustrating an alternative timing adjustment method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative timing adjustment method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of another alternative timing adjustment method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 6 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 7 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 8 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 9 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 10 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 11 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 12 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 13 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 14 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 15 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 16 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 17 is a schematic diagram of yet another alternative timing adjustment method according to an embodiment of the present application;

FIG. 18 is a schematic diagram of an alternative timing adjustment apparatus according to an embodiment of the present application;

FIG. 19 is a block diagram of an alternative timing adjustment product according to an embodiment of the present application;

fig. 20 is a schematic structural diagram of an alternative electronic device according to an embodiment of the application.

Detailed Description

In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

First, partial nouns or terms appearing in the description of the embodiments of the present application are applicable to the following explanations:

HBM: High-Bandwidth Memory, High Bandwidth Memory.

MISR: multiple-input Shift Register, Multiple-input Shift Register.

Loopback Test: and (4) self-loop testing.

At Speed: in the fast operating mode.

DWORD: data Word, Data Word.

Read Register Mode: the register pattern is read.

Tracing: and (5) training.

RDQS: read DQ Strobe, Read data select pulse.

The present application is illustrated below with reference to examples:

according to an aspect of the embodiments of the present application, a timing adjustment method is provided, and optionally, in the present embodiment, the timing adjustment method may be applied to a hardware environment formed by a server 101 and a terminal device 103 as shown in fig. 1. As shown in fig. 1, a server 101 is connected to a terminal 103 via a network, and may be used to provide services for the terminal or applications installed on the terminal, such as video applications, instant messaging applications, browser applications, educational applications, game applications, and the like. The database 105 may be provided on or separate from the server for providing data storage services for the server 101, such as a game data storage server, and the network may include, but is not limited to: a wired network, a wireless network, wherein the wired network comprises: a local area network, a metropolitan area network, and a wide area network, the wireless network comprising: bluetooth, WIFI, and other wireless communication enabled networks, terminal device 103 may be an application configured terminal, and may include, but is not limited to, at least one of: the application 107 using the timing adjustment method is displayed through the terminal device 103 or other connected display Devices by using a Mobile phone (such as an Android Mobile phone, an iOS Mobile phone, etc.), a notebook computer, a tablet computer, a palm computer, an MID (Mobile Internet Devices), a PAD, a desktop computer, a smart television, a smart voice interaction device, a smart home appliance, a vehicle-mounted terminal, an aircraft, etc.

As shown in fig. 1, the timing adjustment method may be implemented in the terminal device 103 by the following steps:

s1, generating a sampling signal on the terminal device 103 in response to an acquired first read instruction, where the first read instruction is used to read training data, where the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

s2, obtaining, at the terminal device 103, first sampling data by sampling the data signals transmitted on the N transmission circuits on the sampling edge of the sampling signal, where N bits in the training data are transmitted on the N transmission circuits as data signals, and the first sampling data is data expressed by using the N bits;

s3, determining, on the terminal device 103, a transmission circuit having a timing offset among the N transmission circuits according to the value of the same bit in the training data and the first sampling data;

s4, the transmission delay on the transmission circuit in which the timing offset exists is adjusted on the terminal device 103 until the center of the data signal transmitted on the transmission circuit in which the timing offset exists is aligned with the sampling edge of the sampling signal.

Optionally, in this embodiment, the timing adjustment method may also be implemented by a server, for example, implemented in the server 101 shown in fig. 1; or by both the terminal device and the server.

The above is merely an example, and the present embodiment is not particularly limited.

Optionally, as an optional implementation manner, as shown in fig. 2, the timing adjustment method includes:

s202, generating a sampling signal in response to an acquired first read instruction, wherein the first read instruction is used for reading training data, the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

s204, sampling data signals transmitted on the N transmission circuits on sampling edges of the sampling signals to obtain first sampling data, wherein N bits in the training data are transmitted on the N transmission circuits as data signals, and the first sampling data are data expressed by the N bits;

s206, determining a transmission circuit with time sequence offset in the N transmission circuits according to the values of the same bits in the training data and the first sampling data;

and S208, adjusting the transmission delay on the transmission circuit with the timing offset until the center of the data signal transmitted on the transmission circuit with the timing offset is aligned with the sampling edge of the sampling signal.

Optionally, in this embodiment of the present application, the timing adjustment method may include, but is not limited to, being applied to any scene where data needs to be read through a memory device, for example, in a data reading process of an application scene of a game application, a live broadcast application, a video production application, an instant messaging application, a traffic application, artificial intelligence, and the like.

Among them, Artificial Intelligence (AI) is a theory, method, technique and application system that simulates, extends and expands human Intelligence using a digital computer or a machine controlled by a digital computer, senses the environment, acquires knowledge and uses the knowledge to obtain the best result. In other words, artificial intelligence is a comprehensive technique of computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a manner similar to human intelligence. Artificial intelligence is the research of the design principle and the implementation method of various intelligent machines, so that the machines have the functions of perception, reasoning and decision making.

The artificial intelligence technology is a comprehensive subject and relates to the field of extensive technology, namely the technology of a hardware level and the technology of a software level. The artificial intelligence infrastructure generally includes technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technologies, operation/interaction systems, mechatronics, and the like. The artificial intelligence software technology mainly comprises a computer vision technology, a voice processing technology, a natural language processing technology, machine learning/deep learning and the like.

Machine Learning (ML) is a multi-domain cross discipline, and relates to a plurality of disciplines such as probability theory, statistics, approximation theory, convex analysis, algorithm complexity theory and the like. The special research on how a computer simulates or realizes the learning behavior of human beings so as to acquire new knowledge or skills and reorganize the existing knowledge structure to continuously improve the performance of the computer. Machine learning is the core of artificial intelligence, is the fundamental approach for computers to have intelligence, and is applied to all fields of artificial intelligence. Machine learning and deep learning generally include techniques such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and formal education learning.

With the research and development of artificial intelligence technology, the artificial intelligence technology is developed and applied in a plurality of fields, for example, common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned driving, autonomous driving, unmanned aerial vehicles, robots, smart medical treatment, smart customer service, and the like.

Optionally, in this embodiment of the application, the first read instruction may include, but is not limited to, an instruction sent by the host for reading data, and taking the HBM device as an example, according to a relevant protocol of the HBM, a data read-write speed of the HBM 2E device may reach a bit rate of up to 3.6 GHz. Because read-write data of the HBM can transmit data on both the rising edge and the falling edge of the clock, the communication clock frequency of the actual HBM 2E is up to 1.8 GHz. At such a high operating frequency, if the data transmission is interfered by noise on the data communication link or crosstalk occurs between data lines, errors in reading and writing data in the fast operating mode are easily caused.

A READ operation of the HBM device is generally organized in a burst form, initiation of the READ burst operation is marked by sending of a READ instruction, and fig. 3 is a schematic diagram of an optional timing adjustment method according to an embodiment of the present application, as shown in fig. 3, where after a READ instruction is sent once, 8-bit data is READ by both a rising edge and a falling edge. The READ instruction of the HBM has a burst length of 2 or 4, respectively.

After the HBM DRAM receives the READ command, the HBM DRAM returns READ data DQ, DM, DBI to the HBM Host, where fig. 4 is a schematic diagram of another optional timing adjustment method according to an embodiment of the present application, a format of the HBM DRAM return data is shown in fig. 4, and relevant timing parameters included in fig. 4 are as follows:

tDQSCK (min/max): the minimum and maximum time ranges between the RDQS _ c rising edge (or RDQS _ t falling edge) and the CK _ c rising edge (or CK _ t falling edge);

tDQSCK: the time delay between the RDQS rising edge and the CK rising edge is described;

tQSH: a time delay is described where the RDQS signal is high for a duration;

tQSL: a time delay is described for the RDQS signal to be low continuously;

tLZ (min/max): describes the minimum and maximum time ranges for the read data to persist from the high impedance state to the low impedance state;

6, tHZ (min/max): describes the minimum and maximum time ranges for the read data to persist from the low impedance state to the high impedance state;

tDQSQ: describes the time delay between the rising edge of RDQS _ t (or the falling edge of RDQS _ c) to the sensing of DQ, DM, and DBI data;

tQH: the time delay from the rising edge of RDQS _ t (or the falling edge of RDQS _ c) to the sensing of DQ, DM, and DBI data to remain stable is described.

Fig. 5 is a schematic diagram of another alternative timing adjustment method according to an embodiment of the present application, where when the HBM DRAM has a length of bl (burst length) 2, the read data output timing is as shown in fig. 5, and it can be seen from fig. 5 that data reading lasts for two consecutive cycles.

Fig. 6 is a schematic diagram of another alternative timing adjustment method according to an embodiment of the present application, where the read data output timing of the HBM DRAM is as shown in fig. 6 if bl (burst length) is 4. As can be seen from fig. 6, the data reading lasts for four consecutive cycles.

The above is merely an example, and the present embodiment is not limited in any way.

Optionally, in this embodiment of the application, the generating of the sampling signal may include, but is not limited to, assembling a corresponding sampling clock with a differential clock signal corresponding to CK _ c or CK _ t according to different services, that is, the generating of the different sampling signal may include, but is not limited to, generating according to the differential clock signal.

Fig. 7 is a schematic diagram of another alternative timing adjustment method according to an embodiment of the present application, and as shown in fig. 7, taking a HBM performing a read operation as an example, the method may include, but is not limited to, the following steps:

when the HBM Host initiates a read operation to the HBM DRAM, the HBM DRAM will return read data to the HBM Host. At the same time, the HBM DRAM also returns a RDQS (read data select pulse) signal matching the read data to the HBM Host. In fig. 6, ACT is a one-time activate command, and PRE is a one-time precharge command. HBM HOST will use this signal as the sampling signal for sampling the read data, so the accuracy of the sampling is highest if it can be guaranteed that the sampling signal RDQS can be aligned to the center of the read data.

Optionally, in this embodiment of the present application, the training data may include, but is not limited to, pre-configured data for training a read data pin, and the training data may include, but is not limited to, data represented by N bits, for example, training data generated by a DBI path including 128-bit DQ, 16-bit DM, and 16-bit.

Optionally, in this embodiment of the present application, the sampling edge of the sampling signal may include, but is not limited to, a rising edge or a falling edge of the sampling signal, the data signals transmitted on the N transmission circuits may include, but is not limited to, data represented by N bits, each transmission circuit transmits data represented by one bit, and the sampling the data signals transmitted on the N transmission circuits may include, but is not limited to, selecting a pulse signal by returning read data matched with the read data when the read data returns, so as to sample the data signals, and obtain the first sampling data.

It should be noted that, N bits in the training data are transmitted as data signals on the N transmission circuits, which means that the training data of each bit is transmitted as a data signal on a corresponding transmission circuit to read the training data represented by the N bits through the N transmission circuits.

Optionally, in this embodiment of the application, the first sample data is data represented by N bits, which may include but is not limited to regarding the first sample data as data to be read by the first read command.

Optionally, in this embodiment of the application, the value of the same bit in the training data and the first sampling data may include, but is not limited to, in the process of transmitting the data signals of N bits on the N transmission circuits, transmitting the data signal of a corresponding bit on each transmission channel, at this time, the training data is known, and it is determined whether the data signal transmitted by the first sampling data on the N transmission circuits is the same as the value of the training data.

For example, the training data may be configured to transmit "1" on each of the N transmission circuits as a value of the data signal, and determine whether the value of the data signal transmitted by the first sampling data on the N transmission circuits is equal to 1, and then determine, as the transmission circuit with the timing offset, the transmission circuit with the value of the data signal transmitted on the N transmission circuits being not equal to 1.

Fig. 8 is a schematic diagram of another alternative timing adjustment method according to an embodiment of the present application, and as shown in fig. 8, taking a HBM performing a read operation as an example, the method may include, but is not limited to, the following steps:

FIG. 8 shows Data being sampled using CLK, which in an HBM read Data scenario is the RDQS signal returned by the HBM DRAM, which contains the DQ, DM and DBI Data returned by the HBM DRAM. In I, the sampling edge of CLK is located at the Data center of Data, at which time the sampling accuracy is highest. In II and III, there is a misalignment of the read data and the sampled RDQS signal, offset from the data center.

In II, the clock sampling edge will drift out of the read data window; in III, although the clock sampling edge does not drift out of the read data window, the sampling edge is too close to the set (or cancel) edge of the data, which causes a timing violation of setup timing (or hold timing) for this sampling. Both of the above cases can cause sampling errors of read data.

Therefore, the read data transfer circuit corresponding to II or III is determined as the transfer circuit having the timing offset.

Optionally, in the embodiment of the present application, the adjusting the transmission delay on the transmission circuit with timing offset may include, but is not limited to, adding a delay circuit to the transmission circuit with timing offset, for example, adding an inverter circuit.

Optionally, in this embodiment, the alignment of the center of the Data signal transmitted on the transmission circuit with timing offset and the sampling edge of the sampling signal may include, but is not limited to, the center of the Data signal transmitted on the transmission circuit with timing offset and the sampling edge of the sampling signal are both as shown in I in fig. 8, and the sampling edge of CLK is located at the center of the Data signal of Data.

As an optional solution, the transmission circuit that determines that there is a timing offset in the N transmission circuits according to values of the same bit in the training data and the first sampling data includes:

s1, determining whether the values of the same bits in the training data and the first sampling data are the same;

s2, when M bits with different values exist in the N bits, determining M transmission circuits in the N transmission circuits as transmission circuits with timing offset, where the M transmission circuits are used to transmit data signals corresponding to the M bits, and M is greater than or equal to 1 and less than or equal to N.

Optionally, in this embodiment of the application, the determining whether the values of the same bit in the training data and the first sampling data are the same may include, but is not limited to, whether the value of bit1 of the training data is the same as the value of bit1 of the first sampling data, if the values are the same, it is considered that the transmission circuit where bit1 is located does not have a timing offset, if the values are different, it is considered that the transmission circuit where bit1 is located has a timing offset, and so on, bit2, bit3, …, and bit n all perform the above determination.

Optionally, in this embodiment, the presence of M bits with different values in the N bits may be understood that M transmission circuits in the N transmission circuits are transmission circuits with timing offset.

As an alternative, adjusting the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampling signal includes:

s1, carrying out first round adjustment on transmission delay on the transmission circuit with timing sequence offset in the N transmission circuits until the center of the data signal transmitted on each transmission circuit in the N transmission circuits is aligned with one sampling edge of the sampling signal respectively;

and S2, under the condition that a transmission circuit with the transmitted data signal not aligned with the target sampling edge exists in the N transmission circuits obtained after the first round of adjustment, carrying out a second round of adjustment on the transmission delay on the transmission circuit with the transmitted data signal not aligned with the target sampling edge until the center of the data signal transmitted on each transmission circuit in the N transmission circuits is aligned with the target sampling edge, wherein the target sampling edge is the sampling edge with the largest number of times of alignment with the centers of the data signals transmitted on the N transmission circuits.

Optionally, in this embodiment of the present application, the first round of adjustment may include, but is not limited to, aligning a center of the data signal transmitted on each of the N transmission circuits with one sampling edge of the sampling signal, respectively, that is, aligning a center of the data signal transmitted on each of the N transmission circuits with the same or different one sampling edge, respectively.

For example, fig. 9 is a schematic diagram of another alternative timing adjustment method according to the embodiment of the present application, and as shown in fig. 9, clock is a sampling signal and includes a plurality of sampling edges (sampling edge 902, sampling edge 904, sampling edge 906), where the centers of the data signals of bit0 and biti are not aligned with sampling edge 904, and the centers of the data signals of bit1 and bitj are aligned with sampling edge 904, at this time, the above first round of adjustment needs to be performed on bit0 and biti, so that the centers of the data signals of bit0 and biti are aligned with at least any one of sampling edge 902, sampling edge 904, and sampling edge 906.

Optionally, in this embodiment of the present application, the second round of adjustment may include, but is not limited to, determining a target sampling edge which is aligned with a center of the data signal transmitted on the N transmission lines for the most number of times, and then moving a center of the data signal transmitted on the transmission line which is not aligned with the target sampling edge to be aligned with the target sampling edge, and specifically, may include, but is not limited to, moving a center of the data signal aligned with a sampling edge other than the target sampling edge to be aligned with the target sampling edge by using a delay unit which increases a time length corresponding to one sampling period.

For example, taking fig. 9 as an example, the centers of the data signals of bit1 and bitj are aligned with the sampling edge 904, and the centers of the data signals of bit0 and biti are aligned with the sampling edge 902 and the sampling edge 906, respectively, after the first round of adjustment, at this time, by adjusting the transmission delays of the transmission circuits of the data signals corresponding to bit0 and biti, the bits 0 and biti are also aligned with the sampling edge 904 until the centers of the data signals transmitted on each of the N transmission circuits are aligned with the sampling edge 904.

Optionally, in this embodiment of the application, when the center of the data signal transmitted through each transmission circuit of the N transmission circuits obtained after the first round of adjustment is aligned with the target sampling edge, the N transmission circuits obtained after the first round of adjustment are determined as N target transmission circuits.

By the embodiment of the application, the data reading pin can be trained before the initial work of the HBM chip, so that the sampling error of a chip data reading path caused by unconvergence of a rear end time sequence and production faults of the HBM chip can be avoided when the chip initially works, and the stability of the data reading path when the chip initially works is ensured; when the HBM chip detects that the PVT has obvious drift, the software configuration chip trains the data reading pin to ensure that the chip cannot cause data transmission errors of a chip data reading channel due to the drift of the PVT; the regular data reading training can be carried out on the HBM chip regularly by using a regular data reading training mechanism contained in hardware, so that the sampling error of the data reading can not occur in the working process of the chip; the single-step data reading training of the software configuration is supported, so that the data reading training of the whole chip can be completed by the software configuration alone. Because the software can complete the action when the system is not busy, the efficiency of the whole system can be ensured on the basis of ensuring that a data reading pin does not have sampling errors.

In the present application, an automatic training mode implemented by a hardware circuit is adopted. Besides the method, the whole training process can be completed by using a software configuration register, namely the software configuration register can manually configure the value of the Step counter, and can configure the Host to send a read data command and the configuration of the MR7 register to read and check the content of the read data received by the HBM DRAM. Thus, the software can independently initiate each step of the single-step training of read data.

As an alternative, the first round of adjusting the transmission delay on the transmission circuit with timing offset in the N transmission circuits until the center of the data signal transmitted on each transmission circuit in the N transmission circuits is aligned with a sampling edge of the sampling signal respectively includes:

performing the following operations on each transmission circuit with timing offset in the N transmission circuits, wherein each transmission circuit with timing offset is a current transmission circuit when the following operations are performed:

under the condition that the data signal transmitted on the current transmission circuit corresponds to the high level of the sampling signal, determining a first edge of a time window in which the data signal transmitted on the current transmission circuit is positioned as a first position, and determining a second edge of the time window in which the data signal is positioned as a second position;

increasing the transmission delay on the current transmission circuit until the first edge moves from the first position to a target position, and determining a first delay amount of the increased transmission delay on the current transmission circuit, wherein the target position corresponds to the sampling edge of the sampling signal;

reducing the reduced transmission delay of the current transmission circuit until the second edge moves from the second position to the target position, and determining a second delay amount of the reduced transmission delay on the current transmission circuit;

and adjusting the time window of the data signal transmitted on the current transmission circuit according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal.

Optionally, in this embodiment of the application, the data signal transmitted on the current transmission circuit corresponds to the high level of the sampling signal, and may include, but is not limited to, that any portion of the time window in which the data signal is located coincides with the high level interval of the sampling signal.

For example, fig. 10 is a schematic diagram of another alternative timing adjustment method according to the embodiment of the present application, as shown in fig. 10, (1) a partial region corresponding to a left edge to a point a of a time window of a data signal coincides with a high level interval of a sampling signal, at which time, the data signal is considered to correspond to a high level of the sampling signal, and (2) all regions corresponding to a left edge to a right edge of the time window of the data signal do not coincide with the high level interval of the sampling signal, at which time, the data signal is considered to correspond to a low level of the sampling signal.

Optionally, in this embodiment, the determining may include, but is not limited to, determining a rising edge of the time window as a first edge, and determining a right rising edge of the time window as a second edge, where the first position is an initial position of the left edge, and the second position is an initial position of the right edge;

optionally, in this embodiment of the application, the increasing the transmission delay of the current transmission circuit may include, but is not limited to, increasing a delay circuit of the current transmission circuit to achieve increasing the transmission delay, and the decreasing the transmission delay of the current transmission circuit may include, but is not limited to, decreasing a delay circuit of the current transmission circuit to achieve decreasing the transmission delay.

Optionally, in this embodiment of the present application, the moving of the first edge from the first position to the target position may include, but is not limited to, adding a delay circuit, so that the time window in which the data signal is transmitted on the current transmission line is moved backward until the left edge of the time window is aligned with the sampling edge of the sampling signal. Moving the second edge from the second position to the target position may include, but is not limited to, moving forward a time window in which the data signal is transmitted over the current transmission line by reducing the delay circuit until a right edge of the time window is aligned with a sampling edge of the sampled signal.

The delay circuit amount increased when the first edge moves from the first position to the target position is a first delay amount, and the delay circuit amount decreased when the second edge moves from the second position to the target position is a second delay amount.

Optionally, in this embodiment of the present application, the adjusting the time window in which the data signal transmitted on the current transmission circuit is located according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal may include, but is not limited to, taking a half of the sum of the first delay amount and the second delay amount as the transmission delay required to be adjusted for aligning the center of the data signal transmitted on the current transmission circuit with the sampling edge of the sampling signal.

That is, by adjusting half of the sum of the first delay amount and the second delay amount, the center of the data signal transmitted on the current transmission line is aligned with the sampling edge of the sampling signal.

For example, fig. 11 is a schematic diagram of another alternative timing adjustment method according to the embodiment of the present application, as shown in fig. 11, during the first adjustment, the initial state of a bit (corresponding to the current transmission circuit) of read data is phase0, and at this time, the value of the bit read back is 1 (corresponding to the data signal transmitted on the current transmission circuit corresponding to the high level of the sampling signal). By adjusting Step Counter to continuously increase the circuit delay of the bit, eventually, the value of the bit read back should be 0 (corresponding to the aforementioned target position), and then the value of Step Counter is recorded as R _ CNT (corresponding to the aforementioned first delay amount).

Thereafter, setting Phase1 to the initial state of Phase0, by adjusting Step Counter to continuously decrease the circuit delay of the bit, eventually, the value of the read back bit should be 0 (corresponding to the aforementioned target position), and then the value of Step Counter is recorded as L _ CNT (corresponding to the aforementioned second delay amount).

At this time, when the circuit delay of the bit is (R _ CNT + L _ CNT)/2, the bit can achieve the purpose of aligning the edge of the sampling clock with the edge of the time window of the data signal.

Continuing to adjust and calculate the circuit delay for each bit according to this step will align the sampled RDQS edge of each read data bit with the data edge. At this point, the first round of adjustment is finished.

As an optional scheme, in a case where there is a transmission circuit whose transmitted data signal is not aligned with the target sampling edge in the N transmission circuits obtained after the first round of adjustment is performed, performing a second round of adjustment on the transmission delay on the transmission circuit whose transmitted data signal is not aligned with the target sampling edge until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, includes:

repeatedly performing the following operations until a center of a data signal transmitted on each of the N transmission circuits is aligned with a target sampling edge, wherein a current sampling edge is initialized to a sampling edge adjacent to the target sampling edge:

determining whether a first group of data signals which are not aligned with the target sampling edge exist in the data signals transmitted on the N transmission circuits or not according to whether the centers of the data signals transmitted on the N transmission circuits are aligned with the target sampling edge or not;

in the presence of the first group of data signals, closing a second group of sampling edges except for a current sampling edge in the sampling signals through clock gating, and keeping the current sampling edge, wherein the second group of sampling edges comprises a target sampling edge, and the current sampling edge is different from the target sampling edge;

determining whether a second set of data signals is present in the first set of data signals that is not aligned with the second set of sample edges based on whether the center of the first set of data signals is aligned with the current sample edge;

in the presence of the second set of data signals, the current sampling edge is updated to a sampling edge of the sampling signal that has not been retained by the clock gating.

Optionally, in this embodiment of the present application, the Clock Gating (Clock-Gating) is an important means for reducing power consumption of the microprocessor, and mainly aims at dynamic power consumption caused by register inversion, and may close one or more sampling cycles of the sampling signal to close a sampling edge that needs to be closed, and reserve the sampling edge that needs to be reserved.

Optionally, in this embodiment, each data signal in the first set of data signals is a data signal whose center is aligned with one sampling edge, but is not aligned with the target sampling edge. When the first group of data signals exist, closing a second group of sampling edges except the current sampling edge in the sampling signals through clock gating, reserving the current sampling edge, closing the target sampling edge, searching whether the first group of data signals are all aligned with the current sampling edge, and adjusting transmission delay by taking the data signals aligned with the current sampling edge as target data signals so that the data signals are not aligned with the current sampling edge but aligned with the target sampling edge after the data signals are aligned.

Optionally, in this embodiment of the application, each data signal in the second group of data signals is a data signal whose center is not aligned with the current sampling edge and is not aligned with the target sampling edge, at this time, by updating the current sampling edge to a sampling edge that is not reserved by clock gating in the sampling signals, it is continuously determined whether the first group of data signals exists in the second group of data signals, and the data signal aligned with the current sampling edge is used as the target data signal to perform adjustment of transmission delay.

For example, fig. 12 is a schematic diagram of still another alternative timing adjustment method according to an embodiment of the present application, as shown in fig. 12, fig. 12A shows a plurality of transmission circuits in which centers of data signals in N transmission circuits are aligned with a target sampling edge, fig. 12B shows that a first group of sampling edges other than the target sampling edge is turned off by clock gating, the target sampling edge is retained, it is determined whether a first group of data signals not aligned with the target sampling edge exists in the data signals transmitted on the N transmission circuits according to whether the centers of the data signals transmitted on the N transmission circuits are aligned with the target sampling edge, fig. 12C shows that in the case of existence of the first group of data signals, a second group of sampling edges other than the current sampling edge in the sampling signals are turned off by clock gating, the current sampling edge is retained, and according to whether the centers of the first group of data signals are aligned with the current sampling edge, in the presence of a target data signal in the first set of data signals, a transmission delay on a transmission circuit that transmitted the target data signal is adjusted.

Optionally, in this embodiment of the present application, in the presence of the second group of data signals, the updating of the current sampling edge to the sampling edge that is not clock-gated to be retained in the sampling signal may be understood as updating the current sampling edge to be the closest to the target sampling edge first, and the sampling edge that is not clock-gated to be retained.

determining a target delay unit in delay control units arranged on transmission circuits with timing deviation, and transmitting corresponding data signals from output positions of the target delay unit, wherein the center of the corresponding data signals transmitted from the output positions of the target delay unit is aligned with sampling edges of sampling signals, one delay control unit is arranged on each transmission path in the N transmission circuits, each delay control unit comprises a preset number of delay units which are sequentially connected in series, and each delay unit is used for delaying the transmission on the transmission circuits by adjusting the unit time length.

Optionally, in this embodiment of the present application, the delay control unit may include, but is not limited to, a delay control circuit, and the delay control circuit may support dynamic adjustment of the delay circuit on the read data transmission path, and support increase or decrease of the delay on the read data path. A delay circuit for adjusting the delay of the bit path is added to the transmission path of the read data for each read data bit.

For example, fig. 13 is a schematic diagram of another alternative timing adjustment method according to the embodiment of the present application, and as shown in fig. 13, the read data path includes 128bit DQ, 16bit DM and 16bit DBI path in total, the DE is a Delay Element unit, and may include 128 DE, and each DE includes 4 inverter circuits. Each DE of the delay control unit includes a tap interface (corresponding to the output position mentioned above), fig. 14 is a schematic diagram of another alternative timing adjustment method according to the embodiment of the present application, and as shown in fig. 14, Step Counter can be used to control the value of the read data bit to be tapped from a certain tap outlet. Therefore, the purpose of adjusting the path delay of the read data, that is, the relative positions of the read data and the RDQS sampling edges can be moved and adjusted, can be achieved.

Fig. 15 is a schematic diagram of an alternative timing adjustment method according to an embodiment of the present application, and an application environment of the timing adjustment is schematically illustrated, as shown in fig. 15, an HBM Host includes four parts of an HBM mode configuration, a read instruction sending unit, a read data path delay control circuit, and a read data training unit. The data reading training unit is responsible for controlling the rest three modules, comparing the read data and completing the whole data reading training process.

As an optional solution, the method further comprises:

after the transmission delay on the transmission circuit with the time sequence offset in the N transmission circuits is adjusted, obtaining N target transmission circuits, wherein the center of a data signal transmitted on each target transmission circuit in the N target transmission circuits is aligned with the sampling edge of a sampling signal;

and in response to the obtained second read instruction, sampling the data signals transmitted on the N target transmission circuits on sampling edges of the sampling signals to obtain second sampling data, wherein the second read instruction is used for reading the target data, the target data is unknown data represented by N bits, the N bits in the target data are transmitted on the N target transmission circuits as data signals, and the second sampling data is data represented by N bits.

Optionally, in this embodiment of the application, after the training of the pins of the N transmission circuits is completed, that is, the transmission delay of the transmission circuit with timing offset in the N transmission circuits is adjusted, the N target transmission circuits may start to transmit unknown target data.

As an optional solution, the method further comprises:

and sending a second read instruction when the target memory is configured to be in a register reading mode, wherein the target memory is divided into a plurality of double-byte registers, and the second read instruction is used for reading target data in a target double-byte register in the plurality of double-byte registers through the N target transmission circuits.

Optionally, in this embodiment of the present application, the target memory may include, but is not limited to, an HBM memory, the second read instruction is used to read target data, and the HBM mode configuration unit is used to configure the DWORD MISR circuit into a DWORD read register mode (corresponding to the read register mode), where the configuration is completed by configuring the mode register MR7 of the HBM.

For example, fig. 16 is a schematic diagram of another alternative timing adjustment method according to an embodiment of the present application, a specific mode of the MR7 is shown in fig. 16, and the steps of configuring the HBM DWORD into a read register mode are as follows:

the values of MR7 are configured as: 8' b00000001, where OP0 is 1, indicating that DWORD Loopback mode is enabled; OP [5:3] is 3' b000, resetting the default value in the DWORD register to 0 xAAAAAh. The rest bits are default values;

the values of MR7 are configured as: 8' b00010011, where OP 0bit 1, indicates DWORD Loopback mode is enabled; OP [2:1] is 2' b01, indicating that the value in the MISR register is read, which is 0 xAAAAAAh because it was reset in step 1; OP [5:3] is 3' b010, configuring the DWORD register in read or write register mode. The rest bits are default values;

at this point, the HBM DRAM has been configured in the DWORD read register mode, and the value in the DWORD register (corresponding to the aforementioned target data) may be read by sending a read instruction.

As an optional scheme, in response to the obtained second read instruction, sampling data signals transmitted on the N target transmission lines on sampling edges of the sampling signal to obtain second sampling data, including:

in response to the acquired second read instruction, the 128-bit memory read data bus signals, the 16-bit read data mask signals and the 16-bit data bus inversion signals transmitted on the 160 target transmission circuits are sampled on the sampling edges of the sampling signals, so as to obtain second sampling data.

Optionally, in this embodiment of the application, the 128-bit memory read data bus signals transmitted on the 160 target transmission circuits may include, but are not limited to, 128-bit DQ signals, the 16-bit read data mask signals may include, but are not limited to, 16-bit DBI signals, and the 16-bit data bus flip signals may include, but are not limited to, 16-bit DM signals.

It should be noted that, the 128-bit DWORD of the data path of the HBM is divided into DWORD0, DWORD1, DWORD2 and DWORD3, and each DWORD is divided into 4 data units of Byte0, Byte1, Byte2 and Byte3 for comparison according to the width of MISR algorithm.

For example, fig. 17 is a schematic diagram of another alternative timing adjustment method according to the embodiment of the present application, as shown in fig. 17, in each Byte, from 19 th bit to 0 th bit, the data of the falling edge of the DBI and the data of the rising edge of the DBI, the data of the falling edge and the data of the rising edge of each bit of 8-bit DQ and the data of the falling edge of the DM and the data of the rising edge of the DM, respectively, the Byte in each DWORD contains a value of 20 bits, and when the DWORD register is reset, the value will become 0 xaaah, and the read command transmitting unit is responsible for transmitting a read command to the HBM DRAM.

in the case that the sampling edge is a rising edge, adjusting the transmission delay on the transmission circuit with the timing offset until the center of the data signal transmitted on the transmission circuit with the timing offset is aligned with the rising edge of the sampling signal; or

In the case where the sampling edge is a falling edge, the transmission delay on the transmission circuit in which the timing offset exists is adjusted until the center of the data signal transmitted on the transmission circuit in which the timing offset exists is aligned with the falling edge of the sampling signal.

Optionally, in this embodiment of the present application, the sampling edge may include, but is not limited to, a rising edge and a falling edge, and the sampling and reading of the data may be implemented by any one of the rising edge and the falling edge, and may also be implemented by both the rising edge and the falling edge.

adjusting transmission delay on the transmission circuit with the time sequence offset until a central point corresponding to the data signal transmitted on the transmission circuit with the time sequence offset is aligned with a sampling edge of the sampling signal, wherein the central point is a central point of a time window where the data signal is located; or

And adjusting the transmission delay on the transmission circuit with the timing deviation until the sampling edge of the sampling signal is positioned in a time sub-window corresponding to the data signal transmitted on the transmission circuit with the timing deviation, wherein the time sub-window is a sub-window including a central point in the time window.

It is understood that in the specific implementation of the present application, related data such as user information, when the above embodiments of the present application are applied to specific products or technologies, user permission or consent needs to be obtained, and the collection, use and processing of related data need to comply with related laws and regulations and standards of related countries and regions.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

According to another aspect of the embodiments of the present application, there is also provided a timing adjustment apparatus for implementing the above timing adjustment method. As shown in fig. 18, the apparatus includes:

a generating module 1802, configured to generate a sampling signal in response to an acquired first read instruction, where the first read instruction is used to read training data, where the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

a sampling module 1804, configured to sample data signals transmitted on N transmission circuits on sampling edges of the sampling signal, so as to obtain first sampling data, where the N bits in the training data are transmitted on the N transmission circuits as data signals, and the first sampling data is data represented by N bits;

a determining module 1806, configured to determine, according to values of the same bit in the training data and the first sampling data, a transmission circuit with a timing offset in the N transmission circuits;

an adjusting module 1808, configured to adjust a transmission delay on the transmission circuit with the timing offset until a center of a data signal transmitted on the transmission circuit with the timing offset is aligned with a sampling edge of the sampling signal.

As an optional scheme, the apparatus is configured to determine, according to values of the same bit in the training data and the first sampling data, a transmission circuit with a timing offset in the N transmission circuits, by: determining whether values of the same bits in the training data and the first sampling data are the same; and under the condition that M bits with different values exist in the N bits, determining M transmission circuits in the N transmission circuits as the transmission circuits with the time sequence offset, wherein the M transmission circuits are used for transmitting data signals corresponding to the M bits, and M is greater than or equal to 1 and less than or equal to N.

As an alternative, the apparatus is configured to adjust the transmission delay on the transmission circuit with timing offset until the center of the data signal transmitted on the transmission circuit with timing offset is aligned with the sampling edge of the sampling signal by:

performing a first round of adjustment on the transmission delay of the transmission circuit with the timing offset in the N transmission circuits until the center of the data signal transmitted on each transmission circuit in the N transmission circuits is aligned with a sampling edge of the sampling signal respectively;

As an alternative, the apparatus is configured to perform a first round adjustment on the transmission delay of the transmission circuit with timing offset in the N transmission circuits until the center of the data signal transmitted on each of the N transmission circuits is aligned with one sampling edge of the sampling signal respectively, by:

increasing a transmission delay on the current transmission circuit until the first edge moves from the first position to a target position, wherein the target position corresponds to a sampling edge of the sampled signal, and determining a first delay amount of the increased transmission delay on the current transmission circuit;

and adjusting a time window in which the data signal transmitted on the current transmission circuit is located according to the first delay amount and the second delay amount, so that the center of the data signal transmitted on the current transmission circuit is aligned with the sampling edge of the sampling signal.

As an optional scheme, in a case that there is a transmission circuit whose transmitted data signal is not aligned with a target sampling edge in N transmission circuits obtained after the first round of adjustment is performed, the apparatus is configured to perform a second round of adjustment on a transmission delay on the transmission circuit whose transmitted data signal is not aligned with the target sampling edge until a center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge by:

determining a target delay unit in delay control units arranged on the transmission circuits with timing sequence offset, and transmitting the corresponding data signal from the output position of the target delay unit, wherein the center of the corresponding data signal transmitted from the output position of the target delay unit is aligned with the sampling edge of the sampling signal, one delay control unit is arranged on each transmission path in the N transmission circuits, and the delay control units comprise a preset number of delay units which are sequentially connected in series, and each delay unit is used for adjusting the transmission delay on the transmission circuit by a unit time length.

As an optional solution, the apparatus is further configured to:

As an alternative, the apparatus is configured to sample the data signals transmitted on the N target transmission lines on the sampling edges of the sampling signal in response to the acquired second read instruction, so as to obtain second sampling data, and includes:

in response to the acquired second read instruction, the 128-bit memory read data bus signals, the 16-bit read data mask signals and the 16-bit data bus flip signals transmitted on the 160 target transmission circuits are sampled on the sampling edge of the sampling signal, so as to obtain the second sampling data.

According to an aspect of the application, there is provided a computer program product comprising a computer program/instructions containing program code for performing the method illustrated by the flow chart. In such embodiments, the computer program may be downloaded and installed from a network via communications portion 1909 and/or installed from removable media 1911. When executed by the central processing unit 1901, the computer program performs various functions provided by the embodiments of the present application.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

Fig. 19 schematically shows a structural block diagram of a computer system of an electronic device for implementing the embodiment of the present application.

It should be noted that the computer system 1900 of the electronic device shown in fig. 19 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown in fig. 19, the computer system 1900 includes a Central Processing Unit (CPU) 1901 that can perform various appropriate actions and processes in accordance with a program stored in a Read-Only Memory (ROM) 1902 or a program loaded from a storage section 1908 into a Random Access Memory (RAM) 1903. In the random access memory 1903, various programs and data necessary for system operation are also stored. The cpu 1901, the rom 1902, and the ram 1903 are connected to each other via a bus 1904. An Input/Output interface 1905(Input/Output interface, i.e., I/O interface) is also connected to the bus 1904.

The following components are connected to the input/output interface 1905: an input section 1906 including a keyboard, a mouse, and the like; an output section 1907 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage section 1908 including a hard disk and the like; and a communications portion 1909 that includes a network interface card, such as a local area network card, modem, and the like. The communication section 1909 performs communication processing via a network such as the internet. A driver 1190 is also connected to the input/output interface 1905 as needed. A removable medium 1911 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 1190 as necessary, so that a computer program read out therefrom is mounted in the storage section 1908 as necessary.

In particular, according to embodiments of the present application, the processes described in the various method flowcharts may be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated by the flow chart. In such embodiments, the computer program may be downloaded and installed from a network via communications portion 1909 and/or installed from removable media 1911. When executed by the central processor 1901, performs various functions defined in the system of the present application.

According to another aspect of the embodiments of the present application, there is also provided an electronic device for implementing the timing adjustment method, where the electronic device may be the terminal device or the server shown in fig. 1. The present embodiment takes the electronic device as a terminal device as an example for explanation. As shown in fig. 20, the electronic device comprises a memory 2002 and a processor 2004, the memory 2002 having stored therein a computer program, the processor 2004 being arranged for executing the steps of any of the method embodiments described above by means of the computer program.

Optionally, in this embodiment, the electronic device may be located in at least one network device of a plurality of network devices of a computer network.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

s1, generating a sampling signal in response to an acquired first read instruction, wherein the first read instruction is used for reading training data, the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

s2, sampling data signals transmitted through the N transmission circuits on sampling edges of the sampling signals to obtain first sampling data, where N bits in the training data are transmitted as data signals through the N transmission circuits, and the first sampling data is data expressed by the N bits;

s3, determining the transmission circuit with time sequence offset in the N transmission circuits according to the values of the same bits in the training data and the first sampling data;

and S4, adjusting the transmission delay on the transmission circuit with the timing offset until the center of the data signal transmitted on the transmission circuit with the timing offset is aligned with the sampling edge of the sampling signal.

Alternatively, it can be understood by those skilled in the art that the structure shown in fig. 20 is only an illustration, and the electronic device may also be a terminal device such as a smart phone (e.g., an Android phone, an iOS phone, etc.), a tablet computer, a palmtop computer, a Mobile Internet Device (MID), a PAD, and the like. Fig. 20 is a diagram illustrating a structure of the electronic device. For example, the electronics may also include more or fewer components (e.g., network interfaces, etc.) than shown in FIG. 20, or have a different configuration than shown in FIG. 20.

The memory 2002 may be configured to store software programs and modules, such as program instructions/modules corresponding to the timing adjustment method and apparatus in the embodiment of the present application, and the processor 2004 executes various functional applications and data processing by running the software programs and modules stored in the memory 2002, that is, the timing adjustment method described above is implemented. The memory 2002 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 2002 may further include memory located remotely from the processor 2004, which may be connected to the terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The memory 2002 may be specifically, but not limited to, used to store information such as training data, target data, and the like. As an example, as shown in fig. 20, the memory 2002 may include, but is not limited to, a generating module 1802, a sampling module 1804, a determining module 1806, and an adjusting module 1808 in the timing adjusting apparatus. In addition, the timing adjustment apparatus may further include, but is not limited to, other module units in the timing adjustment apparatus, which is not described in detail in this example.

Optionally, the transmitting device 2006 is configured to receive or transmit data via a network. Examples of the network may include a wired network and a wireless network. In one example, the transmission device 2006 includes a Network adapter (NIC) that can be connected to a router via a Network cable to communicate with the internet or a local area Network. In one example, the transmission device 2006 is a Radio Frequency (RF) module that is configured to communicate with the internet via wireless.

In addition, the electronic device further includes: a display 2008 for displaying the data signal; and a connection bus 2010 for connecting the respective module components in the above-described electronic apparatus.

In other embodiments, the terminal device or the server may be a node in a distributed system, where the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting a plurality of nodes through a network communication. Nodes can form a Peer-To-Peer (P2P, Peer To Peer) network, and any type of computing device, such as a server, a terminal, and other electronic devices, can become a node in the blockchain system by joining the Peer-To-Peer network.

According to an aspect of the present application, there is provided a computer-readable storage medium, from which a processor of a computer device reads computer instructions, the processor executing the computer instructions, causing the computer device to perform the timing adjustment method provided in the various alternative implementations of the timing adjustment aspect described above.

Alternatively, in the present embodiment, the above-mentioned computer-readable storage medium may be configured to store a computer program for executing the steps of:

and S4, adjusting the transmission delay of the transmission circuit with the timing deviation until the center of the data signal transmitted by the transmission circuit with the timing deviation is aligned with the sampling edge of the sampling signal.

Alternatively, in this embodiment, a person skilled in the art may understand that all or part of the steps in the methods of the foregoing embodiments may be implemented by a program instructing hardware associated with the terminal device, where the program may be stored in a computer-readable storage medium, and the storage medium may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The integrated unit in the above embodiments, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in the above computer-readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including instructions for causing one or more computer devices (which may be personal computers, servers, network devices, or the like) to execute all or part of the steps of the method described in the embodiments of the present application.

In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed client may be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A timing adjustment method, comprising:

generating a sampling signal in response to an acquired first read instruction, wherein the first read instruction is used for reading training data, the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

sampling data signals transmitted on N transmission circuits on sampling edges of the sampling signals to obtain first sampling data, wherein N bits in the training data are transmitted on the N transmission circuits as data signals, and the first sampling data are data represented by the N bits;

determining a transmission circuit with time sequence offset in the N transmission circuits according to the values of the same bits in the training data and the first sampling data;

adjusting a transmission delay on the timing offset transmission circuit until a center of a data signal transmitted on the timing offset transmission circuit is aligned with a sampling edge of the sampling signal.

2. The method of claim 1, wherein determining, according to values of a same bit in the training data and the first sampling data, a transmission circuit with a timing offset in the N transmission circuits comprises:

determining whether values of the same bits in the training data and the first sampling data are the same;

and under the condition that M bits with different values exist in the N bits, determining M transmission circuits in the N transmission circuits as the transmission circuits with the time sequence offset, wherein the M transmission circuits are used for transmitting data signals corresponding to the M bits, and M is greater than or equal to 1 and less than or equal to N.

3. The method of claim 1, wherein the adjusting the transmission delay on the timing offset transmitting circuit until a center of a data signal transmitted on the timing offset transmitting circuit is aligned with a sampling edge of the sampling signal comprises:

4. The method of claim 3, wherein the performing a first round of adjustment on the transmission delay of the transmission circuit with the timing offset in the N transmission circuits until the center of the data signal transmitted on each of the N transmission circuits is aligned with a sampling edge of the sampling signal respectively comprises:

5. The method of claim 3, wherein in a case that there is a transmission circuit, of the N transmission circuits obtained after the first round of adjustment is performed, in which the transmitted data signal is not aligned with the target sampling edge, performing a second round of adjustment on the transmission delay of the transmission circuit, in which the transmitted data signal is not aligned with the target sampling edge, until the center of the data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, comprises:

repeatedly performing the following operations until a center of a data signal transmitted on each of the N transmission circuits is aligned with the target sampling edge, wherein a current sampling edge is initialized to a sampling edge adjacent to the target sampling edge:

6. The method of claim 1, wherein the adjusting the transmission delay on the timing offset transmitting circuit until a center of a data signal transmitted on the timing offset transmitting circuit is aligned with a sampling edge of the sampling signal comprises:

7. The method of claim 1, further comprising:

8. The method of claim 7, further comprising:

9. The method of claim 7, wherein sampling the data signals transmitted on the N target transmission lines on the sampling edges of the sampling signal in response to the acquired second read command to obtain second sampling data comprises:

10. The method of any one of claims 1 to 9, wherein said adjusting the transmission delay on the timing offset transmitting circuit until the center of the data signal transmitted on the timing offset transmitting circuit is aligned with the sampling edge of the sampling signal comprises:

11. The method of any one of claims 1 to 9, wherein said adjusting the transmission delay on the timing offset transmitting circuit until the center of the data signal transmitted on the timing offset transmitting circuit is aligned with the sampling edge of the sampling signal comprises:

12. A timing adjustment apparatus, comprising:

the device comprises a generating module, a sampling module and a sampling module, wherein the generating module is used for generating a sampling signal in response to an acquired first read instruction, the first read instruction is used for reading training data, the training data is known data represented by N bits, and N is a positive integer greater than or equal to 2;

the sampling module is configured to sample data signals transmitted on N transmission circuits on sampling edges of the sampling signals to obtain first sampling data, where the N bits in the training data are transmitted on the N transmission circuits as data signals, and the first sampling data is data represented by the N bits;

a determining module, configured to determine, according to values of the same bit in the training data and the first sampling data, a transmission circuit with a timing offset in the N transmission circuits;

and the adjusting module is used for adjusting the transmission delay on the transmission circuit with the timing deviation until the center of the data signal transmitted on the transmission circuit with the timing deviation is aligned with the sampling edge of the sampling signal.

13. A computer-readable storage medium, characterized in that it comprises a stored program, wherein the program is executable by a terminal device or a computer to perform the method of any one of claims 1 to 11.

14. A computer program product comprising computer program/instructions, characterized in that the computer program/instructions, when executed by a processor, implement the steps of the method as claimed in any one of claims 1 to 11.

15. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to execute the method of any of claims 1 to 11 by means of the computer program.