WO2023201731A1 - 读时序控制方法、装置及计算机可读存储介质 - Google Patents

读时序控制方法、装置及计算机可读存储介质 Download PDF

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Publication number
WO2023201731A1
WO2023201731A1 PCT/CN2022/088597 CN2022088597W WO2023201731A1 WO 2023201731 A1 WO2023201731 A1 WO 2023201731A1 CN 2022088597 W CN2022088597 W CN 2022088597W WO 2023201731 A1 WO2023201731 A1 WO 2023201731A1
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Prior art keywords
read
read timing
chip memory
input data
output
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PCT/CN2022/088597
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English (en)
French (fr)
Inventor
朱文涛
孙高明
袁靖超
周志恒
潘宏鑫
赵敬鹏
段欣
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000912.1A priority Critical patent/CN117280410A/zh
Priority to US18/037,087 priority patent/US20240345943A1/en
Priority to PCT/CN2022/088597 priority patent/WO2023201731A1/zh
Publication of WO2023201731A1 publication Critical patent/WO2023201731A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, the field of display driving technology, and in particular, to a read timing control method, device, and computer-readable storage medium.
  • the Porch parameters include the horizontal total number of lines (HTotal), the horizontal active number of lines (HActive), horizontal synchronization (HSYNC), horizontal trailing edge clamp (HBack Porch, HBP), and horizontal leading edge clamp (HFront Porch, HFP).
  • VBP represents the number of invalid lines after the frame synchronization signal at the beginning of a frame of image
  • VFP represents the number of invalid lines before the frame synchronization signal after the end of a frame of image
  • HBP represents the number of invalid lines from the beginning of the line synchronization signal to a line.
  • the number of clock signals between the start of valid data, HFP represents the number of clock signals between the end of one row of valid data and the start of the next row synchronization signal.
  • the data is usually "Porch converted” - after receiving the data input by the front end according to Porch parameter A , sending the data with the preset Porch parameter B.
  • the advantage of this operation is that when performing display debugging, it is often necessary to adjust the relative position of the data source (Data Source) and the array substrate row driver (Gate Driveron Array, GOA) to improve the display effect. Based on “Porch conversion” (by modifying the preset Assuming Porch parameters) can be implemented very easily.
  • Embodiments of the present disclosure provide a read timing control method, which is applied to a read timing control device.
  • the read timing control device includes an on-chip memory.
  • the read timing control method includes:
  • the read timing is adjusted until the on-chip memory will not be read empty or full, and the data of the on-chip memory is read and output according to the read timing. .
  • performing frame end detection on the input data includes:
  • the position of the current input data is determined to be the end of the frame position.
  • counting the input data rows includes counting the input data rows according to a rising edge of an input DE signal.
  • generating a read timing based on preset Porch parameters includes:
  • the output row counter and output column counter are counted according to the preset Porch parameters.
  • the output row counter is reset, and the output row counter is reset when the next row of data output starts.
  • the output row counter restarts counting; when the output data is at the end of the frame, the output column counter is reset, and the output column counter restarts counting when the next frame data output starts;
  • the read timing is generated according to the values of the output row counter and the output column counter.
  • generating a read timing according to the values of the output row counter and the output column counter includes:
  • the first range and the second range are determined according to the preset Porch parameters, wherein the first range represents the valid data columns of the display panel, the second range represents the valid data rows of the display panel, and the first range and the second range represents the effective data area of the display panel;
  • the read control signal is set to low level.
  • the first range is determined based on the total horizontal row number Htotal, the horizontal trailing edge clamp HBP, and the horizontal leading edge clamp HFP
  • the second range is determined based on the total vertical row number Vtotal, the vertical leading edge clamp VFP, and Vertical trailing edge clamp VBP determined.
  • adjusting the read timing when the on-chip memory is empty or full includes:
  • the vertical trailing edge clamp VBP is increased to delay the high-level read control signal
  • the vertical trailing edge clamp VBP is reduced to advance the high-level read control signal.
  • adjusting the read timing when the on-chip memory is empty or full includes:
  • the vertical leading edge clamp VFP is increased to delay the high-level read control signal
  • the vertical leading edge clamp VFP is reduced to advance the high-level read control signal.
  • the on-chip memory includes: first-in-first-out FIFO memory or random block memory BRAM.
  • An embodiment of the present disclosure also provides a read timing control device, including: a read and write control circuit and an on-chip memory, wherein: the read and write control circuit is configured to write input data into the on-chip memory.
  • the above input data is detected at the end of the frame. After detecting the end of the frame, the input data lines are counted, and the read timing is generated based on the preset Porch parameters. Based on the input data line count and the generated read timing, it is judged whether the on-chip memory will When the on-chip memory will be read empty or full, adjust the read timing until the on-chip memory will not be read empty or full, and read according to the read timing.
  • the data of the on-chip memory is output; the on-chip memory is configured to store input data.
  • the read timing control device further includes a timing circuit, wherein,
  • the timing circuit is configured to generate a horizontal synchronization signal and a frame synchronization signal according to preset Porch parameters, and generate a data valid signal according to the read timing adjusted by the read-write control circuit.
  • An embodiment of the present disclosure also provides a read timing control device, including a memory; and a processor connected to the memory, the memory is used to store instructions, the memory also includes an on-chip memory, and the processor is configured To perform the steps of the read timing control method described in any embodiment of the present disclosure based on instructions stored in the memory.
  • An embodiment of the present disclosure also provides a computer-readable storage medium on which a computer program is stored.
  • the program is executed by a processor, the read timing control method described in any embodiment of the present disclosure is implemented.
  • Figure 1 is an architectural schematic diagram of an exemplary display drive control system
  • Figure 2 is a schematic diagram of an exemplary implementation of a Porch conversion circuit
  • Figure 3 is a schematic structural diagram of a read timing control device provided by an exemplary embodiment of the present disclosure
  • Figure 4 is a schematic flowchart of an automatic adjustment sequence provided by an exemplary embodiment of the present disclosure
  • Figure 5 is a schematic flowchart of a read timing control method provided by an exemplary embodiment of the present disclosure
  • Figures 6A and 6B are schematic diagrams of two exemplary situations in which the read and write timing intervals are unreasonable in this disclosure
  • FIG. 7A is an improvement effect diagram after adopting the read timing control process of the embodiment of the present disclosure for FIG. 6A;
  • Figure 7B is an improved effect diagram after adopting the read timing control process of the embodiment of the present disclosure for Figure 6B;
  • Figure 8 is a schematic flowchart of another read timing control method provided by an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a read timing control device provided by an exemplary embodiment of the present disclosure.
  • a Porch conversion scheme can be summarized as "frame buffer + double rate synchronous dynamic random access memory (DDR)", and its system implementation architecture is shown in Figure 2.
  • the implementation principle of this method is: according to the preset Porch parameter (ie Porch parameter B in Figure 1), the DE/Hs/Vs signal is generated by the timing (Sync_gen) circuit, where the DE signal is the data valid signal and Hs is Horizontal synchronization signal, Vs is the frame synchronization signal; based on the preset Porch parameters, the read and write control (Write/read Control) circuit generates the read control signal of the DDR memory; the DDR memory then outputs the data signal Data according to the read control signal. Since Data and DE/Hs/Vs are essentially generated based on Porch parameters, synchronization can be achieved in principle. In other words, the output data will indeed satisfy this set of preset Porch parameters.
  • frame buffering that is, the stored data is in frames
  • this can cut off the association between the front-end (i.e. player) input and the back-end (i.e. display panel) as much as possible, that is, the front-end and back-end are respectively They work according to their own timing, and there is almost no intersection except data.
  • the implementation of "frame buffer” requires a larger storage space, so DDR is generally used as the storage solution.
  • DDR read and write operations are relatively complex, resulting in long programming and debugging cycles, which is one of the main factors limiting the application of this solution.
  • Embodiments of the present disclosure propose a read timing control method and device. Since on-chip storage resources are used as an implementation method, the implementation difficulty is greatly reduced, and debugging is basically unnecessary, so the debugging cycle can also be effectively reduced.
  • the embodiment of the present disclosure provides a read timing control device, including: a read and write control circuit 301 and an on-chip memory 302, wherein:
  • the read and write control circuit 301 is configured to write the input data into the on-chip memory 302, detect the end of the frame on the input data, count the input data lines after detecting the end of the frame, and generate the read timing according to the preset Porch parameters. , determine whether the on-chip memory 302 will be read empty or full based on the input data line count and the generated read timing. When the on-chip memory 302 will be read empty or full, adjust the read timing, and read the chip according to the read timing. The data in the internal memory 302 is output;
  • On-chip memory 302 is configured to store input data.
  • the read timing control device in the embodiment of the present disclosure uses on-chip memory as a storage carrier.
  • the on-chip memory is the storage resource of the read timing control device, which greatly simplifies the read and write control timing, greatly reduces the difficulty of implementation, and basically does not require debugging. Therefore, the debugging cycle can also be effectively reduced.
  • the storage capacity of the on-chip memory 302 may be set, however, the embodiments of the present disclosure do not limit this. Since the on-chip memory 302 usually has a limited storage capacity, compared to the "frame cache + DDR" solution, the read timing control device in the embodiment of the present disclosure can be summarized as "line cache + on-chip memory", and it is necessary to ensure that the on-chip memory "is not read” Empty, not filled.” In other words, the correlation of the read and write timings needs to be considered (relatively speaking, the read and write timings of the DDR solution are basically independent), and a reasonable time interval should be maintained between the read and write timings.
  • the read timing control device of the embodiment of the present disclosure adopts a method of automatically adjusting the read and write timing to adjust the read timing, which can ensure that the read and write timing is within a reasonable time interval.
  • the names of the read and write control circuits in Figure 2 and Figure 3 are the same, but their functions are different.
  • the read and write control circuit is used to control the input and output of DDR, and the content will be more complicated.
  • the read and write control circuit 301 is used to control the input and output of the on-chip memory 302 and realize automatic adjustment of the read timing, which is relatively simple overall.
  • the read timing control device also includes a timing circuit 303, wherein the timing circuit 303 is configured to generate the Hs signal and the Vs signal according to the preset Porch parameters, and The DE signal is generated according to the read timing adjusted by the read and write control circuit 303 .
  • the function of the sequential circuit in Figure 2 is to generate the DE signal, Hs signal and Vs signal according to the preset Porch parameters; the function of the sequential circuit 303 in Figure 3 is to generate the Hs signal and Vs signal based on the preset Porch parameters. And the DE signal is generated according to the read timing adjusted by the read and write control circuit 301. Therefore, the functions of the two are also different.
  • the read timing control device in the embodiment of the present disclosure can be implemented through a Field Programmable Gate Array (FPGA) or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or can also be implemented through other programmable devices. There are no restrictions on this.
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Circuit
  • the read and write control circuit 301, the on-chip memory 302 and the sequential circuit 303 can all be implemented by FPGA.
  • the sequential circuit 303 and the read-write control circuit 301 in this disclosure can be implemented by a variety of FPGA code logics. This disclosure only limits the functions of the sequential circuit 303 and the read-write control circuit 301 and does not limit the specific code logic.
  • the on-chip memory 302 may include: FIFO (First Input First Output), random block memory (Block Random Access Memory, BRAM) and other memories.
  • FIFO First Input First Output
  • BRAM Block Random Access Memory
  • the on-chip memory 302 can be implemented using the FIFO IP core that comes with the FPGA.
  • the FIFO IP core that comes with the FPGA usually has an empty and full flag signal (Empty, Full), and this signal can be used as a basis for whether the read timing is reasonable.
  • the on-chip memory 302 can be implemented by BRAM.
  • BRAM is the storage unit that comes with the FPGA chip. Like FIFO, it is a small-capacity storage. Therefore, both BRAM and FIFO can be used as line buffers. In order to prevent full writing or empty reading, the read and write timing needs to be strictly controlled. This is a problem faced by both BRAM and FIFO. Since operations on BRAM usually involve addresses and data, they are slightly more complicated than FIFO operations (which only involve data). But the operation difficulty of both is much less than that of DDR.
  • the read timing control device of the embodiment of the present disclosure can be applied to the Porch conversion circuit in the display driver, and can also be applied to any other scenarios that require Porch conversion or read timing control.
  • the present disclosure does not limit this.
  • the timing circuit 303 generates the DE2 signal, the Hs2 signal and the Vs2 signal according to the preset Porch parameter (ie Porch parameter B in Figure 1) and the read timing adjusted by the read and write control circuit 301.
  • the data is transmitted according to Porch parameter A, that is, the input signals of the Porch conversion circuit are Data1 signal, DE1 signal, Hs1 signal and Vs1 signal.
  • the DE1 signal, Hs1 signal and Vs1 signal are generated by the front end according to Porch parameter A.
  • Read The output signals of the timing control device are Data2 signal, DE2 signal, Hs2 signal and Vs2 signal.
  • the Vs signal is used to mark the starting position of each frame of data
  • the Hs signal is used to mark the starting position of each line of data.
  • the effective video signal (effective RGB signal) only accounts for a part of the signal period, and the row blanking and column blanking periods of the signal do not contain valid video data. Therefore, when some circuits process video signals, they must distinguish between intervals that contain valid video signals and blanking intervals that do not contain valid video signals.
  • a DE signal is set in the circuit.
  • the DE signal is a high-level valid signal, and the video data signal corresponding to the high-level period of the DE signal is considered a valid data signal.
  • DE signal, Hs signal, Vs signal, clock signal CLK and digital signal Data DE signal, Hs signal and Vs signal are synchronization signals
  • CLK is a clock signal
  • Data is a data signal. They generally appear at the same time.
  • the DE signal, Hs signal, Vs signal and digital signal Data are all synchronized with the clock signal CLK.
  • the relevant circuit When the DE signal is at a high level and at the rising edge or falling edge of the clock signal CLK, the relevant circuit reads the RGB data to ensure the accuracy of the read data.
  • the condition for the high level of the DE signal when reading data is actually the meaning of selecting valid data. That is, for the back-end circuit, the read control signal generated according to the read timing is the DE signal.
  • end-of-frame detection is performed on input data, including:
  • the position of the current input data is determined to be the end of the frame position.
  • the input data can be detected at the end of the frame according to the width of the low level of the input DE signal.
  • the input data can be detected based on the falling edge of the previous square wave in the input DE signal and The length of the interval between the rising edges of the next square wave is used to detect the end of the frame of the input data.
  • the width of the low level of the DE signal is approximately hundreds of clock intervals, for example, 100 to 200 clock intervals. Between frames, the width of the low level of the DE signal is approximately thousands of clock intervals, for example, 1000 to 2000 clock intervals. Therefore, the first width threshold may be set to x clock intervals. For example, x may be 800. However, the present disclosure does not limit this.
  • the input data rows are counted according to the rising edge of the input DE signal.
  • the rising edge of the input DE signal can be used as the basis for counting input data rows. As shown in Figure 4, every time a rising edge of the DE signal is detected, it is considered that the input data has increased by one row, that is, the input data row counter increases by 1.
  • the input data line counting only counts valid data and does not count erasing data.
  • there are eight channels of input data The data from the first channel to the eighth channel constitute one frame of data. 000000 represents the erasing data.
  • the input data line counter In the erasing data area, the input data line counter is always 0; In the valid data area, the input data row counter increases from 1 to the maximum number of rows (for example, the maximum number of rows can be 63). Then the next frame of data is transmitted, and the input data line counter is cleared and counting starts again.
  • the read timing is generated based on preset Porch parameters, including:
  • the output row counter and output column counter are counted according to the preset Porch parameters.
  • the output row counter is reset (that is, the value of the output row counter is cleared), and The output row counter restarts counting when the next row of data output begins;
  • the output column counter is reset (that is, the value of the output column counter is cleared), and the output column counter is reset when the next frame of data output begins.
  • the column counter restarts counting;
  • the read timing is generated based on the values of the output row counter and output column counter.
  • the input data line counter does not start counting immediately. It needs to wait until the valid data of the next frame is transmitted and starts to increase by 1 after each line is transmitted.
  • the output row counter (H-direction counter) and output column counter (V-direction counter) will start counting from the detected end of the frame.
  • the H-direction counter counts from 0 to the end of HTotal
  • the V-direction counter counts from 0 to the end of VTotal.
  • the output data is valid only when the H-direction counter is located in the first range and the V-direction counter is located in the second range.
  • the first range may be determined based on the values of the total horizontal row number Htotal, the horizontal trailing edge clamp HBP, and the horizontal leading edge clamp HFP
  • the second range may be determined based on the total vertical row number Vtotal, the vertical leading edge clamp VFP, and the vertical trailing edge clamp The value of bit VBP is determined.
  • the read timing is generated based on the values of the output row counter and the output column counter, including:
  • the first range and the second range are determined according to the preset Porch parameters, where the first range represents the valid data columns of the display panel, the second range represents the valid data rows of the display panel, and the first range and the second range represent the effective data rows of the display panel.
  • Valid data area
  • the read control signal is enabled (that is, the read control signal is set to high level);
  • the read control signal is disabled (that is, the read control signal is set to a low level).
  • the capacity of the on-chip memory is designed to cache only one row of data (in actual use, the capacity of the on-chip memory may be designed to cache multiple rows of data, however, this disclosure does not limit this. ).
  • the read timing relative to the input data row count
  • the amount of data that needs to be cached exceeds one row (as shown by the gray shadow in Figure 4), and the generated read timing is unreasonable.
  • the high-level read control signal in the read sequence can be advanced.
  • FIG. 6A and FIG. 6B are schematic diagrams of two exemplary situations in which the read and write timing intervals are unreasonable in this disclosure.
  • the first category is unreasonable, corresponding to the on-chip memory being read empty.
  • the high-level read control signal is too early (when starting to read, the valid data has not yet appeared);
  • the second category is unreasonable, corresponding to The on-chip memory is full, as shown in Figure 6B, and the high-level read control signal is too delayed (when reading starts, several lines of valid data have passed, and the number of lines has exceeded the on-chip memory capacity).
  • the read timing is adjusted, including:
  • the vertical trailing edge clamp VBP is reduced to advance the high-level read control signal.
  • the read timing is adjusted, including:
  • the vertical leading edge clamp VFP is increased to delay the high-level read control signal
  • the vertical leading edge clamp VFP is reduced to advance the high-level read control signal.
  • an embodiment of the present disclosure also provides a read timing control method, which includes the following steps:
  • Step 801 Write the input data into the on-chip memory
  • Step 802 Perform frame end detection on the input data
  • Step 803 After detecting the end of the frame, count the input data lines and generate a read timing according to the preset Porch parameters;
  • Step 804 Determine whether the on-chip memory will be read empty or full based on the input data line count and the generated read timing
  • Step 805 When the on-chip memory will be read empty or full, adjust the read timing until the on-chip memory will not be read empty or full, and read the data from the on-chip memory for output according to the read timing.
  • the read timing control method of the embodiment of the present disclosure adopts the on-chip memory as the storage carrier.
  • the on-chip memory is the storage resource of the read timing control device. Therefore, the read and write control timing of the embodiment of the present disclosure is greatly simplified, thus achieving The difficulty is greatly reduced, and debugging is basically not required, so the debugging cycle can be effectively reduced.
  • the read timing control method of the embodiment of the present disclosure can be implemented through a Field Programmable Gate Array (FPGA) or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or can also be implemented through other programmable devices.
  • FPGA Field Programmable Gate Array
  • ASIC Application Specific Integrated Circuit
  • the read timing control method in the embodiment of the present disclosure can be implemented by a variety of FPGA code logic.
  • the present disclosure only limits the process of the method and does not limit the specific code logic.
  • the read timing control method of the embodiment of the present disclosure can be used for the Porch conversion circuit in the display driver, and can also be used in other scenarios that require Porch conversion or read timing control.
  • the present disclosure does not limit this.
  • end-of-frame detection is performed on input data, including:
  • the position of the current input data is determined to be the end of the frame position.
  • counting the input data rows includes: counting the input data rows according to a rising edge of the input DE signal.
  • the read timing is generated according to preset Porch parameters, including:
  • the output row counter and output column counter are counted according to the preset Porch parameters.
  • the output row counter is reset, and the output row counter is reset when the next row of data output starts.
  • the output row counter restarts counting; when the output data is at the end of the frame, the output column counter is reset, and the output column counter restarts counting when the next frame data output starts;
  • the read timing is generated based on the values of the output row counter and output column counter.
  • the read timing is generated based on the values of the output row counter and the output column counter, including:
  • the first range and the second range are determined according to the preset Porch parameters, where the first range represents the valid data columns of the display panel, the second range represents the valid data rows of the display panel, and the first range and the second range represent the effective data rows of the display panel.
  • Valid data area
  • the read control signal is set to low level.
  • the first range is determined based on the horizontal total row number Htotal, the horizontal trailing edge clamp HBP, and the horizontal leading edge clamp HFP
  • the second range is determined based on the vertical total row number Vtotal, the vertical leading edge clamp VFP, and the vertical trailing edge clamp Bit VBP is determined.
  • the read timing is adjusted, including:
  • the vertical trailing edge clamp VBP is reduced to advance the high-level read control signal.
  • the read timing is adjusted, including:
  • the vertical leading edge clamp VFP is increased to delay the high-level read control signal
  • the vertical leading edge clamp VFP is reduced to advance the high-level read control signal.
  • the on-chip memory includes: first-in-first-out FIFO memory or random block memory BRAM.
  • Embodiments of the present disclosure also provide a read timing control device.
  • the read timing control device may include a processor and a memory storing a computer program that can be run on the processor. When the processor executes the computer program, the present disclosure is implemented. The steps of the read timing control method as described in the previous item.
  • the read timing control device may include: a processor 910, a memory 920, and a bus system 930.
  • the processor 910 and the memory 920 are connected through the bus system 930, and the memory 920 is used to store instructions.
  • the memory 920 also includes an on-chip memory
  • the processor 910 is used to execute the instructions stored in the memory 920 to write the input data into the on-chip memory; detect the end of the frame on the input data; after detecting the end of the frame, perform the input data line Count and generate read timing based on the preset Porch parameters; determine whether the on-chip memory will be read empty or full based on the input data line count and the generated read timing; when the on-chip memory will be read empty or filled, adjust Read timing, and read the data from the on-chip memory for output according to the read timing.
  • the processor 910 can be a central processing unit (Central Processing Unit, CPU).
  • the processor 910 can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASICs), and off-the-shelf programmable gate arrays. (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
  • Memory 920 may include read-only memory and random access memory and provides instructions and data to processor 910 .
  • a portion of memory 920 may also include non-volatile random access memory.
  • memory 920 may also store device type information.
  • bus system 930 may also include a power bus, a control bus, a status signal bus, etc.
  • bus system 930 may also include a power bus, a control bus, a status signal bus, etc.
  • various buses are labeled bus system 930 in Figure 9.
  • the processing performed by the processing device may be completed by instructions in the form of hardware integrated logic circuits or software in the processor 910 . That is to say, the method steps of the embodiments of the present disclosure may be implemented by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.
  • Software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media.
  • the storage medium is located in the memory 920.
  • the processor 910 reads the information in the memory 920 and completes the steps of the above method in combination with its hardware. To avoid repetition, it will not be described in detail here.
  • Embodiments of the present disclosure also provide a computer-readable storage medium.
  • the computer-readable storage medium stores executable instructions.
  • the read timing control provided by any of the above embodiments of the disclosure can be realized.
  • this read timing control method can write input data into the on-chip memory; detect the end of the frame on the input data; after detecting the end of the frame, count the input data lines and generate the read timing according to the preset Porch parameters; according to Input the data line count and the generated read timing to determine whether the on-chip memory will be read empty or full; when the on-chip memory will be read empty or full, adjust the read timing and read the data in the on-chip memory according to the read timing.
  • the method of driving read timing control by executing executable instructions is basically the same as the read timing control method provided by the above embodiments of the present disclosure, and will not be described again here.
  • various aspects of the read timing control method provided by this application can also be implemented in the form of a program product, which includes program code.
  • the program product When the program product is run on a computer device, the program The code is used to cause the computer device to perform the steps in the read timing control method according to various exemplary embodiments of the present application described above in this specification.
  • the computer device can perform the read timing control described in the embodiments of the present application. method.
  • the program product may take the form of any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to: electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • computer storage media includes volatile and nonvolatile media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. removable, removable and non-removable media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, tapes, disk storage or other magnetic storage devices, or may Any other medium used to store the desired information and that can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

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Abstract

一种读时序控制方法、装置及计算机可读存储介质，所述读时序控制装置包括片内存储器，所述读时序控制方法包括：将输入数据写入片内存储器；对所述输入数据进行帧尾检测；检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序；根据输入数据行计数以及生成的读时序判断所述片内存储器是否会被读空或写满；当片内存储器会被读空或写满时，调整所述读时序直到所述片内存储器不会被读空或写满，并依据所述读时序读取所述片内存储器的数据进行输出。

Description

读时序控制方法、装置及计算机可读存储介质 技术领域
本公开实施例涉及但不限于显示驱动技术领域，尤其涉及一种读时序控制方法、装置及计算机可读存储介质。
背景技术
当显示接口传输数据时，有效数据与起始信号(帧同步信号Vs/行同步信号Hs)间存在一定的位置关系。这种关系通常是以一组Porch参数来表征的。示例性的，Porch参数包括水平总行数(HTotal)、水平有效行数(HActive)、水平同步(HSYNC)、水平后沿箝位(HBack Porch，HBP)、水平前沿箝位(HFront Porch，HFP)、水平消隐(HBlanking)、有效视频结束(EAV)、有效视频开始(SAV)、垂直总行数(VTotal)、垂直有效行数(VActive)、垂直前沿箝位(VFront Porch，VFP)、垂直消隐间隔(VBI)、垂直后沿箝位(VBack Porch，VBP)、垂直消隐(VBlanking)等。其中，VBP表示在一帧图像开始时，帧同步信号以后的无效的行数，VFP表示在一帧图像结束后，帧同步信号以前的无效的行数，HBP表示从行同步信号开始到一行的有效数据开始之间的时钟信号的个数，HFP表示一行的有效数据结束到下一个行同步信号开始之间的时钟信号的个数。
如图1所示，当以现场可编程门阵列(Field Programmable Gate Array，FPGA)作为显示驱动方案时，通常会对数据进行“Porch转换”操作——接收到前端按Porch参数A输入的数据后，将数据以预设的Porch参数B发出去。这样操作的好处在于，在进行显示调试时，常需调节数据源(Data Source)与阵列基板行驱动(Gate Driveron Array，GOA)的相对位置来改善显示效果，基于“Porch转换”(通过修改预设Porch参数)可非常方便地加以实现。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种读时序控制方法，应用于读时序控制装置，所述读时序控制装置包括片内存储器，所述读时序控制方法包括：
将输入数据写入片内存储器；
对所述输入数据进行帧尾检测；
检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序；
根据输入数据行计数以及生成的读时序判断所述片内存储器是否会被读空或写满；
当所述片内存储器会被读空或写满时，调整所述读时序直到片内存储器不会被读空或写满，并依据所述读时序读取所述片内存储器的数据进行输出。
在一些示例性实施方式中，所述对所述输入数据进行帧尾检测，包括：
检测输入的DE信号的低电平的宽度；
当输入的DE信号的低电平的宽度大于或等于预设的第一宽度阈值时，判定当前输入数据的位置为帧尾位置。
在一些示例性实施方式中，对所述输入数据行进行计数，包括：根据输入的DE信号的上升沿，对所述输入数据行进行计数。
在一些示例性实施方式中，所述依据预设的Porch参数生成读时序，包括：
以帧尾为起点，根据预设的Porch参数对输出行计数器和输出列计数器进行计数，当输出数据处于行尾时，对所述输出行计数器进行复位，并在下一行数据输出开始时对所述输出行计数器重新开始计数；当输出数据处于帧尾时，对所述输出列计数器进行复位，并在下一帧数据输出开始时对所述输出列计数器重新开始计数；
根据所述输出行计数器和输出列计数器的值生成读时序。
在一些示例性实施方式中，所述根据所述输出行计数器和输出列计数器的值生成读时序，包括：
根据所述预设的Porch参数确定第一范围和第二范围，其中，所述第一 范围表征显示面板的有效数据列，所述第二范围表征显示面板的有效数据行，所述第一范围和第二范围表征显示面板的有效数据区；
当所述输出行计数器位于第一范围且所述输出列计数器位于第二范围时，置读取控制信号为高电平；
当所述输出行计数器位于第一范围以外或者所述输出列计数器位于第二范围以外时，置读取控制信号为低电平。
在一些示例性实施方式中，所述第一范围根据水平总行数Htotal、水平后沿箝位HBP和水平前沿箝位HFP确定，所述第二范围根据垂直总行数Vtotal、垂直前沿箝位VFP和垂直后沿箝位VBP确定。
在一些示例性实施方式中，所述当片内存储器会被读空或写满时，调整读时序，包括：
当所述片内存储器会被读空时，增大垂直后沿箝位VBP，以将高电平读取控制信号延后；
当所述片内存储器会被写满时，减小垂直后沿箝位VBP，以将高电平读取控制信号提前。
在一些示例性实施方式中，所述当片内存储器会被读空或写满时，调整读时序，包括：
当所述片内存储器会被读空时，增大垂直前沿箝位VFP，以将高电平读取控制信号延后；
当所述片内存储器会被写满时，减小垂直前沿箝位VFP，以将高电平读取控制信号提前。
在一些示例性实施方式中，所述片内存储器包括：先进先出FIFO存储器或随机块存储器BRAM。
本公开实施例还提供了一种读时序控制装置，包括：读写控制电路和片内存储器，其中：所述读写控制电路，被配置为将输入数据写入所述片内存储器，对所述输入数据进行帧尾检测，检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序，根据输入数据行计数以及生成的读时序判断所述片内存储器是否会被读空或写满，当所述片内存储器会被读 空或写满时，调整所述读时序直到所述片内存储器不会被读空或写满，并依据所述读时序读取所述片内存储器的数据进行输出；所述片内存储器，被配置为存储输入数据。
在一些示例性实施方式中，该读时序控制装置还包括时序电路，其中，
所述时序电路，被配置为根据预设的Porch参数，产生行同步信号和帧同步信号，并依据所述读写控制电路调整后的读时序产生数据有效信号。
本公开实施例还提供了一种读时序控制装置，包括存储器；和连接至所述存储器的处理器，所述存储器用于存储指令，所述存储器还包括片内存储器，所述处理器被配置为基于存储在所述存储器中的指令，执行本公开任一实施例所述的读时序控制方法的步骤。
本公开实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现本公开任一实施例所述的读时序控制方法。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种示例性的显示驱动控制系统的架构示意图；
图2为一种示例性的Porch转换电路的实现方案示意图；
图3为本公开示例性实施例提供的一种读时序控制装置的结构示意图；
图4为本公开示例性实施例提供的一种自动调节时序的流程示意图；
图5为本公开示例性实施例提供的一种读时序控制方法的流程示意图；
图6A和图6B为本公开示例性的两种读写时序间隔不合理的情况示意图；
图7A为针对图6A采用本公开实施例的读时序控制流程后的改善效果图；
图7B为针对图6B采用本公开实施例的读时序控制流程后的改善效果图；
图8为本公开示例性实施例提供的另一种读时序控制方法的流程示意图；
图9为本公开示例性实施例提供的一种读时序控制装置的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开实施例公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
一种Porch转换方案可归结为“帧缓存+双倍速率同步动态随机存储器(DDR)”，其系统实现架构如图2所示。该方法的实现原理是：根据预设的Porch参数(即图1中的Porch参数B)，由时序(Sync_gen)电路产生出DE/Hs/Vs信号，其中，DE信号为数据有效信号，Hs为行同步信号，Vs为帧同步信号；基于预设的Porch参数，由读写控制(Write/read Control)电路生成DDR存储器的读取控制信号；DDR存储器再根据读取控制信号输出数据信号Data。由于Data和DE/Hs/Vs本质上都是以Porch参数为基础产生的，因而原理上是可以实现同步的。换言之，输出数据确实会满足这组预设的Porch参数。
由于采用“帧缓存”，也即存储的数据是以帧为单位的，这样可以尽可能地切断前端(即播放器)输入和后端(即显示面板)间的关联，即前端和后端分别按照各自的时序在工作，除了数据外几乎没有任何交集。另外，实现“帧缓存”需以较大的存储空间为基础，因而一般选用DDR作为存储方案。但是，DDR读写操作比较复杂，导致编程和调试周期都较长，这是限制该方案应用 的主要因素之一。
本公开实施例提出一种读时序控制方法和装置，由于采用片内存储资源作为实现方式，因而实现难度大大降低，且基本不用调试，故亦可有效缩减调试周期。
如图3所示，本公开实施例提供了一种读时序控制装置，包括：读写控制电路301和片内存储器302，其中：
读写控制电路301，被配置为将输入数据写入片内存储器302，对输入数据进行帧尾检测，检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序，根据输入数据行计数以及生成的读时序判断片内存储器302是否会被读空或写满，当片内存储器302会被读空或写满时，调整读时序，并依据读时序读取片内存储器302的数据进行输出；
片内存储器302，被配置为存储输入数据。
本公开实施例的读时序控制装置采用片内存储器作为存储载体，片内存储器即为读时序控制装置自带的存储资源，使得读写控制时序大大简化，实现难度大大降低，且基本不用调试，故亦可有效缩减调试周期。
在一些示例性实施方式中，片内存储器302的存储容量可设置，然而，本公开实施例对此不作限制。由于片内存储器302通常存储容量有限，相对于“帧缓存+DDR”方案，本公开实施例的读时序控制装置可归结为“行缓存+片内存储器”，需要保证片内存储器“不被读空、不被写满”。换言之，需要考虑读写时序的关联性(相对而言，DDR方案的读写时序基本是独立的)，读写时序间应保持合理的时间间隔。间隔过大便会导致片内存储器302被写满，有效数据丢失；间隔过小则会导致片内存储器302被读空，有效数据中掺杂错误。针对该问题，本公开实施例的读时序控制装置，采用了一种自动调节读写时序的方法调整读时序，可保证读写时序在合理的时间间隔之内。
图2和图3中的读写控制电路的名称相同，但是作用不尽相同。在DDR存储器方案中，读写控制电路用于控制DDR的输入和输出，内容会比较复杂。在片内存储器方案中，读写控制电路301用于控制片内存储器302的输入和输出，以及实现读时序自动调节，整体上比较简洁。
在一些示例性实施方式中，如图3所示，该读时序控制装置还包括时序电路303，其中，该时序电路303，被配置为根据预设的Porch参数，产生Hs信号和Vs信号，并依据读写控制电路303调整后的读时序产生DE信号。
图2中的时序电路的作用是根据预设的Porch参数，产生DE信号、Hs信号和Vs信号；图3中的时序电路303的作用是根据预设的Porch参数，产生Hs信号和Vs信号，并依据读写控制电路301调整后的读时序产生DE信号，因此，两者的作用也不尽相同。
本公开实施例的读时序控制装置，可以通过现场可编程门阵列(Field Programmable Gate Array，FPGA)或专用集成电路(Application Specific Integrated Circuit，ASIC)实现，也可以通过其他可编程器件实现，本公开对此不作限制。
在一些示例性实施方式中，读写控制电路301、片内存储器302和时序电路303均可以通过FPGA实现。
本公开中的时序电路303和读写控制电路301可以由多种FPGA代码逻辑实现，本公开只限定时序电路303和读写控制电路301的功能，而不对具体代码逻辑做限定。
在一些示例性实施方式中，片内存储器302可以包括：FIFO(First Input First Output)、随机块存储器(Block Random Access Memory，BRAM)等存储器。
示例性的，片内存储器302可以利用FPGA自带的FIFO IP核实现，FPGA自带的FIFO IP核通常会有空满标志信号(Empty，Full)，可用该信号作为读时序是否合理的依据。
示例性的，片内存储器302可以通过BRAM实现。BRAM是FPGA芯片自带的存储单元，和FIFO一样都是小容量储存。因此，BRAM和FIFO都可用作行缓存。为了防止写满或读空，需要严格控制读写时序，这是BRAM和FIFO都会面临的问题。由于对BRAM的操作通常会涉及地址和数据，会比FIFO操作(只涉及数据)略微复杂一些。但两者的操作难度都远小于DDR。
本公开实施例的读时序控制装置，可以应用于显示驱动中的Porch转换 电路，也可以应用于其他任意需要Porch转换或读时序控制的场景，本公开对此不作限制。
如图1和图3所示，时序电路303根据预设的Porch参数(即图1中的Porch参数B)以及读写控制电路301调整后的读时序，产生DE2信号、Hs2信号和Vs2信号。在读时序控制装置之前，数据按照Porch参数A传输，即Porch转换电路的输入信号为Data1信号、DE1信号、Hs1信号和Vs1信号，DE1信号、Hs1信号和Vs1信号由前端根据Porch参数A生成，读时序控制装置的输出信号为Data2信号、DE2信号、Hs2信号和Vs2信号。
在显示数据传输过程中，Vs信号的作用是标识处每帧数据的起点位置，Hs信号的作用是标识处每行数据的起点位置。
在输入到显示面板的视频信号中，有效视频信号(有效RGB信号)只占信号周期中的一部分，而信号的行消隐和列消隐期间并不包含有效的视频数据。因此，一些电路在处理视频信号时，必须将包含有效视频信号的区间和不包含有效视频信号的消隐区间区分开来。为了区分有效和无效视频信号，在电路中设置了DE信号。DE信号是一个高电平有效信号，在DE信号高电平期间所对应的视频数据信号被认为是有效数据信号。
DE信号、Hs信号、Vs信号、时钟信号CLK和数字信号Data这五类信号中，DE信号、Hs信号和Vs信号属于同步信号，CLK属于时钟信号，Data属于数据信号，它们一般都是同时出现的，且DE信号、Hs信号、Vs信号和数字信号Data都与时钟信号CLK保持同步。
当DE信号在高电平期间，且在时钟信号CLK的上升沿或下降沿时，相关电路对RGB数据进行读取，以确保读取数据的正确性。数据读取时DE信号高电平的条件实际上就是选取有效数据的含义，即对后端电路来说，依据读时序生成的读取控制信号即为DE信号。
在一些示例性实施方式中，DE信号的高电平的宽度等于水平有效行数Hactive的值。例如，水平有效行数Hactive＝100，则DE信号的高电平的宽度为100个时钟单位。
在一些示例性实施方式中，对输入数据进行帧尾检测，包括：
检测输入的DE信号的低电平的宽度；
当输入的DE信号的低电平的宽度大于或等于预设的第一宽度阈值时，确定当前输入数据的位置为帧尾位置。
本实施例中，可以根据输入的DE信号的低电平的宽度对输入数据进行帧尾检测，示例性的，如图4所示，可以根据输入的DE信号中上一个方波的下降沿与下一个方波的上升沿间的间隔长短对输入数据进行帧尾检测。
示例性的，在行与行之间，DE信号的低电平的宽度大约为上百个时钟间隔，例如，100到200个时钟间隔。在帧与帧之间，DE信号的低电平的宽度大约为上千个时钟间隔，例如，1000到2000个时钟间隔。因此，第一宽度阈值可以设置为x个时钟间隔，示例性的，x可以为800，然而，本公开对此不作限制。
在一些示例性实施方式中，根据输入的DE信号的上升沿，对输入数据行进行计数。
信号的边缘检测在数字电路领域应用比较广泛。因而，可用输入的DE信号的上升沿作为输入数据行计数的依据，如图4所示，每检测到一次DE信号的上升沿就认为输入数据增加了一行，即输入数据行计数器增加1。
本公开实施例中，输入数据行计数仅对有效数据进行计数，对消影数据不进行计数。如图6A或6B所示，输入数据有八个通道，第一通道至第八通道的数据构成一帧数据，000000表示消影数据，在消影数据区，输入数据行计数器一直为0；在有效数据区，输入数据行计数器从1增长至最大行数(示例性的，最大行数可以为63)。然后传输下一帧数据，输入数据行计数器清零重新开始计数。
在一些示例性实施方式中，如图5所示，依据预设的Porch参数生成读时序，包括：
分别设计一个输出行计数器(H向计数器)和一个输出列计数器(V向计数器)；
以帧尾为起点，根据预设的Porch参数对输出行计数器和输出列计数器进行计数，当输出数据处于行尾时，对输出行计数器进行复位(即输出行计 数器的值被清零)，并在下一行数据输出开始时对输出行计数器重新开始计数；当输出数据处于帧尾时，对输出列计数器进行复位(即输出列计数器的值被清零)，并在下一帧数据输出开始时对输出列计数器重新开始计数；
根据输出行计数器和输出列计数器的值生成读时序。
本公开实施例中，检测到帧尾后，输入数据行计数器并不会马上开始计数，需要等到下一帧的有效数据传输过来且每传输一行后开始加1。而输出行计数器(H向计数器)以及输出列计数器(V向计数器)会以检测到的帧尾这个时间点为起点，开始进行计数。
本公开实施例中，H向计数器从0计数到HTotal结束，V向计数器从0计数到VTotal结束，但只有H向计数器位于第一范围且V向计数器位于第二范围时，输出的数据有效。示例性的，第一范围可以根据水平总行数Htotal、水平后沿箝位HBP和水平前沿箝位HFP的值确定，第二范围可以根据垂直总行数Vtotal、垂直前沿箝位VFP和垂直后沿箝位VBP的值确定。
在一些示例性实施方式中，根据输出行计数器和输出列计数器的值生成读时序，包括：
根据预设的Porch参数确定第一范围和第二范围，其中，第一范围表征显示面板的有效数据列，第二范围表征显示面板的有效数据行，第一范围和第二范围表征显示面板的有效数据区；
当输出行计数器位于第一范围且输出列计数器位于第二范围时，使能读取控制信号(即置读取控制信号为高电平)；
当输出行计数器位于第一范围以外或者输出列计数器位于第二范围以外时，禁能读取控制信号(即置读取控制信号为低电平)。
本公开实施例中，检测输入数据行计数与生成的读时序的位置关系是否会导致片内存储器被读空或写满；当输入数据行计数与生成的读时序的位置关系会导致片内存储器被读空或写满时，生成的读时序不合理。
示例性的，假设在设计时，片内存储器的容量被设计为仅能缓存一行数据(实际使用时，片内存储器的容量可以被设计为能缓存多行数据，然而，本公开对此不作限制)。而在图4中，由于读时序(相对于输入数据行计数) 使能较晚，导致需要缓存的数据量超过了一行(如图4中灰色阴影所示)，则生成的读时序不合理，将读时序中的高电平读取控制信号提前方可。
图6A和图6B为本公开示例性的两种读写时序间隔不合理的情况示意图。第一类不合理，对应片内存储器被读空，如图6A所示，高电平读取控制信号太过提前(开始读的时候，有效数据还未出现)；第二类不合理，对应片内存储器被写满，如图6B所示，高电平读取控制信号太过延后(开始读的时候，有效数据已过去若干行，且行数已超过片内存储器容量)。
在一些示例性实施方式中，当片内存储器会被读空或写满时，调整读时序，包括：
当片内存储器会被读空时，增大垂直后沿箝位VBP，以将高电平读取控制信号延后；
当片内存储器会被写满时，减小垂直后沿箝位VBP，以将高电平读取控制信号提前。
示例性的，针对上述两类不合理，采用自动调节读写时序的方法后，实际的改善情况如图7A和图7B所示。对于第一类不合理，如图7A所示，将VBP调大，会自动将读时序中的高电平读取控制信号延后；对于第二类不合理，如图7B所示，将VBP调小，会自动将读时序中的高电平读取控制信号提前。通过这样的调节，可保证读写时序的时间间隔处于合理范围之内，进而保证数据传输不会出错。
在另一些示例性实施方式中，当片内存储器会被读空或写满时，调整读时序，包括：
当片内存储器会被读空时，增大垂直前沿箝位VFP，以将高电平读取控制信号延后；
当片内存储器会被写满时，减小垂直前沿箝位VFP，以将高电平读取控制信号提前。
如图8所示，本公开实施例还提供了一种读时序控制方法，包括如下步骤：
步骤801、将输入数据写入片内存储器；
步骤802、对输入数据进行帧尾检测；
步骤803、检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序；
步骤804、根据输入数据行计数以及生成的读时序判断片内存储器是否会被读空或写满；
步骤805、当片内存储器会被读空或写满时，调整读时序直到片内存储器不会被读空或写满，并依据读时序读取片内存储器的数据进行输出。
本公开实施例的读时序控制方法，通过采用片内存储器作为存储载体，片内存储器即为读时序控制装置自带的存储资源，因此，本公开实施例的读写控制时序大大简化，因而实现难度大大降低，且基本不用调试，故亦可有效缩减调试周期。
本公开实施例的读时序控制方法，可以通过现场可编程门阵列(Field Programmable Gate Array，FPGA)或专用集成电路(Application Specific Integrated Circuit，ASIC)实现，也可以通过其他可编程器件实现，本公开对此不作限制。
本公开实施例的读时序控制方法可由多种FPGA代码逻辑实现，本公开只限定该方法的流程，而不对具体代码逻辑做限定。
本公开实施例的读时序控制方法，可以用于显示驱动中的Porch转换电路，也可以用于其他需要Porch转换或读时序控制的场景，本公开对此不作限制。
在一些示例性实施方式中，对输入数据进行帧尾检测，包括：
检测输入的DE信号的低电平的宽度；
当输入的DE信号的低电平的宽度大于或等于预设的第一宽度阈值时，判定当前输入数据的位置为帧尾位置。
在一些示例性实施方式中，对输入数据行进行计数，包括：根据输入的DE信号的上升沿，对输入数据行进行计数。
在一些示例性实施方式中，依据预设的Porch参数生成读时序，包括：
以帧尾为起点，根据预设的Porch参数对输出行计数器和输出列计数器进行计数，当输出数据处于行尾时，对所述输出行计数器进行复位，并在下一行数据输出开始时对所述输出行计数器重新开始计数；当输出数据处于帧尾时，对所述输出列计数器进行复位，并在下一帧数据输出开始时对所述输出列计数器重新开始计数；
根据输出行计数器和输出列计数器的值生成读时序。
在一些示例性实施方式中，根据输出行计数器和输出列计数器的值生成读时序，包括：
根据预设的Porch参数确定第一范围和第二范围，其中，第一范围表征显示面板的有效数据列，第二范围表征显示面板的有效数据行，第一范围和第二范围表征显示面板的有效数据区；
当输出行计数器位于第一范围且所述输出列计数器位于第二范围时，置读取控制信号为高电平；
当输出行计数器位于第一范围以外或者所述输出列计数器位于第二范围以外时，置读取控制信号为低电平。
在一些示例性实施方式中，第一范围根据水平总行数Htotal、水平后沿箝位HBP和水平前沿箝位HFP确定，第二范围根据垂直总行数Vtotal、垂直前沿箝位VFP和垂直后沿箝位VBP确定。
在一些示例性实施方式中，当片内存储器会被读空或写满时，调整读时序，包括：
当片内存储器会被读空时，增大垂直后沿箝位VBP，以将高电平读取控制信号延后；
当片内存储器会被写满时，减小垂直后沿箝位VBP，以将高电平读取控制信号提前。
在一些示例性实施方式中，当片内存储器会被读空或写满时，调整读时序，包括：
当片内存储器会被读空时，增大垂直前沿箝位VFP，以将高电平读取控制信号延后；
当片内存储器会被写满时，减小垂直前沿箝位VFP，以将高电平读取控制信号提前。
在一些示例性实施方式中，片内存储器包括：先进先出FIFO存储器或随机块存储器BRAM。
本公开实施例还提供了一种读时序控制装置，该读时序控制装置可包括处理器以及存储有可在处理器上运行的计算机程序的存储器，该处理器执行所述计算机程序时实现本公开中如前任一项所述的读时序控制方法的步骤。
如图9所示，在一个示例中，该读时序控制装置可包括：处理器910、存储器920和总线系统930，其中，处理器910和存储器920通过总线系统930相连，存储器920用于存储指令，存储器920还包括片内存储器，处理器910用于执行存储器920存储的指令，以将输入数据写入片内存储器；对输入数据进行帧尾检测；检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序；根据输入数据行计数以及生成的读时序判断片内存储器是否会被读空或写满；当片内存储器会被读空或写满时，调整读时序，并依据读时序读取片内存储器的数据进行输出。
应理解，处理器910可以是中央处理单元(Central Processing Unit，CPU)，处理器910还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
存储器920可以包括只读存储器和随机存取存储器，并向处理器910提供指令和数据。存储器920的一部分还可以包括非易失性随机存取存储器。例如，存储器920还可以存储设备类型的信息。
总线系统930除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图9中将各种总线都标为总线 系统930。
在实现过程中，处理设备所执行的处理可以通过处理器910中的硬件的集成逻辑电路或者软件形式的指令完成。即本公开实施例的方法步骤可以体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等存储介质中。该存储介质位于存储器920，处理器910读取存储器920中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
本公开实施例还提供了一种计算机可读存储介质，该计算机可读存储介质存储有可执行指令，该可执行指令被处理器执行时可以实现本公开上述任一实施例提供的读时序控制方法，该读时序控制方法可以将输入数据写入片内存储器；对输入数据进行帧尾检测；检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序；根据输入数据行计数以及生成的读时序判断片内存储器是否会被读空或写满；当片内存储器会被读空或写满时，调整读时序，并依据读时序读取片内存储器的数据进行输出，从而使读写控制时序大大简化，实现难度大大降低，且基本不用调试，从而可以有效缩减调试周期。通过执行可执行指令驱动读时序控制的方法与本公开上述实施例提供的读时序控制方法基本相同，在此不做赘述。
在一些可能的实施方式中，本申请提供的读时序控制方法的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序产品在计算机设备上运行时，所述程序代码用于使所述计算机设备执行本说明书上述描述的根据本申请各种示例性实施方式的读时序控制方法中的步骤，例如，所述计算机设备可以执行本申请实施例所记载的读时序控制方法。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以是但不限于：电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、 可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (13)

  1. 一种读时序控制方法，应用于读时序控制装置，所述读时序控制装置包括片内存储器，所述读时序控制方法包括：
    将输入数据写入片内存储器；
    对所述输入数据进行帧尾检测；
    检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序；
    根据输入数据行计数以及生成的读时序判断所述片内存储器是否会被读空或写满；
    当片内存储器会被读空或写满时，调整所述读时序直到所述片内存储器不会被读空或写满，并依据所述读时序读取所述片内存储器的数据进行输出。
  2. 根据权利要求1所述的读时序控制方法，其中，所述对所述输入数据进行帧尾检测，包括：
    检测输入的数据有效信号的低电平的宽度；
    当输入的数据有效信号的低电平的宽度大于或等于预设的第一宽度阈值时，判定当前输入数据的位置为帧尾位置。
  3. 根据权利要求1所述的读时序控制方法，其中，对所述输入数据行进行计数，包括：根据输入的数据有效信号的上升沿，对所述输入数据行进行计数。
  4. 根据权利要求1所述的读时序控制方法，其中，所述依据预设的Porch参数生成读时序，包括：
    以帧尾为起点，根据预设的Porch参数对输出行计数器和输出列计数器进行计数，当输出数据处于行尾时，对所述输出行计数器进行复位，并在下一行数据输出开始时对所述输出行计数器重新开始计数；当输出数据处于帧尾时，对所述输出列计数器进行复位，并在下一帧数据输出开始时对所述输出列计数器重新开始计数；
    根据所述输出行计数器和输出列计数器的值生成读时序。
  5. 根据权利要求4所述的读时序控制方法，其中，所述根据所述输出行计数器和输出列计数器的值生成读时序，包括：
    根据所述预设的Porch参数确定第一范围和第二范围，其中，所述第一范围表征显示面板的有效数据列，所述第二范围表征显示面板的有效数据行，所述第一范围和第二范围表征显示面板的有效数据区；
    当所述输出行计数器位于第一范围且所述输出列计数器位于第二范围时，置读取控制信号为高电平；
    当所述输出行计数器位于第一范围以外或者所述输出列计数器位于第二范围以外时，置读取控制信号为低电平。
  6. 根据权利要求5所述的读时序控制方法，其中，所述第一范围根据水平总行数Htotal、水平后沿箝位HBP和水平前沿箝位HFP确定，所述第二范围根据垂直总行数Vtotal、垂直前沿箝位VFP和垂直后沿箝位VBP确定。
  7. 根据权利要求6所述的读时序控制方法，其中，所述当片内存储器会被读空或写满时，调整读时序，包括：
    当所述片内存储器会被读空时，增大垂直后沿箝位VBP，以将高电平读取控制信号延后；
    当所述片内存储器会被写满时，减小垂直后沿箝位VBP，以将高电平读取控制信号提前。
  8. 根据权利要求6所述的读时序控制方法，其中，所述当片内存储器会被读空或写满时，调整读时序，包括：
    当所述片内存储器会被读空时，增大垂直前沿箝位VFP，以将高电平读取控制信号延后；
    当所述片内存储器会被写满时，减小垂直前沿箝位VFP，以将高电平读取控制信号提前。
  9. 根据权利要求1所述的读时序控制方法，其中，所述片内存储器包括： 先进先出FIFO存储器或随机块存储器BRAM。
  10. 一种读时序控制装置，包括存储器；和连接至所述存储器的处理器，所述存储器用于存储指令，所述存储器还包括片内存储器，所述处理器被配置为基于存储在所述存储器中的指令，执行如权利要求1至9中任一项所述的读时序控制方法的步骤。
  11. 一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现如权利要求1至9中任一项所述的读时序控制方法。
  12. 一种读时序控制装置，包括：读写控制电路和片内存储器，其中：
    所述读写控制电路，被配置为将输入数据写入所述片内存储器，对所述输入数据进行帧尾检测，检测到帧尾后，对输入数据行进行计数，并依据预设的Porch参数生成读时序，根据输入数据行计数以及生成的读时序判断所述片内存储器是否会被读空或写满，当所述片内存储器会被读空或写满时，调整所述读时序直到所述片内存储器不会被读空或写满，并依据所述读时序读取所述片内存储器的数据进行输出；
    所述片内存储器，被配置为存储输入数据。
  13. 根据权利要求12所述的读时序控制装置，还包括时序电路，其中，
    所述时序电路，被配置为根据预设的Porch参数，产生行同步信号和帧同步信号，并依据所述读写控制电路调整后的读时序产生数据有效信号。
PCT/CN2022/088597 2022-04-22 2022-04-22 读时序控制方法、装置及计算机可读存储介质 WO2023201731A1 (zh)

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CN101246460A (zh) * 2008-03-10 2008-08-20 华为技术有限公司 缓存数据写入系统及方法和缓存数据读取系统及方法
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CN102855838A (zh) * 2011-06-30 2013-01-02 上海天马微电子有限公司 用于显示器的时序控制器
CN112218012A (zh) * 2020-09-25 2021-01-12 中国科学院合肥物质科学研究院 减小帧转移ccd时钟噪声的时序控制方法、系统及存储介质

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CN101789222A (zh) * 2009-01-22 2010-07-28 联咏科技股份有限公司 用数据使能信号控制显示器时序的方法及时序控制电路
CN102855838A (zh) * 2011-06-30 2013-01-02 上海天马微电子有限公司 用于显示器的时序控制器
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