WO2023201448A1

WO2023201448A1 - Semiconductor element and manufacturing method therefor

Info

Publication number: WO2023201448A1
Application number: PCT/CN2022/000066
Authority: WO
Inventors: 陈志濠; 沈依如
Original assignee: 嘉和半导体股份有限公司
Priority date: 2022-04-19
Filing date: 2022-04-19
Publication date: 2023-10-26

Abstract

A semiconductor element (100), comprising a semiconductor stack (104), an insulation structure (114), an electrode structure (130) and a protective layer (120), wherein the insulation structure (114) is arranged on the semiconductor stack (104), and comprises a first part (116); the first part (116) comprises a first opening (170), the first opening (170) exposing an inner side wall (162) of the insulation structure (114); the protective layer (120) is arranged between the inner side wall (162) and the electrode structure (130), and comprises a second opening (172); the electrode structure (130) is arranged in the first opening (170), is in contact with the protective layer (120), and is electrically connected to the semiconductor stack (104) by means of the second opening (172); and the electrode structure (130) comprises a metal material, the insulation structure (114) comprises a first material, the protective layer (120) comprises a second material, and the reaction temperature between the second material and the metal material is higher than the reaction temperature between the first material and the metal material. Further disclosed is a manufacturing method for the semiconductor element.

Description

Semiconductor components and manufacturing methods

Technical field

The present invention relates to a semiconductor element, in particular to a semiconductor element with an electrode structure and a manufacturing method thereof.

Background technique

In semiconductor technology, III-V compound semiconductors, such as gallium nitride (GaN), have material properties of low on-resistance and high breakdown voltage. High electron mobility transistors made of III-V compound semiconductor materials (high electron mobility transistor, HEMT), can be used to form various integrated circuit devices, such as high-power field effect transistors or high-frequency transistors. HEMT includes compound semiconductor layers with different energy gaps stacked on each other, such as a high energy gap semiconductor layer and a low energy gap semiconductor layer, to have a heterojunction. This heterojunction with discontinuous energy levels will cause two-dimensional electron gas (2-DEG) to form near the heterojunction, thereby transporting carriers in the HEMT. Since HEMT does not use a doped region as the carrier channel of the transistor, but uses 2-DEG as the carrier channel of the transistor, compared with the existing metal oxide semi-field effect transistor (MOSFET), HEMT has many attractive features. Characteristics, such as high electron mobility and the ability to transmit high-frequency signals.

For existing HEMTs, the electrode structure is electrically connected to the semiconductor layer below it, causing current to flow between the electrode structure and the semiconductor layer. However, when current flows through the electrode structure and the semiconductor layer, power loss often occurs, which reduces the electrical performance of the device.

Contents of the invention

In view of this, it is necessary to propose an improved semiconductor device to improve the shortcomings of existing semiconductor devices.

According to some embodiments of the present invention, a semiconductor component is provided, including a semiconductor stack, an insulating structure, an electrode structure and a protective layer. The insulating structure is disposed on the semiconductor stack and includes the first portion. The first portion includes a first opening, and the first opening exposes the inner sidewall of the insulation structure. The protective layer is disposed between the inner wall and the electrode structure and includes a second opening. Wherein, the electrode structure contains metal material. The electrode structure is disposed in the first opening and contacts the protective layer, and is electrically connected to the semiconductor stack through the second opening. The insulating structure includes a first material, the protective layer includes a second material, and the reaction temperature between the second material and the metal material is higher than the reaction temperature between the first material and the metal material.

According to some embodiments of the present invention, a method of manufacturing a semiconductor device is provided, including the following steps. Provides semiconductor stacks. Next, a first insulating layer is disposed on the semiconductor stack, wherein the first insulating layer includes a first opening, and the first opening exposes the inner sidewall of the insulating structure. Fill the first opening with a protective layer and cover the inner wall. The protective layer is subsequently etched to remove part of the protective layer located within the first opening to form a second opening. Then the electrode structure is set so that the protective layer is sandwiched between the electrode structure and the inner wall. Then a heat treatment process is carried out. The first insulating layer includes a first material, the protective layer includes a second material, and the electrode structure includes a metal material. There is a first reaction temperature between the first material and the metal material, and there is a second reaction between the second material and the metal material. temperature, the second reaction temperature is greater than the first reaction temperature, and the temperature of the heat treatment is higher than the first reaction temperature and lower than the second reaction temperature.

In order to have a better understanding of the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings.

Description of the drawings

In order to make the following easier to understand, the drawings and their detailed descriptions may be referred to simultaneously when reading the present invention. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail, and the working principles of the specific embodiments of the present invention are explained. In addition, features in the drawings may not be drawn to actual scale for the sake of clarity, and therefore the dimensions of some features in some drawings may be intentionally exaggerated or reduced.

FIG. 1 is a schematic cross-sectional view of a semiconductor element according to an embodiment of the present invention, wherein the semiconductor element includes a protective layer disposed between an electrode structure and an insulating structure.

2 is a schematic cross-sectional view of a partial region of a semiconductor device according to a modified embodiment of the present invention.

3 to 9 are schematic cross-sectional views of semiconductor device fabrication according to embodiments of the present invention.

FIG. 10 is a flow chart of manufacturing a semiconductor device according to an embodiment of the present invention.

Explanation of reference signs: 100-semiconductor element; 102-substrate; 104-semiconductor stack; 106-buffer layer; 108-channel layer; 109-two-dimensional electron gas region; 110-barrier layer; 112-cap layer; 114 -Insulation structure; 116-first part; 117-end part; 118-second part; 119-extension part; 120-protective layer; 121-recessed part; 123-extension part; 130-electrode structure; 132-drain electrode ; 134-source electrode; 136-gate electrode; 140-interlayer dielectric layer; 150-pad structure; 162-inside wall; 164-top surface; 170-first opening; 172-second opening; 174 - Groove; 180-platform area; 182-first contact port; 184-second contact port; 186-third contact port; 200-semiconductor component; 300-section; 302-section; 304-section; 306-section ; 308-section; 310-section; 312-section; 400- production method; 402-step; 404-step; 406-step; 408-step; 410-step; 412-step; W1-first width; W2- Second width; W3-third width.

Detailed ways

The invention provides several different embodiments for implementing different features of the invention. For simplicity of explanation, examples of specific components and arrangements are also described herein. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or above the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". There are other features between the features", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated reference symbols and/or textual notations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.

In addition, the spatially related descriptive words mentioned in the present invention, such as: "under", "low", "lower", "above", "above", "lower", "top" ", "bottom" and similar words are used to describe the relative relationship between one element or feature and another element or feature in the drawings for the convenience of description. In addition to the orientations shown in the drawings, these spatially related terms are also used to describe possible orientations of semiconductor components during use and operation. As a semiconductor device is oriented differently (rotated 90 degrees or at other orientations), the spatially related description used to describe its orientation should be interpreted in a similar manner.

Although the present invention uses first, second, third, etc. terms to describe various elements, components, regions, layers and/or sections, it should be understood that these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or block from another element, component, region, layer and/or block and do not in themselves mean that the element has any prefix. Ordinal numbers do not represent the arrangement order between one component and another component, or the order in the manufacturing method. Therefore, a first element, component, region, layer or block discussed below can also be termed as a second element, component, region, layer or block without departing from the scope of the specific embodiments of the invention.

The terms "about" or "substantially" mentioned in the present invention usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, without specifically stating "about" or "substantially", the meaning of "about" or "substantially" may still be implied.

In the present invention, "III-V semiconductor" refers to a compound semiconductor containing at least one Group III element and at least one Group V element. Among them, group III elements can be boron (B), aluminum (Al), gallium (Ga) or indium (In), while group V elements can be nitrogen (N), phosphorus (P), arsenic (As) or antimony ( Sb). Furthermore, the "III-V semiconductor" may be a binary compound semiconductor, a ternary compound semiconductor, a quaternary compound semiconductor, a quaternary or higher compound semiconductor, or a combination thereof, but is not limited thereto. For example, it may be aluminum nitride ( AlN), gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs) and other binary compound semiconductors; aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) ), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs) and other ternary semiconductor compounds; or indium aluminum gallium nitride (InAlGaN) or other of quaternary compound semiconductors. Depending on the requirements, the III-V semiconductor may also include dopants and have a specific conductivity type, such as N-type or P-type.

Although the present invention is described below through specific embodiments, the inventive principles of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and these omitted details fall within the scope of knowledge of those with ordinary skill in the art.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1 , a semiconductor device 100 , such as a high electron mobility transistor, includes a semiconductor stack 104 , an insulating structure 114 , an electrode structure 130 and a protective layer 120 . The insulating structure 114 is disposed over the semiconductor stack 104 and includes the first portion 116 . The first portion 116 includes a first opening 170 , and the first opening 170 exposes the inner sidewall 162 of the insulating structure 114 . The protective layer 120 is disposed between the inner wall 162 and the electrode structure 130 and includes a second opening 172 . The electrode structure 130 is disposed in the first opening 170 , contacts the protective layer 120 , and is electrically connected to the semiconductor stack 104 through the second opening 172 . The electrode structure 130 includes a metal material, the insulation structure 114 includes a first material, the protective layer 120 includes a second material, and the reaction temperature between the second material and the metal material is higher than the reaction temperature between the first material and the metal material.

According to some embodiments of the present invention, since the protective layer 120 will be disposed between the electrode structure 130 and the first part 116 of the insulating structure 114, and the second material constituting the protective layer 120 is selected to be between the metal material of the electrode structure 130 Materials with a reaction temperature higher than the reaction temperature between the first material of the insulating structure 114 and the metal material of the electrode structure 130 . The protective layer 120 composed of the above-mentioned selected materials can prevent the electrode structure 130 from directly contacting the first portion 116 of the insulating structure 114 and avoid unnecessary chemical reactions (such as oxidation reactions). In this way, the increase in contact resistance caused by the chemical reaction between the electrode structure 130 and the underlying semiconductor layer can be avoided.

In addition to the above-mentioned components and layers, the semiconductor device 100 may further include other optional components and layers. Each component and layer in the semiconductor device 100 is further described below.

Referring to FIG. 1 , a semiconductor device 100 includes a substrate 102 , which may be an epitaxial substrate (eg, a bulk silicon substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire substrate), a ceramic substrate, or an insulating substrate. The semiconductor substrate is covered by a layer (such as a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate), but is not limited thereto. The entirety or surface of the substrate 102 is electrically insulating, thereby avoiding unnecessary electrical connections between structures respectively disposed above and below the substrate 102 . According to some embodiments of the present invention, the entirety or surface of the substrate 102 may be electrically insulating, thereby further avoiding unnecessary electrical connections between structures respectively disposed above and below the substrate 102 . However, according to other embodiments of the present invention, the substrate 102 may also be conductive and is not limited to an insulating substrate. According to some embodiments, the substrate 102 may also be removed such that the bottom surface of the semiconductor stack 104 is exposed.

The semiconductor stack 104 is disposed on the substrate 102 and includes multiple III-V semiconductor layers. For example, the semiconductor stack 104 includes a buffer layer 106, a channel layer 108 and a barrier layer 110 in order from bottom to top. The buffer layer 106 may be used to reduce the degree of stress or lattice mismatch that exists between the substrate 102 and the semiconductor stack 104. The buffer layer 106 may include a plurality of III-V sub-semiconductors that may constitute the composition. Composition ratio gradient layers or super lattice structure. Among them, the composition gradient layer means that the composition ratio of adjacent sub-semiconductor layers will continue to change along a certain direction, such as aluminum gallium nitride (Al _x Ga _(1-x) N) with a gradient composition ratio, and the composition ratio will continue to change along a certain direction. Moving away from the substrate 102 , the X value decreases in a continuous or stepwise manner. The superlattice structure contains alternately stacked sub-semiconductor layers with slightly different composition ratios. These sub-semiconductor layers are adjacent to each other and appear in pairs (for example, pairs of Al _x1 Ga _(1-x1) N and Al _x2 Ga _{(1- x2)} N, 0≤X1≤0.2, 0.2≤X2≤0.5), as the smallest repeating unit in the superlattice structure.

The channel layer 108 will be disposed on the substrate 102, for example, on the buffer layer 106. The channel layer 108 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layer may be GaN, AlGaN, InGaN or InAlGaN, but is not limited thereto. For example, the channel layer 108 is an undoped III-V semiconductor, such as undoped GaN (undoped-GaN, u-GaN).

The barrier layer 110 will be disposed on the channel layer 108 . Barrier layer 110 may include one or more III-V semiconductor layers, and its composition may be different from that of the III-V semiconductor of channel layer 108 . For example, the material of the barrier layer 110 may include a material with an energy gap larger than that of the channel layer 114 , such as AlN, Al _x Ga _(1-x) N (0<x<1), or a combination thereof. According to an embodiment, the barrier layer 110 may be an N-type III-V semiconductor, such as an AlGaN layer that is N-type in nature, but is not limited thereto.

Since the channel layer 108 and the barrier layer 110 have a discontinuous energy gap, by stacking the channel layer 108 and the barrier layer 110 on top of each other, a heterojunction is formed in the channel layer 114 close to the heterojunction between the channel layer 108 and the barrier layer 116 . Potential energy wells. Electrons will be gathered in potential energy wells due to the piezoelectric effect, thus producing a thin layer with high electron mobility, which is the two-dimensional electron gas (2-DEG) region 109.

According to different requirements, the semiconductor stack 104 may include other semiconductor layers, such as a III-V semiconductor layer disposed between the substrate 102 and the buffer layer 106, or between the buffer layer 106 and the barrier layer 110. For example, the semiconductor stack 104 may further include a nucleation layer (not shown) or a high-resistance layer (not shown). The nucleation layer is a group III-V semiconductor layer, such as a nitride semiconductor layer such as AlN, which allows the semiconductor layer disposed above the nucleation layer to have better crystallinity. A high-resistance layer, such as carbon-doped gallium nitride (c-GaN), will be disposed on the buffer layer 106. It has a higher resistivity than other layers, so it can be avoided to be disposed on the high-resistance layer. A leakage current is generated between the semiconductor layer and the substrate 102.

The capping layer 112 will be disposed on the semiconductor stack 104 and is located between the insulating structure 114 and the semiconductor stack 104. It can be used to eliminate or reduce surface defects existing on the surface of the barrier layer 110, thereby improving the two-dimensional electron gas. Electron mobility in region 109. The capping layer 112 can also be used to protect the underlying semiconductor stack 104 to prevent the semiconductor stack 104 from being damaged during an etching process, such as a contact etching process. Referring to the enlarged partial view of the lower part of FIG. 1 , the cover layer 112 includes a recessed portion 121 and an extending portion 123 , and the extending portion 123 is provided on the periphery of the recessed portion 121 . The bottom surface of the recessed portion 121 has a width, such as a third width W3. The extension 123 includes a nitride insulating material, such as silicon nitride (SiN). The material of the recess 121 includes the same elements as the extension 123 , such as silicon and nitrogen, but the recess 121 additionally includes a conductive component. For example, metal components such as aluminum, tungsten, titanium, vanadium, zirconium, tantalum or their alloys make the overall electrical conductivity of the recessed portion 121 higher than that of the extended portion 123 (that is, the resistivity of the extended portion 123 is higher than that of the recessed portion 121 resistivity).

The insulation structure 114 will be disposed on the capping layer 112 . In addition to the first part 116 , the insulation structure 114 further includes a second part 118 , and the second part 118 is disposed above the first part 116 . Referring to the enlarged partial view of the lower part of FIG. 1 , the bottom surface of the first opening 170 of the first part 116 has a first width W1. The inner side wall 162 of the first part 116 is an inclined surface or an upper concave surface, and the first part 116 also includes a top surface 164 (or referred to as an upper surface). The composition materials of the first part 116 (ie, the first material) and the second part 118 may be different from the composition materials of the capping layer 112 . The first material of the first part 116 may include an oxide insulating material, such as silicon oxide or silicon oxynitride; the constituent material of the second part 118 may also include an oxide insulating material, and may be the same as or different from the first material.

The protective layer 120 is disposed on the first part 116 of the insulating structure 114, so that a part of the protective layer 120 will fill the first opening 170 of the first part 116, and cover the inner side wall 162 of the first part 116; the protective layer 120 The other parts will extend beyond the first opening 170 and cover part of the top surface 164 of the first part 116 . The two opposite protective layers 120 define a second opening 172, and the bottom surface of the second opening 172 has a second width W2. Although the protective layers 120 are separated from each other in FIG. 1 , when viewed from a top view, the two opposite protective layers 120 are connected to each other to form a continuous layer, and both of them will surround the second opening 172 together. The second material of the protective layer 120 may include a nitride material, such as titanium nitride, vanadium nitride, zirconium nitride or tantalum nitride, and may be a single-layer or multi-layer structure, such as a Ti/TiN stack structure.

Electrode structures 130, such as drain electrodes 132 and source electrodes 134, are disposed on the capping layer 112. In addition to filling the second opening 172, the electrode structure 130 also fills the groove 174 in the cap layer 104 to electrically connect the semiconductor layers below it, such as the channel layer 108 and the barrier layer 110. Among them, the electrode structure 130 will have ohmic contact with the underlying capping layer 112 and some layers in the semiconductor stack 104 (such as the channel layer 108). The material of the electrode structure 130 is a low-resistance metal, such as aluminum, but is not limited thereto.

The following describes the arrangement relationship between the capping layer 112, the insulating structure 114 (including the first part 116 and the second part 118), the protective layer 120 and the electrode structure 130. Referring to the enlarged partial view of the lower part of FIG. 1 , the recessed portion 121 of the cover layer 112 will be located below the first opening 170 of the first part 116 and the second opening 172 of the protective layer 120 , and overlap with the second opening 172 , so that the cover layer The recessed portion 121 of 112 is exposed from the bottom surface of the second opening 172 . The protective layer 120 will be sandwiched between the electrode structure 130 and the first part 116, so that the electrode structure 130 will be completely separated from the first part 116 and will not be in direct contact. In addition, the protective layer 120 extending beyond the first opening 170 is interposed between the top surface 164 of the first portion 116 of the insulating structure 114 and the electrode structure 130 . The second part 118 will cover the top surface 164 of the first part 116 , the upper sidewalls and top surface of the protective layer 120 , and the upper sidewalls and top surface of the electrode structure 130 .

Regarding the materials of the first part 116 of the insulating structure 114, the protective layer 120 and the electrode structure 130, when the material of the electrode structure 130 is a conductive material that is easily oxidized (for example, a metal with a work function between 4.0eV and 4.4eV), It is easy to react chemically (such as oxidation reaction) with the non-metallic components in the first part 116 to generate products with lower conductivity (such as metal oxides). In order to avoid the formation of this low conductivity product, the protective layer 120 will be disposed between the electrode structure 130 and the first part 116, and the reaction temperature between the second material of the protective layer 120 and the electrode structure 130 will be higher than the insulation temperature. The reaction temperature between the first material of the structure 114 and the electrode structure 130 prevents the electrode structure 130 from directly contacting the first portion 116 of the insulating structure 114 . In this case, a chemical reaction between the electrode structure 130 and the first portion 116 of the adjacent insulating structure 114 can be avoided, thereby preventing the resistivity of the electrode structure 130 itself from increasing. In some embodiments, the reaction temperature between the second material of the protective layer 120 and the electrode structure 130 is so high that there is no reaction between the second material of the protective layer 120 and the metal material of the electrode structure 130 . In this case, the electrode structure 130 can be prevented from directly contacting the first portion 116 of the insulating structure 114 to produce chemical reactions.

The semiconductor device 100 may include an additional conductive layer, such as a gate electrode 136, disposed on one side of the electrode structure 130, for example, between two electrode structures 130. The gate electrode 136 will be disposed on the capping layer 112 and fill the contact opening in the insulating structure 114, so that part of the gate electrode 136 will penetrate the first portion 116 and the second portion 118 of the insulating structure 114. Furthermore, the gate electrode 136 has an asymmetric structure, and the gate electrode 136 extends toward the drain electrode 132 . The extended portion and the corresponding end will cover the first portion 116 and the second portion 118 of the insulating structure 114 and serve as a field plate of the semiconductor device 100 to regulate the electric field distribution and/or the electric field peak size in the underlying semiconductor stack 104

According to some embodiments of the present invention, the gate electrode 136, the capping layer 112 located directly below the gate electrode 136, and the channel layer 108 located below the gate electrode 136 form a metal-insulator-semiconductor (MIS). ) capacitor structure. In this case, when the semiconductor device 100 is operated, current will be blocked by the capping layer 112 and will not flow between the electrode 130 and the channel layer 108 . In addition, according to some embodiments of the present invention, the gate electrode 136 may penetrate the capping layer 112 to directly contact the barrier layer 110 and form a Schottky contact structure with the barrier layer 110 . In this case, when the semiconductor device 100 is operated, current cannot easily flow through the Schottky contact junction formed between the gate electrode 136 and the barrier layer 110 .

A third insulating layer, such as the interlayer dielectric layer 140 , is disposed on the insulating structure 114 and the gate electrode 136 . The interlayer dielectric layer 140 includes contact openings to expose the underlying drain electrode 132 and the source electrode 134 respectively.

At least two bonding pad structures 150 will be disposed in contact openings in the interlayer dielectric layer 140 to be electrically connected to the drain electrode 132 and the source electrode 134 respectively. The top surface of the bonding pad structure 150 will be exposed between layers. The dielectric layer 140 serves as a region for electrical connection between the semiconductor component 100 and external components. The semiconductor device 100 may also include another bonding pad structure (not shown) electrically connected to the electrode structure (for example, the gate electrode 136). The composition of the interlayer dielectric layer 140 includes insulating materials, such as nitride insulating materials such as Si ₃ N ₄ and AlN, and oxide insulating materials such as Al ₂ O ₃ , SiON, and SiO ₂ , but is not limited thereto.

In addition to the above embodiments, the semiconductor device of the present invention may also have other implementation forms, which are not limited to the above. Variations of the semiconductor element will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments in detail, and will not repeat the same details. In addition, various embodiments of the present invention may use repeated reference symbols and/or textual notations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.

2 is a schematic cross-sectional view of a partial region of a semiconductor device according to a modified embodiment of the present invention. As shown in FIG. 2 , the structure of the semiconductor device 200 of FIG. 2 is similar to the structure of the semiconductor device 100 of FIG. 1 . The main difference between the two is that the first part 116 of the insulation structure of FIG. 2 further includes an end portion 117 and an extension. Department 119. The end portion 117 is disposed between the semiconductor stack 104 and the protective layer 120, and the extension portion 119 extends from one side of the end portion 117, and the top surface of the end portion 117 is higher than the top surface of the extension portion 119. In this case, even if the top surface of the end portion 117 is higher than the top surface of the extension portion 119 , the extension portion 119 still covers the top surface and sidewalls of the semiconductor stack 104 .

In order to enable those with ordinary knowledge in the art to implement the present invention, the manufacturing method of the semiconductor element of the present invention is further described in detail below.

3 to 9 are schematic cross-sectional views of semiconductor device fabrication according to embodiments of the present invention. FIG. 10 is a flow chart of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to cross-section 300 of FIG. 3 , in step 402 of the manufacturing method 400 , a semiconductor stack is provided, for example, the semiconductor stack 104 is provided on the substrate 102 . Each semiconductor layer in the semiconductor stack 104 is sequentially formed on the surface of the substrate 102 through an epitaxial or deposition process. For example, molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), Atomic layer deposition (ALD) or other suitable methods are used to form each semiconductor layer in the semiconductor stack 104 . After the semiconductor stack 104 is formed, a cap layer 112 is formed on the semiconductor stack 104 by, for example, performing a vapor deposition process to form the cap layer 112 . In the subsequent etching process, the capping layer 112 will serve as an etching stop layer. In addition, the capping layer 112 can also serve as a passivation layer to protect the underlying semiconductor stack 104 . For example, the material of the capping layer 112 includes nitride insulating materials (such as silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), aluminum nitride (AlN)), oxide insulating materials (such as aluminum oxide ( Al ₂ O ₃ ), silicon oxide (SiO _x )) or semiconductor material (such as gallium nitride (GaN)), but is not limited thereto. Next, an etching process is performed to remove part of the cap layer 112 and part of the semiconductor stack 104 to form a protruding mesa 180. This mesa 180 will be used to accommodate the gate electrode of the semiconductor device. , source electrode and drain electrode.

Next, in step 404 of the manufacturing method 400, a first insulating layer is disposed on the semiconductor stack, wherein the first insulating layer includes a first opening, and the first opening exposes the inner sidewall of the first insulating structure. As shown in cross-section 302 of FIG. 4 , a deposition process, such as a vapor deposition process, is performed to form a first insulating layer, such as the first portion 116 , covering the semiconductor stack 104 and the capping layer 112 . The material of the first part 116 may be different from the material of the capping layer 112 . For example, the material of the first part 116 may include silicon oxide (SiO _x ) or aluminum oxide (Al ₂ O ₃ ) oxide insulating material, or silicon nitride (Si). ₃ N ₄ ), silicon oxynitride (SiON) nitride insulating material, but is not limited thereto. In addition, the first part 116 is not limited to a single-layer structure, but may also be a multi-layer stacked structure. After the first portion 116 is formed, a partial area of the first portion 116 is etched through to form the first opening 170 . The bottom surface of the first opening 170 has a first width W1, which exposes the inner sidewall 162 of the first insulating layer (eg, the first portion 116) and exposes the underlying cover layer 112.

Afterwards, in step 406 of the manufacturing method 400, a protective layer is filled into the first opening and covers the inner side wall. As shown in cross-section 304 of FIG. 5 , the protective layer 120 will be formed on the surface of the first part 116 in a direction to cover the inner wall 162 and the top surface 164 of the first part 116 and fill the first opening 170 . Since the thickness of the first part 116 is greater than the thickness of the protective layer 120 , the first opening 170 will not be filled by the first part 116 .

Next, in step 408 of the manufacturing method 400, the protective layer is etched to remove the protective layer located in the first opening. As shown in the cross-section 306 of FIG. 6 , the protective layer 120 on the bottom surface of the first opening 170 is removed by performing photolithography and etching processes, and part of the protective layer 120 still covers the inner sidewall 162 of the first part 116 . In addition, part of the capping layer 112 may be removed in this step to form the groove 174 in the capping layer 112 . At this time, the cover layer 112 includes a recessed portion 121 and an extended portion 123 . After the protective layer 120 is etched, the second opening 172 will be formed in the protective layer 120 , and the inner sidewall 162 of the first portion 116 will still be covered by the protective layer 120 .

Next, in step 410 of the manufacturing method 400, the electrode structure is disposed so that the protective layer is sandwiched between the electrode structure and the inner side wall. As shown in cross-section 308 of FIG. 7 , the electrode structure 130 , such as the drain electrode 132 and the source electrode 134 , will fill the opening in the protective layer 120 , so that the protective layer 120 is sandwiched between the electrode structure 130 and the inner sidewall 162 between. The method of forming the electrode structure 130 may include first disposing a conductive layer (not shown) on the first portion 116 . Materials of the conductive layer include metals, alloys or stacked layers thereof. The stacked layers are, for example, Ti/Al, Ti/Al/Ti/TiN, Ti/Al/Ti/Au, Ti/Al/Ni/Au or Ti/Al/Mo. /Au, but not limited to this. Then, an etching process is performed to etch the conductive layer to form the electrode structure 130 . During the etching process to form the electrode structure 130, the protective layer 120 not covered by the electrode structure 130 will be removed, and the cover layer 112 and the first portion 116 may also be partially etched, so that the protective layer 120 not covered by the electrode structure 130 will be etched. The thickness of the first portion 116 is reduced.

Then, in step 412 of the manufacturing method 400, a heat treatment process is performed, wherein the temperature of the heat treatment is higher than the first reaction temperature and lower than the second reaction temperature. As still shown in section 308 of FIG. 7 , the heat treatment process, for example, has a process temperature higher than 600°C. In some embodiments, the heat treatment process temperature is lower than 900°C. The annealing process (anneal) performed in the heat treatment process temperature range and in an inert atmosphere will cause ohmic contact between the electrode structure 130 and at least one of the underlying barrier layer 110 and the channel layer 108 . During the heat treatment process, since the reaction temperature (ie, the first reaction temperature) between the first material of the insulating structure 114 and the metal material of the electrode structure 130 is lower than or equal to the heat treatment process temperature, in order to avoid the reaction between the two, Therefore, the protective layer 120 of an appropriate material is selected and disposed between the electrode structure 130 and the first portion 116 . The reaction temperature (ie, the second reaction temperature) between the second material selected as the protective layer 120 and the metal material of the electrode structure 130 will be higher than the heat treatment process temperature, or even there will be no reaction between the two, so the electrode structure can be avoided 130 and the first portion 116 of the insulating structure 114 produce a chemical reaction, thereby preventing the resistivity of the electrode structure 130 from increasing. In addition, during the heat treatment process, the metal component (such as aluminum) in the electrode structure 130 will diffuse into the recessed portion 121 of the cover layer 112, so that the recessed portion 121 contains the metal component in the electrode structure 130, and makes The resistivity of the recessed portion 121 is lower than that of the surrounding extension portion 123 . Then, a photolithography and etching process is performed to form a first contact 182, such as a gate contact, in the first portion 116, thereby exposing a portion of the capping layer 112. The etching process to form the first contact port 182 includes dry etching or wet etching. Taking the wet etching process as an example, due to the lateral etching characteristics of the wet etching process, the inner wall of the first contact port 182 will be inclined instead of vertical, so that the film layer can be better coated when the subsequent film layer is coated. coverage (such as step coverage), thereby improving component reliability.

After the process stage shown in FIG. 7 is completed, a deposition process, such as a vapor deposition process, is then performed as shown in cross-section 310 of FIG. 8 to form the second portion 118 that covers the first portion 116 in a compliant manner. The material of the second part 118 may be different from the material of the cover layer 112 , and the material of the second part 118 may be the same as or different from the material of the first part 116 . For example, the material of the second part 118 includes insulating materials, such as nitride insulating materials such as Si ₃ N ₄ and AlN, or oxide insulating materials such as Al ₂ O ₃ , SiON, and SiO ₂ , but is not limited thereto. . In addition, the second part 118 is not limited to a single-layer structure, and may also be a multi-layer stacked structure. Afterwards, an etching process, such as a dry etching or a wet etching process, is performed on the second portion 118 to form a second contact port 184, such as a gate contact port, in the second portion 118. After the etching process of the second portion 118 is completed, the first portion 116 and the second portion 118 will exhibit stepped profiles. In some embodiments, the width of the first contact opening 182 is smaller than the width of the second contact opening 184 . In some embodiments, the width of the first contact opening 182 is greater than the width of the second contact opening 184 , that is, the second part 118 is conformably formed on the first part 116 and extends into the first contact opening 182 . A second contact port 184 is formed in 182 .

Next, a conductive layer, such as a gate electrode 136, is formed on the second portion 118 by performing a deposition and patterning process, and the gate electrode 136 fills the first contact opening 182 and the second contact opening 184. The gate electrode 136 extends outward from the second contact port 184 and has an asymmetric cross-sectional structure. The material of the gate electrode 136 may include metal, alloy, semiconductor material, or stacked layers thereof. For example, the gate electrode 136 may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), Aluminum (Al), copper (Cu), molybdenum (Mo) and other suitable conductive materials or combinations of the above.

After completing the process stage of FIG. 8 , as shown in the cross-section 312 of FIG. 9 , a third insulating layer, such as an interlayer dielectric layer 140 , is formed to cover the protective layer 120 , the electrode structure 130 , the second insulating layer 118 and the gate. electrode 136. Next, a third contact opening 186, such as a pad contact opening, is formed in the interlayer dielectric layer 140 to expose the underlying drain electrode 132 and source electrode 134 respectively. The composition of the interlayer dielectric layer 140 is an insulating material, such as a nitride insulating material such as Si ₃ N ₄ and AlN, or an oxide insulating material such as Al ₂ O ₃ , SiON, and SiO ₂ , but is not limited thereto.

Subsequently, at least two pad structures (not shown) will be formed and disposed in the third contact opening 186 of the interlayer dielectric layer 140 to be electrically connected to the drain electrode 132 and the source electrode 134 respectively. The top surface of the bonding pad structure 132 will be exposed to the interlayer dielectric layer 140 to serve as a region for electrical connection between the semiconductor device 100 and external components. Another bonding pad structure (not shown) may also be formed to be electrically connected to the gate electrode 136 . At this point, the semiconductor device 100 shown in FIG. 1 can be obtained.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

A semiconductor component, characterized by containing:

a semiconductor stack;

An insulating structure, disposed on the semiconductor stack, includes a first portion, the first portion includes a first opening, and the first opening exposes an inner wall of the insulating structure;

an electrode structure including a metallic material; and

a protective layer disposed between the inner wall and the electrode structure, including a second opening;

Wherein, the electrode structure is disposed in the first opening, contacts the protective layer, and is electrically connected to the semiconductor stack through the second opening;

Wherein, the insulation structure includes a first material, the protective layer includes a second material, and a reaction temperature between the second material and the metal material is higher than a reaction temperature between the first material and the metal material. .
The semiconductor device of claim 1, wherein the electrode structure fills the second opening.
The semiconductor device of claim 1, wherein a portion of the protective layer is located outside the first opening and on an upper surface of the first portion of the insulating structure.
The semiconductor device of claim 3, wherein the portion of the protective layer is between the upper surface and the electrode structure.
The semiconductor device of claim 4, wherein the electrode structure and the first part of the insulating structure are completely separated from each other and do not contact each other through the protective layer.
The semiconductor device of claim 1, wherein the protective layer covers a top surface and the inner sidewall of the first part.
The semiconductor device of claim 1, wherein the first material includes an oxide material.
The semiconductor device of claim 7, wherein the oxide material includes silicon oxide or silicon oxynitride.
The semiconductor device of claim 1, wherein the second material includes a nitride material.
The semiconductor device of claim 9, wherein the nitride material includes titanium nitride, vanadium nitride, zirconium nitride and/or tantalum nitride.
The semiconductor device of claim 1, wherein the insulating structure further includes a second part covering the first part, the electrode structure and the protective layer.
The semiconductor device of claim 11, further comprising a conductive layer disposed on one side of the electrode structure, wherein an end of the conductive layer covers the first part and the second part of the insulating structure.
The semiconductor device of claim 12, wherein a portion of the conductive layer penetrates the second portion.
The semiconductor device of claim 1, wherein the first part of the insulating structure further includes:

An end portion between the semiconductor stack and the protective layer; and

An extension part extends from one side of the terminal part, wherein the top surface of the terminal part is higher than the top surface of the extension part.
The semiconductor device of claim 1, further comprising a capping layer disposed between the insulating structure and the semiconductor stack, wherein the second opening exposes the capping layer.
The semiconductor device of claim 15, wherein the cover layer includes a recessed portion, and the second opening exposes the recessed portion and overlaps the recessed portion.
The semiconductor device of claim 11, wherein the capping layer further includes an extension portion disposed around the recessed portion, wherein the resistivity of the extension portion is higher than that of the recessed portion, and the extension portion The components of the part and the recessed part are the same.
The semiconductor device of claim 1, wherein the electrode structure includes a source electrode or a drain electrode.
The semiconductor device of claim 1, wherein the electrode structure and the semiconductor stack exhibit ohmic contact.
A method for manufacturing semiconductor components, characterized by comprising:

providing a semiconductor stack;

disposing a first insulating layer on the semiconductor stack, wherein the first insulating layer includes a first opening, and the first opening exposes an inner sidewall of the first insulating layer;

Fill a protective layer into the first opening and cover the inner wall;

Etching the protective layer to remove a portion of the protective layer located within the first opening to form a second opening;

An electrode structure is provided so that the protective layer is sandwiched between the electrode structure and the inner wall; and

Implement a heat treatment process;

The first insulating layer includes a first material, the protective layer includes a second material, the electrode structure includes a metal material, and there is a first reaction temperature between the first material and the metal material, and the second There is a second reaction temperature between the material and the metal material, the second reaction temperature is greater than the first reaction temperature, and the temperature of the heat treatment is higher than the first reaction temperature and lower than the second reaction temperature.
The method of manufacturing a semiconductor device according to claim 20, wherein the thickness of the first insulating layer is greater than the thickness of the protective layer.
The method of manufacturing a semiconductor device according to claim 20, wherein the step of arranging the electrode structure includes:

disposing a conductive layer on the first insulating layer; and

An etching process is performed to etch the conductive layer and the first insulating layer.
The method of manufacturing a semiconductor device according to claim 20, wherein the second opening exposes a portion of the semiconductor stack, the electrode structure is located in the second opening, and after the heat treatment process is performed, the electrode structure and The semiconductor stack exhibits ohmic contact between them.
The method of manufacturing a semiconductor device according to claim 20, wherein after performing the heat treatment process, it further includes:

A second insulating layer is provided to cover the semiconductor stack, the first insulating layer, the protective layer and the electrode structure;

Etch the second insulating layer to form a contact opening;

disposing a conductive layer on the second insulating layer and filling the contact opening; and

A third insulating layer is provided to cover the protective layer, the electrode structure, the second insulating layer and the conductive layer.
The manufacturing method of a semiconductor element as claimed in claim 20, characterized in that:

Before arranging the first insulating layer, it also includes arranging a capping layer on the semiconductor stack;

Before etching the protective layer, exposing a portion of the capping layer;

Before arranging the electrode structure, etching the portion of the capping layer; and

After the heat treatment process, the portion of the capping layer contains the metal component of the electrode structure.