WO2023200630A1 - Étalonnage d'un système amplificateur de modulation de largeur d'impulsion - Google Patents

Étalonnage d'un système amplificateur de modulation de largeur d'impulsion Download PDF

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Publication number
WO2023200630A1
WO2023200630A1 PCT/US2023/017411 US2023017411W WO2023200630A1 WO 2023200630 A1 WO2023200630 A1 WO 2023200630A1 US 2023017411 W US2023017411 W US 2023017411W WO 2023200630 A1 WO2023200630 A1 WO 2023200630A1
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WIPO (PCT)
Prior art keywords
input
output
switched mode
analog
analog integrator
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PCT/US2023/017411
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English (en)
Inventor
John L. Melanson
Original Assignee
Cirrus Logic International Semiconductor Ltd.
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Publication date
Priority claimed from US17/720,869 external-priority patent/US11855592B2/en
Application filed by Cirrus Logic International Semiconductor Ltd. filed Critical Cirrus Logic International Semiconductor Ltd.
Publication of WO2023200630A1 publication Critical patent/WO2023200630A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
    • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/375—Circuitry to compensate the offset being present in an amplifier

Definitions

  • the present disclosure relates in general to circuits for audio devices, including without limitation personal audio devices, such as wireless telephones and media players, and more specifically, to systems and methods for calibrating a pulse width modulation amplifier system.
  • Personal audio devices including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use.
  • Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers.
  • Such circuitry often includes a power amplifier for driving an audio output signal to headphones or speakers.
  • a power amplifier amplifies an audio signal by taking energy from a power supply and controlling an audio output signal to match an input signal shape but with a larger amplitude.
  • a class-D amplifier may comprise an electronic amplifier in which the amplifying devices (e.g., transistors, typically metal-oxide-semiconductor field effect transistors) operate as electronic switches.
  • the amplifying devices e.g., transistors, typically metal-oxide-semiconductor field effect transistors
  • a signal to be amplified may be converted to a series of pulses by pulse-width modulation (PWM), pulse-density modulation (PDM), or another method of modulation, such that the signal is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of the signal.
  • PWM pulse-width modulation
  • PDM pulse-density modulation
  • a characteristic of the pulses of the modulated signal e.g., pulse widths, pulse density, etc.
  • the output pulse train may be converted to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low- pass filter may be inherent in the class-D amplifier or a load driven by the class-D amplifier.
  • Class-D amplifiers are often used due to the fact that they may be more power efficient than linear analog amplifiers, in that class-D amplifiers may dissipate less power as heat in active devices as compared to linear analog amplifiers. In amplifier systems including those having class-D amplifiers, it may be critical to determine and correct for any signal offsets that may exist in the amplifier path.
  • signal offsets may be offsets inherent in integrator stages of a preamplifier stage of the amplifier system, or mismatch of resistors used to set a gain of the amplifier system. Without correction of such signal offsets, signal distortion, signal inaccuracy, and/or other undesirable conditions may persist.
  • one or more disadvantages and problems associated with existing approaches to minimizing offset in a pulse width modulation amplifier system may be reduced or eliminated.
  • a switched mode amplifier system may include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output, include a feedback network coupled between the amplifier output and an input of the analog integrator, include a loop filter configured to generate a digital loop filter output, include a quantizer configured to generate a pulse-width modulated representation of the digital loop filter output; and include a calibration system.
  • the calibration system may be configured to force the input of the analog integrator to a fixed known input value, low-pass filter the pulse-width modulated representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, determine an offset of the switched mode amplifier system based on the filtered quantizer output signal, and correct for the offset.
  • a method may be provided for use in a switched mode amplifier system having a switched mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output, having a feedback network coupled between the amplifier output and an input of the analog integrator, having a loop filter configured to generate a digital loop filter output, and having a quantizer configured to generate a pulse-width modulated representation of the digital loop filter output.
  • the method may include forcing the input of the analog integrator to a fixed known input value, low-pass filtering the pulse-width modulated representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, and determining an offset of the switched mode amplifier system based on the filtered quantizer output signal, and correcting for the offset.
  • a calibration system may be provided for use with a switched mode amplifier system having a switched mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output, having a feedback network coupled between the amplifier output and an input of the analog integrator, having a loop filter configured to generate a digital loop filter output, and having a quantizer configured to generate a pulsewidth modulated representation of the digital loop filter output.
  • the calibration system may be configured to force the input of the analog integrator to a fixed known input value, low-pass filter the pulse-width modulated representation of the digital loop filter output generated by the quantizer to generate a filtered quantizer output signal, determine an offset of the switched mode amplifier system based on the filtered quantizer output signal, and correct for the offset.
  • a switched mode amplifier system may include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output and including a calibration system.
  • the calibration system may be configured to force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determine an offset of the switched mode amplifier system based on the analog signal, and correct for the offset.
  • a method may be provided for use in a switched mode amplifier system having a switched mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output.
  • the method may include forcing the input of the analog integrator to a fixed known input value, forcing the amplifier output to a fixed known duty cycle, measuring an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determining an offset of the switched mode amplifier system based on the analog signal, and correcting for the offset.
  • a calibration system may be provided for use with a switched mode amplifier system having a switched mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output.
  • the calibration system may force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determine an offset of the switched mode amplifier system based on the analog signal, and correct for the offset.
  • a switched mode amplifier system may include a switched mode amplifier comprising having an amplifier input coupled to an output of an analog integrator and an amplifier output and including a calibration system configured to force the input of the analog integrator to a fixed known input value, determine a slew rate of an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, and determine an integrator gain of the switched mode amplifier system based on the slew rate.
  • a method may be provided for use in a switched mode amplifier system having a switched mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output.
  • the method may include forcing the input of the analog integrator to a fixed known input value, determining a slew rate of an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, and determining an integrator gain of the switched mode amplifier system based on the slew rate.
  • a calibration system may be provided for use with a switched mode amplifier system having a switched mode amplifier including an amplifier input coupled to an output of an analog integrator and an amplifier output.
  • the calibration system may be configured to force the input of the analog integrator to a fixed known input value, determine a slew rate of an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, and determine an integrator gain of the switched mode amplifier system based on the slew rate.
  • FIGURE 1 is an illustration of an example personal audio device, in accordance with embodiments of the present disclosure
  • FIGURE 2 illustrates a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure
  • FIGURE 3 illustrates a flow chart of an example method for open-loop calibration of the audio integrated circuit depicted in FIGURE 2, in accordance with embodiments of the present disclosure
  • FIGURE 4 illustrates a flow chart of an example method for determining a gain of the audio integrated circuit depicted in FIGURE 2, in accordance with embodiments of the present disclosure.
  • FIGURE 5 illustrates a flow chart of an example method for closed-loop calibration of the audio integrated circuit depicted in FIGURE 2, in accordance with embodiments of the present disclosure.
  • FIGURE 1 is an illustration of an example personal audio device 1, in accordance with embodiments of the present disclosure.
  • FIGURE 1 depicts personal audio device 1 coupled to a headset 3 in the form of a pair of earbud speakers 8 A and 8B.
  • Headset 3 depicted in FIGURE 1 is merely an example, and it is understood that personal audio device 1 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers.
  • a plug 4 may provide for connection of headset 3 to an electrical terminal of personal audio device 1.
  • Personal audio device 1 may provide a display to a user and receive user input using a touch screen 2, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device 1.
  • personal audio device 1 may include an audio integrated circuit (IC) 9 for generating an analog audio signal for transmission to headset 3 and/or another audio transducer.
  • IC audio integrated circuit
  • FIGURE 2 illustrates a block diagram of selected components of an example audio IC 9 of a personal audio device, in accordance with embodiments of the present disclosure.
  • example audio IC 9 may be used to implement audio IC 9 of FIGURE 1.
  • a microcontroller core 18 may supply a digital audio input signal DIG_IN to a digital-to-analog converter (DAC) 14, which may convert the digital audio input signal to an analog input signal VIN.
  • DAC 14 may supply analog input signal VIN to an amplifier 16 which may amplify or attenuate analog input signal VI to provide an audio output signal VOUT, which may operate a speaker, headphone transducer, a line level signal output, and/or other suitable output.
  • DAC digital-to-analog converter
  • amplifier 16 may include a signal input network 24, a first stage 22 (e.g., an analog front end) configured to receive analog input signal VIN at an amplifier input of amplifier 16 and generate an intermediate signal VINT which is a function of analog input signal VIN, a quantizer 34, a final output stage comprising a class- D audio output stage 42 configured to generate audio output signal VOUT at an amplifier output of amplifier 16 as a function of quantized intermediate signal VINT, a signal feedback network 26 coupled between the amplifier output and the amplifier input, and a control system 28 for controlling the operation of certain components of amplifier 16, as described in greater detail below.
  • Signal input network 24 may include any suitable input network receiving the amplifier input of amplifier 16.
  • signal input network 24 may include variable input resistors 46, wherein resistances of variable input resistors 46 may be controlled by control signals received from control system 28, as described in greater detail below.
  • First stage 22 may include any suitable analog front end circuit for conditioning analog input signal VIN for use by class-D audio output stage 42.
  • first stage 22 may include one or more analog integrators 30 and 32 cascaded in series, as shown in FIGURE 2.
  • Quantizer 34 may comprise any system, device, or apparatus configured to quantize intermediate signal VINT to generate an equivalent digital PWM signal VQUANT. Accordingly, quantizer 34 may be referred to as a digital pulse width modulator. As shown in FIGURE 2, quantizer 34 may receive one or more control signals from control system 28, which may control operation of quantizer 34 during a calibration phase of audio IC 9, as described in greater detail below.
  • Class-D audio output stage 42 may comprise any system, device, or apparatus configured to receive the output of quantizer 34 and drive an output signal VOUT which is an amplified version of analog input signal V IN. Accordingly, class-D audio output stage 42 may comprise a plurality of output switches configured to generate output signal VOUT from the modulated signal VQUA T generated by quantizer 34. After amplification by class- D audio output stage 42, its output pulse train may be converted back to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low-pass filter may be inherent in output circuitry of class-D audio output stage 42 or a load driven by class-D audio output stage 42.
  • Signal feedback network 26 may include any suitable feedback network for feeding back a signal indicative of audio output signal VOUT to the amplifier input of amplifier 16.
  • signal feedback network 26 may include variable feedback resistors 48, wherein resistances of variable feedback resistors 48 are controlled by control signals received from control system 28, as described in greater detail below.
  • control system 28 may recognize that a closed loop gain of amplifier 16 may be set by a ratio of the resistances of variable feedback resistors 48 to the resistances of variable input resistors 46.
  • example audio IC 9 may also include a control system 28.
  • Control system 28 may include any suitable system, device, or apparatus configured to receive information indicative of a signal (e.g., voltage VINT" output by integrator 30 and/or modulated signal VQUANT) within the signal path of amplifier 16 and based at least thereon, perform calibration of audio IC 9.
  • control system 28 may generate a digital trim signal combined by a combiner 20 with digital audio input signal DIG_IN in order to effectively modify digital audio input signal DIG_IN to correct for detected offset within the amplifier system of audio IC 9.
  • control system 28 may generate one or more analog trim signals to modify resistances of one or more of input resistors 46, one or more of feedback resistors 48, and/or parameters of integrator 30 (e.g., modify current sources of an operational amplifier of integrator 30, modify external current sources or resistors that apply an external offset to integrator 30, etc.).
  • parameters of integrator 30 e.g., modify current sources of an operational amplifier of integrator 30, modify external current sources or resistors that apply an external offset to integrator 30, etc.
  • FIGURE 3 illustrates a flow chart of an example method 300 for open-loop calibration of the amplifier system of audio IC 9, in accordance with embodiments of the present disclosure.
  • method 300 may begin at step 302.
  • teachings of the present disclosure may be implemented in a variety of configurations of audio IC 9.
  • the preferred initialization point for method 300 and the order of the steps comprising method 300 may depend on the implementation chosen.
  • control system 28 may initialize digital trim and analog trim values to default values. For example, the digital trim value may be set to zero while analog trim values may be set in accordance with a desired nominal gain for amplifier 16.
  • control system 28 may communicate a control signal to microcontroller core 18 such that microcontroller core 18 outputs a value of zero for digital audio input signal DIG_IN.
  • control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a differential modulated signal VQUANT of zero to class-D audio output stage 42 (e.g., by outputting the same square wave signal on each of its differential outputs), regardless of intermediate voltage VINT generated by first stage 22. By doing so, control system 28 during such open-loop calibration mode effectively breaks/opens the signal feedback loop present during normal operation of audio IC 9.
  • control system 28 may determine if a magnitude of voltage VINT' is below a first predetermined threshold.
  • a substantially non-zero value of voltage VI T' may indicate a presence of offset within the signal path of amplifier 16, including without limitation an offset inherent to integrator 30, offset due to mismatches between input resistors 46, and/or offset due to mismatches between feedback resistors 48.
  • control system 28 may attempt to minimize voltage VINT' during the open-loop calibration mode by varying the digital trim and/or one or more of the analog trims in order to reduce magnitude of voltage VINT' below the first predetermined threshold. Accordingly, if the magnitude of voltage VINT' is below the first predetermined threshold, method 300 may proceed to step 312. Otherwise, method 300 may proceed to step 310.
  • control system 28 may vary the digital trim and/or one or more of the analog trims in an effort to reduce the magnitude of voltage VINT'.
  • method 300 may proceed again to step 308.
  • control system 28 may store the digital trim and/or analog trim settings in order to recall and apply such trim settings during normal operation of the amplifier system.
  • steps may detect and correct for an overall offset of the amplifier system, such steps may not isolate any particular source of offset. However, the following steps may isolate offset due to mismatches between input resistors 46 and/or mismatches between feedback resistors 48.
  • control system 28 may communicate control signals to quantizer 34 to cause quantizer 34 to generate differential PWM outputs of quantizer 34 at a first duty cycle (e.g., a 25% duty cycle) while maintaining the differential modulated signal VQUANT of quantizer 34 to be zero, and determine voltage VI T' resulting therefrom.
  • control system 28 may communicate control signals to quantizer 34 to cause quantizer 34 to generate differential PWM outputs of quantizer 34 at a second duty cycle (e.g., a 75% duty cycle) while maintaining the differential modulated signal VQUANT of quantizer 34 to be zero, and determine voltage VINT' resulting therefrom.
  • control system 28 may generate control signals that vary the common mode voltage of output voltage VOUT between two different levels (e.g., by varying a supply voltage to class-D audio output stage 42).
  • the difference between the value of voltage VINT' at the first duty cycle/first output common mode voltage and the second duty cycle/second output common mode voltage may be indicative of mismatched resistances between input resistors 46 and/or mismatched resistances between feedback resistors 48.
  • control system 28 may generate control signals that vary the common mode voltage of output voltage VOUT among at least three different levels (e.g., at least three different duty cycles), determine the differences in voltage VINT ' at the various duty cycles, and correct for such differences, including correcting for both linear and non-linear mismatches of input resistors 46 and/or both linear and non-linear mismatches of feedback resistors 48.
  • control system 28 may determine if a magnitude of the difference in voltage VINT' between the first duty cycle/first output common mode voltage and the second duty cycle/second output common mode voltage is below a second predetermined threshold. If the magnitude of the difference is below the second predetermined threshold, method 300 may proceed to step 322. Otherwise, method 300 may proceed to step 320.
  • control system 28 may vary the digital trim and/or one or more of the analog trims in an effort to reduce the magnitude of voltage VINT'.
  • method 300 may proceed again to step 314
  • control system 28 may store the digital trim and/or analog trim settings in order to recall and apply such trim settings during normal operation of the amplifier system. After completion of step 322, method 300 may end.
  • the steps of method 300 may be applied to each gain setting of the amplifier system in order to determine offset and perform calibration for each gain setting.
  • FIGURE 3 discloses a particular number of steps to be taken with respect to method 300, it may be executed with greater or fewer steps than those depicted in FIGURE 3.
  • FIGURE 3 discloses a certain order of steps to be taken with respect to method 300, the steps comprising method 300 may be completed in any suitable order.
  • steps 314-322 used to isolate and calibrate for resistor mismatch may be performed prior to steps 302-312 for determining and calibrating for overall offset.
  • Method 300 may be implemented using control system 28, components thereof or coupled thereto, or any other system operable to implement method 300.
  • method 300 may be implemented partially or fully in software and/or firmware embodied in computer-readable media.
  • FIGURE 4 illustrates a flow chart of an example method 400 for determining a gain of the amplifier system of audio IC 9, in accordance with embodiments of the present disclosure.
  • method 400 may begin at step 402.
  • teachings of the present disclosure may be implemented in a variety of configurations of audio IC 9.
  • the preferred initialization point for method 400 and the order of the steps comprising method 400 may depend on the implementation chosen.
  • control system 28 may communicate a control signal to quantizer 34 to cause quantizer 34 to generate a differential modulated signal VQUA T of zero to class-D audio output stage 42 (e.g., by outputting the same square wave signal on each of its differential outputs), regardless of intermediate voltage VINT generated by first stage 22.
  • control system 28 during such open-loop calibration mode effectively breaks/opens the signal feedback loop present during normal operation of audio IC 9.
  • control system 28 may communicate a control signal to microcontroller core 18 such that microcontroller core 18 outputs a value for digital audio input signal DIG_IN such that DAC 14 generates at its output a square wave signal with a small duty cycle (e.g., a minimum duty cycle possible or the smallest non-zero value for DAC 14).
  • a small duty cycle e.g., a minimum duty cycle possible or the smallest non-zero value for DAC 14.
  • the output voltage VINT' generated by integrator 30 may generate a periodic signal between its minimum and maximum values, with a finite slew rate when increasing from its minimum value and its maximum value, and vice versa.
  • the square wave signal may cause the output of voltage VINT' generated by integrator 30 to saturate.
  • the input voltage may be ramped slowly.
  • control system 28 may determine the slew rate of output voltage VINT'.
  • control system 28 may estimate an integrator gain of the amplifier system based on the slew rate, as the integrator gain from an input (e.g., analog input signal VIN) of integrator 30 and the output of integrator 30 (e.g., voltage VINT') may be a function of the slope of voltage VINT'.
  • step 408 method 400 may end.
  • FIGURE 4 discloses a particular number of steps to be taken with respect to method 400, it may be executed with greater or fewer steps than those depicted in FIGURE 4.
  • FIGURE 4 discloses a certain order of steps to be taken with respect to method 400, the steps comprising method 400 may be completed in any suitable order.
  • Method 400 may be implemented using control system 28, components thereof or coupled thereto, or any other system operable to implement method 400. In certain embodiments, method 400 may be implemented partially or fully in software and/or firmware embodied in computer-readable media.
  • control system 28 may also, in addition to or in lieu of the open-loop calibration of method 300, perform calibration while maintaining the amplifier system in a closed- loop configuration, as described below with reference to method 500.
  • FIGURE 5 illustrates a flow chart of an example method 500 for closed-loop calibration of the amplifier system of audio IC 9, in accordance with embodiments of the present disclosure.
  • method 500 may begin at step 502.
  • teachings of the present disclosure may be implemented in a variety of configurations of audio IC 9.
  • the preferred initialization point for method 500 and the order of the steps comprising method 500 may depend on the implementation chosen.
  • control system 28 may initialize digital trim and analog trim values to default values. For example, the digital trim value may be set to zero while analog trim values may be set in accordance with a desired nominal gain for amplifier 16.
  • control system 28 may communicate a control signal to microcontroller core 18 such that microcontroller core 18 outputs a value of zero for digital audio input signal DIG_IN.
  • control system 28 may low-pass filter (e.g., with an averaging filter) modulated signal VQUANT generated by quantizer 34.
  • control system 28 may determine if a magnitude of the low-pass filtered modulated signal VQUANT is below a first predetermined threshold.
  • a substantially non-zero value of low-pass filtered modulated signal VQUANT may indicate a presence of offset within the signal path of amplifier 16, including without limitation an offset inherent to integrator 30, offset due to mismatches between input resistors 46, and/or offset due to mismatches between feedback resistors 48.
  • control system 28 may attempt to minimize low-pass filtered modulated signal VQUANT during the closed-loop calibration mode by varying the digital trim and/or one or more of the analog trims in order to reduce magnitude of low-pass filtered modulated signal VQUANT below the first predetermined threshold. Accordingly, if the magnitude of low- pass filtered modulated signal VQUANT is below the first predetermined threshold, method 500 may proceed to step 512. Otherwise, method 500 may proceed to step 510.
  • control system 28 may vary the digital trim and/or one or more of the analog trims in an effort to reduce the magnitude of low-pass filtered modulated signal VQUANT.
  • method 500 may proceed again to step 506.
  • control system 28 may store the digital trim and/or analog trim settings in order to recall and apply such trim settings during normal operation of the amplifier system.
  • steps may detect and correct for an overall offset of the amplifier system, such steps may not isolate any particular source of offset. However, the following steps may isolate offset due to mismatches between input resistors 46 and/or mismatches between feedback resistors 48.
  • control system 28 may communicate control signals to quantizer 34 to cause quantizer 34 to generate differential PWM outputs of quantizer 34 at a first duty cycle (e.g., a 25% duty cycle), and determine low-pass filtered modulated signal VQUANT resulting therefrom.
  • control system 28 may communicate control signals to quantizer 34 to cause quantizer 34 to generate differential PWM outputs of quantizer 34 at a second duty cycle (e.g., a 75% duty cycle), and determine low-pass filtered modulated signal VQUANT resulting therefrom.
  • control system 28 may generate control signals that vary the common mode voltage of output voltage VOUT between two different levels (e.g., by varying a supply voltage to class-D audio output stage 42).
  • the difference between the value of differential modulated signal VQUANT at the first duty cycle/first output common mode voltage and the second duty cycle/second output common mode voltage may be indicative of mismatched resistances between input resistors 46 and/or mismatched resistances between feedback resistors 48.
  • control system 28 may generate control signals that vary the common mode voltage of output voltage VOUT among at least three different levels (e.g., at least three different duty cycles), determine the differences in voltage VINT' at the various duty cycles, and correct for such differences, including correcting for both linear and non-linear mismatches of input resistors 46 and/or both linear and non-linear mismatches of feedback resistors 48.
  • control system 28 may determine if a magnitude of the difference in low-pass filtered modulated signal VQUANT between the first duty cycle/first output common mode voltage and the second duty cycle/second output common mode voltage is below a second predetermined threshold. If the magnitude of the difference is below the second predetermined threshold, method 500 may proceed to step 522. Otherwise, method 500 may proceed to step 520.
  • control system 28 may vary the digital trim and/or one or more of the analog trims in an effort to reduce the magnitude of differential modulated signal VQUANT.
  • method 500 may proceed again to step 514.
  • control system 28 may store the digital trim and/or analog trim settings in order to recall and apply such trim settings during normal operation of the amplifier system. After completion of step 522, method 500 may end.
  • the steps of method 500 may be applied to each gain setting of the amplifier system in order to determine offset and perform calibration for each gain setting.
  • FIGURE 5 discloses a particular number of steps to be taken with respect to method 500, it may be executed with greater or fewer steps than those depicted in FIGURE 5.
  • FIGURE 5 discloses a certain order of steps to be taken with respect to method 500, the steps comprising method 500 may be completed in any suitable order. For example, in some embodiments, steps 514-522 used to isolate and calibrate for resistor mismatch may be performed prior to steps 502-512 for determining and calibrating for overall offset.
  • Method 500 may be implemented using control system 28, components thereof or coupled thereto, or any other system operable to implement method 500.
  • method 500 may be implemented partially or fully in software and/or firmware embodied in computer-readable media.
  • the calibration operations performed by control system 28 and described above may be performed at any suitable time, including without limitation during a calibration phase occurring at powering-on of audio IC 9, occurring following assembly of audio IC 9, occurring when the amplifier system of audio IC 9 is not in use (e.g., not generating audio content), and/or occurring in response to a change in temperature proximate to audio IC 9.
  • references in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated.
  • each refers to each member of a set or each member of a subset of a set.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un système amplificateur à mode commuté comprenant un amplificateur à mode commuté ayant une entrée d'amplificateur couplée à une sortie d'un intégrateur analogique et une sortie d'amplificateur et comprenant un système d'étalonnage. Le système d'étalonnage peut être configuré pour : forcer l'entrée de l'intégrateur analogique à une valeur d'entrée connue fixe, forcer la sortie d'amplificateur à un cycle de service connu fixe, mesurer un signal analogique généré à la sortie de l'intégrateur analogique en réponse au forçage de l'entrée de l'intégrateur analogique à la valeur fixe, déterminer un décalage du système amplificateur en mode commuté sur la base du signal analogique, et corriger le décalage.
PCT/US2023/017411 2022-04-14 2023-04-04 Étalonnage d'un système amplificateur de modulation de largeur d'impulsion WO2023200630A1 (fr)

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US17/720,869 2022-04-14
US17/720,869 US11855592B2 (en) 2021-11-09 2022-04-14 Calibration of pulse width modulation amplifier system

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WO2023200630A1 true WO2023200630A1 (fr) 2023-10-19

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4274204B2 (ja) * 2006-07-07 2009-06-03 ヤマハ株式会社 Ｄ級増幅器
US20120274399A1 (en) * 2009-11-30 2012-11-01 Seedher Ankit Pop-Up Noise Reduction in a Device
JP2012231264A (ja) * 2011-04-25 2012-11-22 Yamaha Corp 電力増幅器
WO2016003597A2 (fr) * 2014-06-30 2016-01-07 Qualcomm Incorporated Amplificateur de commutation audio
US20180212569A1 (en) * 2017-01-20 2018-07-26 Cirrus Logic International Semiconductor Ltd. Offset calibration for amplifier and preceding circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4274204B2 (ja) * 2006-07-07 2009-06-03 ヤマハ株式会社 Ｄ級増幅器
US20120274399A1 (en) * 2009-11-30 2012-11-01 Seedher Ankit Pop-Up Noise Reduction in a Device
JP2012231264A (ja) * 2011-04-25 2012-11-22 Yamaha Corp 電力増幅器
WO2016003597A2 (fr) * 2014-06-30 2016-01-07 Qualcomm Incorporated Amplificateur de commutation audio
US20180212569A1 (en) * 2017-01-20 2018-07-26 Cirrus Logic International Semiconductor Ltd. Offset calibration for amplifier and preceding circuit

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