WO2023199014A1 - Technique for handling data elements stored in an array storage - Google Patents

Technique for handling data elements stored in an array storage Download PDF

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Publication number
WO2023199014A1
WO2023199014A1 PCT/GB2023/050584 GB2023050584W WO2023199014A1 WO 2023199014 A1 WO2023199014 A1 WO 2023199014A1 GB 2023050584 W GB2023050584 W GB 2023050584W WO 2023199014 A1 WO2023199014 A1 WO 2023199014A1
Authority
WO
WIPO (PCT)
Prior art keywords
array
data elements
storage
vectors
vector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2023/050584
Other languages
English (en)
French (fr)
Inventor
Arnaud Philippe Claude Grasset
Jelena Milanovic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to EP23711541.5A priority Critical patent/EP4508529A1/en
Priority to JP2024559352A priority patent/JP2025511829A/ja
Priority to US18/855,222 priority patent/US12504973B2/en
Priority to IL315584A priority patent/IL315584A/en
Priority to CN202380031668.XA priority patent/CN119137578A/zh
Priority to KR1020247037014A priority patent/KR20250002371A/ko
Publication of WO2023199014A1 publication Critical patent/WO2023199014A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders

Definitions

  • the use of the present technique avoids the need to store logic zero values within vector registers that would otherwise be required to be used as source operands for move instructions used to move those logic zero values into the array storage, hence freeing up one or more vector registers within the vector register file.
  • Such a technique as described above can take advantage of an outer product approach to compute FIR filtering implemented by a sliding window technique, using a square array of data elements.
  • Such a technique typically results in some of the vectors of the square array of output data elements being finalised before other vectors of output data elements, and hence the use of the above described move and zero instruction can enable those finalised vectors of output data elements to be moved out of the array storage, with the associated storage elements being freed up for use in association with other vectors of output data elements.
  • the processor 20 may be arranged to process two dimensional arrays of data elements stored in the array storage 90.
  • the two-dimensional arrays may, in at least some examples, be accessed as one-dimensional vectors of data elements in multiple directions.
  • the array storage 90 may be arranged to store one or more two dimensional arrays of data elements, and each two dimensional array of data elements may form a square array portion of a larger or even higher- dimensioned array of data elements in memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
PCT/GB2023/050584 2022-04-13 2023-03-13 Technique for handling data elements stored in an array storage Ceased WO2023199014A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP23711541.5A EP4508529A1 (en) 2022-04-13 2023-03-13 Technique for handling data elements stored in an array storage
JP2024559352A JP2025511829A (ja) 2022-04-13 2023-03-13 アレイストレージに記憶されたデータ要素を処理するための技術
US18/855,222 US12504973B2 (en) 2022-04-13 2023-03-13 Technique for handling data elements stored in an array storage
IL315584A IL315584A (en) 2022-04-13 2023-03-13 A technique for handling details of data stored in array storage
CN202380031668.XA CN119137578A (zh) 2022-04-13 2023-03-13 用于处置存储在阵列存储装置中的数据元素的技术
KR1020247037014A KR20250002371A (ko) 2022-04-13 2023-03-13 어레이 저장소에 저장되는 데이터 요소를 핸들링하기 위한 기술

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB2205491.0 2022-04-13
GB2205491.0A GB2617828B (en) 2022-04-13 2022-04-13 Technique for handling data elements stored in an array storage

Publications (1)

Publication Number Publication Date
WO2023199014A1 true WO2023199014A1 (en) 2023-10-19

Family

ID=81653132

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2023/050584 Ceased WO2023199014A1 (en) 2022-04-13 2023-03-13 Technique for handling data elements stored in an array storage

Country Status (9)

Country Link
US (1) US12504973B2 (enExample)
EP (1) EP4508529A1 (enExample)
JP (1) JP2025511829A (enExample)
KR (1) KR20250002371A (enExample)
CN (1) CN119137578A (enExample)
GB (1) GB2617828B (enExample)
IL (1) IL315584A (enExample)
TW (1) TW202340948A (enExample)
WO (1) WO2023199014A1 (enExample)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544965A (en) * 1966-03-25 1970-12-01 Burroughs Corp Data processing system
WO2005013084A2 (en) * 2003-07-31 2005-02-10 Cradle Technologies, Inc. Method and system for performing operations on data and transferring data
EP3629154A2 (en) * 2018-09-27 2020-04-01 INTEL Corporation Systems for performing instructions to quickly convert and use tiles as 1d vectors
US20210042261A1 (en) * 2019-08-05 2021-02-11 Arm Limited Data processing
EP3929736A1 (en) * 2020-06-27 2021-12-29 INTEL Corporation Apparatuses, methods, and systems for instructions for moving data between tiles of a matrix operations accelerator and vector registers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040054877A1 (en) * 2001-10-29 2004-03-18 Macy William W. Method and apparatus for shuffling data
US8549265B2 (en) * 2008-08-15 2013-10-01 Apple Inc. Processing vectors using wrapping shift instructions in the macroscalar architecture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544965A (en) * 1966-03-25 1970-12-01 Burroughs Corp Data processing system
WO2005013084A2 (en) * 2003-07-31 2005-02-10 Cradle Technologies, Inc. Method and system for performing operations on data and transferring data
EP3629154A2 (en) * 2018-09-27 2020-04-01 INTEL Corporation Systems for performing instructions to quickly convert and use tiles as 1d vectors
US20210042261A1 (en) * 2019-08-05 2021-02-11 Arm Limited Data processing
EP3929736A1 (en) * 2020-06-27 2021-12-29 INTEL Corporation Apparatuses, methods, and systems for instructions for moving data between tiles of a matrix operations accelerator and vector registers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ROBERT BEDICHEK: "Some Efficient Architecture Simulation Techniques", USENIX CONFERENCE, 1990, pages 53 - 63

Also Published As

Publication number Publication date
GB2617828A (en) 2023-10-25
GB2617828B (en) 2024-06-19
JP2025511829A (ja) 2025-04-16
IL315584A (en) 2024-11-01
US20250173148A1 (en) 2025-05-29
US12504973B2 (en) 2025-12-23
KR20250002371A (ko) 2025-01-07
GB202205491D0 (en) 2022-05-25
TW202340948A (zh) 2023-10-16
EP4508529A1 (en) 2025-02-19
CN119137578A (zh) 2024-12-13

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