WO2023193406A1

WO2023193406A1 - Probe, oscilloscope and digital signal test system

Info

Publication number: WO2023193406A1
Application number: PCT/CN2022/119891
Authority: WO
Inventors: 蒋文裕; 严波; 史慧; 周晨逸; 王悦
Original assignee: 普源精电科技股份有限公司
Priority date: 2022-04-07
Filing date: 2022-09-20
Publication date: 2023-10-12
Also published as: CN114720743A

Abstract

Provided in the embodiments of the present application are a probe, an oscilloscope and a digital signal test system. The probe comprises an input end, a sending signal conversion module and an output end, wherein the input end is used for receiving a digital signal to be tested; the sending signal conversion module is connected between the input end and the output end, and is used for converting, according to a first clock signal, said digital signal, which is received, into a sending signal, which can be received by an analog channel of the oscilloscope; the first clock signal and a second clock signal are same-source clock signals, the second clock signal is a clock signal used when a receiving signal conversion module in the oscilloscope works, and the receiving signal conversion module is a module which is connected to the analog channel so as to receive a sending signal; and the output end is used for outputting the sending signal to the analog channel of the oscilloscope.

Description

Probes, oscilloscopes and digital signal test systems

Related applications

This application claims priority to the Chinese patent application filed on April 7, 2022, with application number 202210361458.4 and titled "Probe, Oscilloscope and Digital Signal Test System", the full text of which is hereby incorporated by reference.

Technical field

The embodiments of the present application relate to the technical field of oscilloscopes, and in particular, to a probe, an oscilloscope and a digital signal testing system.

Background technique

In most oscilloscope applications, the functions of a logic analyzer are integrated, making it an oscilloscope with logic analysis functions. Conventional logic probes generally have one end connected to the digital signal to be measured, and the other end is connected to the digital channel of the oscilloscope through an independent logic probe interface. This kind of probe not only takes up a lot of I/O resources, but also requires an independent logic probe interface to connect to the oscilloscope. The oscilloscope also needs to provide a digital channel socket, which is not conducive to improving product integration.

Related technologies have proposed changing the probe structure so that it can reuse the analog channels of the oscilloscope, thereby improving product integration. However, after the digital signal to be measured is converted from digital to analog by the probe, it is transmitted to the logic channel of the oscilloscope. The signal data needs to be restored in the oscilloscope to convert it back to a digital signal. Data recovery often occurs in this process. Wrong question. How to reduce the probability of data recovery errors has become an urgent technical problem that needs to be solved in this field.

Contents of the invention

In view of this, embodiments of the present application provide a probe, an oscilloscope and a digital signal testing system to solve at least one problem existing in the background technology.

In a first aspect, an embodiment of the present application provides a probe, including: an input terminal, a sending signal conversion module, and an output terminal; wherein,

The input terminal is used to receive the digital signal to be measured;

The transmission signal conversion module is connected between the input terminal and the output terminal, and is used to convert the received digital signal to be measured into a transmission signal that can be received by the analog channel of the oscilloscope according to the first clock signal; Wherein, the first clock signal and the second clock signal are homologous clock signals, the second clock signal is the clock signal used by the receiving signal conversion module in the oscilloscope when working, and the receiving signal conversion module is and The analog channel is connected to receive the module that sends the signal;

The output terminal is used to output the sending signal to the analog channel of the oscilloscope.

In conjunction with the first aspect of the present application, in an optional implementation, the probe further includes: a clock signal generation module and a clock signal transmission component; the clock signal generation module is used to generate the first clock signal and the a second clock signal; the clock signal transmission component is used to transmit the first clock signal to the transmit signal conversion module, and transmit the second clock signal to the receive signal conversion module of the oscilloscope; or,

The probe also includes: a clock signal transmission component for receiving the first clock signal sent by the oscilloscope and transmitting the first clock signal to the sending signal conversion module; or,

The probe further includes: a clock signal transmission component for receiving a first clock signal generated by a clock signal generating device provided outside the probe and the oscilloscope, and transmitting the first clock signal to the sending signal conversion module.

In conjunction with the first aspect of the present application, in an optional implementation manner, the first clock signal is sent to the transmission signal conversion module through a high-speed serial protocol.

In conjunction with the first aspect of the present application, in an optional implementation, the input terminal includes a single-channel digital channel to receive a single-channel digital signal to be measured;

The transmission signal conversion module includes a comparator, the comparator is used to convert the received digital signal to be measured into a binary signal according to the first clock signal;

The output terminal is used to output the binary signal as the sending signal to the analog channel of the oscilloscope.

In conjunction with the first aspect of the present application, in an optional implementation, the input terminal includes a multi-channel digital channel to receive a single digital signal to be tested or multiple digital signals to be tested;

The transmission signal conversion module includes: a comparator and a code type selection unit; wherein the comparator is used to convert the received digital signal to be measured into a binary signal; the code type selection unit is used to selectively output The binary signal of the required pattern;

The output terminal is used to output the binary signal selectively output by the code type selection unit as the sending signal to the analog channel of the oscilloscope.

The transmission signal conversion module includes: a comparator, a coding circuit, and a code selection unit; wherein the comparator is used to convert the received digital signal to be measured into a binary signal; the coding circuit is used to convert The obtained binary signal is encoded to obtain a coded signal; the code type selection unit is used to selectively output the coded signal of a required code type;

The output end is used to output the encoding signal selectively output by the code type selection unit as the sending signal to the analog channel of the oscilloscope.

In conjunction with the first aspect of the present application, in an optional implementation, the code pattern selection unit is configured to obtain the first clock signal and perform a process of selectively outputting a required code pattern according to the first clock signal. The step of encoding a signal.

In conjunction with the first aspect of the present application, in an optional implementation, the transmission signal conversion module includes a parallel-to-serial conversion module.

In conjunction with the first aspect of the present application, in an optional implementation, the transmission signal conversion module includes a comparator, an encoding circuit, a code pattern selection unit, and a parallel-to-serial conversion module.

In the second aspect, an embodiment of the present application provides an oscilloscope, including: an analog channel, a serial-to-parallel conversion module, and a data processing module; wherein,

The serial-to-parallel conversion module is used to send a first clock signal to the probe based on a high-speed serial protocol, and perform serial-to-parallel conversion on the transmission signal from the probe received based on the analog channel and transmit it to the data processing Module; the clock signal used by the serial-to-parallel conversion module when performing serial-to-parallel conversion is a second clock signal, and the second clock signal and the first clock signal are homologous clock signals;

The data processing module processes and outputs the signal converted from serial to parallel by the serial to parallel conversion module.

In a third aspect, an embodiment of the present application provides a digital signal testing system, including: an oscilloscope and a probe; wherein the probe is the probe described in any one of the previous embodiments.

In conjunction with the third aspect of the present application, in an optional implementation manner, the probe is the probe described in the previous embodiment; the oscilloscope is the oscilloscope described in the previous embodiment.

The probe, oscilloscope and digital signal test system provided by the embodiment of the present application, wherein the probe includes: an input end, a transmission signal conversion module, and an output end; the input end is used to receive the digital signal to be measured; the transmission signal conversion module is connected to the input between the terminal and the output terminal, used to convert the received digital signal to be measured into a transmission signal that can be received by the analog channel of the oscilloscope according to the first clock signal; the first clock signal and the second clock signal are homologous clock signals, The second clock signal is the clock signal used by the receiving signal conversion module in the oscilloscope when working. The receiving signal conversion module is a module connected to the analog channel to receive the transmit signal; the output end is used to output the transmit signal to the analog channel of the oscilloscope; so , solves the problem of data recovery errors and improves the accuracy of digital signal testing.

Description of the drawings

The drawings described here are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the attached picture:

Figure 1 is a schematic structural diagram of a probe provided by an embodiment of the present application;

Figures 2a-2c are respectively schematic structural diagrams of the probe provided by the modified embodiment of the present application;

Figure 3 is a schematic structural diagram of a digital signal testing system provided by a specific example of this application;

Figure 4 is a schematic structural diagram of a digital signal testing system provided by another specific example of this application;

Figure 5 is a schematic circuit structure diagram of a digital signal testing system provided by another specific example of this application;

Figure 6 is a schematic diagram of differential phase shift keying modulation;

Figure 7a is a schematic diagram of the principle of generating a modulated signal through the selection method;

Figure 7b is a schematic diagram of the principle of generating a modulated signal through the multiplication method;

Figure 8 is a schematic structural diagram of a digital signal testing system provided by another specific example of this application;

Figure 9 is a schematic structural diagram of a probe provided by another embodiment of the present application;

Figure 10 is a schematic structural diagram of an oscilloscope provided by an embodiment of the present application;

Figure 11 is a schematic structural diagram of a digital signal testing system provided by an embodiment of the present application.

Detailed ways

In order to make the technical solutions and beneficial effects of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application are clearly and completely described below by enumerating specific embodiments. Obviously, the described embodiments are only for the purpose of this application. Apply for some of the embodiments, not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

It should be noted that in this application, words such as "for example" or "exemplary" are used to represent examples, illustrations or explanations. Any embodiment or design described herein as "such as" or "exemplary" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "such as" or "exemplary" is intended to present the concept in a concrete manner.

In this application, the terms "first", "second", "third", etc. are only used for descriptive purposes and serve to distinguish the indicated technical features, and cannot be understood as indicating or implying relative importance. or sequence, nor shall it be understood as implying an implicit indication of the quantity of technical features indicated. Therefore, technical features defined as “first”, “second”, “third”, etc. may include one or more of the technical features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more (including two). It will also be understood that the terms "comprises" and "comprising" mean that the presence of certain features, steps, operations, elements and/or components does not exclude the presence of one or more other features, steps, operations, elements and/or components. exist or add. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

As mentioned before, one end of a conventional logic probe is generally connected to the digital signal to be measured, and the other end is connected to the digital channel of the oscilloscope through an independent logic probe interface. There is a comparator inside the logic probe. After the digital signal to be measured enters the probe, it outputs a binary digital signal (1 or 0) through the comparator. The output digital signal is connected to the digital channel of the oscilloscope through an independent logic probe interface. After the logical data enters the oscilloscope, it is received and sampled through the ordinary I/O (such as differential I/O) port of the sampling processing chip (such as digital chip FPGA/ASIC). This method will occupy a large amount of I/O resources, and the sampling rate is affected by the performance of the I/O port of the FPGA/ASIC chip. It is often only on the order of 1GSa/s and cannot measure higher frequency signals. In addition, the probe needs to be connected to the oscilloscope through an independent logic probe interface, which increases the number of interfaces to be designed; the oscilloscope also needs to provide a digital channel socket, which increases the volume and is not conducive to improving product integration.

Related technologies have proposed changing the probe structure and using a digital-to-analog converter (DAC) inside the probe to convert the input digital signal to be measured into an analog signal, so that the output end can be connected to the analog channel of the oscilloscope; the analog signal enters the oscilloscope Finally, it is converted into a digital signal through the analog-to-digital converter (ADC) in the oscilloscope, and then output after processing. In this way, the analog channels of the oscilloscope are reused and the integration of the product is improved. However, since both DAC and ADC devices require digital clocks to drive, if the clocks of the two devices do not use the same source clock and are not synchronized, there will be a risk of metastability in the ADC sampling input data, ultimately leading to An error occurred in data recovery (decoding). In addition, the principle of the digital-to-analog converter is simple amplitude modulation (AM modulation), that is, converting digital signals into different amplitude representations; and amplitude modulation has the problem of being easily interfered. If there is movement of the line on the path connecting the probe to the oscilloscope, Or the situation of bending may cause the amplitude of the amplitude modulation signal to change, which may also cause data recovery errors.

Based on this, the embodiments of the present application aim to provide a technical solution that can reduce the probability of data recovery errors and improve the accuracy of digital signal testing.

First, please refer to Figure 1. As shown in the figure, the embodiment of the present application provides a probe 100, including: an input terminal 110, a transmission signal conversion module 120, and an output terminal 130.

Here, the probe 100 specifically includes two ends, namely an input end 110 and an output end 130; the input end 110 is used to receive the digital signal to be measured; the output end 130 is used to connect to the oscilloscope 200, specifically to output the sending signal to the oscilloscope. 200 analog channels 210.

The transmission signal conversion module 120 is connected between the input terminal 110 and the output terminal 130, and is used to convert the received digital signal to be measured into a transmission signal that can be received by the analog channel 210 of the oscilloscope 200 according to the first clock signal; wherein, the The first clock signal and the second clock signal are homologous clock signals. The second clock signal is the clock signal used by the receiving signal conversion module 220 in the oscilloscope 200 when working. The receiving signal conversion module 220 is connected to the analog channel 210 to receive the transmit signal. module.

It can be understood that the probe 100 provided in this embodiment is a special logic probe that converts the digital signal to be measured through the internal transmission signal conversion module 120 to realize the conversion of the digital signal into an analog channel that can be used by the oscilloscope 200 210 receives the transmitted signal, thereby realizing the multiplexing of the analog channel of the oscilloscope. The function of the transmission signal conversion module 120 to convert a digital signal into a transmission signal that can be received by the analog channel 210 of the oscilloscope 200 can be implemented using the structure described below in this application, in order to obtain corresponding technical effects; however, it should be noted that the following The described structure should not be understood as a limitation on the transmission signal conversion module 120 in this embodiment. Using other alternative methods in the art to convert digital signals into transmission signals that can be received by the analog channel 210 of the oscilloscope 200 should also be understood as belonging to This embodiment sends the scope of the signal conversion module 120 .

It should be noted that in this embodiment, the transmit signal conversion module 120 performs the step of converting the received digital signal to be measured into a transmit signal according to the first clock signal, and the first clock signal is the same as the receive signal conversion module in the oscilloscope 200 220 uses a clock signal from the same source as the second clock signal when working. In other words, the sending signal conversion module 120 performs synchronous clock processing with the receiving signal conversion module 220, ensuring the accuracy of data sampling and reducing the risk of data recovery errors. .

The source of the first clock signal and the second clock signal may be generated by a clock signal generation module provided in the probe 100, or may be generated by a clock signal generation module provided in the oscilloscope 200, or may be generated by a clock signal generation module provided in the probe 100 and the oscilloscope. 200 is generated by an external clock signal generating device.

Figures 2a to 2c respectively show probe structures provided by various modified embodiments.

Please refer to Figure 2a. In this modified embodiment, the probe 100 further includes: a clock signal generation module 140 and a clock signal transmission component 150. The clock signal generation module 140 is used to generate a first clock signal and a second clock signal; the clock signal transmission component 150 is used to transmit the first clock signal to the sending signal conversion module 120 and the second clock signal to the oscilloscope 200 The received signal conversion module 220.

In the structure shown in FIG. 2b , the probe 100 also includes: a clock signal transmission component 150 for receiving the first clock signal sent by the oscilloscope 200 and transmitting the first clock signal to the transmission signal conversion module 120 . In this modified embodiment, the first clock signal is generated by a clock signal generation module provided within the oscilloscope 200 , and the clock signal generation module provided within the oscilloscope 200 can also generate a second clock signal to receive the signal conversion module 220 to drive.

In the structure shown in Figure 2c, the probe 100 also includes: a clock signal transmission component 150, used to receive the first clock signal generated by the clock signal generation device 300 provided outside the probe 100 and the oscilloscope 200, and transmit the first clock signal transmitted to the transmission signal conversion module 120. In this modified embodiment, the clock signal generating device 300 can also generate a second clock signal, and send the second clock signal to the oscilloscope 200 to drive the received signal conversion module 220 .

It should be noted that although FIG. 2c shows that the first clock signal is directly sent to the probe 100 by the clock signal generating device 300, in this modified embodiment, it is not excluded that the clock signal generating device 300 generates a first clock of the same origin. signal and the second clock signal, send both to the oscilloscope 200 , and then the oscilloscope 200 sends the first clock signal to the probe 100 .

As an optional implementation manner, the first clock signal is sent to the transmission signal conversion module 120 through a high-speed serial protocol. When data is sent to the transmission signal conversion module 120 through the high-speed serial protocol, the first clock signal is, for example, embedded in the data and sent to the transmission signal conversion module 120 . Here, high-speed serial protocols include but are not limited to JESD204.

Next, please refer to Figure 3. In a specific example of the present application, the input end 110 of the probe 100 includes a single-channel digital channel to receive a single-channel digital signal (LA_IN) to be measured. The transmission signal conversion module 120 includes a comparator, which is used to convert the received digital signal to be measured into a binary signal according to the first clock signal. The output terminal 130 is used to output the binary signal as a transmission signal to the analog channel 210 of the oscilloscope 200 .

After the signal is transmitted to the oscilloscope 200, for example, it is transmitted to the analog-to-digital conversion module ("analog-to-digital conversion ADC" in the figure) in the oscilloscope 200 through the analog channel 210, thereby converting it into a digital signal, and then decoding and outputting.

In this specific example, a single LA channel corresponds to a comparator output. After comparing the measured channel, the analog-to-digital conversion module in the oscilloscope 200 is directly used for sampling; and, the comparator serves as the sending unit, and the analogue unit serves as the receiving unit. The digital conversion module uses the synchronization module ("Synchronization SYNC" in the figure) for synchronization processing to ensure the accuracy of data sampling. In addition, since the analog channels of the oscilloscope 200 are reused, there is no need to receive and sample through the ordinary I/O port of the sampling processing chip, which solves the problem of insufficient sampling rate, improves the sampling accuracy, and can realize the measurement of high-frequency signals. In addition, it solves the problem that conventional logic probes and oscilloscopes need to use a separate probe interface and a separate LA socket, improving the integration of the system.

Not only that, in this specific example, the binary signal output by the comparator is directly output to the oscilloscope 200 as a transmit signal, so that the digital 0 and 1 output by the comparator cover the 0 input and full-scale input sampled within the oscilloscope, and the signal amplitude spans Maximum, strong anti-interference ability, further reducing the probability of data recovery errors. Moreover, the probe in this specific example has a simple structure and low cost, and is suitable for measuring a single-channel digital signal to be measured.

Next, please refer to Figure 4. In another specific example of the present application, the input end 110 of the probe 100 includes a multi-channel digital channel to receive a single digital signal to be measured or multiple digital signals to be measured. Figure 4 shows the situation of receiving four channels of digital signals to be tested (LA_IN). It should be understood that this specific example should not be limited to this.

The transmission signal conversion module 120 includes a code type selection unit, and specifically selects the code type of the input digital signal through code type selection; and then passes the analog-to-digital conversion module ("analog-to-digital conversion ADC" in the figure) in the oscilloscope 200 to convert the analog signal Convert to digital signal. Through the synchronization module ("Synchronization SYNC" in the figure), the pattern selection unit as the sending unit and the analog-to-digital conversion module as the receiving unit are synchronized to avoid data sampling errors caused by clock non-synchronization. In addition, it solves the problem that conventional logic probes need to use a separate probe interface and a separate LA socket to connect to the oscilloscope 200, improving the integration of the system. Since the analog channels of the oscilloscope 200 are multiplexed, there is no need to receive and sample through the ordinary I/O port of the sampling processing chip, which solves the problem of insufficient sampling rate (usually the ADC sampling rate can reach tens of GSa/s, which is much higher than the differential I /O sampling rate), which improves the sampling accuracy and enables measurement of high-frequency signals.

Figure 5 is a schematic circuit structure diagram of a digital signal testing system provided in a specific example. The figure shows the circuit structure of the probe 100 (including the transmission signal conversion module 120) in this specific example. As shown in the figure, the transmission signal conversion module 120 includes: a comparator, an encoding circuit, and a code selection unit; wherein the comparator is used to convert the received digital signal to be measured into a binary signal; the encoding circuit is used to convert the converted The binary signal is encoded to obtain a coded signal; the code type selection unit is used to selectively output the coded signal of the required code type.

The output terminal 130 (not shown in the figure) is used to output the encoded signal selectively output by the code type selection unit as a transmission signal to the analog channel 210 of the oscilloscope 200 .

Figure 5 still takes the received digital signal to be tested as four-channel logic signals as an example. The digital signal to be tested generates four-channel binary data through the comparator, and then is encoded by the encoding circuit, and the corresponding code pattern is output through pattern selection. . The signal after pattern selection is sampled through analog-to-digital conversion to obtain a digital signal; then the logic signal is restored through decoding.

Here, the encoding method of the encoding circuit includes but is not limited to Gray code encoding, differential encoding, etc. The encoding of the encoding circuit may also include not changing the binary data generated by the comparator, that is, no substantial encoding is performed.

The corresponding code patterns output by the pattern selection include, for example, AM, FM, PM debugging patterns, etc. In this way, a variety of optional code types are provided for users, allowing users to choose the appropriate code type according to the actual situation. For example, if the line is prone to movement or bending on the path connecting the probe to the oscilloscope, the user can select other patterns besides the AM debugging pattern, such as FM.

Optionally, the transmission signal conversion module 120 may not include an encoding circuit and directly transmit the binary signal output by the comparator to the code type selection unit, thereby selectively outputting the binary signal of the required code type. In this way, the transmission signal conversion module 120 may include a comparator and a code type selection unit; and convert the received digital signal to be measured into a binary signal through the comparator; and selectively output the binary signal of the required code type through the code type selection unit. Signal.

It should be noted that the signal obtained after encoding by the encoding circuit is called the encoded signal. It is only to distinguish it from the binary signal output by the comparator. It does not mean that the encoded signal is not a binary signal. The encoded signal can be encoded. Binary signal.

Figure 5 specifically shows that a 10 MHz homologous clock is used to output the first and second clock signals to the transmitting unit (specifically, the pattern selection unit in the probe 100) and the receiving unit (specifically, the oscilloscope 200). analog-to-digital conversion module). The homologous clock can ensure that the signal frequency is consistent, and a definite phase relationship can be obtained through calibration. The design of a homologous clock is not limited to using a 10MHz clock from the same source. For example, you can also use only a 100MHz clock. The clock signal is multiplied by the phase-locked loop circuit (PLL) to the working frequency of the analog-to-digital conversion module and code selection unit (for example, 2GHz); and is adjusted and calibrated through delay in the sending unit or receiving unit (the specific example shown in Figure 5 is Delay adjustment is performed on the probe end); the receiving unit avoids the metastable interval, obtains the best sampling window, and reduces sampling errors.

It can be understood that the clock-related circuit structure shown in FIG. 5 is also applicable to the specific example shown in FIG. 3; and it should not be understood that the specific examples shown in FIGS. 3 to 5 can only adopt such a circuit structure.

Any one of the comparator, encoding circuit, and pattern selection unit can be used to obtain the first clock signal.

In an optional specific example, the code pattern selection unit is configured to obtain a first clock signal, and perform the step of selectively outputting an encoded signal of a required pattern according to the first clock signal. It can be understood that the pattern selection unit is closer to the output end 130 of the probe 100, that is, closer to the oscilloscope 200, so transmitting the first clock signal to the pattern selection unit is more conducive to clock synchronization between the sending signal and the receiving signal. It is possible to reduce the delay effect on the transmitted signal caused by the line after the pattern selection unit.

In order to clearly explain the encoding method of the encoding circuit, the following takes the encoding method of the encoding circuit as differential encoding as an example for explanation. Differential Encoding refers to the encoding of a digital data stream in which each element, except the first element, is represented as the difference between the element and its previous element.

Figure 6 is a schematic diagram of differential phase shift keying modulation. As shown in the figure, DPSK (Differential Phase Shift Keying) modulation is used as an example. In the figure, CLK is the original data clock and S is the absolute code. , DS is the relative code, MS is the modulated signal. The input signal can be regarded as a square wave signal with an amplitude of ±1, and the modulation process is the result of direct multiplication of the original signal and the carrier signal. The waveform in the figure assumes that each symbol period is an integer multiple of the carrier period. Compared with the relative code and the absolute code, if the absolute code is 0, the original level remains unchanged (for example, in the second cycle, S is low power Level 0, DS keeps the level of the first period unchanged, that is, it is still high level 1); if the absolute code is 1, the level changes (for example, in the third period, S is high level 1, DS changes from The high level 1 in the second cycle is converted into a low level 0). MS is a modulated signal, and the generation method can be multiplication or selection. Figure 7a is a schematic diagram of the principle of generating a modulated signal through the selection method; Figure 7b is a schematic diagram of the principle of generating a modulated signal through the multiplication method. The existing multiplication method or selection method can be used here and will not be discussed further. After modulation, the modulated signal is sent through the link to the receiving unit.

In this specific example, the input end 110 of the probe 100 includes a multi-channel digital channel, which can receive either a single digital signal to be measured or multiple digital signals to be measured. The situation of receiving multiple channels of digital signals to be tested has been described above. As for the situation of receiving a single channel of digital signals to be tested, as an optional implementation method, the single channel digital signal to be tested is output through a comparator. It is a binary signal. When the binary signal passes through the encoding circuit, the encoding circuit does not change the binary data generated by the comparator, that is, no actual encoding is performed, and is directly output to the oscilloscope 200 . As another optional implementation, the probe 100 further includes a selection unit, which is, for example, a switch; the selection unit is used to select the output end of the comparator to be connected to the input end of the encoding circuit, or to select the output end of the comparator to be connected to the input end of the encoding circuit. The output end is connected to the output end 130 of the probe 100; in this way, when receiving a single digital signal to be measured, the selection unit is controlled to connect the output end of the selection comparator to the output end 130 of the probe 100, thus realizing the same process as shown in Figure 3 The signal transmission path is similar to the specific example shown; when receiving multiple digital signals to be measured, the output end of the comparator is connected to the input end of the encoding circuit by controlling the selection unit, so that the binary signal output by the comparator is encoded and After the pattern is selected, it is output to the oscilloscope 200. In this way, the probe 100 provided in this specific example can detect not only a single digital signal to be tested, but also multiple digital signals to be tested.

Figure 8 is a schematic structural diagram of a digital signal testing system provided by another specific example of this application. As shown in the figure, the transmission signal conversion module 120 may include a parallel-to-serial conversion module; specifically, it is a Serdes parallel-to-serial conversion module. Correspondingly, the received signal conversion module 220 in the oscilloscope 200 may include a serial-to-parallel conversion module; specifically, it is a Serdes serial-to-parallel conversion module.

It can be understood that the parallel-to-serial conversion module performs parallel-to-serial conversion on the received parallel data. The serial-converted data is transmitted using a high-speed interface (for example, using the JESD204 high-speed serial protocol for transmission), and a high-speed interface receiver (can It is a Serdes parallel-to-serial converter for FPGA); due to the high speed of the high-speed interface, it can support higher LA sampling rates and more LA channel parallel inputs and transmissions.

A specific example of a high-speed serial protocol is JESD204B/C. The JESD204B/C protocol is used as the high-speed serial port protocol, and the synchronization module is the clock reference of JESD204B/C to ensure that the sending unit and receiving unit are source clock synchronized to ensure link synchronization and stability.

The clock signal used by the parallel-to-serial conversion module when working is the first clock signal; the clock signal used by the serial-to-parallel conversion module in the oscilloscope 200 when working is the second clock signal; the second clock signal and the first clock signal are homologous clock signals. .

It can be understood that this specific example requires an independent probe interface and socket to connect the high-speed serial data output by the probe 100 to the high-speed serial interface in the oscilloscope 200; however, this specific example does not require the use of conventional FPGA differential I/O ports. Instead, a high-speed serial port is used. In this way, higher transmission bandwidth can be obtained and the differential I/O port resources of the FPGA can be saved.

As a specific optional implementation, the transmission signal conversion module 120 may include both a comparator, an encoding circuit, and a code type selection unit, as well as a parallel-to-serial conversion module (refer to FIG. 9 ).

Of course, it can be understood that, for the case where the input end 110 of the probe 100 includes a single digital channel to receive a single digital signal to be measured, the sending signal conversion module 120 may include a comparator and a parallel-to-serial conversion module, which will not be discussed here. describe.

In this way, the data input by the probe is received (LA reception, which can use any of the specific examples shown in Figure 3 or any of the specific examples shown in Figures 4 and 5), and then transmitted to the parallel-to-serial conversion module, and then The serial conversion module transmits to the serial-to-parallel conversion module in the oscilloscope 200 . As a result, higher transmission bandwidth can be obtained, the accuracy of data sampling can be guaranteed, and the integration of the product can be improved.

An embodiment of the present application also provides an oscilloscope. FIG. 10 is a schematic structural diagram of the oscilloscope provided in this embodiment. As shown in the figure, the oscilloscope 200 includes: an analog channel 210, a serial-to-parallel conversion module, and a data processing module 230.

Here, the received signal conversion module 220 specifically adopts a serial-to-parallel conversion module. The serial-to-parallel conversion module is used to send the first clock signal to the probe 100 based on the high-speed serial protocol, and to perform the transmission signal from the probe 100 received based on the analog channel 210. The serial-to-parallel conversion is performed and transmitted to the data processing module 230 .

The clock signal used by the serial-to-parallel conversion module when performing serial-to-parallel conversion is the second clock signal, and the second clock signal and the first clock signal are clock signals of the same origin.

The serial-to-parallel conversion module sends a first clock signal to the probe 100, so that the parallel-to-serial conversion module in the probe 100 operates using the first clock signal.

The data processing module 230 processes and outputs the signal converted from serial to parallel by the serial to parallel conversion module. The data processing module 230 performs sampling/decoding, for example; in addition, the data processing module 230 may also include a CPU to perform operations such as statistics, calibration, and configuration (refer to the oscilloscope 200 in FIG. 5 ).

An embodiment of the present application also provides a digital signal testing system. FIG. 11 is a schematic structural diagram of the digital signal testing system provided by an embodiment of the present application. As shown in the figure, the digital signal testing system 800 includes: an oscilloscope 200 and a probe 100; wherein the probe 100 is the probe provided in any of the aforementioned embodiments.

It can be understood that the oscilloscope 200 can be an existing oscilloscope, or it can be an oscilloscope provided in any of the previous embodiments of this application.

It should be noted that the probe embodiments, oscilloscope embodiments and digital signal test system embodiments provided in the embodiments of this application belong to the same concept; the technical features in the technical solutions recorded in each embodiment shall not conflict with each other unless there is any conflict. , can be combined in any way.

It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes can also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, various technical features of the above embodiments may also be combined arbitrarily to form additional embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementation modes of the present application and do not limit the protection scope of the present application.

Claims

A probe includes: an input terminal, a sending signal conversion module, and an output terminal; wherein,

The input terminal is used to receive the digital signal to be measured;

The transmission signal conversion module is connected between the input terminal and the output terminal, and is used to convert the received digital signal to be measured into a transmission signal that can be received by the analog channel of the oscilloscope according to the first clock signal; Wherein, the first clock signal and the second clock signal are homologous clock signals, the second clock signal is the clock signal used by the receiving signal conversion module in the oscilloscope when working, and the receiving signal conversion module is and The analog channel is connected to receive the module that sends the signal;

The output terminal is used to output the sending signal to the analog channel of the oscilloscope.
The probe according to claim 1, wherein

The probe also includes: a clock signal generation module and a clock signal transmission component; the clock signal generation module is used to generate the first clock signal and the second clock signal; the clock signal transmission component is used to transmit the The first clock signal is transmitted to the transmit signal conversion module, and the second clock signal is transmitted to the receive signal conversion module of the oscilloscope; or,

The probe also includes: a clock signal transmission component for receiving the first clock signal sent by the oscilloscope and transmitting the first clock signal to the sending signal conversion module; or,

The probe further includes: a clock signal transmission component for receiving a first clock signal generated by a clock signal generating device provided outside the probe and the oscilloscope, and transmitting the first clock signal to the sending signal conversion module.
The probe of claim 1, wherein the first clock signal is sent to the transmit signal conversion module through a high-speed serial protocol.
The probe according to claim 1, wherein the input terminal includes a single-channel digital channel to receive a single-channel digital signal to be measured;

The transmission signal conversion module includes a comparator, the comparator is used to convert the received digital signal to be measured into a binary signal according to the first clock signal;

The output terminal is used to output the binary signal as the sending signal to the analog channel of the oscilloscope.
The probe according to claim 1, wherein the input terminal includes a multi-channel digital channel to receive a single digital signal to be measured or multiple digital signals to be measured;

The transmission signal conversion module includes: a comparator and a code type selection unit; wherein the comparator is used to convert the received digital signal to be measured into a binary signal; the code type selection unit is used to selectively output The binary signal of the required pattern;

The output terminal is used to output the binary signal selectively output by the code type selection unit as the sending signal to the analog channel of the oscilloscope.
The probe according to claim 1, wherein the input terminal includes a multi-channel digital channel to receive a single digital signal to be measured or multiple digital signals to be measured;

The transmission signal conversion module includes: a comparator, a coding circuit, and a code selection unit; wherein the comparator is used to convert the received digital signal to be measured into a binary signal; the coding circuit is used to convert The obtained binary signal is encoded to obtain a coded signal; the code type selection unit is used to selectively output the coded signal of a required code type;

The output end is used to output the encoding signal selectively output by the code type selection unit as the sending signal to the analog channel of the oscilloscope.
The probe according to claim 5 or 6, wherein the pattern selection unit is configured to acquire the first clock signal and perform the encoding of selectively outputting the required pattern according to the first clock signal. Signal steps.
The probe according to claim 1, wherein the transmission signal conversion module includes a parallel-to-serial conversion module.
The probe according to claim 1, wherein the transmission signal conversion module includes a comparator, an encoding circuit, a pattern selection unit, and a parallel-to-serial conversion module.
An oscilloscope includes: analog channels, serial-to-parallel conversion module, and data processing module; wherein,

The serial-to-parallel conversion module is used to send a first clock signal to the probe based on a high-speed serial protocol, and perform serial-to-parallel conversion on the transmission signal from the probe received based on the analog channel and transmit it to the data processing Module; the clock signal used by the serial-to-parallel conversion module when performing serial-to-parallel conversion is a second clock signal, and the second clock signal and the first clock signal are homologous clock signals;

The data processing module processes and outputs the signal converted from serial to parallel by the serial to parallel conversion module.
A digital signal testing system, including: an oscilloscope and a probe; wherein,

The probe is the probe according to any one of claims 1-9.
The digital signal testing system according to claim 11, wherein the probe is the probe according to claim 8 or 9; the oscilloscope is the oscilloscope according to claim 10.