WO2023185898A1

WO2023185898A1 - Pixel circuit and display screen

Info

Publication number: WO2023185898A1
Application number: PCT/CN2023/084571
Authority: WO
Inventors: 高取宪一; 寺西康幸
Original assignee: 华为技术有限公司
Priority date: 2022-03-30
Filing date: 2023-03-29
Publication date: 2023-10-05
Also published as: CN116935789A

Abstract

Disclosed are a pixel circuit and a display screen. The pixel circuit comprises a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a driving transistor (DT), a first capacitor (C1), a second capacitor (C2), and a light emitting diode (OLED). The first transistor (T1), the third transistor (T3), the fourth transistor (T4), and the fifth transistor (T5) are indium-gallium-zinc oxide thin film transistors. The second transistor (T2) and the driving transistor (DT) are low-temperature polycrystalline silicon thin film transistors. The present application can be suitable for working in a low-frequency state to reduce power consumption, and a light-emitting state of the organic light-emitting diode (OLED) is not affected.

Description

Pixel circuit and display screen

This application claims priority to the Chinese patent application filed with the China Patent Office on March 30, 2022, with the application number 202210327265.7 and the application name "pixel circuit and display screen", the entire content of which is incorporated into this application by reference.

Technical field

The present invention relates to the field of display technology, and in particular to a pixel circuit and a display screen.

Background technique

OLED displays made of organic light-emitting diodes (OLED) do not require a backlight, and have high contrast, thin thickness, wide viewing angle, fast response speed, can be used in flexible panels, and a wide operating temperature range Its excellent characteristics such as simple structure and simple manufacturing process make it widely used in various display devices.

The organic light-emitting diodes in the OLED display are driven by pixel circuits to emit light. However, the transistors used in existing pixel circuits are usually low temperature polycrystalline silicon (LTPS) thin film transistors (TFT). LTPS TFT has high on-current and is suitable for working under high frequency conditions. However, the power consumption in the high-frequency working state is relatively large, and it is difficult to meet the demand for products to work in the low-frequency state to achieve low power consumption. Therefore, how to design a pixel circuit that can be adapted to operate in a low-frequency state without affecting the light-emitting state of the organic light-emitting diode is an urgent technical problem that those skilled in the art need to solve.

Contents of the invention

The embodiment of the present application discloses a pixel circuit and a display screen, which can be adapted to work in a low-frequency state to reduce power consumption without affecting the light-emitting state of the organic light-emitting diode.

In a first aspect, embodiments of the present application provide a pixel circuit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a driving transistor, a first capacitor, a second capacitor, and a Light emitting diode; the first transistor, the third transistor, the fourth transistor and the fifth transistor are indium gallium zinc oxide thin film transistors, and the second transistor and the driving transistor are low temperature polysilicon thin film transistors;

The first electrode of the first transistor, the first electrode of the fifth transistor, the first end of the first capacitor and the first end of the second capacitor are electrically connected and intersect at the first node;

The second end of the second capacitor, the first electrode of the fourth transistor and the gate of the drive transistor are electrically connected to intersect at the second node;

The second electrode of the first transistor, the first electrode of the driving transistor and the first electrode of the second transistor are electrically connected and intersect at a third node;

The second electrode of the driving transistor, the first electrode of the third transistor and the anode of the light-emitting diode are electrically connected to intersect at a fourth node, and the cathode of the light-emitting diode is grounded;

The second end of the first capacitor is connected to the second electrode of the second transistor, and the second electrode of the second transistor is used to input the power supply voltage;

The gates of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are respectively used to input gate control signals;

The second electrode of the fifth transistor is used to input a data voltage, the second electrode of the third transistor is used to input a first initialization control signal, and the second electrode of the fourth transistor is used to input a second initialization control signal. .

In a possible implementation, during the initialization phase and voltage compensation phase of the pixel circuit, the first crystal tube, the third transistor and the fourth transistor are turned on, the second transistor and the fifth transistor are turned off; the voltage of the fourth node is initialized to the first initialization control signal, and the third transistor is turned off. The voltages of the two nodes are initialized to the second initialization control signal, and the voltages of the third node and the first node are both the difference between the second initialization control signal and the threshold voltage of the driving transistor.

In a possible implementation, during the data writing phase of the pixel circuit, the first transistor and the fifth transistor are turned on, and the second transistor, the third transistor and the fourth transistor are Turn off; the voltage of the first node is the data voltage, and the voltage of the second node is the sum of the data voltage and the threshold voltage of the driving transistor.

In a possible implementation, during the light-emitting phase of the pixel circuit, the second transistor is turned on, and the first transistor, the third transistor, the fourth transistor and the fifth transistor are turned off. ; The driving current generated based on the power supply voltage input by the second electrode of the second transistor drives the light-emitting diode to emit light.

In the pixel circuit provided by the embodiment of the present application, the first transistor, the fourth transistor and the fifth transistor in the leakage path of the first capacitor and the second capacitor used to store data voltage all use indium gallium zinc oxide thin film transistors. The third transistor connected to the light-emitting diode also uses an indium gallium zinc oxide thin film transistor. This reduces the leakage current of the pixel circuit as a whole, keeps the voltage of the pixel circuit stable, and optimizes the display effect of the light-emitting diode. Due to the unique connection relationship of the pixel circuit provided by the embodiments of the present application, the voltage compensation stage and the data writing stage of the pixel circuit can be controlled separately, so that the compensation time can be flexibly adjusted, the compensation result can be optimized, and the display effect can be optimized.

In a possible implementation, the pixel circuit further includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is used to input a third Initialize control signals.

Optionally, the sixth transistor is an indium gallium zinc oxide thin film transistor; or, the sixth transistor is a low temperature polysilicon thin film transistor.

In the pixel circuit provided by the embodiment of the present application, the sixth transistor can be used to initialize the voltage at the third node in the initialization phase, reducing the impact of the residual charge of the previous frame signal at the third node on the voltage compensation phase. , optimizes the effect of voltage compensation, further improves the problem of LED display flicker, and optimizes the display effect of LEDs.

In a possible implementation, the pixel circuit further includes a third capacitor, a first terminal of the third capacitor is electrically connected to the first node, and a second terminal of the third capacitor is electrically connected to the The third node.

In the pixel circuit provided by the embodiment of the present application, the voltage difference of the third capacitor can be used to maintain the voltage at the third node during the light emitting stage. In the light-emitting phase, when the second transistor is turned on, the change in gate voltage of the driving transistor relative to the source voltage decreases, that is, Vgs decreases. The third capacitor can stabilize the voltage, keep Vgs stable and reduce the fluctuation of Vgs, which is equivalent to the effect of voltage compensation, making the voltage compensation effect of the entire pixel circuit more significant.

In a possible implementation, the gate control signal of the fifth transistor and the gate control signal of the sixth transistor are control signals from different rows of gate drive circuits in the same group of gate drive circuits.

In the pixel circuit provided by the embodiment of the present application, since the gate drive circuit is arranged in the outer edge area of the display area of the display device, reusing a group of gate drive circuits can reduce the number of drive circuits, thereby reducing the number of drive circuits in the outer edge area of the display area. area to reduce the width of the display screen.

In a possible implementation, during the initialization phase of the pixel circuit, the sixth transistor, the first transistor, the third transistor and the fourth transistor are turned on, and the second transistor and the The fifth transistor is turned off; the voltage of the fourth node is initialized to the first initialization control signal, the voltage of the second node is initialized to the second initialization control signal, and the voltage of the third node is initialized to The third initialization control signal;

During the voltage compensation phase of the pixel circuit, the sixth transistor is turned off, and the states of the remaining transistors remain as described. In the state of the initialization phase, the voltages of the third node and the first node are both the difference between the second initialization control signal and the threshold voltage of the driving transistor.

In a possible implementation, during the data writing phase of the pixel circuit, the first transistor and the fifth transistor are turned on, and the second transistor, the third transistor, and the fourth transistor are and the sixth transistor is turned off; the voltage of the first node is the data voltage, and the voltage of the second node is the sum of the data voltage and the threshold voltage of the driving transistor.

In a possible implementation, the gate control signals of the first transistor and the fourth transistor are the same signal. In this implementation, during the data writing phase of the pixel circuit, the fifth transistor is turned on, and the first transistor, the second transistor, the third transistor, the fourth transistor and The sixth transistor is turned off; the voltage of the first node is the data voltage, and the voltage of the second node is the sum of the data voltage and the threshold voltage of the driving transistor.

In the pixel circuit provided by the embodiment of the present application, since the gate drive circuit is arranged in the outer edge area of the display area of the display device, reusing the same gate drive signal can reduce the number of drive circuits, thereby reducing the number of drive circuits in the outer edge area of the display area. area to reduce the width of the display screen.

In a possible implementation, during the light-emitting phase of the pixel circuit, the second transistor is turned on, and the first transistor, the third transistor, the fourth transistor, the fifth transistor and the The sixth transistor is turned off; the driving current generated based on the power supply voltage input by the second electrode of the second transistor drives the light-emitting diode to emit light.

In a possible implementation, during the dimming stage of the pixel circuit, the luminous brightness of the light-emitting diode is adjusted by performing pulse width modulation on the gate control signals of the second transistor and the third transistor.

In the pixel circuit provided by the embodiment of the present application, the brightness of the light-emitting diode can be adjusted by performing pulse width modulation on the gate control signals of the second transistor and the third transistor.

Based on the above implementation, it can be seen that the pixel circuit provided by the embodiment of the present application can separately control the voltage compensation stage and the data writing stage of the pixel circuit, thereby flexibly adjusting the compensation time, optimizing the compensation results, and further optimizing the display effect.

In a second aspect, embodiments of the present application provide a display screen. The display screen includes a pixel circuit, a gate drive circuit, a display drive chip and a power supply chip; the gate drive circuit is used to provide a gate for the pixel circuit. Control signals, the display driver chip is used to provide initialization control signals and data voltages for the pixel circuit, the power chip is used to provide power signals for the pixel circuit; the pixel circuit is any one of the above first aspects The pixel circuit.

The beneficial effects achieved by the display screen provided by the embodiments of the present application can be found in the corresponding description in the first aspect above, and will not be described again here.

Description of drawings

Figure 1 shows a schematic diagram of a pixel circuit;

Figure 2 shows a schematic structural diagram of a display device provided by an embodiment of the present application;

Figure 3 shows a schematic structural diagram of a display device provided by an embodiment of the present application;

Figure 4 shows a schematic diagram of a pixel circuit provided by an embodiment of the present application;

Figure 5 shows a timing diagram of a pixel circuit provided by an embodiment of the present application;

Figure 6 shows a schematic diagram of a pixel circuit provided by an embodiment of the present application;

Figure 7 shows a timing diagram of a pixel circuit provided by an embodiment of the present application;

Figure 8 shows a schematic diagram of a pixel circuit provided by an embodiment of the present application;

Figure 9 shows a timing diagram of a pixel circuit provided by an embodiment of the present application;

Figure 10 shows a schematic diagram of the simulation results of the voltage compensation effect provided by the embodiment of the present application;

Figure 11 shows a schematic diagram of the compensation effect provided by the embodiment of the present application;

FIG. 12 shows a timing diagram of a pixel circuit provided by an embodiment of the present application.

Detailed ways

The embodiments of the present application are described below with reference to the accompanying drawings.

In order to facilitate understanding of the solution of the present application, the problems existing in the pixel circuit of the existing OLED display screen are first described with reference to FIG. 1 .

Figure 1 shows the circuit structure of a conventional pixel circuit. The pixel circuit includes 7 thin film transistors (TFT), 1 capacitor Cst and organic light-emitting diode (OLED). The seven TFTs are T1, T2, T3, T4, T5, T6 and DT shown in Figure 1 respectively. Among them, T1 and T4 are indium gallium zinc oxide (IGZO) TFTs, and transistors T2, T3, T5, T6 and DT are low temperature polycrystalline silicon (LTPS) TFTs. The DT is a drive transistor, used to drive the OLED to emit light. The specific connection relationship between the seven TFTs, the capacitor Cst and the OLED is shown in Figure 1 and will not be described again here.

Thin film transistor TFT is a field effect transistor, so the three electrodes of TFT are source, gate and drain. The TFT can control its own on and off by inputting a control signal from the gate.

The turn-on and turn-off of the transistor T1 can be controlled by the gate control signal IGZO G1. The gate control signal IGZO G1 uses IGZO to indicate that the control signal is a control signal that controls the IGZO TFT. The G in G1 indicates the control signal input to the gate. The 1 in G1 is a serial number. Use To distinguish the control signals of different transistors. The meanings of the symbols representing the gate control signals of the transistors described later can be referred to the description here, and will not be described again. The turn-on and turn-off of the transistor T2 and the transistor T6 can be controlled by the gate control signal LTPS G2. The turn-on and turn-off of the transistor T3 can be controlled by the gate control signal LTPS G3. The turn-on and turn-off of the transistor T4 can be controlled by the gate control signal IGZO G4. The turn-on and turn-off of the transistor T5 can be controlled by the gate control signal LTPS G5.

In Figure 1, vinit1 and vinit2 are initialization control signals, which can be an input voltage used to initialize the circuit. V _data is a voltage that represents pixel data. The voltage V _data is written into the circuit and can be used to control the luminance of the OLED. Vss represents the ground terminal voltage.

By controlling the on or off of the above seven transistors, the initialization of the pixel circuit, voltage compensation, data writing and OLED lighting can be achieved.

The initialization of the pixel circuit can restore the pixel circuit to its initial state, reducing the impact of the pixels of the previous frame image on the pixel display of the next frame image. The transistor T4 and the transistor T3 can be controlled to be turned on and other transistors turned off through the gate control signal IGZO G4 and the gate control signal LTPS G3. As a result, the voltage at node N4 is initialized to vinit2, that is, the anode of the OLED is reset. And, the voltage at node N1 can be initialized to vinit1.

Voltage compensation compensates for voltage drops caused by transistor leakage and manufacturing process issues in the circuit. Data writing is to save pixel data in the form of voltage into the capacitor of the pixel circuit. In the pixel circuit shown in Figure 1, voltage compensation and data writing are implemented together. The transistor T5 is controlled to be turned on by the gate control signal LTPS G5, the transistor T1 is controlled to be turned on by the gate control signal IGZO G1, and the other transistors are turned off. At this time, since the voltage of the gate of the transistor DT is lower than the voltage of the source of the transistor DT (the electrode connected to the node N2 of the transistor DT in FIG. 1), the transistor DT is also turned on. This is because the conduction of the transistor DT is controlled by the voltage V _gs . When V _gs < V _th , the DT is turned on. Vgs is the voltage difference between the voltage at the gate of transistor DT relative to the voltage at the source. _Vth is the threshold voltage of transistor DT.

As a result, the data voltage V _data charges the capacitor Cst through the turned-on transistor T5, the transistor DT, and the transistor T1, that is, the data voltage V data charges the gate of the transistor DT. During the charging process, the gate voltage of the transistor DT gradually increases. Until the voltage difference between the gate electrode and the source electrode of the transistor DT is equal to the threshold voltage V _th of the transistor DT, the transistor DT is turned off. at this time, The voltage at the node N2 is V _data , that is, the voltage at the source of the transistor DT is V _data . Then the voltage at node N1 is V _data +V _th . Since transistor T1 is turned on, the voltage at node N3 is equal to the voltage at node N1. That is, the voltage at node N3 is V _data +V _th .

The process of OLED emitting light is the process of driving OLED to emit light through driving current. After the above data is written, the transistors T2 and T6 are controlled to be turned on by the gate control signal LTPS G2, and the other transistors are turned off. The driving current generated by VDD flows through the transistor DT and drives the OLED to emit light. Among them, the capacitor Cst can control the gate voltage of the transistor DT, so that the transistor DT can be turned on normally. The size of the driving current can be expressed by the following formula:

Among them, μ represents the carrier mobility of the transistor DT, W is the width of the channel in the transistor DT, L is the length of the channel in the transistor DT, C _ox is the gate oxide capacitance per unit area of the transistor DT, and V _gs is the transistor The voltage of DT's gate relative to its source. The source voltage of transistor DT is the voltage at node N2. Since transistor T6 is turned on, the voltage at node N2 is equal to VDD. The voltage at the gate of transistor DT is the voltage at node N1. In the above data writing stage, it can be seen that the voltage at node N1 = the voltage at node N3 = V _data + V _th . Then V _gs =(V _data +V _th )-VDD, from which it can be obtained that V _gs -V _th =((V _data +V _th )-VDD)-V _th =V _data -VDD. It can be seen from the formula that the driving current I _ds has nothing to do with the threshold voltage V _th of the transistor DT, thus realizing compensation for the threshold voltage of the transistor DT.

In the pixel circuit shown in Figure 1 above, the transistors T2, T3, T5, T6 and DT are LTPS TFTs. The on-current of LTPS TFTs is high, but the leakage current is also high. When the circuit operates in a low-frequency state (for example, the frequency is 1 to 10 Hz), high leakage current will cause the voltage of the circuit to slowly decrease, causing the OLED to emit different brightness at different times, causing flickering problems. Especially the leakage current of transistors T5 and T2 is too large, which affects the effect of data writing and voltage compensation.

Based on the above description, it can be seen that in the pixel circuit shown in Figure 1, the voltage compensation and data writing processes are completed simultaneously. The compensation time and the data writing time are strongly coupled, and the compensation time cannot be adjusted independently. When different display screens require different compensation times due to process fluctuations, the inability to flexibly adjust the compensation time will affect the voltage compensation effect, thereby affecting the uniformity of the display effect.

In order to solve the above problems, embodiments of the present application provide a pixel circuit and a display device. The pixel circuit can reduce leakage current, thereby maintaining the stability of the circuit voltage and reducing the problem of OLED light flickering. The voltage compensation stage and the data writing stage of the pixel circuit can be controlled separately, so that the compensation time can be flexibly adjusted, the compensation results can be optimized, and the display effect can be optimized.

Referring to FIG. 2 , a schematic circuit structure diagram of a display device 200 provided by an embodiment of the present application is exemplarily introduced. For example, the display device 200 may be a display screen.

As shown in FIG. 2 , the display device 200 includes a display screen substrate 210 and a circuit board 220 . The display screen substrate 210 includes multiple pixel circuits, and one pixel circuit 211 is shown in FIG. 2 as an example. The pixel circuit 211 is connected to the light-emitting diode 214 for driving the light-emitting diode 214 to emit light. The display screen substrate 210 also includes a gate driving circuit 212 and a gate driving circuit 213. The gate driving circuit 212 and the gate driving circuit 213 are respectively connected to the pixel circuit 211. is connected to provide a gate control signal to the pixel circuit 211.

The above-mentioned circuit board 220 includes a display driver chip (display driver integrated circuit, DDIC) 221 and a power chip 222. The display driving chip 221 is connected to the pixel circuit 211, the gate driving circuit 212 and the gate driving circuit 213 respectively. The display driver chip 221 is used to provide power signals and pixel data to the pixel circuit 211 . Furthermore, the display driving chip 221 is used to provide clock signals to the gate driving circuit 212 and the gate driving circuit 213 . The gate driving circuit 212 and the gate driving circuit 213 may provide a gate control signal to the pixel circuit 211 based on the clock signal. The high and low levels of the gate control signal are controlled based on the clock signal.

The power chip 222 is connected to the pixel circuit 211, the gate driving circuit 212 and the gate driving circuit 213 respectively. The power chip 222 can be used to provide required power signals for the pixel circuit 211, the gate driving circuit 212 and the gate driving circuit 213.

In some implementations of the embodiments of the present application, the above-mentioned circuit board 220 may be a flexible printed circuit board.

In some implementations of the embodiments of the present application, the above-mentioned display device 200 can be applied to various electronic devices. For example, the electronic device may include but is not limited to any electronic product based on an intelligent operating system, which can perform human-computer interaction with the user through input devices such as keyboards, virtual keyboards, touch pads, touch screens, and voice control devices. Such as smartphones, tablet computers (tablet personal computer, Tablet PC), handheld computers, wearable electronic devices (such as VR glasses and smart watches, etc.), personal computers (personal computer, PC) and desktop computers. Electronic devices may also include, but are not limited to, any kind of Internet of Things (IoT) devices.

For ease of understanding, FIG. 3 shows a schematic structural diagram of the corresponding display device, taking the electronic device as a smart watch as an example. The display device of the smart watch shown in Figure 3 includes a display area and an outer edge area of the display area. A plurality of pixel circuits are provided in the display area. The plurality of pixel circuits may be arranged in rows, and the number of pixel circuits arranged in each row may be the same or different. A pixel circuit is used to display one pixel. A gate driving circuit may be provided in the outer edge area of the display area. A display driver chip in the flexible printed circuit board is also disposed in the outer edge area of the display area. The flexible printed circuit board can be bent to the backside of the outer edge area of the display area.

For example, in a specific implementation, each pixel circuit can be controlled by multiple sets of gate driving circuits. Each group of gate driving circuits may include a plurality of rows of gate driving circuits, and each row of gate driving circuits in the plurality of rows of gate driving circuits may provide one or more gate control signals. For example, there is a set of gate driving circuits that can provide a light-emitting control signal for the pixel circuit. The light-emitting control signal can be exemplified by referring to the gate control signal Emit of the transistor T2 in FIG. 4 below. In addition, there are one or more sets of gate driving circuits that can provide gate scanning signals for the pixel circuit. The gate scanning signals can be exemplified by the gate control signal scan1 of the transistor T4 and the gate control of the transistor T3 in Figure 4 below. signal scan2 and gate control signal scan3 of transistor T1. Moreover, there are one or more groups of gate driving circuits that can provide other gate control signals for the pixel circuit. The other gate control signals can be exemplarily referred to the gate control signal G1 of the transistor T5 in FIG. 4 below. This is just an example. The embodiment of the present application does not limit how many groups of driving circuits a pixel circuit is controlled by.

It should be noted that the display device shown in FIG. 2 and FIG. 3 is only an example of some components, and the specific implementation may also include other components, which are not limited by the embodiments of the present application.

The pixel circuit provided by the embodiment of the present application can be exemplified by reference to FIG. 4 . The pixel circuit shown in Figure 4 includes 6 thin film transistors TFT, 2 capacitors and 1 OLED. The thin film transistor TFT may include T1, T2, T3, T4, T5, and DT. Among them, the transistors T1, T3, T4 and T5 are IGZO TFTs, and the transistors T2 and DT are LTPS TFTs. DT is a driving transistor, used to drive OLED to emit light. Capacitors include C1 and C2. In the pixel circuit shown in Figure 4, the transistors T1, T4 and T5 in the leakage path of the capacitor C1 and the capacitor C2 used to store the data voltage all use IGZO TFTs. The transistor T3 connected to the OLED also uses IGZO TFT. Compared with the pixel circuit shown in Figure 1 above, the leakage current of the pixel circuit is reduced as a whole, the voltage of the pixel circuit is kept stable, and the display effect of the OLED is optimized. Compared with the pixel circuit shown in FIG. 1, the specific connection relationship of the pixel circuit shown in FIG. 4 is different, such as the number of transistors and the connection position of the transistor T5 for inputting the data voltage V _data . Through the pixel circuit shown in Figure 4, the voltage compensation stage and the data writing stage of the pixel circuit can be controlled separately, so that the compensation time can be flexibly adjusted, the compensation result can be optimized, and the display effect can be optimized.

Each of the six transistors includes a first electrode, a second electrode and a gate electrode. If the first electrode of a transistor is the source, the second electrode of the transistor is the drain. Alternatively, if the first electrode of a transistor is the drain, the second electrode of the transistor is the source. Whether the first electrode of each transistor is the source or the drain is determined based on the actually implemented function. In the same way, whether the second electrode of each transistor is the source or the drain is also determined based on the actual implemented function. The description of the embodiments of the present application does not limit the specific electrode properties of the first electrode and the second electrode. In Figure 4, "①" represents the first electrode of the transistor, and "②" represents the second electrode of the transistor.

In the pixel circuit shown in FIG. 4 , the first electrode of the transistor T1 and the first electrode of the transistor T5 are connected and intersected at the node N1 , and the second electrode of the transistor T1 and the first electrode of the transistor T2 are connected and intersected at the node N3 . The gate of the transistor T1 is connected to the first gate drive circuit. In FIG. 4 , the symbol “(g)” represents the gate of the transistor, and the symbol following “(g)” represents the control signal of the gate. For example, in the symbol "(g)scan3" on the gate of the transistor T1, "(g)" represents the gate of the transistor T1, and "scan3" represents the control signal of the gate. The symbols shown on the gates of other transistors are the same and will not be described again. The first gate driving circuit may generate the gate control signal scan3. The gate control signal scan3 controls the on and off of the transistor T1. For example, the first gate driving circuit may be the gate driving circuit 212 or the gate driving circuit 213 in FIG. 2 , or may be another driving gate circuit not shown in FIG. 2 .

The second electrode of the transistor T2 may be connected to the power chip. The power chip may input the power supply voltage VDD from the second electrode of the transistor T2 to the pixel circuit. The power chip may be, for example, the power chip 222 in FIG. 2 . For example, the VDD may be a high-power power supply voltage PVDD. The gate of the transistor T2 is connected to the second gate drive circuit. The second gate driving circuit may generate the gate control signal Emit. The gate control signal Emit controls the on and off of the transistor T2. The second gate driving circuit may be, for example, the gate driving circuit 212 or the gate driving circuit 213 in FIG. 2 , or may be another driving gate circuit not shown in FIG. 2 .

The second electrode of the transistor T5 is connected to the display driver chip. The display driving chip may input the voltage V _data of the pixel data from the second electrode of the transistor T5 to the pixel circuit. The display driver chip may be, for example, the display driver chip 221 in FIG. 2 . The gate of the transistor T5 is connected to the fifth gate driving circuit. The fifth gate driving circuit may generate the gate control signal G1. The gate control signal G1 controls the on and off of the transistor T5. The fifth gate driving circuit may be, for example, the gate driving circuit 212 or the gate driving circuit 213 in FIG. 2 , or may be another driving gate circuit not shown in FIG. 2 .

The first electrode of the transistor T5 and the first electrode of the transistor T1 are also connected to the first terminal of the capacitor C1 and intersect at the node N1. In Figure 4, “①” is used to indicate the first end of capacitor C1. The second terminal of the capacitor C1 is connected to the second electrode of the transistor T2. In Figure 4, “②” is used to indicate the second end of capacitor C1.

The first electrode of the transistor T5, the first electrode of the transistor T1 and the first end of the capacitor C1 are also connected to the first end of the capacitor C2 and intersect at the node N1. In Figure 4, “①” represents the first end of capacitor C2.

The second terminal of capacitor C2 intersects the first electrode connection of transistor T4 at node N2. In Figure 4, “②” is used to indicate the second end of capacitor C2.

The second electrode of the transistor T4 is connected to the display driver chip. The display driver chip may input the initialization control signal vinit2 from the second electrode of the transistor T4 to the pixel circuit. The display driver chip may be, for example, the one shown in Figure 2 Display driver chip 221. The initialization control signal vinit2 can be an input voltage. The gate of the transistor T4 is connected to the fourth gate driving circuit. The fourth gate driving circuit may generate the gate control signal scan1. The gate control signal scan1 controls the on and off of the transistor T4. The fourth gate driving circuit may be, for example, the gate driving circuit 212 or the gate driving circuit 213 in FIG. 2 , or may be another driving gate circuit not shown in FIG. 2 .

The first electrode of transistor T4 and the second end of capacitor C2 also intersect the gate connection of transistor DT at node N2. The first electrode of the transistor DT is connected to the first electrode of the transistor T2 and is also connected to the second electrode of the transistor T1 and intersects at the node N3. The second electrode of transistor DT intersects the first electrode of transistor T3 at node N4. The first electrode of the transistor DT is the source of the transistor.

The second electrode of the transistor T3 is connected to the display driver chip. The display driver chip may input the initialization control signal vinit1 from the second electrode of the transistor T3 to the pixel circuit. The display driver chip may be, for example, the display driver chip 221 in FIG. 2 . The initialization control signal vinit1 can be an input voltage. The gate of the transistor T3 is connected to the third gate driving circuit. The third gate driving circuit may generate the gate control signal scan2. The gate control signal scan2 controls the on and off of the transistor T3. The third gate driving circuit may be, for example, the gate driving circuit 212 or the gate driving circuit 213 in FIG. 2 , or may be another driving gate circuit not shown in FIG. 2 .

The second electrode of transistor DT and the first electrode of transistor T3 also intersect the anode connection of the OLED at node N4. The cathode of the OLED is connected to the ground terminal voltage Vss. For example, the Vss may be the high-power ground terminal voltage PVss.

In the embodiment of the present application, by controlling the on or off of the transistor, the initialization of the pixel circuit, voltage compensation, data writing and OLED light emission can be realized. The initialization stage of the pixel circuit can restore the pixel circuit to its initial state and reduce the impact of the pixels of the previous frame of image on the pixel display of the next frame of image. The voltage compensation stage compensates for voltage drops caused by transistor leakage and manufacturing process issues in the circuit. The data writing stage is to save the pixel data in the form of voltage into the capacitor of the pixel circuit. The light-emitting stage is the process of driving the OLED to emit light through driving current. The following is a staged description in conjunction with the above-mentioned Figure 4.

In the embodiment of the present application, the control logic of the initialization stage and voltage compensation stage of the pixel circuit is the same. The transistor T1 can be controlled to be turned on by the gate control signal scan3, the transistor T3 can be controlled to be turned on by the gate control signal scan2, the transistor T4 can be controlled to be turned on by the gate control signal scan1, and the transistors T2 and T5 can be controlled to be turned off. Therefore, the voltage at node N4 is initialized to vinit1, that is, the anode of the OLED is reset. So that the voltage at node N2 can be initialized to vinit2. At this time, there is a residual voltage at the node N3 when the pixel of the previous frame was displayed. The residual voltage can be greater than the voltage vinit1, and a current can be generated in the transistor DT. As the current flows, the voltage at node N3 slowly decreases, that is, the voltage at the source of transistor DT slowly decreases. The voltage at the gate of transistor DT, that is, the voltage at node N2, has been initialized to vinit2. When the voltage difference between the voltage at the gate of the transistor DT and the voltage at the source of the transistor DT is V _gs =V _th , the current on the transistor DT is cut off. _Vth is the threshold voltage of the transistor DT. At this time, the voltage at node N3 is vinit2-V _th . Since the transistor T1 is turned on, the voltage at the node N1 is equal to the voltage at the node N3. Then the voltage at node N1 is vinit2-V _th .

In some implementations of the embodiments of the present application, the initialization phase and the voltage compensation phase of the above-mentioned pixel circuit can be performed simultaneously. Alternatively, in some implementations of the embodiments of the present application, the initialization phase of the pixel circuit may be controlled first, and then the voltage compensation phase of the pixel circuit may be controlled and implemented.

After the above initialization is completed, data can be written. The transistor T1 can be controlled to be turned on by the gate control signal scan3, the transistor T5 can be controlled to be turned on by the gate control signal G1, and the transistors T2, T3, T4 and DT can be turned off. Since the transistor T5 is turned on, the voltage V _data of the pixel data starts to be input and charges the capacitor C2. When the charging is completed, the writing of V _data is completed. Capacitor C1 can assist the writing of Vdata, so that the voltage at node N1 is equal to _Vdata after the data is written. Due to the capacitive coupling effect of capacitor C1 and capacitor C2, the voltage difference between node N1 after data is written and before data is written is added to node N2. The voltage of node N1 after data is written is Vdata, and the voltage before data is written is vinit2-V _th . above After initialization, the voltage at node N2 is vinit2. After the data is written, the voltage at the node N2 becomes Vini2+{V _data -(Vini2-V _th )}=V _data +V _th .

After the above data writing is completed, the OLED can be driven to emit light. The transistor T2 can be controlled to be turned on and the transistors T1, T3, T4 and T5 to be turned off through the gate control signal Emit. Since T2 is turned on, the driving current generated based on VDD flows to the transistor DT, and then the driving current is left to the OLED, driving the OLED to emit light. Capacitor C2 can control the gate voltage of DT so that DT can conduct normally. The size of the driving current can be expressed by the following formula:

Among them, μ represents the carrier mobility of the transistor DT, W is the width of the channel in the transistor DT, L is the length of the channel in the transistor DT, C _ox is the gate oxide capacitance per unit area of the transistor DT, and V _gs is the transistor The voltage of DT's gate relative to its source. The source voltage of transistor DT is the voltage at node N3. Since transistor T2 is turned on, the voltage at node N3 is equal to VDD. The voltage at the gate of the transistor DT is the voltage at the node N2. In the above data writing stage, it can be seen that the voltage at the node N2 = V _data + V _th . Then V _gs =(V _data +V _th )-VDD, from which V _gs -V _th =V _data -VDD can be obtained.

It can be seen from the above formula that the driving current I _ds has nothing to do with the voltage V _th of the transistor DT, thus realizing compensation for the threshold voltage of the transistor DT.

In some implementations of the embodiments of this application, after the OLED is driven to emit light, the OLED can also be adjusted through pulse width modulation (PWM) of the gate control signal of the transistor T2 and the gate control signal of the transistor T3. Luminous brightness.

For example, see Figure 5 . Figure 5 shows the timing diagram of the control signals of each transistor in the above-mentioned initialization stage, voltage compensation stage, data writing stage, light-emitting stage and dimming stage.

For example, it is assumed that the transistors T1, T3, T4 and T5 are all turned on when the gate control signal is at a high level, and turned off when the gate control signal is at a low level. The transistor T2 is turned off when the gate control signal is at a high level and turned on when it is at a low level. In Figure 5 you can see:

In the initialization phase, the control gate control signals scan3, scan2 and scan1 are all at a high level, causing the transistors T1, T3 and T4 to all turn on. The control gate control signal Emit is both at a high level, causing the transistor T2 to turn off. Moreover, the control gate control signals G1 are all at a low level, so that the transistors T1, T3 and T4 are all turned on.

In the voltage compensation stage, the control gate control signals scan3, scan2 and scan1 are all at a high level, causing the transistors T1, T3 and T4 to all turn on. The control gate control signal Emit is both at a high level, causing the transistor T2 to turn off. Moreover, the control gate control signals G1 are all at a low level, so that the transistors T1, T3 and T4 are all turned on.

During the data writing phase, the control gate control signals scan3 and G1 are both at a high level, causing the transistors T1 and T5 to both turn on. The control gate control signals scan2 and scan1 are both at a low level, causing both transistors T3 and T4 to be turned on. Moreover, the control gate control signal Emit is both at a high level, causing the transistor T2 to turn off.

During the light-emitting phase, the control gate control signal Emit is at a low level, causing the transistor T2 to be turned on. The control gate control signals scan3, scan2, scan1 and G1 are all at a low level, causing the transistors T1, T3, T4 and T5 to all turn off.

During the dimming stage, the control gate control signals scan3, scan1 and G1 are all at low level, causing the transistors T1, T4 and T5 to all turn off. Then, first control Emit to be at a high level, so that transistor T2 is turned off; and, control scan2 at a high level, causing transistor T3 to turn on. Then, Emit is controlled to be at a low level, so that the transistor T2 is turned on; and scan2 is controlled to be at a low level, so that the transistor T3 is turned off. Then, Emit is controlled to be at a high level, so that the transistor T2 is turned off; and scan2 is controlled to be at a high level, so that the transistor T3 is turned on. The OLED brightness is adjusted by continuously controlling the on and off of transistors T2 and T3.

It should be noted that the timing diagram shown in FIG. 5 is only an example and does not constitute a limitation on the embodiments of the present application. The embodiment of the present application does not limit whether the transistor is turned on at a high level or at a low level, and the above description is only an example.

In the pixel circuit shown in Figure 4 above, the transistors T1, T4 and T5 in the leakage paths of capacitor C1 and capacitor C2 all use IGZO TFTs. Although the on-current of IGZO TFT is not as large as that of LTPS TFT, the on-current of IGZO TFT is moderate and can meet the normal working requirements of the circuit. Although the on-current of LTPS TFT is large, its leakage current is also large. The transistors in the pixel circuit use LTPS TFTs with large leakage current. There is no problem when working in a high-frequency state. However, when working in a low-frequency state, due to the large leakage current of the LTPS TFT, the voltage of the circuit will slowly decrease. As a result, the OLED emits different brightness at different times, causing the problem of flickering. The leakage current of IGZO TFT is small. Under low-frequency operation, it can improve the problem of voltage drop in the circuit, thereby improving the problem of OLED display flicker. Therefore, in the pixel circuit shown in Figure 4 above, the transistors T1, T4 and T5 in the leakage path of the capacitor C1 and the capacitor C2 use IGZO TFT to achieve a low leakage current under low-frequency operation, so that the capacitor C1 The stored charge on capacitor C2 can be maintained efficiently, that is, the voltage in the circuit can be maintained, thereby improving the flicker problem of OLED under low-frequency operation. The transistor T3 connected to the OLED also uses IGZO TFT, thereby reducing the leakage of the transistor T3. Through such a design, the leakage current of the entire pixel circuit can be reduced as a whole, thereby improving the flicker problem of the OLED when the pixel circuit operates in a low-frequency state. Moreover, the pixel circuit shown in Figure 4 can also work in a high-frequency state and still maintain good working performance. That is to say, the pixel circuit shown in Figure 4 provided by the embodiment of the present application can work in both high-frequency and low-frequency states, and improves the flickering problem of OLED when working in low-frequency state, making the OLED display effect better. better.

In the pixel circuit, if the voltage compensation time is insufficient, the compensated voltage will not match the target voltage, causing the compensation effect to be poor and directly affecting the OLED display effect. In the existing solution, voltage compensation and data writing time are strongly coupled, and the voltage compensation time cannot be flexibly adjusted. In the pixel circuit shown in Figure 4 above, the voltage compensation stage and the data writing stage are controlled separately. Therefore, the time of voltage compensation can be flexibly adjusted, for example, by adjusting the rising edge or falling edge of the gate control signal scan2 of the transistor T3, the gate control signal scan1 of the transistor T4, and the gate control signal G1 of the transistor T5 during the compensation phase. time to adjust the voltage compensation time. The time of the rising edge or falling edge can be controlled by a clock signal provided by the display driver chip. That is, the pixel circuit shown in Figure 4 can improve the display effect of OLED by controlling the time of voltage compensation. For different display screens, the voltage compensation time can be adjusted accordingly to achieve a better display effect. The compensation time can be flexibly adjusted according to the process differences of the display screen, which increases the flexibility of pixel circuit application.

The pixel circuit provided by the embodiment of the present application can also be exemplified by reference to FIG. 6 . Compared with the pixel circuit shown in FIG. 4 , the pixel circuit shown in FIG. 6 has an additional transistor T6 . The transistor T6 may be an IGZO TFT. Alternatively, the transistor T6 may be an LTPS TFT.

The second electrode of the transistor T1, the first electrode of the transistor T2 and the first electrode of the transistor DT are all connected to the first electrode of the transistor T6.

The second electrode of the transistor T6 is connected to the display driver chip. The display driver chip may input the initialization control signal vinit3 from the second electrode of the transistor T6 to the pixel circuit. The display driver chip may be, for example, the display driver chip 221 in FIG. 2 . The initialization control signal vinit3 can be an input voltage. The gate of the transistor T6 is connected to the sixth gate drive circuit. The sixth gate driving circuit may generate the gate control signal G2. control signal via the gate G2 controls the on and off of transistor T6. The sixth gate driving circuit may be, for example, the gate driving circuit 212 or the gate driving circuit 213 in FIG. 2 , or may be another driving gate circuit not shown in FIG. 2 .

In some implementations of the embodiments of the present application, the sixth gate driving circuit may be an existing gate driving circuit in the display device, without adding an additional set of gate driving circuits to control the transistor T6. For example, based on the relevant description in FIG. 3 , it can be known that the gate driving circuits in the display device may be arranged in rows. Assume that the gate control signal G1 of the transistor T5 in Figure 6 is provided by the n-th row gate driving circuit of a certain group of gate driving circuits, and the gate control signal G2 of the transistor T6 can be provided by the certain group of gate driving circuits. The gate drive circuit for the n-xth row of the drive circuit is provided. The values of n and x may be integers greater than 1, and n is greater than x. Since the gate drive circuit is disposed in the outer edge area of the display area of the display device, reusing the above-mentioned sixth gate drive circuit eliminates the need to add a new gate drive circuit, thereby reducing the area of the outer edge area of the display area. Displays the width of the screen.

In this embodiment of the present application, the newly added transistor T6 in the pixel circuit shown in Figure 6 is used to initialize the voltage at the node N3. In the initialization phase, the gate control signal scan3 can be used to control the transistor T1 to be turned on, the gate control signal scan2 can be used to control the transistor T3 to be turned on, the gate control signal scan1 can be used to control the transistor T4 to be turned on, and the gate control signal G2 can be used to control the transistor T6 is turned on, and transistors T2 and T5 are turned off. As a result, the voltage at node N4 is initialized to vinit1, that is, the anode of the OLED is reset. Moreover, the voltage at node N2 can be initialized to vinit2, and the voltage at node N3 can be initialized to vinit3. Since the transistor T1 is turned on, the voltage at the node N1 is equal to the voltage at the node N3. After the initialization is completed, the transistor T6 is turned off, causing the voltage compensation phase to be entered. The sixth transistor is in an off state during both the data writing phase and the light emitting phase after the voltage compensation phase of the pixel circuit.

In the voltage compensation stage, at this time, the voltage vinit3 of the node N3 can be set to be greater than the voltage vinit1, and a current can be generated in the transistor DT. As the current flows, the voltage at node N3 slowly decreases, that is, the voltage at the source of transistor DT slowly decreases. The voltage at the gate of transistor DT, that is, the voltage at node N2, has been initialized to vinit2. When the voltage difference between the voltage at the gate of the transistor DT and the voltage at the source of the transistor DT is V _gs =V _th , the current on the transistor DT is cut off. _Vth is the threshold voltage of the transistor DT. At this time, the voltage at node N3 is vinit2-V _th . Since the transistor T1 is turned on, the voltage at the node N1 is equal to the voltage at the node N3. Then the voltage at node N1 is vinit2-V _th .

After the pixel circuit shown in Figure 6 completes the above-mentioned initialization and voltage compensation, it enters the data writing and lighting stages. For the control logic and implementation of the two stages, please refer to the corresponding description of the pixel circuit shown in Figure 4 above, which will not be discussed here. Repeat.

For example, referring to FIG. 7 , a timing diagram of the control signals of each transistor in the initialization phase, voltage compensation phase, data writing phase, light emitting phase, and dimming phase in the pixel circuit shown in FIG. 6 is shown. Compared with the above-mentioned FIG. 5 , the timing diagram shown in FIG. 7 adds the timing of the gate control signal G2 of the transistor T6 . The gate control signal G2 is at a high level only during the initialization stage, causing the transistor T6 to be turned on to complete the initialization at the node N3. After the initialization is completed, the gate control signal G2 is always at a low level, causing the transistor T6 to turn off. The description of the gate control signals G1, Emit, scan1, scan3 and scan2 in Figure 7 can be found in the relevant description of Figure 5 above, and will not be described again here. It should be noted that the timing diagram shown in FIG. 7 is only an example and does not constitute a limitation on the embodiments of the present application.

The pixel circuit shown in Figure 6 above has a new transistor T6 compared to the pixel circuit shown in Figure 4 above. It can be used to initialize the voltage at node N3 during the initialization phase, reducing the residual charge of the previous frame signal at node N3. The effect of the voltage compensation stage is optimized, which further improves the problem of OLED display flicker and optimizes the OLED display effect.

In the pixel circuit shown in Figure 6 above, the transistors T1, T4 and T5 in the leakage path of the capacitor C1 and the capacitor C2 All use IGZO TFT. Although the on-current of IGZO TFT is not as large as that of LTPS TFT, the on-current of IGZO TFT is moderate and can meet the normal working requirements of the circuit. Although the on-current of LTPS TFT is large, its leakage current is also large. The transistors in the pixel circuit use LTPS TFTs with large leakage current. There is no problem when working in a high-frequency state. However, when working in a low-frequency state, due to the large leakage current of the LTPS TFT, the voltage of the circuit will slowly decrease. As a result, the OLED emits different brightness at different times, causing the problem of flickering. The leakage current of IGZO TFT is small. Under low-frequency operation, it can improve the problem of voltage drop in the circuit, thereby improving the problem of OLED display flicker. Therefore, in the pixel circuit shown in Figure 6 above, the transistors T1, T4 and T5 in the leakage path of the capacitor C1 and the capacitor C2 use IGZO TFT to achieve low leakage current under low-frequency operation, so that the capacitor C1 The stored charge on capacitor C2 can be maintained efficiently, that is, the voltage in the circuit can be maintained, thereby improving the flicker problem of OLED under low-frequency operation. The transistor T3 connected to the OLED also uses IGZO TFT, thereby reducing the leakage of the transistor T3. Through such a design, the leakage current of the entire pixel circuit can be reduced as a whole, thereby improving the flicker problem of the OLED when the pixel circuit operates in a low-frequency state. Moreover, the pixel circuit shown in Figure 6 can also work in a high-frequency state and still maintain good working performance. That is to say, the pixel circuit shown in Figure 6 provided by the embodiment of the present application can work in both a high-frequency state and a low-frequency state, and improves the flicker problem of OLED when operating in a low-frequency state, making the OLED display effect better. better.

In the pixel circuit, if the voltage compensation time is insufficient, the compensated voltage will not match the target voltage, causing the compensation effect to be poor and directly affecting the OLED display effect. In the existing solution, voltage compensation and data writing time are strongly coupled, and the voltage compensation time cannot be flexibly adjusted. In the pixel circuit shown in Figure 6 above, the voltage compensation stage and the data writing stage are controlled separately. Therefore, the time of voltage compensation can be flexibly adjusted, for example, by adjusting the rising or falling edges of the gate control signal scan2 of the transistor T3, the gate control signal scan1 of the transistor T4, and the gate control signal G1 of the transistor T5 during the compensation phase. time to adjust the voltage compensation time. The time of the rising edge or falling edge can be controlled by a clock signal provided by the display driver chip. That is, the pixel circuit shown in Figure 6 can improve the display effect of OLED by controlling the time of voltage compensation. For different display screens, the voltage compensation time can be adjusted accordingly to achieve a better display effect. The compensation time can be flexibly adjusted according to the process differences of the display screen, which increases the flexibility of pixel circuit application.

The pixel circuit provided by the embodiment of the present application can also be exemplified by reference to FIG. 8 . Compared with the pixel circuit shown in FIG. 6 , the pixel circuit shown in FIG. 8 adds a capacitor C3.

The first electrode of the transistor T1, the first electrode of the transistor T5, the first terminal of the capacitor C1 and the first terminal of the capacitor C2 are all connected to the first terminal of the capacitor C3. The second electrode of the transistor T1, the first electrode of the transistor T2, the first electrode of the transistor T6, and the first electrode of the transistor DT are all connected to the second end of the capacitor C3. In Figure 8, “①” is used to indicate the first end of the capacitor C3, and “②” is used to indicate the second end of the capacitor C3.

In the specific implementation, the control logic and specific implementation of the initialization stage, voltage compensation stage, data writing stage, light emitting stage and dimming stage in the pixel circuit shown in Figure 8 can be found in the corresponding description of the pixel circuit shown in Figure 6 above. No further details will be given here.

In some implementations of the embodiment of the present application, in the pixel circuit shown in FIG. 8 above, the gate control signal scan3 of the transistor T1 and the gate control signal scan1 of the transistor T4 may be from the same gate drive circuit. road control signal. For convenience of description, the same control signal is denoted as scan’. Similarly, since the gate drive circuit is arranged in the outer edge area of the display area of the display device, reusing the gate drive circuit can reduce the number of drive circuits, thereby reducing the area of the outer edge area of the display area, thereby reducing the width of the display screen.

In some implementations of the embodiments of this application, the above-mentioned transistor T1 and transistor T4 are both turned on at a high level and turned off at a low level. Alternatively, the transistor T1 and the transistor T4 are both turned on at a low level and turned off at a high level. Since the body tube T1 The gate control signal scan3 and the gate control signal scan1 of the transistor T4 are the same control signal, and the transistor T1 and the transistor T4 are turned on or off at the same time. During the data writing stage of the pixel circuit shown in FIG. 8 , only the transistor T5 can be turned on, and the other transistors can be turned off, that is, the transistor T1 is turned off together with the transistor T4.

In addition, in some implementations of the embodiments of this application, the above-mentioned transistor T1 is turned on at a high level and turned off at a low level; and the transistor T4 is turned on at a low level and turned off at a high level. Alternatively, the transistor T1 is turned on at a low level and turned off at a high level; while the transistor T4 is turned on at a high level and turned off at a low level. Since the gate control signal scan3 of the transistor T1 and the gate control signal scan1 of the transistor T4 are the same control signal, one of the transistor T1 and the transistor T4 is in an on state and the other is in an off state at the same time. During the data writing stage of the pixel circuit shown in FIG. 8 , the transistor T1 can be controlled to be in the on state, while the transistor T4 can be controlled to be in the off state. Then the control transistor T5 is turned on, and the remaining transistors are turned off, thereby completing the writing of data.

When the gate control signal scan3 of the transistor T1 and the gate control signal scan1 of the transistor T4 are implemented as the same control signal, the initialization stage, voltage compensation stage, data writing stage, and light emitting stage of the pixel circuit shown in Figure 8 The timing diagram of the control signals of each transistor in the dimming stage can be seen in Figure 9. The description of each stage shown in Figure 9 can be exemplarily referred to the above-mentioned Figure 7 and will not be described again here. It should be noted that the timing diagram shown in FIG. 9 is only an example and does not constitute a limitation on the embodiments of the present application.

Regarding the above-mentioned pixel circuit shown in FIG. 8 , compared with the pixel circuit shown in FIG. 6 , the newly added capacitor C3 can utilize the voltage difference of the capacitor C3 to maintain the voltage at the node N3 during the light emitting stage. In the light-emitting phase, when the transistor T2 is turned on, the change in the gate voltage of the transistor DT relative to the source voltage decreases, that is, Vgs decreases. The capacitor C3 can stabilize the voltage, keep Vgs stable and reduce the fluctuation of Vgs, which is equivalent to the effect of voltage compensation, making the voltage compensation effect of the entire pixel circuit more significant. That is, compared with the pixel circuit shown in FIG. 6 mentioned above, the voltage compensation effect of the pixel circuit shown in FIG. 8 is better. For ease of understanding, reference may be made to FIG. 10 as an example.

FIG. 10 exemplarily shows a schematic diagram of the simulation results of the voltage compensation effect of the pixel circuit shown in FIG. 6 and FIG. 8 . In FIG. 10 , (a) shows a schematic diagram of the simulation results of the pixel circuit shown in FIG. 6 , and (b) shows a schematic diagram of the simulation results of the pixel circuit shown in FIG. 8 . The vertical axis represents the voltage compensation effect, and the horizontal axis represents the data voltage V _data . “Typ” in the icon in Figure 10 represents the typical threshold voltage V _th of the driving TFT, that is, the above-mentioned transistor DT. It can be seen that the compensation effect of the typical voltage is 100%. Take the "Typ-0.5" in the icon in Figure 10 as an example. The "Typ-0.5" in the icon in Figure 10 indicates that the V _th voltage driving the TFT is 0.5V smaller than the typical value. In a specifically manufactured driving TFT, the characteristics of the driving TFT will fluctuate due to the influence of the manufacturing process, which will cause the V _th voltage to change, that is, deviate from the typical threshold voltage. After the V _th voltage changes, if the voltage compensation is still performed according to the typical threshold voltage, the compensation effect will deviate from the ideal 100% compensation effect to a certain extent. If the compensation effect deviates from 100%, the display effect will be affected. The pixel circuit shown in Figure 8 above uses capacitor C3 to reduce V _gs and is affected by the coupling of parasitic capacitance, which can alleviate the impact of V _th voltage changes caused by the manufacturing process to a certain extent. Therefore, from the perspective of compensation effect, the deviation amplitude of the compensation effect of the pixel circuit shown in Figure 8 is smaller than that of the pixel circuit shown in Figure 6, indicating that the compensation effect has been further improved.

In the pixel circuit shown in Figure 8 above, the transistors T1, T4 and T5 in the leakage path of the capacitor C1 and the capacitor C2 all use IGZO TFTs. Although the on-current of IGZO TFT is not as large as that of LTPS TFT, the on-current of IGZO TFT is moderate and can meet the normal working requirements of the circuit. Although the on-current of LTPS TFT is large, its leakage current is also large. The transistors in the pixel circuit use LTPS TFTs with large leakage current. There is no problem when working in a high-frequency state. However, when working in a low-frequency state, due to the large leakage current of the LTPS TFT, the voltage of the circuit will slowly decrease. As a result, the OLED emits different brightness at different times, causing the problem of flickering. The leakage current of IGZO TFT is small. Under low-frequency operation, it can improve the problem of voltage drop in the circuit, thereby improving the problem of OLED display flicker. Therefore, in the above-mentioned pixel circuit shown in Figure 8, the transistors T1, T4 and T5 in the leakage path of the capacitor C1 and the capacitor C2 Using IGZO TFT, low leakage current can be maintained under low-frequency operation, so that the stored charge on capacitor C1 and capacitor C2 can be efficiently maintained, that is, the voltage in the circuit can be maintained, thereby improving the flicker problem of OLED under low-frequency operation. . The transistor T3 connected to the OLED also uses IGZO TFT, thereby reducing the leakage of the transistor T3. Through such a design, the leakage current of the entire pixel circuit can be reduced as a whole, thereby improving the flicker problem of the OLED when the pixel circuit operates in a low-frequency state. Moreover, the pixel circuit shown in Figure 8 can also operate in a high-frequency state and still maintain good operating performance. That is to say, the pixel circuit shown in Figure 8 provided by the embodiment of the present application can work in both a high-frequency state and a low-frequency state, and improves the flickering problem of OLED when operating in a low-frequency state, making the OLED display effect better. better.

In the pixel circuit, if the voltage compensation time is insufficient, the compensated voltage will not match the target voltage, causing the compensation effect to be poor and directly affecting the OLED display effect. In the existing solution, voltage compensation and data writing time are strongly coupled, and the voltage compensation time cannot be flexibly adjusted. In the pixel circuit shown in Figure 8 above, the voltage compensation stage and the data writing stage are controlled separately. Therefore, the time of voltage compensation can be flexibly adjusted, for example, by adjusting the rising edge or falling edge of the gate control signal scan2 of the transistor T3, the gate control signal scan1 of the transistor T4, and the gate control signal G1 of the transistor T5 during the compensation phase. time to adjust the voltage compensation time. The time of the rising edge or falling edge can be controlled by a clock signal provided by the display driver chip. That is, the pixel circuit shown in Figure 8 can improve the display effect of OLED by controlling the time of voltage compensation. For different display screens, the voltage compensation time can be adjusted accordingly to achieve a better display effect. The compensation time can be flexibly adjusted according to the process differences of the display screen, which increases the flexibility of pixel circuit application.

The pixel circuit provided by the embodiment of the present application can also be exemplified by reference to FIG. 11 . Compared with the pixel circuit shown in FIG. 6 , the pixel circuit shown in FIG. 11 is configured such that the gate electrode of the transistor T1 and the gate electrode of the transistor T4 are connected to the same signal output terminal of the same group of gate control circuits. That is, the gate control signal of the transistor T1 and the gate control signal of the transistor T4 are the same gate control signal, and the same gate control signal can be represented by scan4.

Compared with the pixel circuit shown in FIG. 6 , in FIG. 11 , it is also provided that the turn-on and turn-off of the transistor T6 can be controlled by the gate scanning signal scan5 . The gate scanning signal scan5 may be provided by an existing gate drive circuit, that is, the gate scanning signal scan5 may be the same gate as the gate control signal of another transistor (not shown in Figure 11). control signal.

The above arrangement is because the gate drive circuit is arranged in the outer edge area of the display area of the display device. Reusing the gate drive circuit can reduce the number of drive circuits, thereby reducing the area of the outer edge area of the display area, thereby reducing the width of the display screen. .

The control logic and specific implementation of the initialization stage, voltage compensation stage, data writing stage, light emitting stage and dimming stage in the pixel circuit shown in Figure 11 above can be found in the corresponding description of the pixel circuit shown in Figure 6 above, and will not be described again here. .

The timing diagram of the control signals of each transistor in the initialization stage, voltage compensation stage, data writing stage, light emitting stage and dimming stage in the pixel circuit shown in Figure 11 can be seen in Figure 12. It should be noted that the timing diagram shown in FIG. 12 is only an example and does not constitute a limitation on the embodiments of the present application.

In the embodiment of the present application, in the above-mentioned pixel circuits shown in FIGS. 6 and 8 , the gate control signal G1 of the transistor T5 and the gate control signal G2 of the transistor T6 may be driven by the same group of gate driving circuits (referred to as the first gate driving circuit for short). set gate drive circuit) to provide. The gate control signal scan3 of the transistor T1 and the gate control signal scan1 of the transistor T4 may be provided by the same group of gate driving circuits (referred to as the second group of gate driving circuits for short). For example, the gate control signal scan3 and the gate control signal scan1 may be the same control signal of the second group of gate driving circuits. The gate control signal scan2 of the transistor T3 may be provided by a third group of gate driving circuits. The gate control signal Emit of the transistor T2 can be determined by the Four sets of gate drive circuits are provided. The first group of gate driving circuits, the second group of gate driving circuits, the third group of gate driving circuits and the fourth group of gate driving circuits may be different from each other.

In some implementations of the embodiments of the present application, in the above-mentioned pixel circuits shown in FIGS. 6 and 8 , the gate control signal G1 of the transistor T5 and the gate control signal G2 of the transistor T6 can be generated by the above-mentioned first group of gates. driver circuit is provided. Exemplarily, the gate control signal G1 and the gate control signal G2 are provided by gate drive circuits in different rows of the first group of gate drive circuits. For example, the gate control signal G1 of the transistor T5 is provided by the n-th row gate driving circuit of the first group of gate driving circuits, and the gate control signal G2 of the transistor T6 may be provided by the certain group of gate driving circuits. The gate drive circuit of the n-xth row is provided by the gate drive circuit. The gate control signal scan3 of the transistor T1 may be provided by the above-mentioned second group of gate driving circuits. The gate control signal scan2 of the transistor T3 may be provided by the above-mentioned third group of gate driving circuits. The gate control signal Emit of the transistor T2 may be provided by the above-mentioned fourth group of gate driving circuits. The gate control signal scan1 of the transistor T4 may be provided by the fifth group of gate driving circuits. The first group of gate driving circuits, the second group of gate driving circuits, the third group of gate driving circuits, the fourth group of gate driving circuits and the fifth group of gate driving circuits may be different from each other.

In some implementations of the embodiments of the present application, in the above-mentioned pixel circuits shown in FIG. 6 and FIG. 8 , the gate control signal G1 of the transistor T5 may be provided by the above-mentioned first group of gate driving circuits. The gate control signal scan3 of the transistor T1 and the gate control signal scan1 of the transistor T4 may be provided by the above-mentioned second group of gate driving circuits. For example, the gate control signal scan3 and the gate control signal scan1 may be the same control signal of the second group of gate driving circuits. The gate control signal scan2 of the transistor T3 may be provided by the above-mentioned third group of gate driving circuits. The gate control signal Emit of the transistor T2 may be provided by the above-mentioned fourth group of gate driving circuits. The gate control signal G2 of the transistor T6 may be provided by the fifth group of gate driving circuits mentioned above.

In some implementations of the embodiment of the present application, in the pixel circuit shown in FIG. 4 above, the gate control signal scan3 of the transistor T1 and the gate control signal scan1 of the transistor T4 can be provided by the second group of gate drive circuits. . For example, the gate control signal scan3 and the gate control signal scan1 may be the same control signal of the second group of gate driving circuits.

In the above embodiment, the gate control signals of the two transistors are provided by a set of gate drive circuits, which can reduce the number of gate drive circuits, thereby reducing the area of the outer edge area of the display area and reducing the width of the display screen. Optionally, in specific implementation, each transistor may be controlled by an independent gate drive circuit, which is not limited in the embodiments of the present application.

In this application, the terms "first", "second" and other words are used to distinguish the same or similar items with basically the same functions and functions. It should be understood that the terms "first", "second" and "nth" There is no logical or sequential dependency, and there is no limit on the number or execution order. It should also be understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another.

It should also be understood that in each embodiment of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not be determined by the execution order of the embodiments of the present application. The implementation process constitutes no limitation.

It will also be understood that the term "includes" (also "includes," "including," "comprises," and/or "comprising") when used in this specification specifies the presence of stated features, integers, steps, operations, elements , and/or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groupings thereof.

It should also be understood that references throughout the specification to “one embodiment,” “an embodiment,” and “some implementations of the embodiments of this application” mean specific features, structures, or characteristics related to the embodiments or implementations. Include in this application at least one in an embodiment. Therefore, “in one embodiment” or “in an embodiment” and “in some implementations of the embodiments of the present application” appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present application. scope.

Claims

A pixel circuit, characterized in that the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a driving transistor, a first capacitor, a second capacitor and a light-emitting diode; The first transistor, the third transistor, the fourth transistor and the fifth transistor are indium gallium zinc oxide thin film transistors, and the second transistor and the driving transistor are low temperature polysilicon thin film transistors;

The first electrode of the first transistor, the first electrode of the fifth transistor, the first end of the first capacitor and the first end of the second capacitor are electrically connected and intersect at the first node;

The second end of the second capacitor, the first electrode of the fourth transistor and the gate of the drive transistor are electrically connected to intersect at the second node;

The second electrode of the first transistor, the first electrode of the driving transistor and the first electrode of the second transistor are electrically connected and intersect at a third node;

The second electrode of the driving transistor, the first electrode of the third transistor and the anode of the light-emitting diode are electrically connected to intersect at a fourth node, and the cathode of the light-emitting diode is grounded;

The second end of the first capacitor is connected to the second electrode of the second transistor, and the second electrode of the second transistor is used to input the power supply voltage;

The gates of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are respectively used to input gate control signals;

The second electrode of the fifth transistor is used to input a data voltage, the second electrode of the third transistor is used to input a first initialization control signal, and the second electrode of the fourth transistor is used to input a second initialization control signal. .
The pixel circuit of claim 1, wherein the pixel circuit further includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the third node. The electrode is used to input the third initialization control signal.
The pixel circuit of claim 2, wherein the pixel circuit further includes a third capacitor, a first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to the first node. terminal is electrically connected to the third node.
The pixel circuit according to claim 2 or 3, characterized in that the gate control signal of the fifth transistor and the gate control signal of the sixth transistor are gate signals from different rows in the same group of gate driving circuits. control signal for the pole drive circuit.
The pixel circuit according to any one of claims 2 to 4, wherein the sixth transistor is an indium gallium zinc oxide thin film transistor; or the sixth transistor is a low temperature polysilicon thin film transistor.
The pixel circuit according to claim 1, characterized in that, during the initialization phase and the voltage compensation phase of the pixel circuit, the first transistor, the third transistor and the fourth transistor are turned on, and the third transistor is turned on. The second transistor and the fifth transistor are turned off; the voltage of the fourth node is initialized to the first initialization control signal, the voltage of the second node is initialized to the second initialization control signal, and the voltage of the third node is initialized to the first initialization control signal. The voltage of the first node is the difference between the second initialization control signal and the threshold voltage of the driving transistor.
The pixel circuit according to any one of claims 2 to 5, characterized in that, in the initialization stage of the pixel circuit, the sixth transistor, the first transistor, the third transistor and the fourth transistor are The transistor is turned on, the second transistor and the fifth transistor are turned off; the voltage of the fourth node is initialized to the first initialization control signal, and the voltage of the second node is initialized to the second initialization control signal. signal, the voltage of the third node is initialized to the third initialization control signal;

During the voltage compensation phase of the pixel circuit, the sixth transistor is turned off, and the states of the remaining transistors remain as described. In the state of the initialization phase, the voltages of the third node and the first node are both the difference between the second initialization control signal and the threshold voltage of the driving transistor.
The pixel circuit according to claim 1, wherein during the data writing phase of the pixel circuit, the first transistor and the fifth transistor are turned on, and the second transistor and the third transistor are and the fourth transistor is turned off; the voltage of the first node is the data voltage, and the voltage of the second node is the sum of the data voltage and the threshold voltage of the driving transistor.
The pixel circuit according to any one of claims 2 to 5, characterized in that, during the data writing stage of the pixel circuit, the first transistor and the fifth transistor are turned on, and the second transistor, The third transistor, the fourth transistor and the sixth transistor are turned off; the voltage of the first node is the data voltage, and the voltage of the second node is the data voltage and the driving transistor. The sum of the threshold voltages.
The pixel circuit according to any one of claims 2 to 5, characterized in that the gate control signals of the first transistor and the fourth transistor are the same signal.
The pixel circuit of claim 10, wherein during the data writing phase of the pixel circuit, the fifth transistor is turned on, and the first transistor, the second transistor, and the third transistor are , the fourth transistor and the sixth transistor are turned off; the voltage of the first node is the data voltage, and the voltage of the second node is the sum of the data voltage and the threshold voltage of the driving transistor. .
The pixel circuit of claim 1, wherein during the light-emitting phase of the pixel circuit, the second transistor is turned on, and the first transistor, the third transistor, the fourth transistor and the The fifth transistor is turned off; the driving current generated based on the power supply voltage input by the second electrode of the second transistor drives the light-emitting diode to emit light.
The pixel circuit according to any one of claims 2 to 5, characterized in that, during the light-emitting phase of the pixel circuit, the second transistor is turned on, the first transistor, the third transistor, the The fourth transistor, the fifth transistor and the sixth transistor are turned off; the driving current generated based on the power supply voltage input by the second electrode of the second transistor drives the light emitting diode to emit light.
The pixel circuit according to any one of claims 1 to 13, wherein during the dimming stage of the pixel circuit, the gate control signals of the second transistor and the third transistor are pulse width-controlled. Modulation to adjust the brightness of the light emitting diode.
A display screen, characterized in that the display screen includes a pixel circuit, a gate drive circuit, a display drive chip and a power chip; the gate drive circuit is used to provide a gate control signal for the pixel circuit, and the The display driver chip is used to provide initialization control signals and data voltages for the pixel circuit, and the power chip is used to provide power signals for the pixel circuit; the pixel circuit is the pixel according to any one of claims 1-14 circuit.