WO2023185460A1 - 应对帧同步信号切换导致亮度异常的led背光驱动方法 - Google Patents
应对帧同步信号切换导致亮度异常的led背光驱动方法 Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
- G09G3/3413—Details of control of colour illumination sources
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Definitions
- the present invention relates to the technical field of LED backlight display, and in particular, to an LED backlight driving method and system that cope with abnormal brightness caused by frame synchronization signal switching.
- a frame synchronization signal (Vsync signal) is usually provided.
- the frame synchronization signal matches the frames per second (FPS) of the graphics card to eliminate "tearing" in the screen display.
- the frame synchronization signal In a liquid crystal display device with LED as a backlight source, the frame synchronization signal must also be referenced for driving the LED backlight source, and the clock frequency of the corresponding PWM brightness control signal should be generated based on the clock frequency of the frame synchronization signal.
- the duty cycle of the PWM brightness control signal determines the brightness of the LED light string.
- the accuracy requirements of the PWM control signal in order to synchronize the clock frequency of the PWM brightness control signal with the clock frequency of the frame synchronization signal VSYNC, there are usually two methods for generating the PWM brightness control signal in the prior art. First, use a PLL phase-locked loop to process the frame synchronization signal to obtain the required clock frequency of the PWM brightness control signal.
- Another method is to use the high-frequency clock signal inside the LED driver chip, and use the frame synchronization signal to dynamically divide the high-frequency clock signal to obtain the corresponding clock frequency of the PWM brightness control signal.
- This method is similar to using a PLL Phase locked loop is called DPLL in this invention.
- the time required to generate a stable PWM brightness control signal will be significantly less than
- the first method can quickly achieve synchronization between the PWM brightness control signal and the frame synchronization signal, but when the display screen needs to switch the frame synchronization signal, for example, when the clock frequency of the frame synchronization signal changes from 100Hz to 300Hz, the PWM brightness The clock frequency of the control signal will also change accordingly. Because the LED backlight drive unit needs to output multiple channels of PWM brightness control signals, and there is a phase shift between the PWM brightness control signals of different channels.
- the technical purpose to be achieved by the present invention is to suppress abnormal brightness flickering of the display screen caused by switching of frame synchronization signals.
- the present invention provides an LED backlight driving method that copes with abnormal brightness caused by frame synchronization signal switching.
- the LED backlight driving method includes:
- the first frequency division multiple K1 is switched to the second frequency division multiple K2; the second frequency division multiple K2 is greater than the first frequency division multiple K1 ;
- the second frequency division multiple K2 is greater than the first frequency division multiple K1 specifically: (K2/K1) ⁇ 10.
- the step of down-converting the second PWM brightness control signal clock frequency P2 is to control the second frequency division multiple K2 to gradually decrease at a predetermined rate, so that the second PWM brightness control signal The signal clock frequency P2 gradually decreases.
- the predetermined time interval T is less than 500 ms.
- the present invention also provides another LED backlight driving method that copes with abnormal brightness caused by frame synchronization signal switching.
- the LED backlight driving method includes:
- the first PWM brightness control signal clock frequency P1 switches to the predetermined second PWM brightness control signal clock frequency P2;
- the second PWM brightness control signal clock frequency P2 is down-converted, and the second PWM brightness control signal clock frequency P2 is gradually reduced to the target frequency P within a predetermined time interval T.
- the second frequency division multiple K2 is greater than the first frequency division multiple K1 specifically: (K2/K1) ⁇ 10.
- the down-conversion process of the second PWM brightness control signal clock frequency P2 specifically includes controlling the second PWM brightness control signal clock frequency P2 to gradually decrease at a predetermined rate.
- the predetermined time interval T is less than 500 ms.
- the present invention also provides an LED backlight drive system that copes with brightness abnormalities caused by frame synchronization signal switching.
- the LED backlight drive system includes:
- a frame synchronization signal receiving module which is used to receive the frame synchronization signal input from the external LED backlight drive system
- a dynamic frequency division processing module which is used to generate the clock frequency of the PWM brightness control signal with a predetermined frequency division multiple according to the frame synchronization signal;
- a frame synchronization signal switching processing module which is used to process when the frame synchronization signal switches from the first clock frequency F1 to the second clock frequency F2, switching the first frequency division multiple K1 to the second frequency division multiple K2; the second The frequency division multiple K2 is greater than the first frequency division multiple K1; and the dynamic frequency division processing module is controlled to use the second frequency division multiple K2 to perform dynamic frequency division processing based on the first clock frequency F1 of the frame synchronization signal to obtain the second PWM brightness control signal.
- the frame synchronization signal switching processing module is also used to adjust the second PWM brightness control signal clock frequency P2 Perform frequency reduction processing to gradually reduce the second PWM brightness control signal clock frequency P2 to the target frequency P within a predetermined time interval T.
- the present invention also provides an LED backlight drive system that copes with brightness abnormalities caused by frame synchronization signal switching.
- the LED backlight drive system includes:
- a frame synchronization signal receiving module which is used to receive the frame synchronization signal input from the external LED backlight drive system
- a dynamic frequency division processing module which is used to generate the clock frequency of the PWM brightness control signal with a predetermined frequency division multiple according to the frame synchronization signal;
- the frame synchronization signal switching processing module is used to process when the frame synchronization signal switches from the first clock frequency F1 to the second clock frequency F2, when the frame synchronization signal switches from the first clock frequency F1 to the second clock frequency F2,
- the first PWM brightness control signal clock frequency P1 is switched to the predetermined second PWM brightness control signal clock frequency P2;
- the second PWM brightness control signal clock frequency P2 is higher than the target frequency P;
- the frame synchronization signal switching processing module is also used to down-convert the second PWM brightness control signal clock frequency P2, and gradually reduce the second PWM brightness control signal clock frequency P2 to the target frequency P within a predetermined time interval T.
- one or more embodiments of the present invention may have the following advantages:
- the clock frequency of the Vsync frame synchronization signal when the clock frequency of the Vsync frame synchronization signal is switched, the clock frequency of the PWM brightness control signal is actively pushed up, thereby greatly shortening the clock cycle of the PWM brightness control signal. Therefore, the brightness abnormality caused by the clock frequency switching of the PWM brightness control signal is eliminated.
- the change process also becomes extremely fast, achieving an effect that is not easily detectable by the human eye, thus achieving the suppression of brightness abnormalities.
- Figure 1 is a schematic diagram of using dynamic frequency division to generate the PWM brightness control signal clock frequency in the prior art
- Figure 2 is a schematic diagram of changes in the clock frequency of the PWM brightness control signal in an embodiment of the present invention
- FIG. 3 is a schematic diagram of changes in the clock frequency of the PWM brightness control signal in another embodiment of the present invention.
- the clock frequency of the first Vsync frame synchronization signal is 100Hz
- the clock frequency of the second Vsync frame synchronization signal is 300Hz. That is, when the clock frequency of the Vsync frame synchronization signal switches, the clock frequency of the Vsync frame synchronization signal is: 100Hz increased to 300Hz.
- the clock frequency of the PWM brightness control signal is obtained by dynamic frequency division according to the clock frequency of the frame synchronization signal.
- the first frequency division multiple K1 for dynamic frequency division is set to 1000, that is, the first PWM brightness control signal clock frequency corresponding to the first Vsync frame synchronization signal clock frequency is 100KHz.
- this embodiment is different from the prior art in which the first frequency division multiple remains unchanged. And directly set the clock frequency of the second PWM brightness control signal to 300KHz.
- the frequency division multiple is switched from the first frequency division multiple K1 to the second frequency division multiple K2, and the second frequency division multiple K2 is set to be at least 10 times greater than the first frequency division multiple.
- K1 in this embodiment, the second frequency division multiple is 10000.
- the clock frequency of the second PWM brightness control signal becomes 1MHz.
- the clock frequency of the second PWM brightness control signal is much higher. is less than 300KHz, so when the first PWM brightness control signal clock frequency switches to the second PWM brightness control signal clock frequency, although there is still a change in the duty cycle of the PWM brightness control signal, due to the greatly shortened clock cycle, this The abnormal change process of brightness also becomes extremely fast, achieving an effect that is not easily detectable by the human eye, thus achieving the suppression of brightness abnormalities.
- the second PWM brightness control signal clock frequency is increased to 1 MHz according to the second frequency division multiple, since the clock frequency of the PWM brightness control signal is inconsistent with the frequency of the external input second Vsync frame synchronization signal, therefore It is also necessary to further adjust the second PWM brightness control signal clock
- the frequency is down-converted, even if the second frequency division multiple gradually decreases to be consistent with the first frequency division multiple.
- the descending process needs to be completed within a predetermined time interval T, which is set to 500ms in this embodiment. Since each adjustment of the second frequency division multiple will bring about abnormal changes in display brightness, the descending gradient setting of the second frequency division multiple needs to be set finely enough to ensure that there are no obvious brightness changes in the screen brightness.
- the clock frequency of the second PWM brightness control signal needs to be reduced from 1 MHz to 300 KHz.
- the 300 KHz corresponds to the PWM brightness obtained by dynamically dividing the clock frequency of the second Vsync frame synchronization signal at the first frequency division multiple.
- Control signal clock frequency The corresponding frequency division multiple needs to drop from 10000 to 1000. Therefore, to complete the reduction process within 500ms, the second frequency division multiple needs to drop by 16 every millisecond, that is, the second frequency division multiple's decreasing speed is set to 16/ms.
- the clock frequency of the PWM brightness control signal is first greatly increased to greatly shorten the brightness abnormality duration, thereby achieving the technical effect of suppressing display brightness abnormality.
- the clock frequency of the first Vsync frame synchronization signal in this embodiment is 300Hz
- the clock frequency of the second Vsync frame synchronization signal is 100Hz. That is, when the clock frequency of the Vsync frame synchronization signal switches, the Vsync frame
- the synchronization signal clock frequency drops from 300Hz to 100Hz.
- the clock frequency of the PWM brightness control signal is obtained by dynamic frequency division according to the clock frequency of the frame synchronization signal.
- the first frequency division multiple K1 for dynamic frequency division is set to 1000, that is, the first PWM brightness control signal clock frequency corresponding to the first Vsync frame synchronization signal clock frequency is 300KHz.
- this embodiment is different from the previous embodiment 1 in which the first frequency division multiple K1 is increased. Up to the second frequency division multiple K2.
- the LED backlight driving system directly increases the clock frequency of the second PWM brightness control signal to 10 MHz.
- the clock frequency of the second PWM brightness control signal is increased to 1MHz, in order to make the PWM brightness control
- the clock frequency of the control signal is consistent with the clock frequency of the externally input second Vsync frame synchronization signal.
- the clock frequency of the second PWM brightness control signal needs to gradually decrease from 1MHz to 100KHz.
- the descending process needs to be completed within a predetermined time interval T, which is set to 500ms in this embodiment.
- the descending gradient setting of the clock frequency of the second PWM brightness control signal needs to be set finely enough to ensure that there are no obvious brightness changes in the screen brightness.
- the clock frequency of the second PWM brightness control signal needs to drop from 1MHz to 100KHz, so the clock frequency of the second PWM brightness control signal needs to drop by 1.8KHz every millisecond, that is, the clock frequency of the second PWM brightness control signal needs to drop by 1.8KHz/ms.
- the speed drops from 1MHz to 100KHz.
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Abstract
一种应对帧同步信号切换导致亮度异常的LED背光驱动方法，包括：当帧同步信号从第一时钟频率切换至第二时钟频率时，推高PWM亮度控制信号时钟频率，使PWM亮度控制信号时钟频率远高于目标切换频率；从而大大缩短PWM亮度控制信号的时钟周期，使PWM亮度控制信号时钟频率切换所导致的亮度异常变化缩短，从而实现对亮度异常的抑制；随后对PWM亮度控制信号时钟频率进行降频处理，逐步降至目标频率。
Description
本发明涉及LED背光显示技术领域，尤其涉及一种应对帧同步信号切换导致亮度异常的LED背光驱动方法及系统。
随着液晶显示技术的发展，以LED作为背光源的液晶显示技术已经广泛的应用于目前的液晶显示装置中。在以液晶显示技术中通常会设置有帧同步信号(Vsync信号)，该帧同步信号与显卡的每秒传输帧数(FPS)相匹配，从而实现消除画面显示的“撕裂”。
在LED作为背光源的液晶显示装置中，对于LED背光源的驱动同样要参考帧同步信号，并基于帧同步信号的时钟频率产生对应的PWM亮度控制信号的时钟频率。PWM亮度控制信号的占空比决定了LED灯串的亮度大小。考虑到对PWM控制信号的精度要求，为了使PWM亮度控制信号的时钟频率与帧同步信号VSYNC的时钟频率同步，现有技术中生成PWM亮度控制信号通常有两种方案来产生。其一，使用PLL锁相环对帧同步信号进行处理，已获得需要的PWM亮度控制信号的时钟频率。另一种方法是利用LED驱动芯片内部的高频时钟信号，利用帧同步信号对该高频时钟信号做动态分频处理已获得对应的PWM亮度控制信号的时钟频率，这种方法类似于使用PLL锁相环，本发明中称其为DPLL。如图1所示，在这种方法中可以设定分频倍数K，即PWM亮度控制信号时钟频率＝K*帧同步信号时钟频率
针对上述两种PWM亮度控制信号的时钟频率的生成方法，针对第一种，由于PLL锁相环负反馈的特性，其生成稳定的PWM亮度控制信号必然需要较长的时间。
针对第二种方法，其生成稳定的PWM亮度控制信号的所需时间会明显少于
第一种方法，能够较快的实现PWM亮度控制信号与帧同步信号之间的同步，但在显示画面需要切换帧同步信号时，例如帧同步信号的时钟频率从100Hz变为300Hz时，PWM亮度控制信号的时钟频率也会随之发生变化。由于LED背光驱动单元需要输出多路的通道的PWM亮度控制信号，且不同通道的PWM亮度控制信号之间存在相移。因此帧同步信号的切换时间点无论如何设置都将导致切换时间点处的PWM亮度控制信号的时钟频率出现前后不一致，从而导致PWM亮度控制信号的占空比在切换时间点处发生变化，从而造成在进行帧同步信号切换时，画面亮度出现亮度的异常变化。
由此可见现有技术中需要一种能够应对上述在帧同步信号切换时发生的显示亮度异常的LED驱动方法。
发明内容
本发明所要实现的技术目的在于能够抑制由帧同步信号的切换造成的显示画面亮度异常闪烁。
基于上述技术目的，本发明提供一种应对帧同步信号切换导致亮度异常的LED背光驱动方法，所述LED背光驱动方法包括：
基于帧同步信号的第一时钟频率F1使用第一分频倍数K1进行动态分频处理，以获得第一PWM亮度控制信号时钟频率P1；即：P1＝K1*F1；
当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，将第一分频倍数K1切换至第二分频倍数K2；所述第二分频倍数K2大于第一分频倍数K1；
基于帧同步信号的第一时钟频率F1使用第二分频倍数K2进行动态分频处理，以获得第二PWM亮度控制信号时钟频率P2；即：P2＝K2*F1；
随后对第二PWM亮度控制信号时钟频率P2进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P，所述目标频率P为：P＝K1*F2；且有P＜P2。
在一个实施例中，所述第二分频倍数K2大于第一分频倍数K1具体为：(K2/K1)≥10。
在一个实施例中，所述对第二PWM亮度控制信号时钟频率P2进行降频处理具体为以预定速率控制第二分频倍数K2逐渐下降，从而使第二PWM亮度控制
信号时钟频率P2逐渐下降。
在一个实施例中，所述预定时间间隔T小于500ms。
本发明同时还提供另一种应对帧同步信号切换导致亮度异常的LED背光驱动方法，所述LED背光驱动方法包括：
基于帧同步信号的第一时钟频率F1使用第一分频倍数K1进行动态分频处理，以获得第一PWM亮度控制信号时钟频率P1；即：P1＝K1*F1；
当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，所述第一PWM亮度控制信号时钟频率P1切换至预定的第二PWM亮度控制信号时钟频率P2；
所述第二PWM亮度控制信号时钟频率P2高于目标频率P；所述目标频率P为：P＝K1*F2；即K1*F2＜P2；
随后对第二PWM亮度控制信号时钟频率P2进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P。
在一个实施例中，所述第二分频倍数K2大于第一分频倍数K1具体为：(K2/K1)≥10。
在一个实施例中，所述对第二PWM亮度控制信号时钟频率P2进行降频处理具体为以预定速率控制第二PWM亮度控制信号时钟频率P2逐渐下降。
在一个实施例中，所述预定时间间隔T小于500ms。
本发明还提供一种应对帧同步信号切换导致亮度异常的LED背光驱动系统，所述LED背光驱动系统包括：
帧同步信号接收模块，其用于接收外部输入LED背光驱动系统的帧同步信号；
动态分频处理模块，其用于根据帧同步信号以预定的分频倍数生成PWM亮度控制信号的时钟频率；
帧同步信号切换处理模块，其用于处理当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，将第一分频倍数K1切换至第二分频倍数K2；所述第二分频倍数K2大于第一分频倍数K1；并控制动态分频处理模块基于帧同步信号的第一时钟频率F1使用第二分频倍数K2进行动态分频处理，以获得第二PWM亮度控制信号时钟频率P2；即：P2＝K2*F1；
所述帧同步信号切换处理模块还用于对第二PWM亮度控制信号时钟频率P2
进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P，所述目标频率P为：P＝K1*F2；且有P＜P2。
本发明还提供一种应对帧同步信号切换导致亮度异常的LED背光驱动系统，所述LED背光驱动系统包括：
帧同步信号接收模块，其用于接收外部输入LED背光驱动系统的帧同步信号；
动态分频处理模块，其用于根据帧同步信号以预定的分频倍数生成PWM亮度控制信号的时钟频率；
帧同步信号切换处理模块，其用于处理当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，将所述第一PWM亮度控制信号时钟频率P1切换至预定的第二PWM亮度控制信号时钟频率P2；所述第二PWM亮度控制信号时钟频率P2高于目标频率P；所述目标频率P为：P＝K1*F2；即K1*F2＜P2；
所述帧同步信号切换处理模块还用于对第二PWM亮度控制信号时钟频率P2进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
本发明中通过在Vsync帧同步信号时钟频率进行切换时，主动推高PWM亮度控制信号时钟频率，从而大大缩短PWM亮度控制信号的时钟周期，因此由PWM亮度控制信号时钟频率切换所导致的亮度异常变化过程也变得极快，达到人眼不易察觉的效果，从而实现对亮度异常的抑制。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是现有技术中使用动态分频生成PWM亮度控制信号时钟频率的示意图；
图2是本发明一实施例中PWM亮度控制信号时钟频率变化示意图；
图3是本发明另一实施例中PWM亮度控制信号时钟频率变化示意图。
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
实施例1
如图2所示，本实施例中第一Vsync帧同步信号时钟频率为100Hz，第二Vsync帧同步信号时钟频率为300Hz，即当Vsync帧同步信号时钟频率发生切换时Vsync帧同步信号时钟频率由100Hz升高至300Hz。PWM亮度控制信号的时钟频率根据帧同步信号的时钟频率进行动态分频获得，本实施例中在帧同步信号没有进行切换之前，即LED背光驱动系统所接收到的外部输入的Vsync帧同步信号处于第一Vsync帧同步信号时钟频率时，进行动态分频的第一分频倍数K1设置为1000，即第一Vsync帧同步信号时钟频率所对应的第一PWM亮度控制信号时钟频率为100KHz。
当帧同步信号发生变化时，即第一Vsync帧同步信号时钟频率跳变为第二Vsync帧同步信号时钟频率时，本实施例并不同于现有技术中的保持第一分频倍数不变，而直接将第二PWM亮度控制信号时钟频率为300KHz。本实施例中在帧同步信号发生切换之后，分频倍数从第一分频倍数K1切换为第二分频倍数K2，所述第二分频倍数K2设置为至少大于10倍第一分频倍数K1，本实施例中第二分频倍数取10000。这时由于第二分频倍数高于第一分频倍数，因此在帧同步信号切换后，第二PWM亮度控制信号时钟频率变为1MHz，这时的第二PWM亮度控制信号时钟频率是远高于300KHz的，因此在第一PWM亮度控制信号时钟频率切换至第二PWM亮度控制信号时钟频率时，虽然依然存在PWM亮度控制信号的占空比变化，但是由于时钟周期的大大缩短，因此这种亮度的异常变化过程也变得极快，达到人眼不易察觉的效果，从而实现对亮度异常的抑制。
本实施例中，在第二PWM亮度控制信号时钟频率根据第二分频倍数被提高到1MHz以后，由于PWM亮度控制信号的时钟频率与外部的输入的第二Vsync帧同步信号的频率不一致，因此还需要进一步的对第二PWM亮度控制信号时钟
频率进行降频处理，即使第二分频倍数逐渐下降至与第一分频倍数一致。该下降过程需要在预定时间间隔T内完成，本实施例中设定为500ms。由于第二分频倍数的每次调整都会带来显示亮度的异常变化，因此第二分频倍数的下降梯度设置的需要足够精细才能保证画面亮度不存在较为明显的亮度变化。本实施例中第二PWM亮度控制信号时钟频率需要从1MHz下降到300KHz，所述300KHz即对应于在于在第一分频倍数下对第二Vsync帧同步信号时钟频率进行动态分频获得的PWM亮度控制信号时钟频率。对应的分频倍数需要从10000下降至1000，因此在500ms内完成改下降过程，则需要每毫秒内第二分频倍数下降16，即第二分频倍数的下降速度设定为16/ms。
通过上述在帧同步信号进行切换时，先大幅提高PWM亮度控制信号的时钟频率从而大幅缩短亮度异常时长从而达到抑制显示亮度异常的技术效果。
实施例2
如图3所示，本实施例中，本实施例中第一Vsync帧同步信号时钟频率为300Hz，第二Vsync帧同步信号时钟频率为100Hz，即当Vsync帧同步信号时钟频率发生切换时Vsync帧同步信号时钟频率由300Hz下降至100Hz。PWM亮度控制信号的时钟频率根据帧同步信号的时钟频率进行动态分频获得，本实施例中在帧同步信号没有进行切换之前，即LED背光驱动系统所接收到的外部输入的Vsync帧同步信号处于第一Vsync帧同步信号时钟频率时，进行动态分频的第一分频倍数K1设置为1000，即第一Vsync帧同步信号时钟频率所对应的第一PWM亮度控制信号时钟频率为300KHz。
当帧同步信号发生变化时，即第一Vsync帧同步信号时钟频率跳变为第二Vsync帧同步信号时钟频率时，本实施例并不同于前述实施例1中的将第一分频倍数K1升高至第二分频倍数K2。本实施例中，由LED背光驱动系统直接将第二PWM亮度控制信号时钟频率提升至10MHz。与前述实施例1中的技术效果相同地，在第一PWM亮度控制信号时钟频率切换至第二PWM亮度控制信号时钟频率时，虽然依然存在PWM亮度控制信号的占空比变化，但是由于时钟周期的大大缩短，因此这种亮度的异常变化过程也变得极快，达到人眼不易察觉的效果，从而实现对亮度异常的抑制。
在第二PWM亮度控制信号时钟频率提升至1MHz后，为了使PWM亮度控
制信号的时钟频率与外部的输入的第二Vsync帧同步信号的时钟频率一致，第二PWM亮度控制信号时钟频率需要从1MHz逐渐下降至100KHz。与实施例1相同，该下降过程需要在预定时间间隔T内完成，本实施例中设定为500ms。且由于第二分频倍数的每次调整都会带来显示亮度的异常变化，因此第二PWM亮度控制信号时钟频率的下降梯度设置的需要足够精细才能保证画面亮度不存在较为明显的亮度变化。本实施例中，第二PWM亮度控制信号时钟频率需要从1MHz下降到100KHz，因此需要每毫秒第二PWM亮度控制信号时钟频率下降1.8KHz，即第二PWM亮度控制信号时钟频率以1.8KHz/ms的速度从1MHz下降到100KHz。
以上所述，仅为本发明的具体实施案例，本发明的保护范围并不局限于此，任何熟悉本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的保护范围之内。
Claims (10)
- 一种应对帧同步信号切换导致亮度异常的LED背光驱动方法，其特征在于，所述LED背光驱动方法包括：基于帧同步信号的第一时钟频率F1使用第一分频倍数K1进行动态分频处理，以获得第一PWM亮度控制信号时钟频率P1；即：P1＝K1*F1；当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，将第一分频倍数K1切换至第二分频倍数K2；所述第二分频倍数K2大于第一分频倍数K1；基于帧同步信号的第一时钟频率F1使用第二分频倍数K2进行动态分频处理，以获得第二PWM亮度控制信号时钟频率P2；即：P2＝K2*F1；随后对第二PWM亮度控制信号时钟频率P2进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P，所述目标频率P为：P＝K1*F2；且有P＜P2。
- 根据权利要求1所述的LED背光驱动方法，其特征在于，所述第二分频倍数K2大于第一分频倍数K1具体为：(K2/K1)≥10。
- 根据权利要求1所述的LED背光驱动方法，其特征在于，所述对第二PWM亮度控制信号时钟频率P2进行降频处理具体为以预定速率控制第二分频倍数K2逐渐下降，从而使第二PWM亮度控制信号时钟频率P2逐渐下降。
- 根据权利要求1所述的LED背光驱动方法，其特征在于，所述预定时间间隔T小于500ms。
- 一种应对帧同步信号切换导致亮度异常的LED背光驱动方法，其特征在于，所述LED背光驱动方法包括：基于帧同步信号的第一时钟频率F1使用第一分频倍数K1进行动态分频处理，以获得第一PWM亮度控制信号时钟频率P1；即：P1＝K1*F1；当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，所述第一PWM亮度控制信号时钟频率P1切换至预定的第二PWM亮度控制信号时钟频率P2；所述第二PWM亮度控制信号时钟频率P2高于目标频率P；所述目标频率P为：P＝K1*F2；即K1*F2＜P2；随后对第二PWM亮度控制信号时钟频率P2进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P。
- 根据权利要求5所述的LED背光驱动方法，其特征在于，所述第二分频倍数K2大于第一分频倍数K1具体为：(K2/K1)≥10。
- 根据权利要求5所述的LED背光驱动方法，其特征在于，所述对第二PWM亮度控制信号时钟频率P2进行降频处理具体为以预定速率控制第二PWM亮度控制信号时钟频率P2逐渐下降。
- 根据权利要求5所述的LED背光驱动方法，其特征在于，所述预定时间间隔T小于500ms。
- 一种应对帧同步信号切换导致亮度异常的LED背光驱动系统，其特征在于，所述LED背光驱动系统包括：帧同步信号接收模块，其用于接收外部输入LED背光驱动系统的帧同步信号；动态分频处理模块，其用于根据帧同步信号以预定的分频倍数生成PWM亮度控制信号的时钟频率；帧同步信号切换处理模块，其用于处理当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，将第一分频倍数K1切换至第二分频倍数K2；所述第二分频倍数K2大于第一分频倍数K1；并控制动态分频处理模块基于帧同步信号的第一时钟频率F1使用第二分频倍数K2进行动态分频处理，以获得第二PWM亮度控制信号时钟频率P2；即：P2＝K2*F1；所述帧同步信号切换处理模块还用于对第二PWM亮度控制信号时钟频率P2进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P，所述目标频率P为：P＝K1*F2；且有P＜P2。
- 一种应对帧同步信号切换导致亮度异常的LED背光驱动系统，其特征在于，所述LED背光驱动系统包括：帧同步信号接收模块，其用于接收外部输入LED背光驱动系统的帧同步信号；动态分频处理模块，其用于根据帧同步信号以预定的分频倍数生成PWM亮度控制信号的时钟频率；帧同步信号切换处理模块，其用于处理当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，当帧同步信号从第一时钟频率F1切换至第二时钟频率F2时，将所述第一PWM亮度控制信号时钟频率P1切换至预定的第二PWM亮度控制信号时钟频率P2；所述第二PWM亮度控制信号时钟频率P2高于目标频率P；所述目标频率P为：P＝K1*F2；即K1*F2＜P2；所述帧同步信号切换处理模块还用于对第二PWM亮度控制信号时钟频率P2进行降频处理，在预定时间间隔T内将第二PWM亮度控制信号时钟频率P2逐步将至目标频率P。
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