WO2023178576A1 - Display control method, display control apparatus, and intelligent terminal - Google Patents

Display control method, display control apparatus, and intelligent terminal Download PDF

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Publication number
WO2023178576A1
WO2023178576A1 PCT/CN2022/082614 CN2022082614W WO2023178576A1 WO 2023178576 A1 WO2023178576 A1 WO 2023178576A1 CN 2022082614 W CN2022082614 W CN 2022082614W WO 2023178576 A1 WO2023178576 A1 WO 2023178576A1
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Prior art keywords
video
refresh rate
logic chip
decoded
logic
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PCT/CN2022/082614
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French (fr)
Chinese (zh)
Inventor
郭斌
黄秋升
付玉红
梁宁
鲁文怡
Original Assignee
康佳集团股份有限公司
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Application filed by 康佳集团股份有限公司 filed Critical 康佳集团股份有限公司
Priority to PCT/CN2022/082614 priority Critical patent/WO2023178576A1/en
Priority to CN202280000775.1A priority patent/CN117121087A/en
Publication of WO2023178576A1 publication Critical patent/WO2023178576A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

Definitions

  • the present invention relates to the technical field of large-screen ultra-high definition display, and in particular to a display control method, a display control device and an intelligent terminal.
  • 8K high resolution and 120Hz high refresh rate provide excellent film and television effects and have become one of the hot spots for consumers.
  • each node in the transmission chain needs to have 8K120Hz processing capabilities (such as recording and editing of program sources, video compression, content distribution, network transmission, set-top box reception, video decompression, high-speed transmission from set-top box to TV, TV video processing and display), otherwise, the final presentation of the original image content of 8K120Hz video cannot be guaranteed.
  • the current development of the display industry is not balanced before and after the 8K120Hz ecological chain.
  • the technical problem to be solved by the present invention is to provide a display control method, a display control device, a refresh rate conversion method and an intelligent terminal in view of the above-mentioned defects of the prior art, aiming to solve the problem that low refresh rate source video cannot be displayed in the prior art.
  • the display module with high refresh rate prevents users from viewing smoother and clearer video images.
  • an embodiment of the present invention also provides a display control device, wherein the device includes: two logic chips for converting a source video with a first refresh rate into a target video with a second refresh rate, wherein, The first refresh rate is less than the second refresh rate;
  • a logic board connected to the two logic chips, for converting the target video into a low-voltage differential signal
  • a display module is connected to the logic board and used to display the low-voltage differential signal.
  • an embodiment of the present invention provides a display control method, wherein the method includes:
  • the source video is refresh rate converted to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;
  • the target video is input into the display module and displayed through the display module.
  • the two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module; the two logic chips are based on , perform refresh rate conversion on the source video, and obtain the target video with the second refresh rate including:
  • a target video with a second refresh rate is obtained.
  • obtaining the target video with the second refresh rate based on the first logic chip, the second logic chip and the second decoded video includes:
  • obtaining the first region video based on the second decoded video and the first logic chip includes:
  • the second video is motion compensated through the motion compensation module in the first logic chip to obtain a second motion compensated video
  • the second motion compensated video is protocol encoded to obtain the first region video.
  • obtaining the second region video according to the second decoded video and the second logic chip includes:
  • the third video is motion compensated through the motion compensation module in the second logic chip to obtain a third motion compensated video
  • the third motion compensated video is protocol encoded to obtain a second region video.
  • the step of converting the source video to a refresh rate based on two logic chips to obtain a target video with a second refresh rate includes:
  • obtaining two regional videos based on the two third decoded videos includes:
  • Each third decoded video is refresh rate converted through the double-rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate;
  • Each fourth motion compensated video is protocol encoded to obtain two regional videos.
  • embodiments of the present invention further provide a smart terminal, including a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors.
  • the one or more programs include a method for executing the display control method as described in any one of the above.
  • embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute any one of the above.
  • the embodiment of the present invention first obtains the source video with the first refresh rate; and then converts the source video to the refresh rate based on two logic chips to obtain the target video with the second refresh rate; wherein, the The first refresh rate is less than or equal to the second refresh rate; finally, the target video is input to the display module and displayed through the display module; it can be seen that the present invention can convert the source video with a low refresh rate based on two logic chips. Converted into a higher refresh rate video, allowing users to watch smoother and clearer video images.
  • Figure 1 is a functional block diagram of an 8K120Hz display driving solution provided by the prior art.
  • FIG. 2 is a functional block diagram of a display control device provided by an embodiment of the present invention.
  • Figure 3 is a schematic flowchart of a display control method provided by an embodiment of the present invention.
  • FIG. 4 is a functional block diagram of modules inside two FPGAs of an 8K120Hz display driving solution technology provided by an embodiment of the present invention.
  • FIG. 5 is a functional block diagram of an 8K60Hz display driving solution (same hardware and same platform as the 8K120Hz driving solution) provided by an embodiment of the present invention.
  • Figure 6 is a timing diagram of 8K60Hz frame synchronization signals at two FPGA input terminals according to an embodiment of the present invention.
  • FIG. 7 is a timing diagram of 8K120Hz frame synchronization signals at the output terminals of two FPGAs according to an embodiment of the present invention.
  • FIG. 8 is an image rendering before and after a motion compensation module according to an embodiment of the present invention.
  • Figure 9 is a functional block diagram of the internal structure of an intelligent terminal provided by an embodiment of the present invention.
  • the present invention discloses a display control method, a display control device, an intelligent terminal and a storage medium.
  • the equipment included in the above technology has bottlenecks and defects: (1) Refresh of the output signal The highest frame rate is only 8K60Hz. (2) Use at least 4 FPGAs to achieve basic functions. FPGAs have more data, which increases the complexity of system design, and the more FPGAs, the lower the reliability of operation. Take the existing 201610695970.7 (invention title: display control device, display control method and display device) as prior art.
  • the equipment included in this technology uses at least 4 FPGA chips (including 2 data generation chips and 2 data processing chips) as the basic structure. It supports left and right split screens for input data, and also supports left and right input data. The upper and lower quad-split screens are decoded and processed, and finally the driver TCON is sent to light up the screen, but this technology only supports 8K60Hz.
  • this embodiment provides a display control method that can convert a source video with a low refresh rate into a video with a higher refresh rate, so that the user can watch smoother and clearer video images.
  • the source video with the first refresh rate is first obtained; then the source video is refresh rate converted to obtain the target video with the second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; Finally, the target video is input into the display module and displayed through the display module.
  • This embodiment provides a display control device, which includes:
  • a logic board connected to the two logic chips, for converting the target video into a low-voltage differential signal
  • a display module is connected to the logic board and used to display the low-voltage differential signal.
  • the source video signal in the present invention can come from the VbyOne signal of the commercial display device of the SoC (including but not limited to commercial advertising display screen), or can also come from the computer (or set-top box) output HDMI2.1 or DP Signal.
  • the source video has a lower first refresh rate, which can be converted into a target video with a higher refresh rate through two logic chips, and then the target video output by the two logic chips (Tcon board) is converted into a low-voltage differential signal through the logic board. (LVDS), and finally the low-voltage differential signal is displayed through the display module connected to the logic board, that is to say, the display module is lit by driving the logic board.
  • This embodiment provides a display control method, which can be applied to smart terminals with large-screen ultra-high-definition displays. As shown specifically in Figure 3, the method includes:
  • Step S100 Obtain the source video of the first refresh rate
  • the first refresh rate is 60 Hz or lower, and the resolution of the source video may be 4K or 8K. In this embodiment, the resolution of the source video is 8K, and the refresh rate is 60 Hz. First obtain the 8K60Hz source video to prepare for subsequent refresh rate conversion.
  • the existing technology uses four logic chips to complete the refresh rate conversion, which requires greater resource consumption.
  • the present invention only uses two logic chips, which can save half of the resources.
  • there is also technology to convert 60Hz to 120Hz in the existing technology but it is based on resolutions below 2K and cannot convert the refresh rate of videos with higher resolutions such as 4K or even 8K, which will reduce the resolution and cause the video Low quality.
  • the logic chip can be an ASIC chip, an FPGA chip, etc.
  • the logic chip is an FPGA chip. That is to say, converting the source video with the first refresh rate into the target video with the second refresh rate is refreshed through the FPGA chip. rate conversion.
  • the present invention uses two of the above-mentioned logic chips.
  • the cost is lower, because if the algorithm of 8K120Hz ultra-high-definition display is realized by only one FPGA chip, due to the ultra-high-definition algorithm
  • the complexity is very high, the data processing volume is large, and the logic resources it requires are also very high. Therefore, an FPGA chip used to implement 8K120Hz needs to use a large amount of resources and a large number of dedicated differential high-speed transceivers (Serdes). Advanced FPGA chips are very expensive).
  • the two FPGAs with medium logic resources used in the present invention have exactly the same internal modules and identical development programs, which can speed up the time spent on project development.
  • the present invention can be applied according to actual needs, and can be applied to two display modules on the market (8K60Hz display module, 8K120Hz display module) with the same hardware and the same platform, as shown in Figure 3, with the added layout Market flexibility further saves procurement costs.
  • the 8K60Hz display module is an existing technology and will not be described again here.
  • the second refresh rate is 120Hz, and the second refresh rate is higher than the first refresh rate; because the existing technology can only generate 8K60Hz source video, but cannot generate 8K120Hz source video, it makes the mature mass production End-user 8K120Hz display modules cannot be widely used, so this application converts 8K60Hz source video into 8K120Hz video so that users can watch smoother and clearer video images.
  • the existing 8K120Hz display driver solution Figure 1
  • it has a more realistic and delicate display effect, while reducing the problems of motion smear and motion jitter, making the motion picture smoother and clearer.
  • This system can break the bottleneck of the existing digital TV broadcast network without 8K120Hz source and ensure the optimal display of 8K120Hz client.
  • the system has high operation reliability, low production cost and is easy to promote quickly.
  • the input interface types include VbyOne input interface and HDMI2.1/DP1.4 input interface.
  • the source video input by both interfaces requires two logic chips. However, the specific connection methods of the source video and logic chip are different. Through two Even when the logic chip performs refresh rate conversion, the target video of the second refresh rate can be obtained. Therefore, the present invention has a wider application and can be applied to commercial display devices without SoC (including but not limited to commercial advertising display screens). It can also directly use a computer (or set-top box) to output HDMI2.1 or DP signals and access the present invention.
  • the system shown in Figure 3 can drive and light up the commercial display device.
  • the two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module; step S200 includes the following steps:
  • the first logic chip and the second logic chip are both FPGA chips with the same internal structure.
  • the first refresh rate is 60Hz and the second refresh rate is 120Hz.
  • the video source comes from a set-top box/computer through HDMI2. .1/DP1.4 interface input, HDMI2.1/DP1.4 protocol can transmit 32 lanes, because one HDMI2.1/DP1.4 interface can meet the minimum transmission bandwidth requirement of 8K60Hz, so all (whole picture) 8K60Hz images All can be input to any one of the two FPGA chips (for example, the example in Figure 3 shows that it is only transmitted to FPGA#1), and decoded through the HDMI2.1/DP1.4 protocol in any one FPGA chip, we get The second decoded video, finally, the target video with the second refresh rate can be obtained based on the second decoded video, the first logic chip and the second logic chip.
  • Step S202 includes the following steps:
  • obtaining the first area video is to pass the second decoded video through the double-rate synchronous dynamic random access memory in the first logic chip. Convert the refresh rate to obtain a second video with a second refresh rate; perform motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensated video; convert the second
  • the motion compensation video is protocol encoded to obtain the first region video.
  • the internal module structures of the first logic chip and the second logic chip are the same.
  • the second decoded video is obtained by decoding the HDMI2.1/DP1.4 protocol in either logic chip.
  • the subsequent module is: They are the same, but are located on the first logic chip and the second logic chip respectively.
  • the second decoded video performs motion compensation on the second video through the motion compensation module in the first logic chip to obtain the second motion compensated video, and then performs protocol encoding to obtain the first area video; according to the second decoding video and the second logic chip to obtain the second area video.
  • the second decoded video is refresh rate converted through the double rate synchronous dynamic random access memory in the second logic chip to obtain the second refresh. rate the third video; perform motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensated video; perform protocol encoding on the third motion compensated video to obtain Second area video.
  • the second decoded video performs motion compensation on the third video through the motion compensation module in the second logic chip to obtain the third motion compensated video, and then performs protocol encoding through the VbyOne protocol to obtain the second Regional video.
  • the first area video and the second area video may be upper and lower half-screen videos of a screen area, or may be left and right half-screen videos of a screen area.
  • FPGA#1 transmits the right half-screen image of the 8K60Hz image decoded by the HDMI2.1/DP1.4 protocol to FPGA#2 through image mutual transmission signals.
  • the processing modes of the two FPGA chips are exactly the same.
  • the first area video and the second area video are respectively left and right half-screen videos of a screen area. Finally, the first area video and the second area video are merged to obtain a target video with a second refresh rate, and the target video is a complete screen video.
  • the motion compensation module uses a dynamic imaging system to insert a motion compensation frame between the traditional two frames of images to increase the refresh rate, so that the motion picture is clearer and smoother, and is better than the normal response effect.
  • the method of converting the source video to a refresh rate based on two logic chips to obtain a target video with a second refresh rate includes the following steps: inputting the source video to each of the logic chips respectively, and passing the second refresh rate to the source video.
  • the communication protocol is decoded to obtain two third decoded videos; each of the third decoded videos is refresh rate converted through the double rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate;
  • Use the motion compensation module to perform motion compensation on each of the fourth videos to obtain two fourth motion compensated videos; perform protocol encoding on each fourth motion compensated video to obtain two regional videos; combine the two regional videos Merge to obtain the target video with the second refresh rate.
  • the first refresh rate is 60Hz and the second refresh rate is 120Hz.
  • the video signal source output by the front-end 8KSoC is an 8K60Hz picture, which is sent to the receiving end of the FPGA through the VbyOne protocol, which requires 32lane differential signals (each lane rate is 2.97Gbps) to meet the minimum requirement of 8K60Hz transmission bandwidth (Note: the transmission bandwidth of 8K60Hz is about 90Gbps, and at least 32 lane VbyOne signals are required to meet the transmission requirements.
  • the VbyOne protocol can only transmit 16lane, so the present invention uses 16lane of 8K60Hz
  • the source video is distributed and input into each of the logic chips, and decoded through the VbyOne protocol to obtain the third decoded video corresponding to each of the logic chips.
  • the first 16 lanes transmit the left half screen of the 8K60Hz video
  • the last 16 lanes transmit the left half screen of the 8K60Hz video
  • 16lane transmits the right half-screen image of the 8K60Hz video.
  • each third decoded video is refresh rate converted through the double-rate synchronous dynamic random access memory to obtain the fourth video corresponding to each of the logic chips. ; In this way, there are two fourth videos.
  • Each fourth video is motion compensated through the motion compensation module to obtain a fourth motion compensated video corresponding to each of the logic chips.
  • each fourth motion compensation video is protocol encoded through the VbyOne protocol to obtain the regional video corresponding to each of the logic chips; in practice, the transmission bandwidth of 8K120Hz is about 180Gbps, which requires at least 64lane VbyOne signals to meet the transmission requirements).
  • the two regional videos are left and right half-screen videos respectively.
  • the two regional videos are merged to obtain the target video with the second refresh rate.
  • the function of FPGA#1 is to perform protocol decoding on the VbyOne signal (16lane) received by the receiving end.
  • the protocol encodes the 120Hz left half screen image into a 32 lane VbyOne signal and sends it to the 8K120Hz Tcon Board.
  • the Tcon Board drives and lights up the 8K120Hz display module.
  • FPGA#2 functions the same as FPGA#1.
  • the two FPGAs can transmit pixel clock synchronization signals to each other to ensure that the left and right half-screen images output to the Tcon board are completely synchronized in time to avoid screen tearing problems.
  • the refresh rate of the source video remains unchanged, and the refresh rate before and after the refresh rate conversion remains unchanged.
  • the video source is 8K60Hz.
  • the display module is also 8K60Hz, the module inside an FPGA chip is consistent with the FPGA#1 part (or FPGA#2 part) in Figure 4. At this time, only one FPGA is needed to realize all functions, and the same hardware circuit, the same FPGA chip, and the same modules inside the FPGA chip are used as the 8K120Hz architecture diagram ( Figure 4). The difference is that only one FPGA is used (FPGA#1 is used as an example in Figure 5) and the module presets inside the FPGA are different.
  • the first refresh rate is equal to the second refresh rate
  • decoding is performed through the first communication protocol to obtain the first decoded video
  • the first decoded video is refreshed through the double-rate synchronous dynamic random access memory. Convert to obtain the first video with the second refresh rate; perform motion compensation on the first video through the motion compensation module to obtain the first motion compensated video; perform protocol encoding on the first motion compensated video to obtain the second Refresh rate target video.
  • the first communication protocol is HDMI2.1/DP1.4.
  • the video source comes from the set-top box/computer and is input through the HDMI2.1/DP1.4 interface.
  • the first refresh rate is equal to the second refresh rate, such as Input the 8K60Hz source video and the target video is 8K60Hz.
  • the first refresh rate is equal to the second refresh rate, such as Input the 8K60Hz source video and the target video is 8K60Hz.
  • the first decoded video is refresh rate converted through the double rate synchronous dynamic random access memory to obtain the first video with the second refresh rate; at this time, in order to maintain the internal module structure of the 8K60Hz FPGA chip and the internal module structure of the 8K120Hz FPGA chip
  • the module structure is the same, so the FPGA chip still includes double-rate synchronous dynamic random access memory, but no interpolation is performed, so that the output and input data rates are the same. In this way, the refresh rates of the first video and the first decoded video are the same.
  • the first video is motion compensated through the motion compensation module to obtain a first motion compensated video; in this way, the first motion compensated video presents a more realistic and delicate display effect, and at the same time can reduce the problems of motion smear and motion jitter. , making the motion picture smoother and clearer.
  • the first motion compensation video is encoded with HDMI2.1/DP1.4 protocol to obtain the target video with the second refresh rate.
  • the two FPGAs have no constraint relationship and can change their positions arbitrarily.
  • the implementation of the FPGA internal module in the present invention is as follows:
  • the internal module parts of the two FPGAs are shown in Figure 4.
  • the total amount of data processed and the functions implemented by FPGA#1 and FPGA#2 are the same (the difference is that FPGA#1 processes the image data of the left half of the screen, and FPGA#2 processes the image data of the right half of the screen). Therefore, the internal modules of FPGA#1 and FPGA#2 are consistent.
  • the VbyOne protocol decoding module or HDMI2.1/DP1.4 protocol decoding module decodes and outputs the image data of the left half of the screen, which will be cached in asynchronous FiFo (the FiFo has a small capacity, such as 8K resolution half (3840 rows of pixel storage space), and then under the constraints of the input frame synchronization control modules inside FPGA#1 and FPGA#2, the left half-screen image data in FPGA#1 and the right half-screen image in FPGA#2 The data is synchronously aligned in time and output to the back-end DDR read-write control module, and also output to the back-end dual-port RAM1 module (the cache capacity of dual-port RAM1 is about 5 lines, each line has 7680 pixels, and is used for the motion compensation module Do interpolation calculations).
  • the input frame synchronization control module is responsible for constraining the left and right half-screen image data received by the two FPGAs.
  • the implementation timing is shown in Figure 6.
  • the input frame synchronization signals that FPGA#1 needs to transmit to FPGA#2 include: (1) Pixel CLK1: left half screen image pixel clock, frequency is about 75MHz, this clock is generated by the PLL inside FPGA#1; (2) Input DE1: Left half screen image data valid signal, this signal is generated by the front-end VbyOne protocol decoding module or HDMI2.1/DP1.4 protocol decoding module.
  • the input frame synchronization signal that FPGA#2 needs to transmit to FPGA#1 includes Pixel CLK2: the right half-screen image pixel clock with a frequency of about 75MHz. This clock is generated by the PLL inside the FPGA#2 chip; (3) Input DE2: Right half screen image data valid signal, this signal is generated by the front-end VbyOne protocol decoding module or HDMI2.1/DP1.4 protocol decoding module. When this signal is high, it means that the pixel data at this time is valid.
  • FPGA#1 will calculate the time difference with the internal pixel data of FPGA#2 (as shown in Figure 6, for example, the input pixel data of FPGA#1 (left half screen) is greater than the input pixel data of FPGA#2 (right half screen) input pixel data 2 clock cycles faster).
  • FPGA#2 will also calculate the time difference with the internal pixel data of FPGA#1 (that is, the input pixel data of FPGA#2 (right half screen) is 2 clock cycles slower than that of FPGA#1).
  • frame synchronization can be triggered at the preset position (for example, in Figure 6, the position is the 1st pixel data of the input line 1 of FPGA#2 to start triggering frame synchronization.
  • the trigger position can be selected based on the capacity of asynchronous FiFo) , starting from the trigger position, the cached image data will be read continuously from asynchronous FiFo.
  • the left and right half-screen image data input by two FPGAs can be realized, ensuring that each frame is synchronously aligned in time, and avoiding the problem of screen tearing of the left and right half-screen input images.
  • the DDR read and write control module is responsible for writing the image data sent by the previous module (asynchronous FiFo) into the DDR storage unit in real time.
  • the image data of the previous frame is continuously read from the DDR storage unit and sent to the dual-port RAM2 module (the cache capacity of the dual-port RAM2 is about 5 lines, each 7680 pixels per row, used for interpolation calculations by the motion compensation module).
  • the dual-port RAM2 large capacity as the image output buffer to facilitate the interpolation calculation of the motion compensation module.
  • the function of the output frame synchronization control module is to independently generate the total pixel scanning timing of the 8K120Hz image.
  • Two FPGAs are connected through the output frame synchronization signal to ensure that each frame of the 8K120Hz scanning timing within the two chips is synchronously aligned.
  • one of the FPGAs can be preset to independently generate the DE signal of 8K120Hz pixel scanning (the example in Figure 7 is that FPGA#1 independently generates and outputs the DE1 signal), and then transmits this signal to another FPGA ( Figure 7 The example in is FPGA#2), another FPGA chip will sample this signal, but because sampling takes 1 clock cycle, FPGA#2 will delay 1 clock when receiving the DE1 signal from FPGA#1.
  • FPGA#1 can be preset to be transmitted to FPGA#2, or FPGA#2 can be preset to be transmitted to FPGA#1 (for example, in Figure 7, FPGA#1 is transmitted to FPGA#2).
  • the trigger frame synchronization position can be preset (for example, in Figure 7, the trigger frame synchronization position is the first pixel in row 1 where FPGA#2 receives the DE1 signal from FPGA#1 data position), after frame synchronization processing, the output DE of FPGA#1 and FPGA#2 will be synchronously aligned, as shown in Figure 7, the self-generated output DE 1 after synchronization within the frame synchronization module of the output end of the FPGA#1 chip , the self-generated output DE2 will be synchronously aligned with the internal synchronization of the output terminal frame synchronization module in the FPGA#2 chip.
  • the self-generated output DE1 signal after synchronization will control the [DDR read and write control module] to read the pixel image data of the previous frame from the DDR storage unit ( left half of the screen).
  • the self-generated output DE2 signal after synchronization will control the [DDR Read and Write Control Module] to read the pixels of the previous frame from the DDR memory unit. Image data (right half of screen).
  • the image data of the previous frame is continuously read from the DDR storage unit and will be cached in the dual-port RAM2.
  • the motion compensation module will receive the current frame (Kth frame) image data of the dual-port RAM1 and the previous frame (K-1st frame) image data in the dual-port RAM2.
  • the motion compensation module will process the two frames of 8K60Hz.
  • the image data is analyzed and calculated, and an 8K120Hz image with motion compensation effect is output, as shown in Figure 8.
  • the output 8K120Hz image with motion compensation has a motion enhancement effect, which can reduce image smear and jitter problems, making the motion scene smoother and clearer.
  • FPGA#1 finally encodes the 8K120Hz image with motion compensation (left half of the screen) using the VbyOne protocol into a 32 lane VbyOne signal, sends it to the back-end Tcon board, and drives the left half of the screen to light up.
  • FPGA#2 finally encodes the 8K120Hz image with motion compensation (right half of the screen) using the VbyOne protocol into a 32 lane VbyOne signal, sends it to the back-end Tcon board, and drives the right half of the screen to light up.
  • the display module is a Tcon board. After the target video is input to the back-end Tcon board, the display module is driven to light up.
  • the present invention also provides an intelligent terminal, the functional block diagram of which can be shown in Figure 9 .
  • the intelligent terminal includes a processor, memory, network interface, display screen, and temperature sensor connected through a system bus.
  • the processor of the smart terminal is used to provide computing and control capabilities.
  • the memory of the smart terminal includes non-volatile storage media and internal memory.
  • the non-volatile storage medium stores operating systems and computer programs.
  • This internal memory provides an environment for the execution of operating systems and computer programs in non-volatile storage media.
  • the network interface of the smart terminal is used to communicate with external terminals through network connections.
  • the computer program implements a display control method when executed by the processor.
  • the display screen of the smart terminal can be a liquid crystal display or an electronic ink display.
  • the temperature sensor of the smart terminal is pre-set inside the smart terminal for detecting the operating temperature of the internal device.
  • FIG. 9 is only a block diagram of a partial structure related to the solution of the present invention, and does not constitute a limitation on the smart terminal to which the solution of the present invention is applied.
  • Specific smart terminals may include There may be more or fewer parts than shown, or certain parts may be combined, or may have a different arrangement of parts.
  • a smart terminal including a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors.
  • One or more programs contain instructions for:
  • the target video is input into the display module and displayed through the display module.
  • Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
  • SRAM static RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDRSDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM synchronous chain Synchlink DRAM
  • Rambus direct RAM
  • DRAM direct memory bus dynamic RAM
  • RDRAM memory bus dynamic RAM
  • the present invention discloses a display control method, a display control device, an intelligent terminal and a storage medium.
  • the method includes: obtaining a source video with a first refresh rate; performing refresh rate conversion on the source video to obtain The target video at the second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; the target video is input into the display module and displayed by the display module.
  • the invention can convert a source video with a low refresh rate into a video with a higher refresh rate, so that users can watch smoother and clearer video images.
  • the present invention proposes an 8K120Hz display control system and display device, which supports converting the 8K60Hz input source refresh rate to 120Hz output and drives the display module (including but not limited to LCD, LED 8K120Hz display large screen), which is consistent with the existing 8K120Hz Compared with the display driver solution (as shown in Figure 1), it has a more realistic and delicate display effect. It can also reduce the problems of motion smear and motion jitter, making the motion picture smoother and clearer.
  • This system can break the bottleneck of the existing digital TV broadcast network without 8K120Hz source and ensure the optimal display of 8K120Hz client.
  • the system has high operation reliability, low production cost and is easy to promote quickly.
  • the present invention can realize all functions by using two FPGA chips with medium logic resources, and the cost is lower than using only one FPGA chip with large-capacity logic resources.
  • Reason If the algorithm of 8K120Hz ultra-high-definition display is implemented only through one FPGA chip, due to the high complexity of the ultra-high-definition algorithm and the large amount of data processing, the logic resources required are also very high, so the implementation of 8K120Hz uses An FPGA chip requires an advanced FPGA chip with large resources and many dedicated differential high-speed transceivers (Serdes), which is very expensive).
  • the two FPGAs with medium logic resources used in the present invention have exactly the same internal modules and identical development programs, which can speed up the time spent on project development.
  • the present invention can be applied according to actual needs, and can be applied to two display modules (8K60Hz display module, 8K120Hz display module) on the market with the same hardware and the same platform, increasing market layout flexibility and further saving procurement costs.
  • the present invention discloses a display control method. It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or changes can be made according to the above descriptions. All these improvements All modifications and transformations shall fall within the protection scope of the appended claims of the present invention.

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Abstract

A display control method, a display control apparatus, and an intelligent terminal. The method comprises: acquiring a source video having a first refresh rate (S100); on the basis of two logic chips, performing refresh rate conversion on the source video to obtain a target video having a second refresh rate (S200), wherein the first refresh rate is less than or equal to the second refresh rate; and inputting the target video into a display module, and displaying the target video by means of the display module (S300). On the basis of the two logic chips, the source video having a low refresh rate can be converted into a video having a higher refresh rate, such that a user can watch a smoother and clearer video picture.

Description

一种显示控制方法、显示控制装置及智能终端A display control method, display control device and intelligent terminal 技术领域Technical field
本发明涉及大屏超高清显示技术领域，尤其涉及的是一种显示控制方法、显示控制装置及智能终端。The present invention relates to the technical field of large-screen ultra-high definition display, and in particular to a display control method, a display control device and an intelligent terminal.
背景技术Background technique
在高端大尺寸显示市场应用中，8K高分辨率加上120Hz高刷新率的影视效果出色，成为消费者关注的热点之一。要把8K120Hz视频内容从直播现场或者电视频道发送到电视显示终端并最终呈现给用户，传输链条的每一个节点都需要具备8K120Hz的处理能力(比如节目源的录制采编、视频压缩、内容分发、网络传输、机顶盒接收、视频解压缩、机顶盒到电视的高速传输、电视的视频处理及显示)，否则，8K120Hz视频原始图像内容的最后呈现得不到保证。但是目前显示行业在8K120Hz的生态链前后发展并不平衡，前端节目信源质量最高只有8K60Hz，而后端的8K120Hz显示模组早已成熟量产，使得低刷新率源视频无法在高刷新率的显示模组中显示，导致用户无法观看到更加流畅清晰的视频画面。In high-end large-size display market applications, 8K high resolution and 120Hz high refresh rate provide excellent film and television effects and have become one of the hot spots for consumers. To send 8K120Hz video content from the live broadcast site or TV channel to the TV display terminal and finally present it to the user, each node in the transmission chain needs to have 8K120Hz processing capabilities (such as recording and editing of program sources, video compression, content distribution, network transmission, set-top box reception, video decompression, high-speed transmission from set-top box to TV, TV video processing and display), otherwise, the final presentation of the original image content of 8K120Hz video cannot be guaranteed. However, the current development of the display industry is not balanced before and after the 8K120Hz ecological chain. The highest quality of front-end program sources is only 8K60Hz, while the back-end 8K120Hz display modules have long been mature for mass production, making it impossible for low refresh rate source videos to be displayed on high refresh rate display modules. display, resulting in users being unable to watch smoother and clearer video images.
因此，现有技术还有待改进和发展。Therefore, the existing technology still needs to be improved and developed.
发明内容Contents of the invention
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种显示控制方法、显示控制装置、刷新率转换方法及智能终端，旨在解决现有技术中低刷新率源视频无法在高刷新率的显示模组中显示，导致用户无法观看到更加流畅清晰的视频画面的问题。The technical problem to be solved by the present invention is to provide a display control method, a display control device, a refresh rate conversion method and an intelligent terminal in view of the above-mentioned defects of the prior art, aiming to solve the problem that low refresh rate source video cannot be displayed in the prior art. The display module with high refresh rate prevents users from viewing smoother and clearer video images.
本发明解决问题所采用的技术方案如下：The technical solutions adopted by the present invention to solve the problem are as follows:
第一方面，本发明实施例还提供一种显示控制装置，其中，所述装置包括：两个逻辑芯片，用于将第一刷新率的源视频转换成第二刷新率的目标视频，其中，所述第一刷新率小于第二刷新率；In a first aspect, an embodiment of the present invention also provides a display control device, wherein the device includes: two logic chips for converting a source video with a first refresh rate into a target video with a second refresh rate, wherein, The first refresh rate is less than the second refresh rate;
逻辑板，与两个所述逻辑芯片连接，用于将所述目标视频转换成低压差分信号；A logic board, connected to the two logic chips, for converting the target video into a low-voltage differential signal;
显示模组，与所述逻辑板连接，用于将所述低压差分信号显示。A display module is connected to the logic board and used to display the low-voltage differential signal.
第二方面，本发明实施例提供一种显示控制方法，其中，所述方法包括：In a second aspect, an embodiment of the present invention provides a display control method, wherein the method includes:
获取第一刷新率的源视频；Get the source video with the first refresh rate;
基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于或者等于第二刷新率；Based on two logic chips, the source video is refresh rate converted to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;
将所述目标视频输入显示模组，并通过所述显示模组显示。The target video is input into the display module and displayed through the display module.
在一种实现方式中，两个所述逻辑芯片为第一逻辑芯片和第二逻辑芯片；每个所述逻辑芯片包括双倍速率同步动态随机存储器和运动补偿模块；所述基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频包括：In one implementation, the two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module; the two logic chips are based on , perform refresh rate conversion on the source video, and obtain the target video with the second refresh rate including:
将所述源视频输入到所述第一逻辑芯片，通过所述第一通信协议进行解码，得到第二解码视频；Input the source video to the first logic chip, decode it through the first communication protocol, and obtain a second decoded video;
基于所述第一逻辑芯片、所述第二逻辑芯片和所述第二解码视频，得到第二刷新率的目标视频。Based on the first logic chip, the second logic chip and the second decoded video, a target video with a second refresh rate is obtained.
在一种实现方式中，所述基于所述第一逻辑芯片、所述第二逻辑芯片和所述第二解码视频，得到第二刷新率的目标视频包括：In one implementation, obtaining the target video with the second refresh rate based on the first logic chip, the second logic chip and the second decoded video includes:
根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频；According to the second decoded video and the first logic chip, a first area video is obtained;
根据所述第二解码视频和所述第二逻辑芯片，得到第二区域视频；According to the second decoded video and the second logic chip, a second regional video is obtained;
将第一区域视频和第二区域视频进行合并，得到第二刷新率的目标视频。Merge the first area video and the second area video to obtain a target video with a second refresh rate.
在一种实现方式中，所述根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频包括：In one implementation, obtaining the first region video based on the second decoded video and the first logic chip includes:
将所述第二解码视频通过所述第一逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第二视频；Perform refresh rate conversion on the second decoded video through the double-rate synchronous dynamic random access memory in the first logic chip to obtain a second video with a second refresh rate;
通过所述第一逻辑芯片中的所述运动补偿模块将所述第二视频进行运动补偿，得到第二运动补偿视频；The second video is motion compensated through the motion compensation module in the first logic chip to obtain a second motion compensated video;
将所述第二运动补偿视频进行协议编码，得到第一区域视频。The second motion compensated video is protocol encoded to obtain the first region video.
在一种实现方式中，所述根据所述第二解码视频和所述第二逻辑芯片，得到第二区域视频包括：In one implementation, obtaining the second region video according to the second decoded video and the second logic chip includes:
将所述第二解码视频通过所述第二逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第三视频；Perform refresh rate conversion on the second decoded video through the double-rate synchronous dynamic random access memory in the second logic chip to obtain a third video with a second refresh rate;
通过所述第二逻辑芯片中的所述运动补偿模块将所述第三视频进行运动补偿，得到第三运动补偿视频；The third video is motion compensated through the motion compensation module in the second logic chip to obtain a third motion compensated video;
将所述第三运动补偿视频进行协议编码，得到第二区域视频。The third motion compensated video is protocol encoded to obtain a second region video.
在一种实现方式中，所述基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频包括：In one implementation, the step of converting the source video to a refresh rate based on two logic chips to obtain a target video with a second refresh rate includes:
将所述源视频分别输入到每个所述逻辑芯片，通过所述第二通信协议进行解码，得到两个第三解码视频；Input the source video to each of the logic chips respectively, decode it through the second communication protocol, and obtain two third decoded videos;
根据两个所述第三解码视频，得到两个区域视频；According to the two third decoded videos, two regional videos are obtained;
将两个区域视频进行合并，得到第二刷新率的目标视频。Merge the two regional videos to obtain the target video with the second refresh rate.
在一种实现方式中，所述根据两个所述第三解码视频，得到两个区域视频包括：In one implementation, obtaining two regional videos based on the two third decoded videos includes:
将每个所述第三解码视频均通过所述双倍速率同步动态随机存储器进行刷新率转换，得到两个第二刷新率的第四视频；Each third decoded video is refresh rate converted through the double-rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate;
通过所述运动补偿模块将每个所述第四视频进行运动补偿，得到两个第四运动补偿视频；Perform motion compensation on each of the fourth videos through the motion compensation module to obtain two fourth motion compensated videos;
将每个第四运动补偿视频进行协议编码，得到两个区域视频。Each fourth motion compensated video is protocol encoded to obtain two regional videos.
第三方面，本发明实施例还提供一种智能终端，包括有存储器，以及一个或者一个以上的程序，其中一个或者一个以上程序存储于存储器中，且经配置以由一个或者一个以上处理器执行所述一个或者一个以上程序包含用于执行如上述任意一项所述的显示控制方法。In a third aspect, embodiments of the present invention further provide a smart terminal, including a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors. The one or more programs include a method for executing the display control method as described in any one of the above.
第四方面，本发明实施例还提供一种非临时性计算机可读存储介质，当所述存储介质中的指令由电子设备的处理器执行时，使得电子设备能够执行如上述中任意一项所述的显示控制方法。In a fourth aspect, embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute any one of the above. The display control method described above.
本发明的有益效果：本发明实施例首先获取第一刷新率的源视频；然后基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于或者等于第二刷新率；最后将所述目标视频输入显示模组，并通过所述显示模组显示；可见，本发明基于两个逻辑芯片就可以将低刷新率的源视频转化为更高刷新率的视频，使得用户能观看到更加流畅清晰的视频画面。Beneficial effects of the present invention: The embodiment of the present invention first obtains the source video with the first refresh rate; and then converts the source video to the refresh rate based on two logic chips to obtain the target video with the second refresh rate; wherein, the The first refresh rate is less than or equal to the second refresh rate; finally, the target video is input to the display module and displayed through the display module; it can be seen that the present invention can convert the source video with a low refresh rate based on two logic chips. Converted into a higher refresh rate video, allowing users to watch smoother and clearer video images.
附图说明Description of the drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.
图1为现有技术提供的8K120Hz显示驱动方案原理框图。Figure 1 is a functional block diagram of an 8K120Hz display driving solution provided by the prior art.
图2为本发明实施例提供的显示控制装置的原理框图。FIG. 2 is a functional block diagram of a display control device provided by an embodiment of the present invention.
图3为本发明实施例提供的显示控制方法流程示意图。Figure 3 is a schematic flowchart of a display control method provided by an embodiment of the present invention.
图4为本发明实施例提供的一种实施方式的8K120Hz显示驱动方案技术两颗FPGA内部的模块的原理框图。FIG. 4 is a functional block diagram of modules inside two FPGAs of an 8K120Hz display driving solution technology provided by an embodiment of the present invention.
图5为本发明实施例提供的一种实施方式的8K60Hz显示驱动方案(与8K120Hz驱动方案同硬件、同平台)的原理框图。FIG. 5 is a functional block diagram of an 8K60Hz display driving solution (same hardware and same platform as the 8K120Hz driving solution) provided by an embodiment of the present invention.
图6为本发明实施例提供的一种实施方式的两颗FPGA输入端8K60Hz帧同步信号时序图。Figure 6 is a timing diagram of 8K60Hz frame synchronization signals at two FPGA input terminals according to an embodiment of the present invention.
图7为本发明实施例提供的一种实施方式的两颗FPGA输出端8K120Hz帧同步信号时序图。FIG. 7 is a timing diagram of 8K120Hz frame synchronization signals at the output terminals of two FPGAs according to an embodiment of the present invention.
图8为本发明实施例提供的一种实施方式的运动补偿模块前后的图像效果图。FIG. 8 is an image rendering before and after a motion compensation module according to an embodiment of the present invention.
图9为本发明实施例提供的智能终端的内部结构原理框图。Figure 9 is a functional block diagram of the internal structure of an intelligent terminal provided by an embodiment of the present invention.
具体实施方式Detailed ways
本发明公开了一种显示控制方法、显示控制装置、智能终端及存储介质，为使本发明的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。The present invention discloses a display control method, a display control device, an intelligent terminal and a storage medium. In order to make the purpose, technical solutions and effects of the present invention clearer and clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本发明的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。应该理解，当我们称元件被“连接”或“耦接”到另一元件时，它可以直接连接或耦接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。Those skilled in the art will understand that, unless expressly stated otherwise, the singular forms "a", "an", "the" and "the" used herein may also include the plural form. It should be further understood that the word "comprising" used in the description of the present invention refers to the presence of stated features, integers, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more other features, Integers, steps, operations, elements, components and/or groups thereof. It will be understood that when we refer to an element being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Additionally, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. As used herein, the term "and/or" includes all or any unit and all combinations of one or more of the associated listed items.
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本发明所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should also be understood that terms, such as those defined in general dictionaries, are to be understood to have meanings consistent with their meaning in the context of the prior art, and are not to be used in an idealistic or overly descriptive manner unless specifically defined as here. to explain the formal meaning.
由于现有技术中，随着大屏显示、8K超高清分辨率、120Hz高刷新率等技术的发展，上述技术(发明点)所包括的设备存在的瓶颈及缺陷：(1)输出信号的刷新帧率最高仅8K60Hz。(2)使用至少4颗FPGA方可实现基本功能，FPGA的数据较多，增加了系统设计的复杂度，而且FPGA数量越多运行的可靠性越低。以现有的201610695970.7(发明名称：显示控制装置、显示控制方法和显示装置)为已有技术。该技术(发明点)所包括的设备，以至少4颗FPGA芯片(包括2颗数据生成芯片、2颗数据处理芯片)做为基本架构，支持输 入数据左右二分屏、也支持输入数据左右、上下四分屏解码与处理，最后送出驱动TCON点亮屏幕，但该技术仅支持8K60Hz。Due to the existing technology, with the development of large-screen display, 8K ultra-high definition resolution, 120Hz high refresh rate and other technologies, the equipment included in the above technology (point of invention) has bottlenecks and defects: (1) Refresh of the output signal The highest frame rate is only 8K60Hz. (2) Use at least 4 FPGAs to achieve basic functions. FPGAs have more data, which increases the complexity of system design, and the more FPGAs, the lower the reliability of operation. Take the existing 201610695970.7 (invention title: display control device, display control method and display device) as prior art. The equipment included in this technology (point of invention) uses at least 4 FPGA chips (including 2 data generation chips and 2 data processing chips) as the basic structure. It supports left and right split screens for input data, and also supports left and right input data. The upper and lower quad-split screens are decoded and processed, and finally the driver TCON is sent to light up the screen, but this technology only supports 8K60Hz.
市场上已量产的大部分8K120Hz整机(电视机)的方案，缺陷：1.通过加入一颗图像缩放IC(Scalar IC)来完成4K放大到8K解析度，放大后的图像是有损的会丢失部分细节画质效果差。2.图像缩放IC(Scalar IC)因其开发技术复杂，生产量少，且技术掌握在少数几家开发商，因此其采购价格非常昂贵。且该技术不支持8K60Hz信号源输入。以现有市场上已量产的大部分8K120Hz整机(电视机)的方案如图1所示，输入信源仅支持4K解析度(3840x2160),通过加入一颗图像缩放IC(Scalar IC)来完成4K放大到8K，最后点亮屏幕。虽然也可以满足基本的影视效果，但是此方案缺点是图像放大过程是有损的，画质效果有所损失。Most of the 8K120Hz complete machine (TV) solutions that have been mass-produced on the market have defects: 1. By adding an image scaling IC (Scalar IC) to complete 4K amplification to 8K resolution, the amplified image is lossy. Some details will be lost and the image quality will be poor. 2. Image scaling IC (Scalar IC) has complex development technology, low production volume, and the technology is controlled by a few developers, so its purchase price is very expensive. And this technology does not support 8K60Hz signal source input. The solutions of most 8K120Hz complete machines (TVs) that have been mass-produced on the market are shown in Figure 1. The input source only supports 4K resolution (3840x2160). By adding an image scaling IC (Scalar IC) Complete the enlargement from 4K to 8K, and finally light up the screen. Although it can also meet the basic film and television effects, the disadvantage of this solution is that the image amplification process is lossy and the image quality effect is lost.
为了解决现有技术的问题，本实施例提供了一种显示控制方法，可以将低刷新率的源视频转化为更高刷新率的视频，使得用户能观看到更加流畅清晰的视频画面。具体实施时，首先获取第一刷新率的源视频；然后将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于或者等于第二刷新率；最后将所述目标视频输入显示模组，并通过所述显示模组显示。In order to solve the problems of the existing technology, this embodiment provides a display control method that can convert a source video with a low refresh rate into a video with a higher refresh rate, so that the user can watch smoother and clearer video images. During specific implementation, the source video with the first refresh rate is first obtained; then the source video is refresh rate converted to obtain the target video with the second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; Finally, the target video is input into the display module and displayed through the display module.
示例性设备Example device
本实施例提供一种显示控制装置，所述装置包括：This embodiment provides a display control device, which includes:
两个逻辑芯片，用于将第一刷新率的源视频转换成第二刷新率的目标视频，其中，所述第一刷新率小于第二刷新率；Two logic chips for converting the source video at the first refresh rate into the target video at the second refresh rate, wherein the first refresh rate is smaller than the second refresh rate;
逻辑板，与两个所述逻辑芯片连接，用于将所述目标视频转换成低压差分信号；A logic board, connected to the two logic chips, for converting the target video into a low-voltage differential signal;
显示模组，与所述逻辑板连接，用于将所述低压差分信号显示。A display module is connected to the logic board and used to display the low-voltage differential signal.
具体地，如图2所示本发明中的源视频信号可以来自SoC的商业显示设备(包括但不限于商业广告显示屏)的VbyOne信号，也可以来自电脑(或机顶盒)输出HDMI2.1或者DP信号。源视频的第一刷新率较低，通过两个逻辑芯片可以转换为更高刷新率的目标视频，然后通过逻辑板将两个所述逻辑芯片(Tcon板)输出的目标视频转换成低压差分信号(LVDS),最后通过所述逻辑板连接的显示模组将所述低压差分信号显示，也就是说通过逻辑板驱动点亮所述显示模组。Specifically, as shown in Figure 2, the source video signal in the present invention can come from the VbyOne signal of the commercial display device of the SoC (including but not limited to commercial advertising display screen), or can also come from the computer (or set-top box) output HDMI2.1 or DP Signal. The source video has a lower first refresh rate, which can be converted into a target video with a higher refresh rate through two logic chips, and then the target video output by the two logic chips (Tcon board) is converted into a low-voltage differential signal through the logic board. (LVDS), and finally the low-voltage differential signal is displayed through the display module connected to the logic board, that is to say, the display module is lit by driving the logic board.
示例性方法Example methods
本实施例提供一种显示控制方法，该方法可以应用于大屏超高清显示的智能终端。具体如图3所示，所述方法包括：This embodiment provides a display control method, which can be applied to smart terminals with large-screen ultra-high-definition displays. As shown specifically in Figure 3, the method includes:
步骤S100、获取第一刷新率的源视频；Step S100: Obtain the source video of the first refresh rate;
具体地，第一刷新率为60Hz或者更低，源视频的分辨率可以为4K或者8K，在本实施例中，源视频的分辨率为8K，刷新率为60Hz。先获取8K60Hz的源视频，为后续进行刷新率转换做准备。Specifically, the first refresh rate is 60 Hz or lower, and the resolution of the source video may be 4K or 8K. In this embodiment, the resolution of the source video is 8K, and the refresh rate is 60 Hz. First obtain the 8K60Hz source video to prepare for subsequent refresh rate conversion.
得到源视频后，就可以执行如图3所示的如下步骤：S200、基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于第二刷新率；After obtaining the source video, you can perform the following steps as shown in Figure 3: S200. Based on two logic chips, refresh rate conversion is performed on the source video to obtain a target video with a second refresh rate; wherein, the first The refresh rate is less than the second refresh rate;
具体地，现有技术通过4颗逻辑芯片来完成刷新率的转换，需要消耗更大的资源，而本发明只需要采用两颗逻辑芯片，可以节省一半的资源。此外，现有技术中也有将60Hz转换为120Hz的技术，但是其基于2K以下的分辨率，无法对4K乃至8K等更高分辨率的视频进行刷新率的转换，会使得分辨率降低，导致视频质量低下。逻辑芯片可以为ASIC芯片，FPGA芯片等，在本实施例中，逻辑芯片为FPGA芯片，也就是说将第一刷新率的源视频转换为第二刷新率的目标视频是通过FPGA芯片来完成刷新率转换。为了节省资源，本发明采用2颗所述逻辑芯片，相对于只使用1颗大容量逻辑资源FPGA芯片成本更低，因为8K120Hz超高清显示的算法若只通过一颗FPGA芯片实现，由于超高清算法的复杂度很高，数据处理量很大，其所需要的逻辑资源也是非常高的，因此实现8K120Hz所采用的一颗FPGA芯片需要选用资源量大、专用差分高速收发器(Serdes)较多的高级FPGA芯片，其成本是非常昂贵的)。其次，本发明使用的两颗中等逻辑资源的FPGA，内部模块完全相同，开发程序也完全相同，可加快工程开发所耗时间。Specifically, the existing technology uses four logic chips to complete the refresh rate conversion, which requires greater resource consumption. However, the present invention only uses two logic chips, which can save half of the resources. In addition, there is also technology to convert 60Hz to 120Hz in the existing technology, but it is based on resolutions below 2K and cannot convert the refresh rate of videos with higher resolutions such as 4K or even 8K, which will reduce the resolution and cause the video Low quality. The logic chip can be an ASIC chip, an FPGA chip, etc. In this embodiment, the logic chip is an FPGA chip. That is to say, converting the source video with the first refresh rate into the target video with the second refresh rate is refreshed through the FPGA chip. rate conversion. In order to save resources, the present invention uses two of the above-mentioned logic chips. Compared with using only one large-capacity logic resource FPGA chip, the cost is lower, because if the algorithm of 8K120Hz ultra-high-definition display is realized by only one FPGA chip, due to the ultra-high-definition algorithm The complexity is very high, the data processing volume is large, and the logic resources it requires are also very high. Therefore, an FPGA chip used to implement 8K120Hz needs to use a large amount of resources and a large number of dedicated differential high-speed transceivers (Serdes). Advanced FPGA chips are very expensive). Secondly, the two FPGAs with medium logic resources used in the present invention have exactly the same internal modules and identical development programs, which can speed up the time spent on project development.
进一步地，本发明可根据实际需求应用，在同硬件、同平台下即可适用于市场上的两种显示模组(8K60Hz显示模组、8K120Hz显示模组),如图3所示，增加布局市场灵活性，进一步节省采购成本。8K60Hz显示模组为现有技术，在此不再赘述。Further, the present invention can be applied according to actual needs, and can be applied to two display modules on the market (8K60Hz display module, 8K120Hz display module) with the same hardware and the same platform, as shown in Figure 3, with the added layout Market flexibility further saves procurement costs. The 8K60Hz display module is an existing technology and will not be described again here.
在本实施例中，第二刷新率为120Hz,第二刷新率高于第一刷新率；由于现有技术只能产生8K60Hz的源视频，而无法产生8K120Hz的源视频，使得成熟量产的后端8K120Hz显示模组无法得到广泛应用，故本申请通过将8K60Hz的源视频转化为8K120Hz视频，使得用户能观看到更加流畅清晰的视频画面。与现有的8K120Hz显示驱动方案(如图1)相对比，具有更真实细腻的显示效果，同时可减少运动拖影、运动抖动的问题，使得运动画面更加流畅清晰。此系统可打破现有的数字电视广播网络无8K120Hz信源的瓶颈，保证8K120Hz用户端的最优显示，并且系统运行可靠性高，生产成本低，便于快速推广。In this embodiment, the second refresh rate is 120Hz, and the second refresh rate is higher than the first refresh rate; because the existing technology can only generate 8K60Hz source video, but cannot generate 8K120Hz source video, it makes the mature mass production End-user 8K120Hz display modules cannot be widely used, so this application converts 8K60Hz source video into 8K120Hz video so that users can watch smoother and clearer video images. Compared with the existing 8K120Hz display driver solution (Figure 1), it has a more realistic and delicate display effect, while reducing the problems of motion smear and motion jitter, making the motion picture smoother and clearer. This system can break the bottleneck of the existing digital TV broadcast network without 8K120Hz source and ensure the optimal display of 8K120Hz client. The system has high operation reliability, low production cost and is easy to promote quickly.
此外，输入接口类型包括VbyOne输入接口、HDMI2.1/DP1.4输入接口，两种接口输入的源视频都需要采用两个逻辑芯片，但是源视频与逻辑芯片具体的连接方法不同，通过两个所述逻辑芯片进行刷新率转换，都可以得到第二刷新率的目标视频。因此，本发明应用 更广泛，可应用于没有SoC的商业显示设备(包括但不限于商业广告显示屏)，也可以直接使用电脑(或机顶盒)输出HDMI2.1或者DP信号，接入本发明所示的系统，如图3所示，即可驱动点亮该商业显示设备。In addition, the input interface types include VbyOne input interface and HDMI2.1/DP1.4 input interface. The source video input by both interfaces requires two logic chips. However, the specific connection methods of the source video and logic chip are different. Through two Even when the logic chip performs refresh rate conversion, the target video of the second refresh rate can be obtained. Therefore, the present invention has a wider application and can be applied to commercial display devices without SoC (including but not limited to commercial advertising display screens). It can also directly use a computer (or set-top box) to output HDMI2.1 or DP signals and access the present invention. The system shown in Figure 3 can drive and light up the commercial display device.
在一种实现方式中，两个所述逻辑芯片为第一逻辑芯片和第二逻辑芯片；每个所述逻辑芯片包括双倍速率同步动态随机存储器和运动补偿模块；步骤S200包括如下步骤：In one implementation, the two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module; step S200 includes the following steps:
S201、将所述源视频输入到所述第一逻辑芯片，通过所述第一通信协议进行解码，得到第二解码视频；S201. Input the source video to the first logic chip, decode it through the first communication protocol, and obtain a second decoded video;
S202、基于所述第一逻辑芯片、所述第二逻辑芯片和所述第二解码视频，得到第二刷新率的目标视频。S202. Based on the first logic chip, the second logic chip and the second decoded video, obtain a target video with a second refresh rate.
具体地，在步骤S201中，第一逻辑芯片和第二逻辑芯片均为FPGA芯片，其内部构造一样，第一刷新率为60Hz，第二刷新率为120Hz，视频源来自机顶盒/电脑，通过HDMI2.1/DP1.4接口输入，HDMI2.1/DP1.4协议能传输32 lane，因一路HDMI2.1/DP1.4接口即可满足8K60Hz的传输带宽最低需求，所以全部(整图)8K60Hz画面皆输入到两颗FPGA中的任意一颗FPGA芯片即可(比如图3中举例说明只传输到FPGA#1)，通过任意一颗FPGA芯片中的HDMI2.1/DP1.4协议进行解码，得到第二解码视频，最后根据第二解码视频、第一逻辑芯片和第二逻辑芯片就可以得到第二刷新率的目标视频。Specifically, in step S201, the first logic chip and the second logic chip are both FPGA chips with the same internal structure. The first refresh rate is 60Hz and the second refresh rate is 120Hz. The video source comes from a set-top box/computer through HDMI2. .1/DP1.4 interface input, HDMI2.1/DP1.4 protocol can transmit 32 lanes, because one HDMI2.1/DP1.4 interface can meet the minimum transmission bandwidth requirement of 8K60Hz, so all (whole picture) 8K60Hz images All can be input to any one of the two FPGA chips (for example, the example in Figure 3 shows that it is only transmitted to FPGA#1), and decoded through the HDMI2.1/DP1.4 protocol in any one FPGA chip, we get The second decoded video, finally, the target video with the second refresh rate can be obtained based on the second decoded video, the first logic chip and the second logic chip.
步骤S202包括如下步骤：Step S202 includes the following steps:
S2021、根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频；S2021. Obtain the first region video according to the second decoded video and the first logic chip;
S2022、根据所述第二解码视频和所述第二逻辑芯片，得到第二区域视频；S2022. Obtain the second region video according to the second decoded video and the second logic chip;
S2023、将第一区域视频和第二区域视频进行合并，得到第二刷新率的目标视频。S2023. Merge the first area video and the second area video to obtain the target video with the second refresh rate.
具体地，根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频为将所述第二解码视频通过所述第一逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第二视频；通过所述第一逻辑芯片中的所述运动补偿模块将所述第二视频进行运动补偿，得到第二运动补偿视频；将所述第二运动补偿视频进行协议编码，得到第一区域视频。实际中，所述第一逻辑芯片和所述第二逻辑芯片的内部模块构造一样，此时通过任一逻辑芯片中的HDMI2.1/DP1.4协议解码得到第二解码视频后续经过的模块是相同的，只是分别位于第一逻辑芯片和第二逻辑芯片。第二解码视频通过第一逻辑芯片中的所述运动补偿模块将所述第二视频进行运动补偿，得到第二运动补偿视频，然后进行协议编码，得到第一区域视频；根据所述第二解码视频和所述第二逻辑芯片，得到第二区域视频具体为将所述第二解码视频通过所述第二逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第三视频；通过所述第二逻辑芯片中的所述运 动补偿模块将所述第三视频进行运动补偿，得到第三运动补偿视频；将所述第三运动补偿视频进行协议编码，得到第二区域视频。基于同样的道理，第二解码视频通过第二逻辑芯片中的所述运动补偿模块将所述第三视频进行运动补偿，得到第三运动补偿视频，然后进行通过VbyOne协议进行协议编码，得到第二区域视频。第一区域视频和第二区域视频可以为一个屏幕区域的上下半屏视频，也可以为一个屏幕区域的左右半屏视频。例如：FPGA#1将HDMI2.1/DP1.4协议解码出的8K60Hz画面的右半屏画面，通过图像互传信号，传输给FPGA#2。之后两颗FPGA后续的图像数据处理部分，两块FPGA芯片的处理模式完全相同。在本实施例中，第一区域视频和第二区域视频分别为一个屏幕区域的左右半屏视频。最后将第一区域视频和第二区域视频进行合并，得到第二刷新率的目标视频，目标视频为一个完整的屏幕视频。运动补偿模块采用动态映像系统，在传统的两帧图像之间加插一帧运动补偿帧，将刷新率提高，这样运动画面更加清晰流畅，优于常态响应效果。Specifically, according to the second decoded video and the first logic chip, obtaining the first area video is to pass the second decoded video through the double-rate synchronous dynamic random access memory in the first logic chip. Convert the refresh rate to obtain a second video with a second refresh rate; perform motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensated video; convert the second The motion compensation video is protocol encoded to obtain the first region video. In practice, the internal module structures of the first logic chip and the second logic chip are the same. At this time, the second decoded video is obtained by decoding the HDMI2.1/DP1.4 protocol in either logic chip. The subsequent module is: They are the same, but are located on the first logic chip and the second logic chip respectively. The second decoded video performs motion compensation on the second video through the motion compensation module in the first logic chip to obtain the second motion compensated video, and then performs protocol encoding to obtain the first area video; according to the second decoding video and the second logic chip to obtain the second area video. Specifically, the second decoded video is refresh rate converted through the double rate synchronous dynamic random access memory in the second logic chip to obtain the second refresh. rate the third video; perform motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensated video; perform protocol encoding on the third motion compensated video to obtain Second area video. Based on the same principle, the second decoded video performs motion compensation on the third video through the motion compensation module in the second logic chip to obtain the third motion compensated video, and then performs protocol encoding through the VbyOne protocol to obtain the second Regional video. The first area video and the second area video may be upper and lower half-screen videos of a screen area, or may be left and right half-screen videos of a screen area. For example: FPGA#1 transmits the right half-screen image of the 8K60Hz image decoded by the HDMI2.1/DP1.4 protocol to FPGA#2 through image mutual transmission signals. In the subsequent image data processing part of the two FPGAs, the processing modes of the two FPGA chips are exactly the same. In this embodiment, the first area video and the second area video are respectively left and right half-screen videos of a screen area. Finally, the first area video and the second area video are merged to obtain a target video with a second refresh rate, and the target video is a complete screen video. The motion compensation module uses a dynamic imaging system to insert a motion compensation frame between the traditional two frames of images to increase the refresh rate, so that the motion picture is clearer and smoother, and is better than the normal response effect.
在另外一种实现方式中，由于2个逻辑芯片的内部结构完全相同。所述基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频包括如下步骤：将所述源视频分别输入到每个所述逻辑芯片，通过所述第二通信协议进行解码，得到两个第三解码视频；将每个所述第三解码视频均通过所述双倍速率同步动态随机存储器进行刷新率转换，得到两个第二刷新率的第四视频；通过所述运动补偿模块将每个所述第四视频进行运动补偿，得到两个第四运动补偿视频；将每个第四运动补偿视频进行协议编码，得到两个区域视频；将两个区域视频进行合并，得到第二刷新率的目标视频。In another implementation, the internal structures of the two logic chips are exactly the same. The method of converting the source video to a refresh rate based on two logic chips to obtain a target video with a second refresh rate includes the following steps: inputting the source video to each of the logic chips respectively, and passing the second refresh rate to the source video. The communication protocol is decoded to obtain two third decoded videos; each of the third decoded videos is refresh rate converted through the double rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate; Use the motion compensation module to perform motion compensation on each of the fourth videos to obtain two fourth motion compensated videos; perform protocol encoding on each fourth motion compensated video to obtain two regional videos; combine the two regional videos Merge to obtain the target video with the second refresh rate.
在本实施例中，第一刷新率为60Hz，第二刷新率为120Hz，此时前端8KSoC输出的视频信号源为8K60Hz画面，通过VbyOne协议发送到FPGA的接收端，其中需要32lane差分信号(每lane速率为2.97Gbps)才能满足8K60Hz的传输带宽最低需求(备注：8K60Hz的传输带宽约90Gbps，至少要求32 lane VbyOne信号才能满足传输需求。而VbyOne协议只能传输16lane，本发明故将16lane的8K60Hz的源视频分布输入至每个所述逻辑芯片中，通过VbyOne协议进行解码，得到每个所述逻辑芯片对应的第三解码视频，其中，前16lane传输的是8K60Hz视频的左半屏画面，后16lane传输的是8K60Hz视频的右半屏画面。然后将每个所述第三解码视频均通过所述双倍速率同步动态随机存储器进行刷新率转换，得到每个所述逻辑芯片对应的第四视频；这样第四视频有两个，通过所述运动补偿模块将每个所述第四视频进行运动补偿，得到每个所述逻辑芯片对应的第四运动补偿视频，第四运动补偿视频有两个，接着将每个第四运动补偿视频通过VbyOne协议进行协议编码，得到每个所述逻辑芯片对应的区域视频；实际中，8K120Hz的传输带宽约180Gbps至少要求64lane的VbyOne信号才能满足传输需求)。在本实施例中，两个区域视频分别为左右半屏视频。最 终将两个区域视频进行合并，得到第二刷新率的目标视频。在本实施例中，FPGA#1的作用是对接收端收到的VbyOne信号(16lane)进行协议解码，解码出左半屏画面之后，再将画面的刷新率从60Hz转换到120Hz，最后使用VbyOne协议对该120Hz左半屏画面编码成32 lane VbyOne信号发送到8K120Hz Tcon板端(Tcon Board)，Tcon板驱动并点亮8K120Hz显示模组。相同地，FPGA#2的作用与FPGA#1一样。此外两颗FPGA之间可互传像素时钟同步信号，确保输出到Tcon板的左、右半屏画面时间上完全同步，避免出现画面撕裂问题。In this embodiment, the first refresh rate is 60Hz and the second refresh rate is 120Hz. At this time, the video signal source output by the front-end 8KSoC is an 8K60Hz picture, which is sent to the receiving end of the FPGA through the VbyOne protocol, which requires 32lane differential signals (each lane rate is 2.97Gbps) to meet the minimum requirement of 8K60Hz transmission bandwidth (Note: the transmission bandwidth of 8K60Hz is about 90Gbps, and at least 32 lane VbyOne signals are required to meet the transmission requirements. The VbyOne protocol can only transmit 16lane, so the present invention uses 16lane of 8K60Hz The source video is distributed and input into each of the logic chips, and decoded through the VbyOne protocol to obtain the third decoded video corresponding to each of the logic chips. Among them, the first 16 lanes transmit the left half screen of the 8K60Hz video, and the last 16 lanes transmit the left half screen of the 8K60Hz video. 16lane transmits the right half-screen image of the 8K60Hz video. Then each third decoded video is refresh rate converted through the double-rate synchronous dynamic random access memory to obtain the fourth video corresponding to each of the logic chips. ; In this way, there are two fourth videos. Each fourth video is motion compensated through the motion compensation module to obtain a fourth motion compensated video corresponding to each of the logic chips. There are two fourth motion compensated videos. , and then each fourth motion compensation video is protocol encoded through the VbyOne protocol to obtain the regional video corresponding to each of the logic chips; in practice, the transmission bandwidth of 8K120Hz is about 180Gbps, which requires at least 64lane VbyOne signals to meet the transmission requirements). In this embodiment, the two regional videos are left and right half-screen videos respectively. Finally, the two regional videos are merged to obtain the target video with the second refresh rate. In this embodiment, the function of FPGA#1 is to perform protocol decoding on the VbyOne signal (16lane) received by the receiving end. After decoding the left half of the screen, it then converts the refresh rate of the screen from 60Hz to 120Hz, and finally uses VbyOne The protocol encodes the 120Hz left half screen image into a 32 lane VbyOne signal and sends it to the 8K120Hz Tcon Board. The Tcon Board drives and lights up the 8K120Hz display module. Likewise, FPGA#2 functions the same as FPGA#1. In addition, the two FPGAs can transmit pixel clock synchronization signals to each other to ensure that the left and right half-screen images output to the Tcon board are completely synchronized in time to avoid screen tearing problems.
在另一种实现方式中，当所述第一刷新率等于所述第二刷新率时，相当于源视频的刷新率不变，通过刷新率转换之前和之后的刷新率不变，此时采用一个逻辑芯片即可。在本实施例中，视频源为8K60Hz，当显示模组也为8K60Hz时，1颗FPGA芯片内部的模块与图4之中的FPGA#1部分(或者FPGA#2部分)一致。此时，仅需要1颗FPGA即可实现全部功能，且与8K120Hz架构图(如图4)使用相同的硬件电路、相同FPGA芯片、以及FPGA芯片内部相同的模块。不同点在于只需使用1颗FPGA(如图5中举例以FPGA#1说明)以及FPGA内部的模块预设置不同。In another implementation, when the first refresh rate is equal to the second refresh rate, the refresh rate of the source video remains unchanged, and the refresh rate before and after the refresh rate conversion remains unchanged. In this case, use Just one logic chip. In this embodiment, the video source is 8K60Hz. When the display module is also 8K60Hz, the module inside an FPGA chip is consistent with the FPGA#1 part (or FPGA#2 part) in Figure 4. At this time, only one FPGA is needed to realize all functions, and the same hardware circuit, the same FPGA chip, and the same modules inside the FPGA chip are used as the 8K120Hz architecture diagram (Figure 4). The difference is that only one FPGA is used (FPGA#1 is used as an example in Figure 5) and the module presets inside the FPGA are different.
当所述第一刷新率等于所述第二刷新率时，通过第一通信协议进行解码，得到第一解码视频；将所述第一解码视频通过所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第一视频；通过所述运动补偿模块将所述第一视频进行运动补偿，得到第一运动补偿视频；将所述第一运动补偿视频进行协议编码，得到第二刷新率的目标视频。When the first refresh rate is equal to the second refresh rate, decoding is performed through the first communication protocol to obtain the first decoded video; the first decoded video is refreshed through the double-rate synchronous dynamic random access memory. Convert to obtain the first video with the second refresh rate; perform motion compensation on the first video through the motion compensation module to obtain the first motion compensated video; perform protocol encoding on the first motion compensated video to obtain the second Refresh rate target video.
具体地，第一通信协议为HDMI2.1/DP1.4，此时，视频源来自机顶盒/电脑，通过HDMI2.1/DP1.4接口输入，当第一刷新率等于第二刷新率时，比如输入8K60Hz的源视频，目标视频为8K60Hz，先通过HDMI2.1/DP1.4协议将8K60Hz的源视频进行解码，得到第一解码视频。然后将所述第一解码视频通过所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第一视频；此时为了保持8K60Hz的FPGA芯片内部模块结构和8K120Hz的FPGA芯片内部模块结构相同，故FPGA芯片仍然包括双倍速率同步动态随机存储器，只是不做插值，使得输出和输入的数据速率相同，这样，得到的第一视频和第一解码视频的刷新率相同。然后通过所述运动补偿模块将所述第一视频进行运动补偿，得到第一运动补偿视频；这样，第一运动补偿视频呈现更真实细腻的显示效果，同时可减少运动拖影、运动抖动的问题，使得运动画面更加流畅清晰。最后将所述第一运动补偿视频进行HDMI2.1/DP1.4协议编码，得到第二刷新率的目标视频。Specifically, the first communication protocol is HDMI2.1/DP1.4. At this time, the video source comes from the set-top box/computer and is input through the HDMI2.1/DP1.4 interface. When the first refresh rate is equal to the second refresh rate, such as Input the 8K60Hz source video and the target video is 8K60Hz. First, decode the 8K60Hz source video through the HDMI2.1/DP1.4 protocol to obtain the first decoded video. Then the first decoded video is refresh rate converted through the double rate synchronous dynamic random access memory to obtain the first video with the second refresh rate; at this time, in order to maintain the internal module structure of the 8K60Hz FPGA chip and the internal module structure of the 8K120Hz FPGA chip The module structure is the same, so the FPGA chip still includes double-rate synchronous dynamic random access memory, but no interpolation is performed, so that the output and input data rates are the same. In this way, the refresh rates of the first video and the first decoded video are the same. Then, the first video is motion compensated through the motion compensation module to obtain a first motion compensated video; in this way, the first motion compensated video presents a more realistic and delicate display effect, and at the same time can reduce the problems of motion smear and motion jitter. , making the motion picture smoother and clearer. Finally, the first motion compensation video is encoded with HDMI2.1/DP1.4 protocol to obtain the target video with the second refresh rate.
进一步地，两颗FPGA无约束关系，可任意调换位置，本发明中的FPGA内部模块的实现方式如下：Furthermore, the two FPGAs have no constraint relationship and can change their positions arbitrarily. The implementation of the FPGA internal module in the present invention is as follows:
两颗FPGA的内部模块部分，如图4所示。其中FPGA#1与FPGA#2所处理的数据总量、 实现的功能是相同的(不同点在于FPGA#1处理的是左半屏图像数据，FPGA#2处理的是右半屏图像数据)，因此FPGA#1与FPGA#2内部模块是一致的。The internal module parts of the two FPGAs are shown in Figure 4. The total amount of data processed and the functions implemented by FPGA#1 and FPGA#2 are the same (the difference is that FPGA#1 processes the image data of the left half of the screen, and FPGA#2 processes the image data of the right half of the screen). Therefore, the internal modules of FPGA#1 and FPGA#2 are consistent.
在FPGA#1内部，VbyOne协议解码模块或者HDMI2.1/DP1.4协议解码模块解码输出左半屏的图像数据，将会缓存在异步FiFo之中(该FiFo容量较小，例如8K解析度半行3840个像素存储空间)，然后在FPGA#1与FPGA#2内部的输入端帧同步控制模块的约束下，使得FPGA#1中的左半屏图像数据与FPGA#2中的右半屏图像数据在时间上同步对齐，输出给后端的DDR读写控制模块，同时也输出给后端的双口RAM1模块(双口RAM1的缓存容量约为5行,每行7680个像素，用于运动补偿模块做插值计算)。Inside FPGA#1, the VbyOne protocol decoding module or HDMI2.1/DP1.4 protocol decoding module decodes and outputs the image data of the left half of the screen, which will be cached in asynchronous FiFo (the FiFo has a small capacity, such as 8K resolution half (3840 rows of pixel storage space), and then under the constraints of the input frame synchronization control modules inside FPGA#1 and FPGA#2, the left half-screen image data in FPGA#1 and the right half-screen image in FPGA#2 The data is synchronously aligned in time and output to the back-end DDR read-write control module, and also output to the back-end dual-port RAM1 module (the cache capacity of dual-port RAM1 is about 5 lines, each line has 7680 pixels, and is used for the motion compensation module Do interpolation calculations).
其中输入端帧同步控制模块负责约束两颗FPGA收到的左右半屏图像数据，实现时序如图6所示，图中表示了一帧时间内图像的数字信号时序图，其中一帧有M行，每行有N个像素(即8K画面M＝4320；N＝7680)。此时FPGA#1需要传输给FPGA#2的输入帧同步信号包括：(1)Pixel CLK1：左半屏图像像素时钟，频率约75MHz，该时钟由FPGA#1内部的PLL产生；(2)输入DE1：左半屏图像数据有效信号，该信号由前端VbyOne协议解码模块或者HDMI2.1/DP1.4协议解码模块产生，当该信号高表示此时的像素数据有效。相同地，FPGA#2需要传输给FPGA#1的输入帧同步信号包括Pixel CLK2：右半屏图像像素时钟，频率约75MHz，该时钟由FPGA#2芯片内部的PLL产生；(3)输入DE2：右半屏图像数据有效信号，该信号由前端VbyOne协议解码模块或者HDMI2.1/DP1.4协议解码模块产生，当该信号高表示此时的像素数据有效。经过上述的信号互传，FPGA#1将计算出与FPGA#2内部像素数据的时间差(如图6中举例为FPGA#1(左半屏)的输入像素数据比FPGA#2(右半屏)的输入像素数据快2个时钟周期)。相同地，FPGA#2也会计算出与FPGA#1内部像素数据的时间差(即FPGA#2(右半屏)的输入像素数据比FPGA#1慢2个时钟周期)。之后可在预设的位置触发帧同步(如图6中举例位置为FPGA#2的输入第1行第1个像素数据开始触发帧同步，实际应用当中可依据异步FiFo的容量来选择触发位置)，在触发位置开始将从异步FiFo连续读取出缓存的图像数据。通过以上步骤，即可实现两颗FPGA输入的左右半屏图像数据，在时间上保证每一帧都是同步对齐的，避免出现左右半屏输入图像画面撕裂问题。输入端8K60Hz帧同步，以及输出端8K120Hz帧同步。使用异步FiFo(小容量)作为图像输入端缓存器。The input frame synchronization control module is responsible for constraining the left and right half-screen image data received by the two FPGAs. The implementation timing is shown in Figure 6. The figure shows the digital signal timing diagram of the image within one frame, and one frame has M lines. , each row has N pixels (i.e. 8K picture M=4320; N=7680). At this time, the input frame synchronization signals that FPGA#1 needs to transmit to FPGA#2 include: (1) Pixel CLK1: left half screen image pixel clock, frequency is about 75MHz, this clock is generated by the PLL inside FPGA#1; (2) Input DE1: Left half screen image data valid signal, this signal is generated by the front-end VbyOne protocol decoding module or HDMI2.1/DP1.4 protocol decoding module. When this signal is high, it means that the pixel data at this time is valid. Similarly, the input frame synchronization signal that FPGA#2 needs to transmit to FPGA#1 includes Pixel CLK2: the right half-screen image pixel clock with a frequency of about 75MHz. This clock is generated by the PLL inside the FPGA#2 chip; (3) Input DE2: Right half screen image data valid signal, this signal is generated by the front-end VbyOne protocol decoding module or HDMI2.1/DP1.4 protocol decoding module. When this signal is high, it means that the pixel data at this time is valid. After the above signal exchange, FPGA#1 will calculate the time difference with the internal pixel data of FPGA#2 (as shown in Figure 6, for example, the input pixel data of FPGA#1 (left half screen) is greater than the input pixel data of FPGA#2 (right half screen) input pixel data 2 clock cycles faster). Similarly, FPGA#2 will also calculate the time difference with the internal pixel data of FPGA#1 (that is, the input pixel data of FPGA#2 (right half screen) is 2 clock cycles slower than that of FPGA#1). Afterwards, frame synchronization can be triggered at the preset position (for example, in Figure 6, the position is the 1st pixel data of the input line 1 of FPGA#2 to start triggering frame synchronization. In actual applications, the trigger position can be selected based on the capacity of asynchronous FiFo) , starting from the trigger position, the cached image data will be read continuously from asynchronous FiFo. Through the above steps, the left and right half-screen image data input by two FPGAs can be realized, ensuring that each frame is synchronously aligned in time, and avoiding the problem of screen tearing of the left and right half-screen input images. 8K60Hz frame synchronization at the input end, and 8K120Hz frame synchronization at the output end. Use asynchronous FiFo (small capacity) as the image input buffer.
DDR读写控制模块，负责将前一模块(异步FiFo)送出的图像数据，实时地写入到DDR存储单元中。与此同时，在输出端帧同步控制模块的约束下，从DDR存储单元中连续读取前一帧的图像数据，并送出给双口RAM2模块(双口RAM2的缓存容量约为5行,每行7680个像素，用于运动补偿模块做插值计算)。使用双口RAM(大容量)作为图像输出端缓存 器，便于运动补偿模块的插值计算。The DDR read and write control module is responsible for writing the image data sent by the previous module (asynchronous FiFo) into the DDR storage unit in real time. At the same time, under the constraints of the output frame synchronization control module, the image data of the previous frame is continuously read from the DDR storage unit and sent to the dual-port RAM2 module (the cache capacity of the dual-port RAM2 is about 5 lines, each 7680 pixels per row, used for interpolation calculations by the motion compensation module). Use dual-port RAM (large capacity) as the image output buffer to facilitate the interpolation calculation of the motion compensation module.
输出端帧同步控制模块，其功能是自主产生8K120Hz图像的像素扫描总时序，其中两颗FPGA通过输出帧同步信号联系，保证两颗芯片内部的8K120Hz扫描时序每一帧都是同步对齐的。其中，可预设其中一颗FPGA自主产生8K120Hz像素扫描的DE信号(如图7中的举例为FPGA#1自主产生并输出DE1信号)，而后将此信号传输到另一颗FPGA(如图7中的举例为FPGA#2)，另一颗FPGA芯片将采样到此信号，但是因为采样需要耗时1个时钟周期，所以FPGA#2接收到来自FPGA#1的DE1信号将延时1时钟。The function of the output frame synchronization control module is to independently generate the total pixel scanning timing of the 8K120Hz image. Two FPGAs are connected through the output frame synchronization signal to ensure that each frame of the 8K120Hz scanning timing within the two chips is synchronously aligned. Among them, one of the FPGAs can be preset to independently generate the DE signal of 8K120Hz pixel scanning (the example in Figure 7 is that FPGA#1 independently generates and outputs the DE1 signal), and then transmits this signal to another FPGA (Figure 7 The example in is FPGA#2), another FPGA chip will sample this signal, but because sampling takes 1 clock cycle, FPGA#2 will delay 1 clock when receiving the DE1 signal from FPGA#1.
所以输出端帧同步模块，需要在FPGA#1与FPGA#2之间传输的同步信号只有一个：8K120Hz像素扫描的DE信号。其中，可预设FPGA#1传输到FPGA#2，也可预设FPGA#2传输到FPGA#1(如图7中的举例为FPGA#1传输到FPGA#2)。Therefore, in the output frame synchronization module, there is only one synchronization signal that needs to be transmitted between FPGA#1 and FPGA#2: the DE signal of 8K120Hz pixel scanning. Among them, FPGA#1 can be preset to be transmitted to FPGA#2, or FPGA#2 can be preset to be transmitted to FPGA#1 (for example, in Figure 7, FPGA#1 is transmitted to FPGA#2).
在输出端帧同步模块中，可预设触发帧同步位置(如图7之中的举例，其触发帧同步位置为FPGA#2接收到来自FPGA#1的DE1信号的第1行第1个像素数据位置)，经过帧同步处理之后，FPGA#1与FPGA#2的输出DE将同步对齐，如图7所示，FPGA#1芯片内输出端帧同步模块内部的同步之后的自产生输出DE 1，与FPGA#2芯片内输出端帧同步模块内部的同步之后的自产生输出DE2将同步对齐。In the output frame synchronization module, the trigger frame synchronization position can be preset (for example, in Figure 7, the trigger frame synchronization position is the first pixel in row 1 where FPGA#2 receives the DE1 signal from FPGA#1 data position), after frame synchronization processing, the output DE of FPGA#1 and FPGA#2 will be synchronously aligned, as shown in Figure 7, the self-generated output DE 1 after synchronization within the frame synchronization module of the output end of the FPGA#1 chip , the self-generated output DE2 will be synchronously aligned with the internal synchronization of the output terminal frame synchronization module in the FPGA#2 chip.
在FPGA#1芯片内部的[输出端帧同步模块]之中，同步之后的自产生输出DE1信号将控制着[DDR读写控制模块]，从DDR存储单元读取上一帧的像素图像数据(左半屏)。In the [output frame synchronization module] inside the FPGA#1 chip, the self-generated output DE1 signal after synchronization will control the [DDR read and write control module] to read the pixel image data of the previous frame from the DDR storage unit ( left half of the screen).
相同地，在FPGA#2芯片内部的[输出端帧同步模块]之中，同步之后的自产生输出DE2信号将控制着[DDR读写控制模块]，从DDR存储单元读取上一帧的像素图像数据(右半屏)。Similarly, in the [Output Frame Synchronization Module] inside the FPGA#2 chip, the self-generated output DE2 signal after synchronization will control the [DDR Read and Write Control Module] to read the pixels of the previous frame from the DDR memory unit. Image data (right half of screen).
从DDR存储单元连续读取到前一帧图像数据，将会缓存到双口RAM2之中。运动补偿模块将收到双口RAM1的当前帧(第K帧)图像数据，以及双口RAM2中的前一帧(第K-1帧)图像数据，运动补偿模块将会对这两帧8K60Hz的图像数据进行分析计算，并输出带有运动补偿效果的8K120Hz图像，如图8所示。输出的带有运动补偿的8K120Hz图像具有运动增强效果，可减少画面拖影、抖动问题，使得运动场景更加流畅清晰。The image data of the previous frame is continuously read from the DDR storage unit and will be cached in the dual-port RAM2. The motion compensation module will receive the current frame (Kth frame) image data of the dual-port RAM1 and the previous frame (K-1st frame) image data in the dual-port RAM2. The motion compensation module will process the two frames of 8K60Hz. The image data is analyzed and calculated, and an 8K120Hz image with motion compensation effect is output, as shown in Figure 8. The output 8K120Hz image with motion compensation has a motion enhancement effect, which can reduce image smear and jitter problems, making the motion scene smoother and clearer.
FPGA#1最后将带有运动补偿的8K120Hz图像(左半屏)使用VbyOne协议进行协议编码成32 lane VbyOne信号，发送到后端Tcon板，驱动点亮左半屏幕。FPGA#2最后将带有运动补偿的8K120Hz图像(右半屏)使用VbyOne协议进行协议编码成32 lane VbyOne信号，发送到后端Tcon板，驱动点亮右半屏幕。 FPGA#1 finally encodes the 8K120Hz image with motion compensation (left half of the screen) using the VbyOne protocol into a 32 lane VbyOne signal, sends it to the back-end Tcon board, and drives the left half of the screen to light up. FPGA#2 finally encodes the 8K120Hz image with motion compensation (right half of the screen) using the VbyOne protocol into a 32 lane VbyOne signal, sends it to the back-end Tcon board, and drives the right half of the screen to light up.
得到第二刷新率的目标视频后，就可以执行如图3所示的如下步骤：S300、将所述目标视频输入显示模组，并通过所述显示模组显示。After obtaining the target video with the second refresh rate, the following steps as shown in Figure 3 can be performed: S300, input the target video into the display module and display it through the display module.
在本实施例中，显示模组为Tcon板，将所述目标视频输入到后端Tcon板后，驱动点亮 显示模组。In this embodiment, the display module is a Tcon board. After the target video is input to the back-end Tcon board, the display module is driven to light up.
基于上述实施例，本发明还提供了一种智能终端，其原理框图可以如图9所示。该智能终端包括通过系统总线连接的处理器、存储器、网络接口、显示屏、温度传感器。其中，该智能终端的处理器用于提供计算和控制能力。该智能终端的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作系统和计算机程序。该内存储器为非易失性存储介质中的操作系统和计算机程序的运行提供环境。该智能终端的网络接口用于与外部的终端通过网络连接通信。该计算机程序被处理器执行时以实现一种显示控制方法。该智能终端的显示屏可以是液晶显示屏或者电子墨水显示屏，该智能终端的温度传感器是预先在智能终端内部设置，用于检测内部设备的运行温度。Based on the above embodiments, the present invention also provides an intelligent terminal, the functional block diagram of which can be shown in Figure 9 . The intelligent terminal includes a processor, memory, network interface, display screen, and temperature sensor connected through a system bus. Among them, the processor of the smart terminal is used to provide computing and control capabilities. The memory of the smart terminal includes non-volatile storage media and internal memory. The non-volatile storage medium stores operating systems and computer programs. This internal memory provides an environment for the execution of operating systems and computer programs in non-volatile storage media. The network interface of the smart terminal is used to communicate with external terminals through network connections. The computer program implements a display control method when executed by the processor. The display screen of the smart terminal can be a liquid crystal display or an electronic ink display. The temperature sensor of the smart terminal is pre-set inside the smart terminal for detecting the operating temperature of the internal device.
本领域技术人员可以理解，图9中的原理图，仅仅是与本发明方案相关的部分结构的框图，并不构成对本发明方案所应用于其上的智能终端的限定，具体的智能终端可以包括比图中所示更多或更少的部件，或者组合某些部件，或者具有不同的部件布置。Those skilled in the art can understand that the schematic diagram in Figure 9 is only a block diagram of a partial structure related to the solution of the present invention, and does not constitute a limitation on the smart terminal to which the solution of the present invention is applied. Specific smart terminals may include There may be more or fewer parts than shown, or certain parts may be combined, or may have a different arrangement of parts.
在一个实施例中，提供了一种智能终端，包括有存储器，以及一个或者一个以上的程序，其中一个或者一个以上程序存储于存储器中，且经配置以由一个或者一个以上处理器执行所述一个或者一个以上程序包含用于进行以下操作的指令：In one embodiment, a smart terminal is provided, including a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors. One or more programs contain instructions for:
获取第一刷新率的源视频；Get the source video with the first refresh rate;
将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于或者等于第二刷新率；Perform refresh rate conversion on the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;
将所述目标视频输入显示模组，并通过所述显示模组显示。The target video is input into the display module and displayed through the display module.
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本发明所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage. In the media, when executed, the computer program may include the processes of the above method embodiments. Any reference to memory, storage, database or other media used in the various embodiments provided by the present invention may include non-volatile and/or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
综上所述，本发明公开了一种显示控制方法、显示控制装置、智能终端及存储介质， 所述方法包括：获取第一刷新率的源视频；将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于或者等于第二刷新率；将所述目标视频输入显示模组，并通过所述显示模组显示。本发明可以将低刷新率的源视频转化为更高刷新率的视频，使得用户能观看到更加流畅清晰的视频画面。To sum up, the present invention discloses a display control method, a display control device, an intelligent terminal and a storage medium. The method includes: obtaining a source video with a first refresh rate; performing refresh rate conversion on the source video to obtain The target video at the second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; the target video is input into the display module and displayed by the display module. The invention can convert a source video with a low refresh rate into a video with a higher refresh rate, so that users can watch smoother and clearer video images.
详细效果描述为：The detailed effect description is:
本发明提出了一种8K120Hz显示控制系统及显示装置，支持将8K60Hz输入信源刷新率转换到120Hz输出并驱动显示模组(包括但不限于LCD、LED 8K120Hz显示大屏)，与现有的8K120Hz显示驱动方案(如图1)相对比，具有更真实细腻的显示效果，同时可减少运动拖影、运动抖动的问题，使得运动画面更加流畅清晰。此系统可打破现有的数字电视广播网络无8K120Hz信源的瓶颈，保证8K120Hz用户端的最优显示，并且系统运行可靠性高，生产成本低，便于快速推广。The present invention proposes an 8K120Hz display control system and display device, which supports converting the 8K60Hz input source refresh rate to 120Hz output and drives the display module (including but not limited to LCD, LED 8K120Hz display large screen), which is consistent with the existing 8K120Hz Compared with the display driver solution (as shown in Figure 1), it has a more realistic and delicate display effect. It can also reduce the problems of motion smear and motion jitter, making the motion picture smoother and clearer. This system can break the bottleneck of the existing digital TV broadcast network without 8K120Hz source and ensure the optimal display of 8K120Hz client. The system has high operation reliability, low production cost and is easy to promote quickly.
本发明采用2颗中等逻辑资源的FPGA芯片即可实现全部功能，相对于只使用1颗大容量逻辑资源FPGA芯片成本更低。(原因：8K120Hz超高清显示的算法若只通过一颗FPGA芯片实现，由于超高清算法的复杂度很高，数据处理量很大，其所需要的逻辑资源也是非常高的，因此实现8K120Hz所采用的一颗FPGA芯片需要选用资源量大、专用差分高速收发器(Serdes)较多的高级FPGA芯片，其成本是非常昂贵的)。其次，本发明使用的两颗中等逻辑资源的FPGA，内部模块完全相同，开发程序也完全相同，可加快工程开发所耗时间。The present invention can realize all functions by using two FPGA chips with medium logic resources, and the cost is lower than using only one FPGA chip with large-capacity logic resources. (Reason: If the algorithm of 8K120Hz ultra-high-definition display is implemented only through one FPGA chip, due to the high complexity of the ultra-high-definition algorithm and the large amount of data processing, the logic resources required are also very high, so the implementation of 8K120Hz uses An FPGA chip requires an advanced FPGA chip with large resources and many dedicated differential high-speed transceivers (Serdes), which is very expensive). Secondly, the two FPGAs with medium logic resources used in the present invention have exactly the same internal modules and identical development programs, which can speed up the time spent on project development.
本发明可根据实际需求应用，在同硬件、同平台下即可适用于市场上的两种显示模组(8K60Hz显示模组、8K120Hz显示模组)增加布局市场灵活性，进一步节省采购成本。The present invention can be applied according to actual needs, and can be applied to two display modules (8K60Hz display module, 8K120Hz display module) on the market with the same hardware and the same platform, increasing market layout flexibility and further saving procurement costs.
应用更广泛，可应用于没有SoC的商业显示设备(包括但不限于商业广告显示屏)，直接使用电脑(或机顶盒)输出HDMI2.1或者DP信号，接入本发明所示的系统(如图3)，即可驱动点亮该商业显示设备。It has a wider application and can be applied to commercial display equipment without SoC (including but not limited to commercial advertising display screens). It can directly use a computer (or set-top box) to output HDMI2.1 or DP signals and connect to the system shown in the present invention (as shown in the figure). 3), you can drive and light up the commercial display device.
基于上述实施例，本发明公开了一种显示控制方法，应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。Based on the above embodiments, the present invention discloses a display control method. It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or changes can be made according to the above descriptions. All these improvements All modifications and transformations shall fall within the protection scope of the appended claims of the present invention.

Claims (15)

  1. 一种显示控制装置，其特征在于，所述装置包括：A display control device, characterized in that the device includes:
    两个逻辑芯片，用于将第一刷新率的源视频转换成第二刷新率的目标视频，其中，所述第一刷新率小于第二刷新率；Two logic chips for converting the source video at the first refresh rate into the target video at the second refresh rate, wherein the first refresh rate is smaller than the second refresh rate;
    逻辑板，与两个所述逻辑芯片连接，用于将所述目标视频转换成低压差分信号；A logic board, connected to the two logic chips, for converting the target video into a low-voltage differential signal;
    显示模组，与所述逻辑板连接，用于将所述低压差分信号显示。A display module is connected to the logic board and used to display the low-voltage differential signal.
  2. 一种显示控制方法，其特征在于，所述方法包括：A display control method, characterized in that the method includes:
    获取第一刷新率的源视频；Get the source video with the first refresh rate;
    基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于或者等于第二刷新率；Based on two logic chips, the source video is refresh rate converted to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;
    将所述目标视频输入显示模组，并通过所述显示模组显示。The target video is input into the display module and displayed through the display module.
  3. 根据权利要求2所述的显示控制方法，其特征在于，两个所述逻辑芯片为第一逻辑芯片和第二逻辑芯片；每个所述逻辑芯片包括双倍速率同步动态随机存储器和运动补偿模块；所述基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频包括：The display control method according to claim 2, wherein the two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module. ; Based on two logic chips, the source video is refresh rate converted to obtain a target video with a second refresh rate including:
    将所述源视频输入到所述第一逻辑芯片，通过所述第一通信协议进行解码，得到第二解码视频；Input the source video to the first logic chip, decode it through the first communication protocol, and obtain a second decoded video;
    基于所述第一逻辑芯片、所述第二逻辑芯片和所述第二解码视频，得到第二刷新率的目标视频。Based on the first logic chip, the second logic chip and the second decoded video, a target video with a second refresh rate is obtained.
  4. 根据权利要求3所述的显示控制方法，其特征在于，所述基于所述第一逻辑芯片、所述第二逻辑芯片和所述第二解码视频，得到第二刷新率的目标视频包括：The display control method according to claim 3, wherein obtaining the target video of the second refresh rate based on the first logic chip, the second logic chip and the second decoded video includes:
    根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频；According to the second decoded video and the first logic chip, a first area video is obtained;
    根据所述第二解码视频和所述第二逻辑芯片，得到第二区域视频；According to the second decoded video and the second logic chip, a second regional video is obtained;
    将第一区域视频和第二区域视频进行合并，得到第二刷新率的目标视频。Merge the first area video and the second area video to obtain a target video with a second refresh rate.
  5. 根据权利要求4所述的显示控制方法，其特征在于，所述根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频包括：The display control method according to claim 4, wherein obtaining the first area video according to the second decoded video and the first logic chip includes:
    将所述第二解码视频通过所述第一逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第二视频；Perform refresh rate conversion on the second decoded video through the double-rate synchronous dynamic random access memory in the first logic chip to obtain a second video with a second refresh rate;
    通过所述第一逻辑芯片中的所述运动补偿模块将所述第二视频进行运动补偿，得到第二运动补偿视频；The second video is motion compensated through the motion compensation module in the first logic chip to obtain a second motion compensated video;
    将所述第二运动补偿视频进行协议编码，得到第一区域视频。The second motion compensated video is protocol encoded to obtain the first region video.
  6. 根据权利要求4所述的显示控制方法，其特征在于，所述根据所述第二解码视频和所 述第二逻辑芯片，得到第二区域视频包括：The display control method according to claim 4, wherein obtaining the second area video according to the second decoded video and the second logic chip includes:
    将所述第二解码视频通过所述第二逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第三视频；Perform refresh rate conversion on the second decoded video through the double-rate synchronous dynamic random access memory in the second logic chip to obtain a third video with a second refresh rate;
    通过所述第二逻辑芯片中的所述运动补偿模块将所述第三视频进行运动补偿，得到第三运动补偿视频；The third video is motion compensated through the motion compensation module in the second logic chip to obtain a third motion compensated video;
    将所述第三运动补偿视频进行协议编码，得到第二区域视频。The third motion compensated video is protocol encoded to obtain a second region video.
  7. 根据权利要求3所述的显示控制方法，其特征在于，所述基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频包括：The display control method according to claim 3, wherein the step of converting the source video to a refresh rate based on two logic chips to obtain a target video with a second refresh rate includes:
    将所述源视频分别输入到每个所述逻辑芯片，通过所述第二通信协议进行解码，得到两个第三解码视频；Input the source video to each of the logic chips respectively, decode it through the second communication protocol, and obtain two third decoded videos;
    根据两个所述第三解码视频，得到两个区域视频；According to the two third decoded videos, two regional videos are obtained;
    将两个区域视频进行合并，得到第二刷新率的目标视频。Merge the two regional videos to obtain the target video with the second refresh rate.
  8. 根据权利要求7所述的显示控制方法，其特征在于，所述根据两个所述第三解码视频，得到两个区域视频包括：The display control method according to claim 7, wherein obtaining two regional videos based on the two third decoded videos includes:
    将每个所述第三解码视频均通过所述双倍速率同步动态随机存储器进行刷新率转换，得到两个第二刷新率的第四视频；Each third decoded video is refresh rate converted through the double-rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate;
    通过所述运动补偿模块将每个所述第四视频进行运动补偿，得到两个第四运动补偿视频；Perform motion compensation on each of the fourth videos through the motion compensation module to obtain two fourth motion compensated videos;
    将每个第四运动补偿视频进行协议编码，得到两个区域视频。Each fourth motion compensated video is protocol encoded to obtain two regional videos.
  9. 一种智能终端，其特征在于，包括有存储器，以及一个或者一个以上的程序，其中一个或者一个以上程序存储于存储器中，且经配置以由一个或者一个以上处理器执行所述一个或者一个以上程序用于执行显示控制方法，所述方法包括步骤：An intelligent terminal, characterized in that it includes a memory and one or more programs, wherein one or more programs are stored in the memory and configured to execute the one or more programs by one or more processors The program is used to execute a display control method, and the method includes the steps:
    获取第一刷新率的源视频；Get the source video with the first refresh rate;
    基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频；其中，所述第一刷新率小于或者等于第二刷新率；Based on two logic chips, the source video is refresh rate converted to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;
    将所述目标视频输入显示模组，并通过所述显示模组显示。The target video is input into the display module and displayed through the display module.
  10. 根据权利要求9所述的智能终端，其特征在于，两个所述逻辑芯片为第一逻辑芯片和第二逻辑芯片；每个所述逻辑芯片包括双倍速率同步动态随机存储器和运动补偿模块；所述基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频包括：The smart terminal according to claim 9, wherein the two logic chips are a first logic chip and a second logic chip; each logic chip includes a double-rate synchronous dynamic random access memory and a motion compensation module; Based on two logic chips, the source video is refresh rate converted to obtain the target video with the second refresh rate including:
    将所述源视频输入到所述第一逻辑芯片，通过所述第一通信协议进行解码，得到第二解码视频；Input the source video to the first logic chip, decode it through the first communication protocol, and obtain a second decoded video;
    基于所述第一逻辑芯片、所述第二逻辑芯片和所述第二解码视频，得到第二刷新率的目标视频。Based on the first logic chip, the second logic chip and the second decoded video, a target video with a second refresh rate is obtained.
  11. 根据权利要求10所述的智能终端，其特征在于，所述基于所述第一逻辑芯片、所述第二逻辑芯片和所述第二解码视频，得到第二刷新率的目标视频包括：The smart terminal according to claim 10, characterized in that, based on the first logic chip, the second logic chip and the second decoded video, obtaining the target video with the second refresh rate includes:
    根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频；According to the second decoded video and the first logic chip, a first area video is obtained;
    根据所述第二解码视频和所述第二逻辑芯片，得到第二区域视频；According to the second decoded video and the second logic chip, a second regional video is obtained;
    将第一区域视频和第二区域视频进行合并，得到第二刷新率的目标视频。Merge the first area video and the second area video to obtain a target video with a second refresh rate.
  12. 根据权利要求11所述的智能终端，其特征在于，所述根据所述第二解码视频和所述第一逻辑芯片，得到第一区域视频包括：The smart terminal according to claim 11, wherein obtaining the first region video based on the second decoded video and the first logic chip includes:
    将所述第二解码视频通过所述第一逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第二视频；Perform refresh rate conversion on the second decoded video through the double-rate synchronous dynamic random access memory in the first logic chip to obtain a second video with a second refresh rate;
    通过所述第一逻辑芯片中的所述运动补偿模块将所述第二视频进行运动补偿，得到第二运动补偿视频；The second video is motion compensated through the motion compensation module in the first logic chip to obtain a second motion compensated video;
    将所述第二运动补偿视频进行协议编码，得到第一区域视频。The second motion compensated video is protocol encoded to obtain the first region video.
  13. 根据权利要求11所述的智能终端，其特征在于，所述根据所述第二解码视频和所述第二逻辑芯片，得到第二区域视频包括：The smart terminal according to claim 11, wherein obtaining the second area video according to the second decoded video and the second logic chip includes:
    将所述第二解码视频通过所述第二逻辑芯片中的所述双倍速率同步动态随机存储器进行刷新率转换，得到第二刷新率的第三视频；Perform refresh rate conversion on the second decoded video through the double-rate synchronous dynamic random access memory in the second logic chip to obtain a third video with a second refresh rate;
    通过所述第二逻辑芯片中的所述运动补偿模块将所述第三视频进行运动补偿，得到第三运动补偿视频；The third video is motion compensated through the motion compensation module in the second logic chip to obtain a third motion compensated video;
    将所述第三运动补偿视频进行协议编码，得到第二区域视频。The third motion compensated video is protocol encoded to obtain a second region video.
  14. 根据权利要求10所述的智能终端，其特征在于，所述基于两个逻辑芯片，将所述源视频进行刷新率转换，得到第二刷新率的目标视频包括：The smart terminal according to claim 10, wherein the step of converting the source video to a refresh rate based on two logic chips to obtain a target video with a second refresh rate includes:
    将所述源视频分别输入到每个所述逻辑芯片，通过所述第二通信协议进行解码，得到两个第三解码视频；Input the source video to each of the logic chips respectively, decode it through the second communication protocol, and obtain two third decoded videos;
    根据两个所述第三解码视频，得到两个区域视频；According to the two third decoded videos, two regional videos are obtained;
    将两个区域视频进行合并，得到第二刷新率的目标视频。Merge the two regional videos to obtain the target video with the second refresh rate.
  15. 根据权利要求14所述的智能终端，其特征在于，所述根据两个所述第三解码视频，得到两个区域视频包括：The smart terminal according to claim 14, wherein obtaining two regional videos based on the two third decoded videos includes:
    将每个所述第三解码视频均通过所述双倍速率同步动态随机存储器进行刷新率转换，得到两个第二刷新率的第四视频；Each third decoded video is refresh rate converted through the double-rate synchronous dynamic random access memory to obtain two fourth videos with a second refresh rate;
    通过所述运动补偿模块将每个所述第四视频进行运动补偿，得到两个第四运动补偿视频；Perform motion compensation on each of the fourth videos through the motion compensation module to obtain two fourth motion compensated videos;
    将每个第四运动补偿视频进行协议编码，得到两个区域视频。Each fourth motion compensated video is protocol encoded to obtain two regional videos.
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