CN117121087A - Display control method, display control device and intelligent terminal - Google Patents
Display control method, display control device and intelligent terminal Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000006243 chemical reaction Methods 0.000 claims abstract description 32
- 230000001360 synchronised effect Effects 0.000 claims description 23
- 238000004891 communication Methods 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 13
- 238000003860 storage Methods 0.000 description 11
- 230000005540 biological transmission Effects 0.000 description 9
- 238000011161 development Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 5
- 238000004422 calculation algorithm Methods 0.000 description 4
- 238000004590 computer program Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 101100325756 Arabidopsis thaliana BAM5 gene Proteins 0.000 description 3
- 102100031584 Cell division cycle-associated 7-like protein Human genes 0.000 description 3
- 101000777638 Homo sapiens Cell division cycle-associated 7-like protein Proteins 0.000 description 3
- 101150046378 RAM1 gene Proteins 0.000 description 3
- 101100476489 Rattus norvegicus Slc20a2 gene Proteins 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
Abstract
A display control method, a display control device and an intelligent terminal, wherein the method comprises the following steps: acquiring a source video of a first refresh rate (S100); based on the two logic chips, the source video is subjected to refresh rate conversion to obtain a target video with a second refresh rate (S200), wherein the first refresh rate is smaller than or equal to the second refresh rate; the target video is input to the display module and displayed through the display module (S300). The source video with low refresh rate can be converted into video with higher refresh rate based on two logic chips, so that a user can watch smoother and clearer video pictures.
Description
The invention relates to the technical field of large-screen ultra-high definition display, in particular to a display control method, a display control device and an intelligent terminal.
In high-end large-size display market application, the video effect of 8K high resolution plus 120Hz high refresh rate is excellent, and the video effect becomes one of the hot spots of consumer interest. To transmit 8K120Hz video content from a live broadcast or tv channel to a tv display terminal and eventually to a user, each node of the transmission chain needs to have 8K120Hz processing capability (such as recording and editing of a program source, video compression, content distribution, network transmission, set-top box reception, video decompression, high-speed transmission from a set-top box to a tv, video processing and display of a tv), otherwise, the final presentation of the original image content of the 8K120Hz video is not guaranteed. However, the current display industry is unbalanced in the front and back development of an 8K120Hz ecological chain, the highest quality of a front-end program information source is only 8K60Hz, and an 8K120Hz display module at the rear end is mature and produced in quantity, so that a source video with a low refresh rate cannot be displayed in a display module with a high refresh rate, and a user cannot watch a smoother and clearer video picture.
Accordingly, there is a need for improvement and development in the art.
Disclosure of Invention
The invention aims to solve the technical problems that a display control method, a display control device, a refresh rate conversion method and an intelligent terminal are provided for overcoming the defects in the prior art, and the problems that a source video with a low refresh rate cannot be displayed in a display module with a high refresh rate, so that a user cannot watch a smoother and clearer video picture in the prior art are solved.
The technical scheme adopted by the invention for solving the problems is as follows:
in a first aspect, an embodiment of the present invention further provides a display control apparatus, where the apparatus includes: the two logic chips are used for converting the source video with the first refresh rate into the target video with the second refresh rate, wherein the first refresh rate is smaller than the second refresh rate;
the logic board is connected with the two logic chips and is used for converting the target video into a low-voltage differential signal;
and the display module is connected with the logic board and used for displaying the low-voltage differential signals.
In a second aspect, an embodiment of the present invention provides a display control method, where the method includes:
acquiring a source video with a first refresh rate;
Based on the two logic chips, carrying out refresh rate conversion on the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;
and inputting the target video into a display module and displaying the target video through the display module.
In one implementation, the two logic chips are a first logic chip and a second logic chip; each logic chip comprises a double-rate synchronous dynamic random access memory and a motion compensation module; the step of converting the refresh rate of the source video based on the two logic chips to obtain a target video with a second refresh rate comprises the following steps:
inputting the source video to the first logic chip, and decoding the source video through the first communication protocol to obtain a second decoded video;
and obtaining a target video with a second refresh rate based on the first logic chip, the second logic chip and the second decoded video.
In one implementation, the obtaining the target video at the second refresh rate based on the first logic chip, the second logic chip, and the second decoded video includes:
obtaining a first region video according to the second decoded video and the first logic chip;
Obtaining a second region video according to the second decoded video and the second logic chip;
and combining the first area video and the second area video to obtain a target video with a second refresh rate.
In one implementation, the obtaining the first region video according to the second decoded video and the first logic chip includes:
the second decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory in the first logic chip, so that a second video with a second refresh rate is obtained;
performing motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensation video;
and carrying out protocol coding on the second motion compensation video to obtain a first region video.
In one implementation, the obtaining the second region video according to the second decoded video and the second logic chip includes:
the second decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory in the second logic chip, and a third video with a second refresh rate is obtained;
performing motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensation video;
And carrying out protocol coding on the third motion compensation video to obtain a second region video.
In one implementation manner, the performing refresh rate conversion on the source video based on the two logic chips to obtain a target video with a second refresh rate includes:
respectively inputting the source videos to each logic chip, and decoding the source videos through the second communication protocol to obtain two third decoded videos;
obtaining two region videos according to the two third decoded videos;
and merging the two region videos to obtain the target video with the second refresh rate.
In one implementation, the obtaining two area videos according to the two third decoded videos includes:
carrying out refresh rate conversion on each third decoded video through the double-rate synchronous dynamic random access memory to obtain a fourth video with two second refresh rates;
performing motion compensation on each fourth video through the motion compensation module to obtain two fourth motion compensation videos;
and carrying out protocol coding on each fourth motion compensation video to obtain two region videos.
In a third aspect, an embodiment of the present invention further provides an intelligent terminal, including a memory, and one or more programs, where the one or more programs are stored in the memory, and configured to be executed by the one or more processors, where the one or more programs include a display control method according to any one of the foregoing embodiments.
In a fourth aspect, embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when executed by a processor of an electronic device, enables the electronic device to perform the display control method as set forth in any one of the above.
The invention has the beneficial effects that: the embodiment of the invention firstly acquires a source video with a first refresh rate; then, based on the two logic chips, the source video is subjected to refresh rate conversion to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; finally, inputting the target video into a display module and displaying the target video through the display module; therefore, the invention can convert the source video with low refresh rate into the video with higher refresh rate based on two logic chips, so that the user can watch smoother and clearer video pictures.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
Fig. 1 is a schematic block diagram of an 8K120Hz display driving scheme provided in the prior art.
Fig. 2 is a schematic block diagram of a display control apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic flow chart of a display control method according to an embodiment of the present invention.
Fig. 4 is a schematic block diagram of modules inside two FPGAs according to an 8K120Hz display driving scheme according to an embodiment of the present invention.
Fig. 5 is a schematic block diagram of an 8K60Hz display driving scheme (same hardware and same platform as the 8K120Hz driving scheme) according to an embodiment of the present invention.
Fig. 6 is a timing chart of 8K60Hz frame synchronization signals at two FPGA input terminals according to an embodiment of the present invention.
Fig. 7 is a timing chart of 8K120Hz frame synchronization signals at two FPGA output terminals according to an embodiment of the present invention.
Fig. 8 is a diagram showing the image effects before and after a motion compensation module according to an embodiment of the present invention.
Fig. 9 is a schematic block diagram of an internal structure of an intelligent terminal according to an embodiment of the present invention.
The invention discloses a display control method, a display control device, an intelligent terminal and a storage medium, and in order to make the purposes, technical schemes and effects of the invention clearer and more definite, the invention is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
With the development of technologies such as large screen display, 8K ultra-high definition, 120Hz high refresh rate and the like in the prior art, the devices included in the above technologies (invention points) have bottlenecks and defects: (1) the refresh frame rate of the output signal is only 8K60Hz at maximum. (2) The basic functions can be realized by using at least 4 FPGAs, the data of the FPGAs are more, the complexity of system design is increased, and the running reliability is lower as the number of the FPGAs is larger. The conventional 201610695970.7 (title of the invention: display control device, display control method and display device) is known. The technology (invention point) comprises equipment, at least 4 FPGA chips (comprising 2 data generating chips and 2 data processing chips) are used as a basic framework, left and right two screens of input data are supported, left and right, upper and lower four screens of input data are also supported for decoding and processing, and finally a driving TCON (traffic control) lighting screen is sent out, but the technology only supports 8K60Hz.
Most of schemes of 8K120Hz complete machines (televisions) which are produced in mass on the market have the defects that: 1. 4K magnification to 8K resolution is accomplished by adding an image scaling IC (scaler IC), and the magnified image is lossy and loses part of detail image quality. 2. Image scaling ICs (scaler ICs) are very expensive to purchase because of their complex development technology, low throughput, and technology mastering in a few developers. And the technology does not support 8K60Hz source input. As shown in fig. 1, the scheme of the whole machine (television) with the volume of most 8K120Hz in the existing market is that the input information source only supports 4K resolution (3840 x 2160), and 4K amplification to 8K is completed by adding an image scaling IC (scaler IC), and finally the screen is lightened. Although the basic video effect can be satisfied, this scheme has a disadvantage in that the image enlarging process is lossy and the image quality effect is lost.
In order to solve the problems in the prior art, the present embodiment provides a display control method, which can convert a source video with a low refresh rate into a video with a higher refresh rate, so that a user can watch a smoother and clearer video picture. In the implementation, firstly, acquiring a source video with a first refresh rate; then, the source video is subjected to refresh rate conversion to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; and finally, inputting the target video into a display module and displaying the target video through the display module.
Exemplary apparatus
The present embodiment provides a display control apparatus including:
the two logic chips are used for converting the source video with the first refresh rate into the target video with the second refresh rate, wherein the first refresh rate is smaller than the second refresh rate;
the logic board is connected with the two logic chips and is used for converting the target video into a low-voltage differential signal;
and the display module is connected with the logic board and used for displaying the low-voltage differential signals.
Specifically, the source video signal in the present invention as shown in fig. 2 may be a VbyOne signal from a commercial display device (including but not limited to a commercial display screen) of the SoC, or may be an HDMI2.1 or DP signal from a computer (or set-top box). The first refresh rate of the source video is lower, the source video can be converted into a target video with a higher refresh rate through two logic chips, then the target video output by the two logic chips (Tcon boards) is converted into a Low Voltage Differential Signaling (LVDS) through a logic board, and finally the low voltage differential signaling is displayed through a display module connected with the logic board, namely the display module is driven to be lightened through the logic board.
Exemplary method
The embodiment provides a display control method which can be applied to an intelligent terminal with large-screen ultra-high definition display. As shown in fig. 3, the method includes:
step S100, acquiring a source video with a first refresh rate;
specifically, the first refresh rate is 60Hz or less, the resolution of the source video may be 4K or 8K, and in this embodiment, the resolution of the source video is 8K, and the refresh rate is 60Hz. Firstly, 8K60Hz source video is acquired, and preparation is made for the subsequent refresh rate conversion.
After the source video is obtained, the following steps may be performed as shown in fig. 3: s200, based on two logic chips, carrying out refresh rate conversion on the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than the second refresh rate;
specifically, in the prior art, the conversion of the refresh rate is completed through 4 logic chips, and more resources are required to be consumed, but only two logic chips are required to be adopted, so that half of resources can be saved. In addition, there is a technology of converting 60Hz into 120Hz in the prior art, but because of the resolution below 2K, the refresh rate conversion cannot be performed on the video with higher resolution such as 4K or 8K, which reduces the resolution and results in low video quality. The logic chip may be an ASIC chip, an FPGA chip, or the like, and in this embodiment, the logic chip is an FPGA chip, that is, the conversion of the source video with the first refresh rate into the target video with the second refresh rate is completed through the FPGA chip. In order to save resources, the invention adopts 2 logic chips, and compared with the method which only uses 1 high-capacity logic resource FPGA chip, the cost is lower, because if the algorithm of 8K120Hz ultra-high definition display is realized by only one FPGA chip, the complexity of the ultra-high definition algorithm is very high, the data processing capacity is very high, and the required logic resource is very high, so that the realization of one FPGA chip adopted by 8K120Hz requires to select an advanced FPGA chip with large resource quantity and more special differential high-speed transceivers (Serdes), and the cost is very expensive. And secondly, the two FPGAs with medium logic resources are completely identical in internal modules and development programs, so that the time consumed by engineering development can be shortened.
Furthermore, the application can be applied according to actual demands, and can be applied to two display modules (8K 60Hz display module and 8K120Hz display module) on the market under the same hardware and the same platform, as shown in FIG. 3, thereby increasing the flexibility of layout market and further saving purchasing cost. The 8K60Hz display module is the prior art and will not be described in detail herein.
In this embodiment, the second refresh rate is 120Hz, which is higher than the first refresh rate; because the prior art can only generate 8K60Hz source video, but cannot generate 8K120Hz source video, the mature mass-produced rear-end 8K120Hz display module cannot be widely applied, and the application enables a user to watch smoother and clearer video pictures by converting the 8K60Hz source video into the 8K120Hz video. Compared with the existing 8K120Hz display driving scheme (as shown in figure 1), the display device has a more real and fine display effect, and meanwhile, the problems of motion smear and motion shake can be reduced, so that a moving picture is smoother and clearer. The system can break the bottleneck that the existing digital television broadcasting network has no 8K120Hz information source, ensures the optimal display of the 8K120Hz user terminal, has high system operation reliability and low production cost, and is convenient for quick popularization.
In addition, the input interface types comprise a Vbyone input interface and an HDMI2.1/DP1.4 input interface, two logic chips are needed to be adopted for source videos input by the two interfaces, but the specific connection methods of the source videos and the logic chips are different, and the target videos with the second refresh rate can be obtained by carrying out refresh rate conversion through the two logic chips. Therefore, the invention has wider application, can be applied to commercial display equipment without SoC (including but not limited to commercial display screen), can also directly use computer (or set top box) to output HDMI2.1 or DP signal, and is connected to the system shown in the invention, as shown in figure 3, the commercial display equipment can be driven to be lightened.
In one implementation, the two logic chips are a first logic chip and a second logic chip; each logic chip comprises a double-rate synchronous dynamic random access memory and a motion compensation module; step S200 includes the steps of:
s201, inputting the source video to the first logic chip, and decoding the source video through the first communication protocol to obtain a second decoded video;
s202, obtaining a target video with a second refresh rate based on the first logic chip, the second logic chip and the second decoded video.
Specifically, in step S201, the first logic chip and the second logic chip are FPGA chips, the internal structures of the first logic chip and the second logic chip are the same, the first refresh rate is 60Hz, the second refresh rate is 120Hz, the video source is input from the set top box/computer through the HDMI2.1/DP1.4 interface, the HDMI2.1/DP1.4 protocol can transmit 32 lane, and since one path of HDMI2.1/DP1.4 interface can meet the minimum requirement of transmission bandwidth of 8K60Hz, all (whole diagram) 8K60Hz pictures can be input to any one FPGA chip of the two FPGAs (for example, only to fpga#1 in fig. 3), decoding is performed through the HDMI2.1/DP1.4 protocol in any one FPGA chip, so as to obtain the second decoded video, and finally, the first logic chip and the second logic chip can obtain the target video of the second refresh rate according to the second decoded video.
Step S202 includes the steps of:
s2021, obtaining a first area video according to the second decoded video and the first logic chip;
s2022, obtaining a second region video according to the second decoded video and the second logic chip;
and S2023, merging the first area video and the second area video to obtain a target video with a second refresh rate.
Specifically, according to the second decoded video and the first logic chip, obtaining a first region video, namely performing refresh rate conversion on the second decoded video through the double-rate synchronous dynamic random access memory in the first logic chip, and obtaining a second video with a second refresh rate; performing motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensation video; and carrying out protocol coding on the second motion compensation video to obtain a first region video. In practice, the internal modules of the first logic chip and the second logic chip are identical in structure, and at this time, the modules which are decoded by the HDMI2.1/DP1.4 protocol in any logic chip to obtain the second decoded video and subsequently pass through are identical, but are respectively located in the first logic chip and the second logic chip. The second decoded video carries out motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensation video, and then carries out protocol coding to obtain a first region video; according to the second decoded video and the second logic chip, a second region video is obtained, specifically, the second decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory in the second logic chip, and a third video with a second refresh rate is obtained; performing motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensation video; and carrying out protocol coding on the third motion compensation video to obtain a second region video. Based on the same principle, the second decoded video performs motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensation video, and then performs protocol coding through a Vbyone protocol to obtain a second region video. The first area video and the second area video may be upper and lower half-screen videos of one screen area, or may be left and right half-screen videos of one screen area. For example: the FPGA #1 transmits the right half screen picture of the 8K60Hz picture decoded by the HDMI2.1/DP1.4 protocol to the FPGA #2 through the image mutual transmission signal. And then the subsequent image data processing parts of the two FPGAs have the same processing mode of the two FPGA chips. In this embodiment, the first area video and the second area video are left and right half-screen videos of one screen area, respectively. And finally, merging the first area video and the second area video to obtain a target video with a second refresh rate, wherein the target video is a complete screen video. The motion compensation module adopts a dynamic mapping system, and a frame of motion compensation frame is inserted between two traditional frames of images, so that the refresh rate is improved, and the moving picture is clearer and smoother and better than the normal response effect.
In another implementation, the internal structure of the 2 logic chips is identical. The step of converting the refresh rate of the source video based on the two logic chips to obtain a target video with a second refresh rate comprises the following steps: respectively inputting the source videos to each logic chip, and decoding the source videos through the second communication protocol to obtain two third decoded videos; carrying out refresh rate conversion on each third decoded video through the double-rate synchronous dynamic random access memory to obtain a fourth video with two second refresh rates; performing motion compensation on each fourth video through the motion compensation module to obtain two fourth motion compensation videos; carrying out protocol coding on each fourth motion compensation video to obtain two region videos; and merging the two region videos to obtain the target video with the second refresh rate.
In this embodiment, the first refresh rate is 60Hz, the second refresh rate is 120Hz, at this time, the video signal source output by the front end 8KSoC is an 8K60Hz picture, and the video signal source is sent to the receiving end of the FPGA through the VbyOne protocol, where a 32-lane differential signal (each lane rate is 2.97 Gbps) is required to meet the minimum transmission bandwidth requirement of the 8K60Hz (note: the transmission bandwidth of the 8K60Hz is about 90Gbps, at least the 32-lane VbyOne signal is required to meet the transmission requirement), the VbyOne protocol can only transmit 16 lanes, and the invention inputs the 8K60Hz source video distribution of the 16 lanes into each of the logic chips, decodes the 8K60Hz source video through the VbyOne protocol, and obtains a third decoded video corresponding to each of the logic chips, where the first 16 lanes transmit a left half screen of the 8K60Hz video, and the second 16 lanes transmit a right half screen of the 8K60Hz video, then each of the third decoded video is converted through the random access memory, and compensates the fourth video corresponding to the fourth video motion compensation module, and the fourth video compensation is performed to obtain a motion compensation video corresponding to the fourth video compensation bandwidth requirement of the fourth video corresponding to the fourth video chip, and the fourth video compensation is required to be at least 180 Hz, and the fourth video compensation is obtained. In this embodiment, the two area videos are left and right half-screen videos, respectively. And finally, combining the two region videos to obtain the target video with the second refresh rate. In this embodiment, the fpga#1 performs protocol decoding on the VbyOne signal (16 lane) from the receiving end, after decoding the left half-screen picture, the refresh rate of the picture is converted from 60Hz to 120Hz, and finally the VbyOne signal is encoded into a 32lane VbyOne signal by using the VbyOne protocol, and the 32lane VbyOne signal is sent to the 8K120Hz Tcon Board end (Tcon Board), where the Tcon Board drives and lights the 8K120Hz display module. Similarly, fpga#2 functions as fpga#1. In addition, the two FPGAs can mutually transmit pixel clock synchronous signals, so that the left half screen picture and the right half screen picture output to the Tcon plate are ensured to be completely synchronous in time, and the problem of picture tearing is avoided.
In another implementation, when the first refresh rate is equal to the second refresh rate, the refresh rate corresponding to the source video is unchanged, and the refresh rate before and after the refresh rate conversion is unchanged, and then a logic chip is adopted. In this embodiment, the video source is 8K60Hz, and when the display module is also 8K60Hz, the modules inside 1 FPGA chip are identical to the fpga#1 (or fpga#2) in fig. 4. At this time, only 1 FPGA is needed to realize all functions, and the same hardware circuit, the same FPGA chip, and the same module inside the FPGA chip are used with the 8K120Hz architecture diagram (as in fig. 4). The difference is that only 1 FPGA (as illustrated by FPGA #1 in fig. 5) is used and the modules inside the FPGA are preset differently.
When the first refresh rate is equal to the second refresh rate, decoding is performed through a first communication protocol to obtain a first decoded video; the first decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory, so that a first video with a second refresh rate is obtained; performing motion compensation on the first video through the motion compensation module to obtain a first motion compensation video; and carrying out protocol coding on the first motion compensation video to obtain a target video with a second refresh rate.
Specifically, the first communication protocol is HDMI2.1/DP1.4, at this time, the video source is input from the set top box/computer through the HDMI2.1/DP1.4 interface, and when the first refresh rate is equal to the second refresh rate, for example, 8K60Hz source video is input, and the target video is 8K60Hz, the 8K60Hz source video is decoded through the HDMI2.1/DP1.4 protocol, so as to obtain the first decoded video. Then, the first decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory, so that a first video with a second refresh rate is obtained; in order to keep the internal module structure of the 8K60Hz FPGA chip and the internal module structure of the 8K120Hz FPGA chip the same, the FPGA chip still comprises a double-rate synchronous dynamic random access memory, and only interpolation is not performed, so that the output and input data rates are the same, and the refresh rates of the obtained first video and the first decoded video are the same. Then, the first video is subjected to motion compensation through the motion compensation module to obtain a first motion compensation video; therefore, the first motion compensation video presents a more real and fine display effect, and meanwhile, the problems of motion smear and motion shake can be reduced, so that a moving picture is smoother and clearer. And finally, performing HDMI2.1/DP1.4 protocol coding on the first motion compensation video to obtain a target video with a second refresh rate.
Furthermore, the two FPGAs have no constraint relation and can be randomly changed in position, and the implementation mode of the internal modules of the FPGAs is as follows:
the internal module portions of the two FPGAs are shown in fig. 4. The total data amount and the realized functions processed by the FPGA#1 and the FPGA#2 are the same (the difference is that the FPGA#1 processes left half-screen image data and the FPGA#2 processes right half-screen image data), so that the internal modules of the FPGA#1 and the FPGA#2 are consistent.
In the fpga#1, the VbyOne protocol decoding module or the HDMI2.1/DP1.4 protocol decoding module decodes and outputs the left half-screen image data, which is buffered in the asynchronous FiFo (the FiFo has smaller capacity, for example, 3840 pixel storage spaces in 8K resolution half-line), and then under the constraint of the input-end frame synchronization control module in the fpga#1 and the fpga#2, the left half-screen image data in the fpga#1 and the right half-screen image data in the fpga#2 are aligned synchronously in time, and output to the DDR read-write control module in the back end, and also output to the dual-port RAM1 module in the back end (the buffer capacity of the dual-port RAM1 is about 5 lines, 7680 pixels in each line for the motion compensation module to perform interpolation calculation).
The input end frame synchronization control module is responsible for constraining left and right half-screen image data received by two FPGAs, the implementation time sequence is shown in fig. 6, a digital signal time sequence diagram of an image in one frame time is shown in the diagram, wherein one frame has M rows, and each row has N pixels (namely 8K pictures M=4320; N=7680). The input frame synchronization signal that fpga#1 needs to transmit to fpga#2 at this time includes: (1) Pixel CLK1: a left half-screen image pixel clock, at a frequency of about 75MHz, generated by a PLL inside FPGA # 1; (2) input DE1: a left half-screen image data valid signal, which is generated by the front-end VbyOne protocol decoding module or the HDMI2.1/DP1.4 protocol decoding module, when the signal high indicates that the pixel data at this time is valid. Similarly, the input frame synchronization signal that fpga#2 needs to transmit to fpga#1 includes Pixel CLK2: a right half-screen image pixel clock, at a frequency of about 75MHz, generated by a PLL inside the FPGA #2 chip; (3) input DE2: the right half screen image data valid signal is generated by the front end VbyOne protocol decoding module or the HDMI2.1/DP1.4 protocol decoding module, when the signal high indicates that the pixel data at this time is valid. Through the above signal mutual transmission, the fpga#1 will calculate a time difference from the pixel data inside the fpga#2 (as exemplified by the input pixel data of the fpga#1 (left half panel) in fig. 6, which is faster than the input pixel data of the fpga#2 (right half panel) by 2 clock cycles). Similarly, fpga#2 also calculates the time difference from the pixel data inside fpga#1 (i.e., the input pixel data of fpga#2 (right half-panel) is 2 clock cycles slower than fpga#1). Then, frame synchronization can be triggered at a preset position (for example, in fig. 6, the input line 1 and pixel 1 of the position of fpga#2 start triggering frame synchronization, in practical application, the trigger position can be selected according to the capacity of the asynchronous FiFo), and buffered image data will be continuously read out from the asynchronous FiFo at the trigger position. Through the steps, the left half screen image data and the right half screen image data which are input by two FPGAs can be realized, each frame is ensured to be aligned synchronously in time, and the problem of tearing of left half screen input image pictures and right half screen input image pictures is avoided. Input 8K60Hz frame sync and output 8K120Hz frame sync. An asynchronous FiFo (small capacity) is used as the image input buffer.
The DDR read-write control module is responsible for writing the image data sent by the previous module (asynchronous FiFo) into the DDR storage unit in real time. Meanwhile, under the constraint of the frame synchronization control module at the output end, the image data of the previous frame is continuously read from the DDR storage unit and sent to the dual-port RAM2 module (the buffer capacity of the dual-port RAM2 is about 5 lines, 7680 pixels in each line are used for interpolation calculation by the motion compensation module). And a dual-port RAM (high capacity) is used as an image output end buffer, so that the interpolation calculation of the motion compensation module is facilitated.
The output end frame synchronization control module is used for autonomously generating a pixel scanning total time sequence of an 8K120Hz image, wherein two FPGAs are connected through output frame synchronization signals, and each frame of the 8K120Hz scanning time sequences in the two chips is ensured to be aligned synchronously. Wherein, it can be preset that one FPGA autonomously generates the DE signal of 8K120Hz pixel scan (for example, fpga#1 autonomously generates and outputs the DE1 signal in fig. 7), and then transmits the signal to another FPGA (for example, fpga#2 in fig. 7), and the other FPGA chip samples the signal, but since sampling takes 1 clock cycle, fpga#2 delays 1 clock from receiving the DE1 signal from fpga#1.
So the output end frame synchronization module needs only one synchronization signal transmitted between the FPGA#1 and the FPGA#2: DE signal for 8K120Hz pixel scan. Wherein, the fpga#1 may be preset to be transferred to the fpga#2, or the fpga#2 may be preset to be transferred to the fpga#1 (for example, fpga#1 is transferred to fpga#2 in fig. 7).
In the output end frame synchronization module, a trigger frame synchronization position (for example, the trigger frame synchronization position is the 1 st row 1 st pixel data position of the fpga#2 receiving the DE1 signal from the fpga#1) may be preset (for example, in fig. 7), after the frame synchronization process, the outputs DE of the fpga#1 and the fpga#2 will be aligned synchronously, as shown in fig. 7, the self-generated output DE1 after the synchronization inside the output end frame synchronization module in the fpga#1 chip and the self-generated output DE2 after the synchronization inside the output end frame synchronization module in the fpga#2 chip will be aligned synchronously.
Among the [ output frame synchronization module ] inside the fpga#1 chip, the self-generated output DE1 signal after synchronization will control the [ DDR read/write control module ], reading the pixel image data of the previous frame from the DDR memory cell (left half screen).
Similarly, among the [ output frame synchronization module ] inside the fpga#2 chip, the self-generated output DE2 signal after synchronization will control the [ DDR read/write control module ], reading the pixel image data of the previous frame from the DDR memory cell (right half-panel).
The image data of the previous frame read continuously from the DDR memory cell is buffered in the dual port RAM 2. The motion compensation module will receive the current frame (the K-th frame) image data of the dual-port RAM1 and the previous frame (the K-1 st frame) image data of the dual-port RAM2, and the motion compensation module will analyze and calculate the two frames of 8K60Hz image data and output an 8K120Hz image with motion compensation effect, as shown in fig. 8. The output 8K120Hz image with motion compensation has a motion enhancement effect, can reduce the problems of picture smear and shake, and enables a motion scene to be smoother and clearer.
The FPGA #1 finally performs protocol encoding on the 8K120Hz image (left half screen) with motion compensation using VbyOne protocol into a 32-lane VbyOne signal, and sends the signal to the back-end Tcon board, so as to drive the left half screen to be lightened. The FPGA #2 finally uses VbyOne protocol to perform protocol encoding on the 8K120Hz image (right half screen) with motion compensation into a 32-lane VbyOne signal, and sends the signal to the back-end Tcon board, so as to drive the right half screen to be lightened.
After obtaining the target video at the second refresh rate, the following steps may be performed as shown in fig. 3: s300, inputting the target video into a display module and displaying the target video through the display module.
In this embodiment, the display module is a Tcon board, and after the target video is input to the rear end Tcon board, the display module is driven to be lightened.
Based on the above embodiment, the present invention further provides an intelligent terminal, and a functional block diagram thereof may be shown in fig. 9. The intelligent terminal comprises a processor, a memory, a network interface, a display screen and a temperature sensor which are connected through a system bus. The processor of the intelligent terminal is used for providing computing and control capabilities. The memory of the intelligent terminal comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the intelligent terminal is used for communicating with an external terminal through network connection. The computer program is executed by a processor to implement a display control method. The display screen of the intelligent terminal can be a liquid crystal display screen or an electronic ink display screen, and a temperature sensor of the intelligent terminal is arranged in the intelligent terminal in advance and used for detecting the running temperature of internal equipment.
It will be appreciated by those skilled in the art that the schematic diagram in fig. 9 is merely a block diagram of a portion of the structure related to the present invention and is not limiting of the smart terminal to which the present invention is applied, and that a specific smart terminal may include more or less components than those shown in the drawings, or may combine some components, or have a different arrangement of components.
In one embodiment, a smart terminal is provided that includes a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, the one or more programs comprising instructions for:
acquiring a source video with a first refresh rate;
converting the refresh rate of the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;
and inputting the target video into a display module and displaying the target video through the display module.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
In summary, the invention discloses a display control method, a display control device, an intelligent terminal and a storage medium, wherein the method comprises the following steps: acquiring a source video with a first refresh rate; converting the refresh rate of the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate; and inputting the target video into a display module and displaying the target video through the display module. The invention can convert the source video with low refresh rate into the video with higher refresh rate, so that a user can watch smoother and clearer video pictures.
The detailed effects are described as follows:
the invention provides an 8K120Hz display control system and a display device, which support the conversion of the refresh rate of an 8K60Hz input information source to 120Hz output and drive a display module (including but not limited to LCD and LED 8K120Hz display large screen), compared with the existing 8K120Hz display driving scheme (as shown in figure 1), the display control system and the display device have more real and fine display effects, and can reduce the problems of motion smear and motion shake, so that a moving picture is smoother and clearer. The system can break the bottleneck that the existing digital television broadcasting network has no 8K120Hz information source, ensures the optimal display of the 8K120Hz user terminal, has high system operation reliability and low production cost, and is convenient for quick popularization.
The invention can realize all functions by adopting 2 FPGA chips with medium logic resources, and has lower cost compared with the FPGA chips with 1 large-capacity logic resource. (because the ultra-high definition display algorithm of 8K120Hz is realized by only one FPGA chip, the complexity of the ultra-high definition algorithm is high, the data processing capacity is high, the required logic resources are also high, and therefore, one FPGA chip adopted for realizing 8K120Hz needs to be an advanced FPGA chip with large resource quantity and more special differential high-speed transceivers (Serdes), and the cost is very expensive). And secondly, the two FPGAs with medium logic resources are completely identical in internal modules and development programs, so that the time consumed by engineering development can be shortened.
The invention can be applied according to actual demands, can be suitable for two display modules (8K 60Hz display module and 8K120Hz display module) on the market under the same hardware and the same platform, increases the flexibility of layout market, and further saves purchasing cost.
The system is widely applied, can be applied to commercial display equipment (including but not limited to commercial advertisement display screens) without SoC, directly uses a computer (or a set top box) to output HDMI2.1 or DP signals, and is connected with the system (such as figure 3) shown in the invention, so that the commercial display equipment can be driven to be lightened.
Based on the above embodiments, the present invention discloses a display control method, it should be understood that the application of the present invention is not limited to the above examples, and those skilled in the art can make modifications or changes according to the above description, and all such modifications and changes should fall within the scope of the appended claims.
Claims (15)
- A display control apparatus, characterized in that the apparatus comprises:the two logic chips are used for converting the source video with the first refresh rate into the target video with the second refresh rate, wherein the first refresh rate is smaller than the second refresh rate;the logic board is connected with the two logic chips and is used for converting the target video into a low-voltage differential signal;and the display module is connected with the logic board and used for displaying the low-voltage differential signals.
- A display control method, characterized in that the method comprises:acquiring a source video with a first refresh rate;based on the two logic chips, carrying out refresh rate conversion on the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;and inputting the target video into a display module and displaying the target video through the display module.
- The display control method according to claim 2, wherein the two logic chips are a first logic chip and a second logic chip; each logic chip comprises a double-rate synchronous dynamic random access memory and a motion compensation module; the step of converting the refresh rate of the source video based on the two logic chips to obtain a target video with a second refresh rate comprises the following steps:inputting the source video to the first logic chip, and decoding the source video through the first communication protocol to obtain a second decoded video;and obtaining a target video with a second refresh rate based on the first logic chip, the second logic chip and the second decoded video.
- The display control method of claim 3, wherein the obtaining the target video at the second refresh rate based on the first logic chip, the second logic chip, and the second decoded video comprises:obtaining a first region video according to the second decoded video and the first logic chip;obtaining a second region video according to the second decoded video and the second logic chip;and combining the first area video and the second area video to obtain a target video with a second refresh rate.
- The display control method according to claim 4, wherein obtaining a first area video from the second decoded video and the first logic chip comprises:the second decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory in the first logic chip, so that a second video with a second refresh rate is obtained;performing motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensation video;and carrying out protocol coding on the second motion compensation video to obtain a first region video.
- The display control method according to claim 4, wherein obtaining a second area video from the second decoded video and the second logic chip comprises:the second decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory in the second logic chip, and a third video with a second refresh rate is obtained;performing motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensation video;And carrying out protocol coding on the third motion compensation video to obtain a second region video.
- The display control method according to claim 3, wherein the performing refresh rate conversion on the source video based on the two logic chips to obtain the target video with the second refresh rate includes:respectively inputting the source videos to each logic chip, and decoding the source videos through the second communication protocol to obtain two third decoded videos;obtaining two region videos according to the two third decoded videos;and merging the two region videos to obtain the target video with the second refresh rate.
- The display control method according to claim 7, wherein the obtaining two region videos from the two third decoded videos includes:carrying out refresh rate conversion on each third decoded video through the double-rate synchronous dynamic random access memory to obtain a fourth video with two second refresh rates;performing motion compensation on each fourth video through the motion compensation module to obtain two fourth motion compensation videos;and carrying out protocol coding on each fourth motion compensation video to obtain two region videos.
- An intelligent terminal comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors for performing a display control method, the method comprising the steps of:acquiring a source video with a first refresh rate;based on the two logic chips, carrying out refresh rate conversion on the source video to obtain a target video with a second refresh rate; wherein the first refresh rate is less than or equal to the second refresh rate;and inputting the target video into a display module and displaying the target video through the display module.
- The intelligent terminal of claim 9, wherein the two logic chips are a first logic chip and a second logic chip; each logic chip comprises a double-rate synchronous dynamic random access memory and a motion compensation module; the step of converting the refresh rate of the source video based on the two logic chips to obtain a target video with a second refresh rate comprises the following steps:inputting the source video to the first logic chip, and decoding the source video through the first communication protocol to obtain a second decoded video;And obtaining a target video with a second refresh rate based on the first logic chip, the second logic chip and the second decoded video.
- The intelligent terminal of claim 10, wherein the obtaining the target video at the second refresh rate based on the first logic chip, the second logic chip, and the second decoded video comprises:obtaining a first region video according to the second decoded video and the first logic chip;obtaining a second region video according to the second decoded video and the second logic chip;and combining the first area video and the second area video to obtain a target video with a second refresh rate.
- The intelligent terminal of claim 11, wherein the obtaining a first region video from the second decoded video and the first logic chip comprises:the second decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory in the first logic chip, so that a second video with a second refresh rate is obtained;performing motion compensation on the second video through the motion compensation module in the first logic chip to obtain a second motion compensation video;And carrying out protocol coding on the second motion compensation video to obtain a first region video.
- The intelligent terminal of claim 11, wherein the obtaining a second region video from the second decoded video and the second logic chip comprises:the second decoded video is subjected to refresh rate conversion through the double-rate synchronous dynamic random access memory in the second logic chip, and a third video with a second refresh rate is obtained;performing motion compensation on the third video through the motion compensation module in the second logic chip to obtain a third motion compensation video;and carrying out protocol coding on the third motion compensation video to obtain a second region video.
- The intelligent terminal of claim 10, wherein the performing refresh rate conversion on the source video based on the two logic chips to obtain the target video with the second refresh rate comprises:respectively inputting the source videos to each logic chip, and decoding the source videos through the second communication protocol to obtain two third decoded videos;obtaining two region videos according to the two third decoded videos;and merging the two region videos to obtain the target video with the second refresh rate.
- The intelligent terminal of claim 14, wherein obtaining two region videos from two of the third decoded videos comprises:carrying out refresh rate conversion on each third decoded video through the double-rate synchronous dynamic random access memory to obtain a fourth video with two second refresh rates;performing motion compensation on each fourth video through the motion compensation module to obtain two fourth motion compensation videos;and carrying out protocol coding on each fourth motion compensation video to obtain two region videos.
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| PCT/CN2022/082614 WO2023178576A1 (en) | 2022-03-23 | 2022-03-23 | Display control method, display control apparatus, and intelligent terminal |
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| US20040252756A1 (en) * | 2003-06-10 | 2004-12-16 | David Smith | Video signal frame rate modifier and method for 3D video applications |
| CN105704407B (en) * | 2016-01-29 | 2017-12-22 | 京东方科技集团股份有限公司 | A kind of display processing unit, device and method |
| CN105979118A (en) * | 2016-05-03 | 2016-09-28 | 乐视控股（北京）有限公司 | Video processing system and multimedia playing device provided with same |
| CN108924621B (en) * | 2018-07-12 | 2019-10-29 | 深圳创维－Rgb电子有限公司 | Display methods, device and television set, storage medium |
| CN109801586B (en) * | 2019-03-26 | 2021-01-26 | 京东方科技集团股份有限公司 | Display controller, display control method and system and display device |
| CN111050149A (en) * | 2019-12-24 | 2020-04-21 | 苏州乐梦光电科技有限公司 | Video processing method, device and equipment for projection system and storage medium |
| CN111726477A (en) * | 2020-06-30 | 2020-09-29 | 中航华东光电有限公司 | IPS screen ghost eliminating method in special application environment |
| CN113141537A (en) * | 2021-04-02 | 2021-07-20 | Oppo广东移动通信有限公司 | Video frame insertion method, device, storage medium and terminal |
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