WO2023176282A1

WO2023176282A1 - Electric power conversion device

Info

Publication number: WO2023176282A1
Application number: PCT/JP2023/005386
Authority: WO
Inventors: 雄志荒木; 辰樹柏原; 孝次小林
Original assignee: サンデン株式会社
Priority date: 2022-03-18
Filing date: 2023-02-16
Publication date: 2023-09-21
Also published as: JP2023138042A

Abstract

Provided is an electric power conversion apparatus comprising an inverter circuit 28 for applying a phase voltage at connection points of upper and lower arm switching elements 18A–18F of various phases to a load, and a control device 21, wherein the control device 21 performs switching control of the upper and lower arm switching elements 18A–18F such that the number of variations of a common mode voltage in a predetermined measured bandwidth becomes equal to or fewer than a predetermined prescribed number N (N being an integer equal to or greater than 1) regardless of the measurement timing, whereby variations of the common mode voltage, which may cause common mode noise, become equal to or fewer than the prescribed number at any measurement timing, so that both the noise peak value and the noise average value can be suppressed, and electric current distortion can also be suppressed.

Description

power converter

The present invention relates to a power conversion device that converts DC voltage to AC voltage.

Various pulse width modulation (PWM) methods have been proposed in the past for suppressing conduction noise propagating to a power supply, but the methods can be broadly divided into two. One is a method that completely suppresses fluctuations in the common mode voltage that cause common mode noise, and the other is a method that partially suppresses fluctuations in the common mode voltage while allowing the fluctuations.

The former method includes pulse width modulation that outputs only odd voltage vectors or only even voltage vectors. According to this method, it is possible to completely suppress fluctuations in common mode voltage within a carrier period. There is also pulse width modulation that switches between outputting only odd-numbered voltage vectors and outputting only even-numbered voltage vectors depending on the electrical angle phase. Also by this method, fluctuations in the common mode voltage can be largely suppressed (see, for example, Patent Document 1).

The latter method includes pulse width modulation that matches (shifts) the timing of the rise and fall of the phase voltage of a specific phase with the rise and fall of the phase voltage of other phases in a PWM pattern (for example, Patent Document (see 2). Furthermore, fluctuations in the common mode voltage can also be suppressed by pulse width modulation of two-phase modulation in which switching of one phase is fixed and switching of the other two phases is fixed (see, for example, Patent Document 3).

However, although the former method (Patent Document 1) is the most effective method for suppressing common mode voltage fluctuations, it has limitations on the voltage vector that can be used. The disadvantage is that the maximum amplitude that can be achieved is limited, and the modulation rate that can be output is limited. Therefore, when driving a compressor motor, etc., noise is excited due to current distortion, making it difficult to apply, or when the rotation speed and modulation rate are high, the modulation method as in Patent Document 3 is difficult to apply. It is necessary to switch.

On the other hand, although the latter method (Patent Document 2, Patent Document 3) can utilize the linear output region to the normal maximum and achieve a high modulation rate, the effect of suppressing common mode voltage fluctuation is still lower than that of the former method. inferior to the method. In addition, in Patent Document 3, two-phase modulation and three-phase modulation are switched depending on the operating range, and it is possible to switch between the former method and the latter method described above in the same way, but the switching shock of the pulse width modulation method occurs.

Patent No. 5397448 WO2019/180763 Patent No. 5298003 Patent No. 5976067

Here, noise measurement in a typical three-phase inverter is performed by connecting an artificial power supply network (LISN) to the input section, and capturing the output of this artificial power supply network with a spectrum analyzer or EMC receiver. These spectrum analyzers and EMC receivers have a predetermined measurement bandwidth called resolution bandwidth (RBW), and for noise measurement, the section defined by this measurement bandwidth becomes a measurement window (frequency window). Outputs frequency components as spectral intensity. In this case, if a plurality of the same frequency components exist within the measurement window, the spectral intensities are integrated by the number of times they appear.

FIG. 10 shows such a measurement window and measurement waveform. Note that FIG. 10 shows the case of FFT analysis. FFT analysis is performed only on waveforms observed in the measurement window. Therefore, there is no problem if the window length of the measurement window and the period of the measurement waveform match as shown in FIG. 10, but if the period of the measurement window and the measurement waveform are different as shown in FIG. Since frequency analysis is performed on a discontinuous waveform, a frequency spectrum that does not actually exist may be observed, and depending on the phase observed in the measurement window, the intensity of the spectrum may be excessively measured. There is. As a countermeasure, a window function is used in FFT analysis, and in spectrum analyzers and EMC receivers, an IF filter (bandpass filter) corresponds to the window function.

In the EMI test, the above measurements are performed at each frequency point for a specified period of time. The maximum value of the time response at each frequency point becomes the noise peak value, and the average value of the time response becomes the noise average value. On the other hand, since the conventional common mode noise suppression method described above is based on pulse shifting, there are operations in which common mode voltage fluctuations are concentrated.

FIG. 13 shows an example of occurrence of common mode noise (conduction noise) in the conventional common mode noise suppression method. In the example shown in Figure 13, the occurrence of common mode noise is suppressed to two times in each control cycle, and common mode noise occurs four times in the measurement window indicated by X1 in the figure, and twice in the measurement window indicated by X3. ing. However, in the measurement window indicated by X2 where common mode voltage fluctuations are concentrated, it is measured that the common mode voltage fluctuations have occurred six times, so there is a problem that the noise peak value is the result of six measurements.

For example, in Patent Document 4, a carrier waveform whose spectrum is spread by a carrier generator is calculated for each of three phases according to a spectrum spread index defined by a spectrum spread index command generator, and switching of each phase is performed by spectrum spread. The frequency is spread and the peak of electromagnetic noise caused by switching is reduced, but in the noise measurement mentioned above, this is a reduction in the noise average value, and on the contrary, it worsens the noise peak value. Ta.

The present invention was made in order to solve the conventional technical problem, and it is possible to reduce the fluctuation of the common mode voltage, which is a cause of common mode noise, to a specified number of times or less regardless of the timing of measurement. It is an object of the present invention to provide a power conversion device that can suppress both a noise peak value and a noise average value, and further suppress current distortion.

The power conversion device of the present invention converts a DC voltage into an AC voltage, and includes an inverter circuit that applies a phase voltage to a load at a connection point of upper and lower arm switching elements of each phase, and a switching element of each upper and lower arm switching element. The control device is configured to control the number of fluctuations of the common mode voltage in a predetermined measurement bandwidth to be equal to or less than a predetermined number of times N (N is an integer of 1 or more) regardless of the measurement timing. The present invention is characterized by controlling the switching of the upper and lower arm switching elements.

In the power conversion device of the invention of claim 2, in the above invention, the control device simultaneously switches the upper and lower arm switching elements of different phases to opposite polarities to each other, thereby reducing the number of fluctuations of the common mode voltage to a prescribed number of times N or less. It is characterized by

In the power conversion device of the invention of claim 3, in the invention of claim 1, the control device refers to the voltage vector pattern in the previous control cycle, and the number of fluctuations of the common mode voltage in the measurement bandwidth is determined regardless of the measurement timing. The present invention is characterized in that it includes a voltage pattern group generation unit that generates a plurality of voltage vector patterns that occur a prescribed number of times N or less.

In the power conversion device of the invention according to claim 4, in the above invention, when the switching frequency is larger than the measurement bandwidth, the voltage pattern group generation unit generates an even voltage vector next to an even voltage vector or an odd voltage vector in one control period. By outputting an odd-numbered voltage vector next to the vector, a voltage vector pattern is generated that simultaneously switches the upper and lower arm switching elements of different phases to mutually opposite polarities, and the number of fluctuations of the common mode voltage is kept below the specified number of times N. Features.

In the power conversion device of the invention of claim 5, in the invention of claim 3 or 4, the voltage pattern group generation section adds a constraint condition such that the number of times of switching of each phase in one control period is equal to or less than a predetermined limit number of times. It is characterized by generating multiple voltage vector patterns.

In the power conversion device of the invention of claim 6, in the invention of claim 3 or 4, the control device includes a current command calculation unit that calculates a current command value and a voltage vector pattern that is generated by the voltage pattern group generation unit. The optimal voltage vector pattern that minimizes the error between the current command value and the current predicted value is selected from among the voltage vector patterns generated by the current prediction calculation unit that calculates the current predicted value and the voltage pattern group generation unit. It is characterized by having a voltage pattern selection section.

In the power conversion device according to the seventh aspect of the present invention, the inverter circuit drives the motor by applying a phase voltage at a connection point between the upper and lower arm switching elements of each phase to the motor.

In the power conversion device of the invention of claim 8, in the invention of claim 6, the optimal voltage pattern selection section selects the optimal voltage vector pattern based on the number of fluctuations of the common mode voltage and the error between the current command value and the current predicted value. It is characterized by selecting.

In the power conversion device of the invention according to claim 9, in the above invention, the optimum voltage pattern selection section prioritizes the number of fluctuations of the common mode voltage higher than the error between the current command value and the current predicted value, and selects the optimum voltage pattern. It is characterized by selecting a voltage vector pattern.

According to the present invention, in a power conversion device that converts DC voltage to AC voltage, an inverter circuit that applies phase voltage to a load at a connection point of upper and lower arm switching elements of each phase and switching of each upper and lower arm switching element is controlled. The controller includes a control device that controls the frequency of fluctuation of the common mode voltage in a predetermined measurement bandwidth to be equal to or less than a predetermined number of times N (N is an integer of 1 or more), regardless of the measurement timing. Since the upper and lower arm switching elements are subjected to switching control, it is possible to suppress and minimize both the average value and the peak value of common mode noise generated due to fluctuations in common mode voltage. Furthermore, it is possible to suppress the occurrence of electromagnetic interference to peripheral devices due to concentration of common mode voltage fluctuations and concentration of common mode noise.

In this case, if the control device according to the second aspect of the invention simultaneously switches the upper and lower arm switching elements of different phases to opposite polarities, the number of times the common mode voltage fluctuates is equal to or less than the prescribed number N. Particularly when the switching frequency is larger than the measurement bandwidth, the number of fluctuations in the common mode voltage can be smoothly controlled to be equal to or less than the prescribed number of times N.

Further, according to the invention of claim 3, the control device refers to the voltage vector pattern in the previous control cycle, and detects a plurality of cases in which the number of fluctuations of the common mode voltage in the measurement bandwidth is equal to or less than the prescribed number of times N regardless of the measurement timing. If the configuration includes a voltage pattern group generation section that generates voltage vector patterns, the peak value of common mode noise can be effectively controlled to be equal to or less than the prescribed number of times N.

In this case, as in the invention of claim 4, when the switching frequency is larger than the measurement bandwidth, the voltage pattern group generation section generates an even voltage vector after an even voltage vector or a voltage vector after an odd voltage vector in one control period. By outputting an odd voltage vector, a voltage vector pattern is generated that simultaneously switches the upper and lower arm switching elements of different phases to mutually opposite polarities, and the number of fluctuations of the common mode voltage is preferably set to be equal to or less than the prescribed number of times N.

Further, as in the invention of claim 5, if the voltage pattern group generation section generates a plurality of voltage vector patterns by adding a constraint condition such that the number of switching times of each phase in one control period is equal to or less than a predetermined limit number of times, It is also possible to prevent the inconvenience that the switching frequency exceeds the rated frequency of the semiconductor that constitutes the control device.

Furthermore, according to the invention of claim 6, the control device includes a current command calculation unit that calculates a current command value, and a current prediction calculation unit that calculates a current predicted value of each voltage vector pattern generated by the voltage pattern group generation unit. , the configuration includes an optimal voltage pattern selection unit that selects a voltage vector pattern that minimizes the error between the current command value and the current predicted value from among the voltage vector patterns generated in the voltage pattern group generation unit. It becomes possible to suppress the average value of common mode noise while taking current response into consideration. In addition, since current distortion can be suppressed over the entire operating range, noise is less likely to be excited, making it extremely effective when driving a motor as a load, for example, as in the seventh aspect of the invention.

In this case, the optimum voltage pattern selection section may select the optimum voltage vector pattern based on the number of fluctuations of the common mode voltage and the error between the current command value and the predicted current value. , it becomes possible to smoothly realize both suppression of common mode noise and improvement of current response.

Further, according to the invention of claim 9, the optimum voltage pattern selection section selects the optimum voltage vector pattern by giving a higher priority to the number of fluctuations of the common mode voltage than the error between the current command value and the current predicted value. By doing so, it becomes possible to select an optimal voltage vector pattern with good current response while reliably suppressing fluctuations in the common mode voltage.

1 is an electrical circuit diagram of a power conversion device according to an embodiment of the present invention; FIG. FIG. 3 is a diagram showing the relationship between voltage vectors and phase voltages. FIG. 3 is a diagram showing a voltage vector (output basic vector). 2 is a diagram illustrating an example of a voltage vector pattern generated by a voltage pattern group generation unit of the control device in FIG. 1. FIG. FIG. 2 is a diagram illustrating an example of a voltage vector pattern search operation performed by a voltage pattern group generation unit of the control device in FIG. 1; FIG. 2 is a diagram showing operating waveforms at a low modulation rate by the power conversion device of the present invention in FIG. 1; FIG. 2 is a diagram showing operating waveforms of the power conversion device of the present invention in FIG. 1 at a medium modulation rate. FIG. 2 is a diagram showing operating waveforms at a high modulation rate by the power conversion device of the present invention in FIG. 1; FIG. 2 is a diagram showing an example of common mode noise generation in the power conversion device of the present invention shown in FIG. 1; FIG. 6 is a diagram showing a measurement window and a measurement waveform when the window length of the measurement window and the period of the measurement waveform match. FIG. 7 is a diagram showing a measurement window and a measurement waveform when the window length of the measurement window and the period of the measurement waveform are different. 12 is a diagram showing a measured waveform to be analyzed in the case of FIG. 11. FIG. FIG. 3 is a diagram illustrating an example of common mode noise generation in a conventional power conversion device.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. A power conversion device 1 according to an embodiment of the present invention drives a motor 8 (load) of a so-called inverter-integrated electric compressor that constitutes a refrigerant circuit of a vehicle air conditioner installed in a vehicle such as an electric vehicle. It is something.

(1) Circuit configuration of power converter 1 In FIG. 1, power converter 1 of the embodiment includes a three-phase inverter circuit 28 and a control device 21. The inverter circuit 28 converts the DC voltage of a DC power source (vehicle battery: e.g. DC 350V) 29 into three-phase (U-phase voltage Vu, V-phase voltage Vv, W-phase voltage Vw) AC voltage and applies it to the motor 8. This is a circuit that does this. In this case, the motor 8 of the embodiment is an IPMSM (Interior Permanent Magnet Synchronous Motor).

The inverter circuit 28 has a U-phase half-bridge circuit 19U, a V-phase half-bridge circuit 19V, and a W-phase half-bridge circuit 19W. Each phase half-bridge circuit 19U to 19W is connected to an upper arm switching element 18A to 18C, respectively. and lower arm switching elements 18D to 18F. Further, a flywheel diode 31 is connected in antiparallel to each of the switching elements 18A to 18F. In the embodiment, each of the upper and lower arm switching elements 18A to 18F is composed of an insulated gate bipolar transistor (IGBT) in which a MOS structure is incorporated in the gate portion.

The collectors of the upper arm switching elements 18A to 18C of the inverter circuit 28 are connected to the upper arm power supply line (positive bus line) 10 of the DC power supply 29. On the other hand, the emitters of the lower arm switching elements 18D to 18F of the inverter circuit 28 are connected to the lower arm power supply line (negative bus) 15 of the DC power supply 29.

In this case, the emitter of the upper arm switching element 18A of the U-phase half bridge circuit 19U and the collector of the lower arm switching element 18D are connected in series, and the emitter of the upper arm switching element 18B and the lower arm switching element of the V-phase half bridge circuit 19V are connected in series. 18E are connected in series, and the emitter of the upper arm switching element 18C and the collector of the lower arm switching element 18F of the W-phase half bridge circuit 19W are connected in series.

The connection point between the upper arm switching element 18A and the lower arm switching element 18D of the U-phase half bridge circuit 19U (midpoint of the upper and lower arms: U-phase voltage Vu) is connected to the U-phase armature coil of the motor 8, The connection point between the upper arm switching element 18B and the lower arm switching element 18E of the V-phase half bridge circuit 19V (midpoint of the upper and lower arms: V-phase voltage Vv) is connected to the V-phase armature coil of the motor 8, and the W-phase A connection point between the upper arm switching element 18C and the lower arm switching element 18F of the half bridge circuit 19W (midpoint between the upper and lower arms: W-phase voltage Vw) is connected to the W-phase armature coil of the motor 8.

(2) Configuration of the control device 21 Next, the control device 21 is composed of a microcomputer (semiconductor) having a processor, and in the embodiment inputs the rotation speed command value from the ECU of the vehicle, and receives the motor current ( Based on these, the ON/OFF state (switching) of each switching element 18A to 18F of the inverter circuit 28 is controlled. Specifically, the gate voltage applied to the gate of each switching element 18A to 18F is controlled.

The control device 21 of the embodiment includes a dq-axis current command calculation unit 33 as a current command calculation unit, a voltage pattern group generation unit 34, a dq-axis current prediction calculation unit 35 as a current prediction calculation unit, and an optimal voltage pattern selection 36, a gate driver 37, and

current sensors

26A and 26B each comprising a current transformer for measuring U-phase current iu and W-phase current iw, which are U-phase and W-phase motor currents (phase currents) flowing through the motor 8. have. Further, an electrical angle θrm is obtained from the motor 8.

In the embodiment, the current sensor 26A measures the U-phase current iu, the current sensor 26B measures the W-phase current iw, and the V-phase current iv is calculated from these. , iv, and iw may be measured by a current sensor. In addition, as for the method of detecting the motor current of each phase, in addition to measuring with the

current sensors

26A and 26B as in the embodiment, the current value of the lower arm power supply line 15 is detected with a shunt resistor, and the current value and the motor 8 There is no particular limitation on the method of detecting and estimating each phase current, as there are methods of estimating it from the operating state of the current.

(3) Gate driver 37
First, the gate driver 37 selects the gate voltages of the

switching elements

18A and 18D of the U-phase inverter 19U, and the switching element 18B of the V-phase inverter 19V, based on the optimal voltage vector pattern selected by the optimal voltage pattern selection section 36 as described later. A gate voltage of 18E and a gate voltage of switching

elements

18C and 18F of W-phase inverter 19W are generated.

Then, each of the switching elements 18A to 18F of the inverter circuit 28 is driven ON/OFF based on the gate voltage output from the gate driver 37. That is, when the gate voltage is in an ON state (predetermined voltage value), the switching element is turned on, and when the gate voltage is in an OFF state (zero), the switching element is turned off. When the switching elements 18A to 18F are the above-mentioned IGBTs, the gate driver 37 is a circuit for applying a gate voltage to the IGBTs based on a PWM signal, and is composed of a photocoupler, a logic IC, a transistor, etc. Ru.

Then, the voltage at the connection point between the upper arm switching element 18A and the lower arm switching element 18D of the U-phase half bridge circuit 19U is applied (output) to the U-phase armature coil of the motor 8 as the U-phase voltage Vu (phase voltage). , the voltage at the connection point between the upper arm switching element 18B and the lower arm switching element 18E of the V-phase half-bridge circuit 19V is applied (output) to the V-phase armature coil of the motor 8 as a V-phase voltage Vv (phase voltage), The voltage at the connection point between the upper arm switching element 18C and the lower arm switching element 18F of the W-phase half-bridge circuit 19W is applied (output) to the W-phase armature coil of the motor 8 as the W-phase voltage Vw (phase voltage).

(4) dq-axis current command calculation section 33
The dq-axis current command calculation unit 33 of the embodiment outputs a d-axis current command value i _d ^ref and a q-axis current command value i _q ^ref as current command values. In this case, the q-axis current command value i _q ^ref is calculated from the PI calculation and the relational expression between the q-axis current and torque. In addition, in the notation of the formula described later, the subscripts and superscripts of the d-axis current command value i _d ^ref and the q-axis current command value i _q ^ref are written in the same position above and below, but they are the same as the above notation. (the same applies hereinafter).

Here, if we summarize the High and Low states of the U-phase voltage Vu, V-phase voltage Vv, and W-phase voltage Vw applied to the armature coil of each phase of the motor 8, the 8 of V0 to V7 as shown in FIG. It can be expressed in the state of two voltage vectors (output fundamental vectors). Among these, V1, V3, and V5 are odd voltage vectors, V2, V4, and V6 are even voltage vectors, and V0 and V7 are zero voltage vectors. When each voltage vector is shown in the αβ axis voltage space, it becomes as shown in Figure 3. Become.

(5) Voltage pattern group generation unit 34
Next, the voltage pattern group generation unit 34 of the embodiment refers to the voltage vector pattern in the previous control cycle, and determines the number of fluctuations of the common mode voltage Vc of the motor 8 in the measurement bandwidth in the noise measurement described above at the measurement timing. A plurality of voltage vector patterns are generated in which the number of switching times in one control period is equal to or less than a predetermined limit number M regardless of the number of times of switching. In the embodiment, it is assumed that the switching frequency is sufficiently larger than the measurement bandwidth.

That is, the voltage pattern group generation unit 34 of the embodiment generates voltage vector pattern candidates by setting the following constraint conditions, taking into account the measurement bandwidth and the number of switching times (switching frequency) of each phase of the inverter circuit 28. generate.
Constraint condition 1: The number of fluctuations in the common mode voltage Vc is equal to or less than the specified number of times N, regardless of the timing of measurement. This specified number of times N is an integer greater than or equal to 1, but in the following explanation, N=1.
Constraint condition 2: In the voltage vector pattern output in one control period, the number of switching times (switching frequency) of each phase of the inverter circuit 28 is equal to or less than the limit number M. This limited number of times M is a value that does not exceed the rated switching frequency of the switching element (semiconductor) constituting the inverter circuit 28, and in the following description, M=2.

(5-1) Operation of the voltage pattern group generation section 34 Hereinafter, the operation procedure of the voltage pattern group generation section 34 of the embodiment will be specifically explained with reference to FIGS. 4 and 5. In the example, the voltage vector resolution of one control period is set to 5 (5 sections), and the voltage vector pattern in the previous control period in that case is shown on the left side of FIG. 4, and the voltage vector pattern in the current control period determined as a candidate is shown. An example is shown on the right. Note that steps 1 to 6 in FIG. 4 correspond to steps 1 to 6 in FIG. Determine the voltage vector pattern in the control period. Further, V1 to V6 in each figure are the voltage vectors (output basic vectors, other than zero voltage vectors) described above.

First, in step 1, the voltage pattern group generation unit 34 refers to the voltage vector patterns (V4, V4, V2, V3, V5) in the previous control cycle. Here, when outputting the even voltage vectors V2, V4, V6 after the even voltage vectors V2, V4, V6, the upper and lower arm switching elements 18A to 18F of different phases are simultaneously switched to opposite polarities. , the common mode voltage Vc does not change. Similarly, when outputting odd voltage vectors V1, V3, and V5 next to odd voltage vectors V1, V3, and V5, the upper and lower arm switching elements 18A to 18F of different phases are simultaneously switched to opposite polarities. Common mode voltage Vc does not change.

On the other hand, if an odd voltage vector is output after an even voltage vector, or if an even voltage vector is output after an odd voltage vector, the common mode voltage Vc will fluctuate. In the voltage vector pattern in the previous control cycle, the odd voltage vector V3 is output after the even voltage vector V2, so the common mode voltage Vc fluctuates once, and the specified number of times N (1: constraint condition 1). Therefore, as the voltage vector that can be output next to the last odd voltage vector V5, a voltage vector in which there is no fluctuation in the common mode voltage Vc is searched for, and in step 1 of the embodiment, for example, the odd voltage vector V5 is selected.

Next, in step 2, a voltage vector to be output next to the last voltage vector V5 of the voltage vector pattern (V4, V2, V3, V5, V5) determined in step 1 is searched. In this case, since the common mode voltage Vc still fluctuates once, a voltage vector in which the common mode voltage Vc does not fluctuate is searched for, and in step 2 of the embodiment, for example, an odd voltage vector V1 is selected.

Next, in step 3, a voltage vector to be output next to the last voltage vector V1 of the voltage vector pattern (V2, V3, V5, V5, V1) determined in step 2 is searched. In this case, since there is no variation in the common mode voltage Vc, all voltage vectors become candidates, and in step 3 of the embodiment, for example, the odd voltage vector V3 is selected.

Next, in step 4, a voltage vector to be output next to the last voltage vector V3 of the voltage vector pattern (V3, V5, V5, V1, V3) determined in step 3 is searched. In this case as well, since there is no variation in the common mode voltage Vc, all voltage vectors become candidates, and in step 4 of the embodiment, for example, the odd voltage vector V3 is selected.

Note that in step 1 of FIG. 5, the odd voltage vector V5 is used, but other odd voltage vectors V1 and V3 may be used. Similarly, in step 2, the odd voltage vector V1 is used, but other odd voltage vectors V3 and V5 may be used. Further, although the odd voltage vector V3 is used in step 3, other voltage vectors V1, V2, V4 to V6 may be used. Similarly, in step 4, the odd voltage vector V3 is used, but other voltage vectors V1, V2, V4 to V6 may be used, and the options for which the number of fluctuations of the common mode voltage Vc is N(1) or less are sequentially output.

Next, in step 5, a voltage vector to be output next to the last voltage vector V3 of the voltage vector pattern (V5, V5, V1, V3, V3) determined in step 4 is searched. In this case as well, since there is no variation in the common mode voltage Vc, all voltage vectors become candidates, but constraint condition 2 is also taken into consideration. In this case, a voltage vector (voltage vector that satisfies the constraint condition 2 on the number of switching times) in which the number of times of switching (switching frequency) of each phase is equal to or less than the above-mentioned limit number of times M(2) is searched for. In the embodiment, in step 6, the even voltage vector V4 is determined as a voltage vector that satisfies the first constraint on the variation of the common mode voltage Vc and the second constraint on the number of switching times. This becomes the voltage vector pattern (V5, V1, V3, V3, V4) in the current control cycle shown in FIG. 4, and is saved as a candidate for the voltage vector pattern to be output.

As described above, the voltage vector pattern in the current control cycle is searched by referring to the voltage vector pattern in the previous control cycle. Although the number of combinations of voltage vector patterns as a search result changes depending on the voltage vector pattern of the previous control cycle, in the embodiment, there are about 400 combinations (a set of voltage vector patterns) at most. Further, the search for constraint condition 1 regarding fluctuations in the common mode voltage Vc is performed in all steps in FIG. In this way, by considering the fluctuations in the common mode voltage Vc in all steps, a voltage vector pattern is established in which the number of fluctuations in the common mode voltage Vc is N(1) or less no matter where it is measured. By searching for a voltage vector pattern by the voltage pattern group generation unit 34, the peak value of common mode noise is suppressed at the input voltage vector pattern stage.

(6) dq-axis current prediction calculation unit 34
Next, the dq-axis current prediction calculation unit 34 of the embodiment predicts and outputs the d-axis current i _d and the q-axis current i _q as current predicted values. The prediction formulas for the d-axis current i _d and the q-axis current i _q are derived by discretizing (zero-order hold) the IPMSM state equation shown in equation (I) as shown in equation (II) and equation (III). I do.

In addition, in formula (I), i _d is the d-axis current, i _q is the q-axis current, v _d is the d-axis voltage, v _q is the q-axis voltage, L _d is the d-axis inductance, L _q is the q-axis inductance, R _a is the winding resistance, k _E is the induced voltage constant, and ω _re is the electrical angular velocity.

In addition, in formulas (II) and (III), x(t) is the state quantity at time t (dq-axis current), x[k] is the state quantity at the k-th sample point (discrete representation), and u(t ) is the input at time t (the control input is the dq-axis voltage, the disturbance input is the induced voltage, the input is the sum of the control input and disturbance input), u[k] is the input at the k-th sample point (discrete representation), A _c is the free motion parameter of the state quantity in the continuous domain, b _c is the influence parameter of the input on the state quantity in the continuous domain, A _d is the expression of the parameter A _c in the discrete domain, and b _d is the expression of the parameter b _c in the discrete domain. The expression T _p is the prediction period at which the model predictions are made.

x[k] in formula (III) is the k-th state quantity, and is the initial value of the dq-axis current output by the dq-axis current command calculation unit 33. The second state quantity x[k+1] (dq-axis current) is predicted from this initial value. The dq-axis current prediction calculation unit 34 solves Equation (III) for each section of the voltage vector pattern described above, and calculates the instantaneous predicted value of each section (5 sections in the embodiment) and the average predicted value of the control period.

The prediction formulas when the control period is divided into five sections as described above are as shown in the following formulas (IV) to (VII). Note that although the A matrix and the b matrix depend on the electrical angular velocity ω _re , since there is little variation per control cycle, they are approximately constant values.

Note that in formula (IV), x[k+1] to x[k+5] are predicted values corresponding to the first to fifth sections of the voltage vector pattern described above. Further, in formula (VI), C _dqn αβ is a rotation matrix at k+n sample points. In the formula, _dqn and αβ are written in the same position above and below, but they are the same. Also, in equation (VII), vαβ _n is the αβ voltage input at k+n sample points.

The voltage vector of the control input is defined on the αβ coordinate. Therefore, at each sampling point, dq-axis conversion is performed in consideration of the phase lead for each prediction cycle (underlined part of formula (VI)).

(7) Optimal voltage pattern selection section 36
Next, the optimal voltage pattern selection unit 36 of the embodiment selects a set of voltage vector patterns (up to 400 patterns) that satisfy the constraints (constraints 1 and 2) generated by the voltage pattern group generation unit 34. The current command values (d-axis current command value i _d ^ref , q-axis current command value i _q ^ref ) calculated by the dq-axis current command calculation unit 33 and the current value predicted value (d A voltage vector pattern with a minimum error from the axis current i _d and the q-axis current i _q is selected.

(7-1) Operation of the optimal voltage pattern selection unit 36 The optimal voltage pattern selection unit 36 of the embodiment specifically calculates the cost of each voltage vector pattern using the following formulas (VIII) to (XI). . As a result of the cost calculation, the voltage vector pattern with the minimum cost C (evaluation index) of the voltage vector pattern is output as the optimal voltage vector pattern.

In the formula (VIII), C is the cost of the voltage vector pattern, W _max is the weighting coefficient for the ripple caused by vector switching (the weighting coefficient of the maximum instantaneous error cost), and W _ave is the responsiveness of the dq-axis current. (weighting coefficient of average error cost), W _Vc is a weighting coefficient (number of common mode voltage fluctuations) that determines the control priority of common mode voltage fluctuation and current error (error between current command value and current predicted value). weighting coefficient). Furthermore, C _Vc is the number of fluctuations in the common mode voltage in the voltage vector pattern, E _max is the maximum instantaneous error cost, and E _ave is the average error cost.

In addition, in formula (X), W _d is the d-axis weighting coefficient, W _q is the q-axis weighting coefficient, max() is the function that outputs the maximum value of the argument in (), and abs() is the function that outputs the maximum value of the argument in (). The function that outputs the absolute value, x ^ref [k] is the state quantity command value calculated at k sample points (i _d ^ref [k] is the d-axis current command value, i _q ^ref [k] is the q-axis current command value ).

The first and second terms on the right side of formula (VIII) are costs due to current error (error between current command value and current predicted value), and the third term is cost due to common mode voltage fluctuation. . The optimum voltage pattern selection unit 36 of the embodiment basically selects the one with the minimum current error cost as the optimum voltage vector pattern from among the voltage vector patterns without common mode voltage fluctuations. That is, the priority of the number of fluctuations of the common mode voltage is made higher than the current error (error between the current command value and the current predicted value). In addition, if the current error is too large in a voltage vector pattern without common mode voltage fluctuations, select the voltage vector pattern with the minimum current error cost as the optimal voltage vector pattern from among the voltage vector patterns that include common mode voltage fluctuations. do.

The ratio of the weighting coefficients W _max , W _ave , and W _Vc determines to what extent ([A]) the current error should prioritize the voltage vector pattern without common mode voltage fluctuations. This makes it possible to select a voltage vector pattern with good current response, that is, with little current error, while suppressing common mode voltage fluctuations. Note that since only the number of fluctuations of the common mode voltage in each control cycle is optimized here, the noise average value is suppressed. This is because it is evaluated whether the common mode voltage is varied or not in each control cycle.

(7-2) Example of Selection of Optimal Voltage Vector Pattern Next, an example of selecting the optimal voltage vector pattern using equation (VIII) will be described. Now, if the weighting coefficient W _max =1.0, the weighting coefficient W _ave = 1.0, and the weighting coefficient W _Vc = 2.5, E _max = 1.0, E _ave = 1.0, C _Vc = 0. Consider voltage vector pattern 1 with E _max =0.0, E _ave =0.0, and voltage vector pattern 2 with C _Vc =1.0. Voltage vector pattern 1 has no common mode voltage fluctuation but has some current error, and voltage vector pattern 2 shows an ideal current response but has common mode voltage fluctuation.

In the above case, the cost C1 of voltage vector pattern 1 and the cost C2 of voltage vector pattern 2 derived from formula (VIII) are:
C1=1.0×1.0+1.0×1.0+2.5×0.0=2.0
C2=1.0×0.0+1.0×0.0+2.5×1.0=2.5
becomes. In the case of the above weighting coefficient ratio, voltage vector pattern 1, which has a current error but has no common mode voltage fluctuation, is selected as the optimal voltage vector pattern.

Also, voltage vector pattern 3 with E _max =2.0, E _ave =2.0, C _Vc =0, and voltage vector pattern 3 with E _max =0.0, E _ave =1.0, C _Vc =1.0. Consider pattern 4. Both voltage vector pattern 3 and voltage vector pattern 4 are cases where a current error exists.

In the above case, the cost C3 of voltage vector pattern 3 and the cost C4 of voltage vector pattern 4 derived from formula (VIII) are:
C3=1.0×2.0+1.0×2.0+2.5×0.0=4.0
C4=1.0×0.0+1.0×1.0+2.5×1.0=3.5
becomes. Voltage vector pattern C4 has a good current response even when taking common mode voltage fluctuations into consideration, and voltage vector pattern C3 has no common mode voltage fluctuations, but the current error is too large, so voltage vector pattern 4 is selected by comparing costs C4 and C3. will be selected as the optimal voltage vector pattern.

As a result of the evaluation using the above-mentioned formula (VIII), the optimum voltage pattern selection unit 36 of the embodiment basically gives priority to a voltage vector pattern without common mode voltage fluctuation in terms of cost. Even when there is no common mode voltage variation, if the current error is large, a voltage vector pattern with a small current error and common mode voltage variation is selected as the optimal voltage vector pattern.

Further, the optimization calculation of formula (VIII) is performed in each control cycle, and the current error is minimized while suppressing the common mode voltage fluctuation by successive optimization. Therefore, the current error is minimized while suppressing the noise average value.

6 to 9 show the results according to the present invention. Figure 6 shows the waveforms of the U-phase current iu and common mode voltage Vc at a low modulation rate, Figure 7 shows the waveforms of the U-phase current iu and common mode voltage Vc at a medium modulation rate, and Figure 8 shows the waveforms of the U-phase current iu and common mode voltage Vc at a high modulation rate. It shows the waveforms of the U-phase current iu and the common mode voltage Vc at the time. When the modulation rate is low, the common mode voltage Vc does not fluctuate, and as the modulation rate increases from the medium modulation rate to the high modulation rate, the common mode voltage Vc fluctuates. It can be seen that the current response is improved while suppressing fluctuations in the mode voltage Vc.

Further, FIG. 9 shows an example of the occurrence of common mode noise (conduction noise) according to the results of the present invention for comparison with the conventional example shown in FIG. 13. As is clear from Fig. 9, no matter what timing the measurement is taken, the number of times the noise occurs within the window divided by the measurement window is four times (two times in one control cycle), and the noise peak value is suppressed.

As described in detail above, according to the power conversion device 1 of the present invention, the control device 21 controls the number of fluctuations of the common mode voltage Vc in a predetermined measurement bandwidth to a predetermined number of times N (N is Since the voltage vector pattern is generated to control the switching of the upper and lower arm switching elements 18A to 18F, the average value and the peak value of the common mode noise generated due to fluctuations in the common mode voltage Vc are generated. It becomes possible to suppress and minimize both. Further, it is also possible to suppress the occurrence of electromagnetic interference to peripheral devices due to the concentration of fluctuations in the common mode voltage Vc and the concentration of common mode noise.

Further, in the embodiment, the control device 21 simultaneously switches the upper and lower arm switching elements 18A to 18F of different phases to mutually opposite polarities, so that the number of fluctuations of the common mode voltage Vc is kept below the specified number of times N. In particular, when the switching frequency is larger than the measurement bandwidth, the number of fluctuations of the common mode voltage Vc can be smoothly controlled to be equal to or less than the prescribed number of times N.

Further, in the embodiment, the control device 21 refers to the voltage vector pattern in the previous control cycle, and selects a plurality of voltage vectors for which the number of fluctuations of the common mode voltage Vc in the measurement bandwidth is equal to or less than the prescribed number of times N regardless of the measurement timing. Since the voltage pattern group generation unit 34 that generates patterns is included, the peak value of common mode noise can be effectively controlled to be equal to or less than the prescribed number of times N.

In this case, when the switching frequency is larger than the measurement bandwidth, the voltage pattern group generation unit 34 of the embodiment generates an even voltage vector V2, V4, V6, or By outputting odd voltage vectors V1, V3, and V5 next to odd voltage vectors V1, V3, and V5, a voltage vector pattern is generated that simultaneously switches the upper and lower arm switching elements 18A to 18F of different phases to mutually opposite polarities. , the number of fluctuations of the common mode voltage Vc is set to be equal to or less than a specified number of times N, and a constraint condition is added that the number of switching times of each phase in one control period is equal to or less than a predetermined limited number of times M, so that a plurality of voltage vector patterns are generated. Therefore, it is possible to prevent the inconvenience of the switching frequency exceeding the rated switching frequency of the switching element (semiconductor) constituting the inverter circuit 28.

Furthermore, in the embodiment, the control device 21 includes a dq-axis current command calculation unit 33 that calculates current command values (d-axis current command value i _d ^ref , q-axis current command value i _q ^ref ), and a voltage pattern group generation unit 34 . The dq-axis current prediction calculation unit 35 calculates the current predicted value (d-axis current i _d , q-axis current i _q ) of each voltage vector pattern generated by the voltage vector pattern generated by the voltage pattern group generation unit 34. Since it has an optimal voltage pattern selection unit 36 that selects the voltage vector pattern that minimizes the error between the current command value and the current predicted value from among the be able to suppress it. In addition, since current distortion can be suppressed over the entire operating range, noise is less likely to be excited, which is extremely effective when driving the motor 8 as a load as in the embodiment.

In this case, in the embodiment, the optimal voltage pattern selection unit 36 selects the optimal voltage vector pattern based on the number of fluctuations in the common mode voltage Vc and the error (current error) between the current command value and the current predicted value. Therefore, it becomes possible to smoothly realize both suppression of common mode noise Vc and improvement of current response.

Further, in the embodiment, the optimum voltage pattern selection unit 36 sets the priority of the number of fluctuations of the common mode voltage Vc higher than the error (current error) between the current command value and the current predicted value, and selects the optimum voltage vector pattern. Since the selection is made, it is possible to select an optimal voltage vector pattern with good current response while reliably suppressing fluctuations in the common mode voltage Vc.

Note that the numerical values shown in the examples are not limited thereto. Furthermore, although the embodiment has been described using the example of driving the motor (load) of an electric compressor, the present invention is not limited thereto, and is also effective when driving a motor other than the motor of the electric compressor. Further, in inventions other than claim 9, the present invention can be applied to various power conversion devices that convert DC voltage to AC voltage using an inverter and apply it to a load.

1 Power converter 8 Motor 18A to 18F Upper and lower arm switching elements 19U U-phase inverter 19V V-phase inverter 19W W-phase inverter 21 Control device 28 Inverter circuit 33 dq-axis current command calculation unit (current command calculation unit)
34 Voltage pattern group generation unit 35 dq-axis current prediction calculation unit (current prediction calculation unit)
36 Optimal voltage pattern selection section 37 Gate driver

Claims

In a power conversion device that converts DC voltage to AC voltage,
an inverter circuit that applies the phase voltage at the connection point of the upper and lower arm switching elements of each phase to the load;
comprising a control device that controls switching of each of the upper and lower arm switching elements,
The control device controls the upper and lower arm switching elements so that the number of fluctuations of the common mode voltage in a predetermined measurement bandwidth is equal to or less than a predetermined number of times N (N is an integer of 1 or more) regardless of the measurement timing. A power conversion device characterized by switching control.
The power supply according to claim 1, wherein the control device makes the number of fluctuations of the common mode voltage equal to or less than the prescribed number of times N by simultaneously switching the upper and lower arm switching elements of different phases to mutually opposite polarities. conversion device.
The control device refers to voltage vector patterns in the previous control cycle and generates a plurality of voltage vector patterns in which the number of fluctuations of the common mode voltage in the measurement bandwidth is equal to or less than the specified number of times N regardless of the measurement timing. The power conversion device according to claim 1, further comprising a voltage pattern group generation section.
When the switching frequency is larger than the measurement bandwidth, the voltage pattern group generation section outputs an even voltage vector after an even voltage vector or an odd voltage vector after an odd voltage vector in one control period. , generating a voltage vector pattern that simultaneously switches the upper and lower arm switching elements of different phases to mutually opposite polarities, and making the number of fluctuations of the common mode voltage equal to or less than the specified number of times N. conversion device.
3. The voltage pattern group generation unit generates the plurality of voltage vector patterns by adding a constraint condition such that the number of switching times of each phase in one control period is equal to or less than a predetermined limit number of times. 4. The power conversion device according to 4.
The control device includes:
a current command calculation unit that calculates a current command value;
a current prediction calculation unit that calculates a current predicted value of each voltage vector pattern generated by the voltage pattern group generation unit;
It is characterized by comprising an optimum voltage pattern selection unit that selects a voltage vector pattern that minimizes the error between the current command value and the current predicted value from among the voltage vector patterns generated in the voltage pattern group generation unit. The power conversion device according to claim 3 or claim 4.
The power conversion device according to claim 6, wherein the inverter circuit drives the motor by applying a phase voltage at a connection point of the upper and lower arm switching elements of each phase to the motor.
7. The optimal voltage pattern selection unit selects the optimal voltage vector pattern based on the number of fluctuations of the common mode voltage and an error between the current command value and the predicted current value. power converter.
The optimum voltage pattern selection unit selects the optimum voltage vector pattern by giving a higher priority to the number of fluctuations of the common mode voltage than the error between the current command value and the predicted current value. The power conversion device according to claim 8.