WO2023173943A1 - 一种用于信号完整性仿真的激励信号生成方法及装置 - Google Patents

一种用于信号完整性仿真的激励信号生成方法及装置 Download PDF

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Publication number
WO2023173943A1
WO2023173943A1 PCT/CN2023/073994 CN2023073994W WO2023173943A1 WO 2023173943 A1 WO2023173943 A1 WO 2023173943A1 CN 2023073994 W CN2023073994 W CN 2023073994W WO 2023173943 A1 WO2023173943 A1 WO 2023173943A1
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Prior art keywords
code stream
sequence
victim
attack
segment
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PCT/CN2023/073994
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English (en)
French (fr)
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穆敬彬
吴少校
王朋凯
甘霖
李思霖
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北京地平线机器人技术研发有限公司
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Publication of WO2023173943A1 publication Critical patent/WO2023173943A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD

Definitions

  • the present disclosure relates to the field of signal simulation, and in particular, to an excitation signal generation method and device for signal integrity simulation.
  • SI Signal Integrity
  • PRBS Physical-Random Binary Sequence
  • PRBS codes are usually used to construct excitation signals for transmission channels, and the excitation signals are input to each transmission channel for simulation.
  • the interference information included in the excitation signal constructed using PRBS codes is relatively one-sided. The transmission channel stimulated by the excitation signal has less response to interference, and the simulation results are not accurate enough.
  • the present disclosure provides an excitation signal generation method and device for signal integrity simulation to solve the problem of inaccurate simulation results of traditional excitation signals.
  • the present disclosure provides an excitation signal generation method for signal integrity simulation, including:
  • the victim code stream and the attack code stream are constructed; wherein, the victim code stream and the attack code stream both include multiple code stream segments; the first code stream segment of the victim code stream is the A code stream sequence, the second code stream segment of the victim code stream is the second code stream sequence; the first code stream segment and the second code stream segment of the attack code stream are both the first code stream sequence or the second code stream sequence; The first code stream segment and the second code stream segment of the victim code stream are any two of the multiple code stream segments of the victim code stream, and the first code stream segment and the second code stream segment of the attack code stream are the attack code stream Any two of the multiple code stream segments, the first code stream segment of the victim code stream corresponds to the position of the first code stream segment of the attack code stream, and the second code stream segment of the victim code stream corresponds to the position of the attack code stream The position of the second code stream segment corresponds;
  • the excitation signals corresponding to each branch in the link to be simulated are generated.
  • an excitation signal generation device for signal integrity simulation including:
  • the first building module used to construct the first code stream sequence and the second code stream sequence, where the first code stream sequence is a pseudo-random binary sequence,
  • the second code stream sequence is a sequence obtained by inverting the value of each bit of the first code stream sequence;
  • the second building module used to construct the victim code stream and the attack code stream based on the first code stream sequence and the second code stream sequence constructed by the first building module; wherein the victim code stream and the attack code stream both include multiple code streams segment; the first code stream segment of the victim code stream is the first code stream sequence, and the second code stream segment of the victim code stream is the second code stream sequence; the first code stream segment and the second code stream segment of the attack code stream are both is the first code stream sequence or the second code stream sequence; the first code stream segment and the second code stream segment of the victim code stream are any two of the multiple code stream segments of the victim code stream, and the first code stream segment of the attack code stream The code stream segment and the second code stream segment are any two of the multiple code stream segments of the attack code stream.
  • the position of the first code stream segment of the victim code stream corresponds to the position of the first code stream segment of the attack code stream.
  • the victim code stream The position of the second code stream segment of the code stream corresponds to the position of the second code stream segment of the attack code stream
  • Excitation signal generation module used to generate excitation signals corresponding to each branch in the link to be simulated based on the victim code stream and attack code stream constructed by the second building module.
  • the present disclosure provides a computer-readable storage medium.
  • the storage medium stores a computer program.
  • the computer program is used to execute the excitation signal generation method for signal integrity simulation in any embodiment of the first aspect.
  • an electronic device including:
  • Memory used to store instructions executable by the processor
  • a processor configured to read executable instructions from the memory and execute the executable instructions to implement the excitation signal generation method for signal integrity simulation in any embodiment of the first aspect.
  • the excitation signal generation method and device for signal integrity simulation can construct an excitation signal.
  • the excitation signal is constructed based on a pseudo-random binary sequence, so it can stimulate reflections and inter-symbol interference. and general crosstalk.
  • the excitation signal also includes odd-mode excitation and even-mode excitation. After the excitation signal is input to the link to be simulated, the odd-mode crosstalk and even-mode crosstalk effects can be stimulated, and the generated interference information is relatively comprehensive.
  • the present disclosure constructs corresponding excitation signals for each branch, so that the simulation results of each branch can be quickly obtained, and the accuracy of the simulation is greatly improved.
  • Figure 1 is a transmission channel modeling method provided by an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a model formed after modeling a transmission channel provided by an exemplary embodiment of the present disclosure.
  • FIG. 3 is a schematic flowchart of an excitation signal generation method for signal integrity simulation provided by an exemplary embodiment of the present disclosure.
  • Figure 4 is a schematic flowchart of constructing an attack code flow provided by an exemplary embodiment of the present disclosure.
  • FIG. 5 is a schematic flowchart of determining simulation excitation time provided by an exemplary embodiment of the present disclosure.
  • Figure 6 is an excitation signal generation device for signal integrity simulation provided by an exemplary embodiment of the present disclosure.
  • Figure 7 is another excitation signal generation device for signal integrity simulation provided by an exemplary embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure.
  • the transmission channel refers to the channel specifically used for signal transmission in the circuit structure.
  • High-speed circuits as large-scale and ultra-large-scale integrated circuits, are also a type of circuit and also have the above problems.
  • reflection is an echo on a transmission line. That is, part of the signal power (voltage and current) is transmitted to the line and reaches the load, and the other part of the signal power is reflected back to the source. Reflections are generally caused by the impedance mismatch between the source and load ends of the transmission line. Variations in cabling geometry, incorrect wire termination, transmission through connectors, and power plane discontinuities can all cause such reflections.
  • Crosstalk is the noise on the line caused by the coupling of mutual inductance and mutual capacitance between transmission lines.
  • Crosstalk includes odd mode (Odd) crosstalk and even mode (Even) crosstalk.
  • Inter-code interference Affected by system transmission characteristics, the pulse waveforms of adjacent symbols may overlap each other. This overlap between adjacent symbols is called inter-code interference.
  • signal integrity simulation can be performed.
  • the specific simulation steps can be: model the transmission channel, input the excitation signal to the modeled transmission channel, and observe the time of the excitation signal after passing through a section of the transmission channel.
  • Domain waveform or eye diagram to determine the quality of the circuit transmission channel.
  • the time domain is used to describe the relationship between physical signals and time.
  • the time domain waveform of a signal can express the change of the signal over time, and the waveforms of each symbol are overlapped together using cumulative superposition.
  • the “eye”-shaped waveform formed after superposition is the Eye Diagram.
  • the eye diagram contains a wealth of information. The impact of signal interference can be observed from the eye diagram, which reflects the overall characteristics of the digital signal, thereby estimating the quality of the system.
  • the excitation signal for signal integrity simulation is generally composed of PRBS codes.
  • the excitation signal composed of PRBS codes can reflect the comprehensive impact of reflection, inter-symbol interference and crosstalk to a certain extent, it is difficult to simulate more complex situations, such as odd-mode crosstalk and even-mode crosstalk. Odd-mode crosstalk and even-mode crosstalk are important factors in evaluating Eye Width. Therefore, the excitation signal constructed by PRBS code is used for simulation.
  • the excitation signal constructed by PRBS code includes relatively one-sided interference information and cannot accurately judge the signal. Completeness, simulation results are not accurate enough.
  • the present disclosure provides an excitation signal generation method for signal integrity simulation.
  • the excitation signal generated by this method can cover relatively complex scenarios such as reflection, inter-symbol interference, general crosstalk, odd mode crosstalk, even mode crosstalk, etc.
  • the excitation signal generated by the above method is applied to the During the signal integrity simulation process, the accuracy of the simulation results can be improved.
  • the transmission channel can be modeled and analyzed by extracting S parameters.
  • S parameter (S parameter, scattering parameter) is a network parameter based on the relationship between incident waves and reflected waves.
  • the S parameters reflect the information of the transmission channel through the reflected signal of the device port and the signal transmitted from this port to another port. Specific information such as loss, impedance continuity, reflection, delay, crosstalk, etc. of the interconnection channel.
  • each port and the interconnection between ports are realized by modeling the transmission channel.
  • a transmission channel modeling method is provided according to an exemplary embodiment of the present disclosure.
  • FIG. 2 a schematic diagram of a model formed after modeling a transmission channel is provided according to an exemplary embodiment of the present disclosure. Steps to model a transmission channel can include:
  • Step 110 Model according to the physical structure of the transmission channel. Including setting the physical properties of the model (such as stacking structure, material properties, length, width, and height, etc.).
  • modeling the transmission channel can include modeling various passive components in the entire transmission channel. In the complete circuit structure, it is generally divided into passive parts and active parts according to whether a power supply is needed. , the channel formed for the passive part is the transmission channel.
  • Passive components can work without being connected to a power source and receiving corresponding signals in circuit design. Passive components can be packages, printed circuit boards (PCBs), connectors, discrete devices, etc. Among them, discrete devices are mainly resistors, inductors and capacitors.
  • Step 120 Establish the excitation port for the signal to be extracted.
  • step 120 sets an excitation port for the transmission channel to be simulated, and the excitation port is used to input the excitation signal and extract S parameters.
  • Step 130 Set the electromagnetic field solution parameters.
  • the solution parameters may include solution frequency, convergence conditions, radiation boundaries, etc., which are not specifically limited in this disclosure.
  • Step 140 Solve the electromagnetic field.
  • the solved model can be stored in the form of a scattering parameter (S parameter) file.
  • Step 150 Cascade all models to build a complete link to be simulated.
  • Step 160 Add sender and receiver active models.
  • the active model can be an IBIS model (Input/Output Buffer Information Specification, IBIS) or a spice model.
  • IBIS Input/Output Buffer Information Specification
  • an excitation signal composed of a certain code pattern can be applied to the transmitter for transient circuit simulation, and then the received time domain waveform or eye diagram can be viewed at the receiver.
  • steps 110 to 160 can be completed by relying on EDA (Electronic Design Automation, Electronic Design Automation) tools.
  • EDA Electronic Design Automation, Electronic Design Automation
  • FIG. 3 is a schematic flowchart of an excitation signal generation method for signal integrity simulation provided by an exemplary embodiment of the present disclosure. The method Includes the following steps:
  • Step 210 Construct the first code stream sequence and the second code stream sequence
  • the first code stream sequence P is a pseudo-random binary sequence
  • the second code stream sequence P' is a sequence obtained by inverting the value of each bit of the first code stream sequence P.
  • the PRBS code (pseudo-random binary sequence) contains a certain combination of 0 and 1, and the probability of occurrence of 0 and 1 presents a certain randomness.
  • the use of PRBS code can effectively combine the reflection and When inter-code interference occurs, it can also reflect certain crosstalk information. Therefore, the first code stream sequence and the second code stream sequence constructed by the present disclosure relying on the PRBS code can be used as the basis for constructing the excitation signal to facilitate subsequent use of the excitation signal for signal integrity simulation.
  • the first code stream sequence may be PRBS(N), where the value of N represents the total number of 0s and 1s in the first code stream sequence, and N may be a natural number other than 0.
  • N may be a natural number other than 0.
  • PRBS7 is used to construct the first code stream sequence
  • N is 127, that is, the length of the first code stream sequence is 127 bits.
  • PRBS(N) of a set of N-bit code streams be the first code stream sequence P, and invert each bit in the first code stream sequence P to obtain a new set of code stream sequences, that is, the second code stream sequence.
  • Stream sequence P' During the inversion process, if the original bit in the first code stream sequence P is 1, it will become 0 after inversion. If the original bit in the first code stream sequence P is 0, it will become 1 after inversion. For example, four bits of the first code stream sequence P are 1011, and the second code stream sequence P' obtained after inversion is 0100.
  • step 210 a modeling step may also be included.
  • the structure of the target circuit is modeled, and the link to be simulated corresponding to the structure of the target circuit is obtained.
  • the link to be simulated may include multiple branches.
  • the structure of the target circuit is generally complex and can include multiple adjacent transmission channels. Therefore, the link to be simulated obtained after modeling the structure of the target circuit can include multiple branches, and there can be multiple branches between them. adjacent positional relationship.
  • the process of modeling the structure of the target circuit can be performed according to steps 110 to 160, and the link to be simulated is the simulation model formed after modeling.
  • Step 220 Construct a victim code stream and an attack code stream according to the first code stream sequence and the second code stream sequence.
  • the victim code stream V and the attack code stream A both include multiple code stream segments; the first code stream segment of the victim code stream V is the first code stream sequence, and the second code stream segment of the victim code stream V is the second code stream sequence.
  • the first code stream segment of code stream V corresponds to the position of the first code stream segment of attack code stream A
  • the second code stream segment of victim code stream V corresponds to the position of the second code stream segment of attack code stream A.
  • the victim code stream V and the attack code stream A can be used to form an odd mode excitation or an even mode excitation between the corresponding two branches.
  • the first code stream sequence is 1011
  • the second code stream sequence is 0100
  • the first code stream segment of the victim code stream V is the first code stream sequence
  • the second code stream segment of the victim code stream V is the second code stream
  • the attack code stream A can be 10111011 or 01000100.
  • the attack code stream A is 10111011
  • the position between the attack code stream A and the victim code stream V can be formed at the position of the first code stream segment.
  • Even mode excitation can form an odd mode excitation at the position of the second code stream segment.
  • the attack code stream A is 01000100
  • the position between the attack code stream A and the victim code stream V at the first code stream segment can Odd mode excitation is formed, and even mode excitation can be formed at the position of the second code stream segment.
  • the number of code stream segments included in the victim code stream V and the attack code stream A can be designed according to the actual situation, and this disclosure does not specifically limit this.
  • first code stream sequence P and the second code stream sequence P' are only exemplary descriptions and do not describe the actual implementation of the first code stream sequence P and the second code stream sequence P'.
  • the number of digits of 0/1 included and the distribution of 0/1 constitute any limitation.
  • Step 230 Generate excitation signals corresponding to each branch in the link to be simulated based on the victim code stream and the attack code stream.
  • the excitation signal includes the victim code stream V and/or the attack code stream A.
  • the first code stream sequence and the second code stream sequence are constructed with PRBS codes, and then the attack code stream and the victim code stream are respectively constructed based on the first code stream sequence and the second code stream sequence.
  • the excitation signal generation method provided by this disclosure also includes constructing an excitation signal for each branch based on the victim code stream and the attack code stream.
  • the excitation signal includes relatively comprehensive interference information and can stimulate reflection, odd mode crosstalk, even mode crosstalk and For problems such as inter-code interference, the worst case scenario of each branch can be stimulated at once, and the simulation results of each branch can be quickly obtained, and the accuracy of the simulation results will be greatly improved.
  • the method provided by the present disclosure can also be include:
  • Step 310 Construct the third code stream sequence and the fourth code stream sequence.
  • the third code stream sequence H is an all-1 code stream sequence, that is, each bit of the third code stream sequence H is 1.
  • the third code stream sequence H may be 1111.
  • the fourth code stream sequence L is an all-zero code stream sequence, that is, each bit of the fourth code stream sequence L is 0.
  • the fourth code stream sequence L may be 0000.
  • the third code stream sequence H and the fourth code stream sequence can also be all N bits, where N can be a natural number except 0.
  • N is 127, that is, the length of the first code stream sequence P is 127 bits (binary digit, bit).
  • the stream sequences L and N may also be 127, that is, the lengths of the third code stream sequence H and the fourth code stream sequence L are 127 bits.
  • Step 320 Construct an attack code stream based on the third code stream sequence and the fourth code stream sequence.
  • the excitation signal is further constructed based on the attack pattern A composed of the third code stream sequence H and the fourth code stream sequence L.
  • the excitation signal including attack pattern A remains in a high or low state, and there is no state change.
  • the adjacent branch of the branch that inputs the excitation signal including attack pattern A the adjacent branch When the excitation signal contains victim pattern V, the branch containing the excitation signal of attack pattern A will not cause crosstalk problems to its adjacent branches. The adjacent branches will only exhibit inter-symbol interference and/or Reflection problem.
  • third code stream sequence H and the fourth code stream sequence L are only exemplary descriptions and do not describe the third code stream sequence H and the fourth code stream sequence L.
  • the actual number of 0/1 bits included in the third code stream sequence H and the fourth code stream sequence L constitutes no limitation.
  • the attack code stream A may also specifically include the following content:
  • the third code stream segment of the attack code stream is the third code stream sequence
  • the fourth code stream segment of the attack code stream is the fourth code stream sequence
  • the third code stream segment of the attack code stream is the fourth code stream sequence
  • the fourth code stream segment of the attack code stream is the third code stream sequence.
  • the third code stream segment and the fourth code stream segment of the attack code stream A are any two of the multiple code stream segments of the attack code stream A that are different from the first code stream segment and the second code stream segment. That is to say, the multiple code stream segments that constitute the attack code stream A are not limited to the order of the first code stream segment - the second code stream segment - the third code stream segment - the fourth code stream segment.
  • composition of the attack code stream A can be: the first code stream segment and the second code stream segment are both the first code stream sequence P, or both are the second code stream sequence P', and the third code stream segment
  • the stream segment is the third code stream sequence H
  • the fourth code stream sequence is the fourth code stream sequence L, in which the first code stream segment, the second code stream segment, the third code stream segment and the fourth code stream segment are attack Any one of multiple code stream segments of the code stream.
  • examples of attack code stream A are as follows: PPHL, P'P'HL, HP'P'L, HPPL, etc., which are not exhaustive here.
  • the victim code stream V may also specifically include the following content:
  • the third code stream segment of the victim code stream is the first code stream sequence or the second code stream sequence
  • the fourth code stream segment of the victim code stream is the first code stream sequence or the second code stream sequence
  • the third code stream segment and the fourth code stream segment of the victim code stream V are any two of the multiple code stream segments of the victim code stream V that are different from the first code stream segment and the second code stream segment. That is to say, the multiple code stream segments that constitute the victim code stream V are not limited to the order of the first code stream segment - the second code stream segment - the third code stream segment - the fourth code stream segment. Moreover, the position of the third code stream segment of the victim code stream V corresponds to the position of the third code stream segment of the attack code stream A, and the position of the fourth code stream segment of the victim code stream V corresponds to the position of the fourth code stream segment of the attack code stream A. The location corresponds.
  • the composition of the victim code stream V can be: the first code stream segment is the first code stream sequence P, the second code stream segment is the second code stream sequence P', or the first code stream segment is the second code stream sequence P'.
  • the code stream sequence P', the second code stream segment is the first code stream sequence P.
  • the third code stream segment is the first code stream sequence P or the second code stream sequence P', and the fourth code stream segment is the first code stream sequence P or the second code stream sequence P'. That is to say, the victim code stream V at least includes a first code stream sequence P and a second code stream sequence P'. Then, there are 14 combinations of victim code stream V.
  • victim code stream V based on attack code stream A is as follows: when attack code stream A is PPHL, victim code stream V can be PP'PP, PP'PP', PP'P'P, PP'P'P',P'PPP,P'PPP',P'PP'P,P'PP'P'P'. Other situations in which code stream V is victimized will not be listed here.
  • the victim code stream V and the attack code stream A both include four code stream segments
  • the lengths of the victim code stream V and the attack code stream A are 4N
  • N can be a natural number except 0.
  • the attack code stream A provided by the present disclosure may include four code stream segments.
  • the four code stream segments may be the first code stream sequence P, the second code stream sequence P', and the third code stream respectively.
  • the victim code stream V may also include four code stream segments. Among these four code stream segments, two of them are the first code stream sequence and the second code stream sequence, and the other two are the first code stream sequence and/or The second code stream sequence. In this way, the excitation signal formed by the attack code stream A and the victim code stream V can be used to stimulate problems such as odd-mode crosstalk, even-mode crosstalk, inter-symbol interference, and reflection.
  • the attack code stream A provided by the present disclosure may also include only two code stream segments, and the two code stream segments may both be the first code stream sequence or the second code stream sequence.
  • the victim code pattern V may also include only two code stream segments, and the two code stream segments may be the first code stream sequence and the second code stream sequence respectively. In this way, the excitation signal formed by the attack code stream A and the victim code stream V can be used to stimulate problems such as odd-mode crosstalk and even-mode crosstalk.
  • the attack code stream A provided by the present disclosure may also include only two code stream segments.
  • the two code stream segments may be the third code stream sequence and the fourth code stream sequence.
  • the victim code stream V may also be It may include only two code stream segments, and the two code stream segments may be the first code stream sequence and/or the second code stream sequence.
  • the excitation signal formed by the attack code stream A and the victim code stream V can be used to stimulate inter-symbol interference and reflection problems.
  • an attack excitation signal is constructed from the attack code stream A, and a victim excitation signal is formed from the victim code stream V.
  • One branch is selected as the attack line (Aggressor), and the other branch is selected as the victim line (Victim).
  • step 230 may specifically include: each branch includes a first branch and a second branch, the excitation signal corresponding to the first branch contains the attack code stream, and the excitation signal corresponding to the second branch contains the victimization code stream. Code stream, odd mode excitation or even mode excitation is formed between the first branch and the second branch.
  • a certain item of the first excitation signal is a victim code stream
  • the item in the second excitation signal corresponding to the victim code stream of the first excitation signal is an attack code stream
  • first branch and second branch are any two adjacent branches among all the branches of the link to be simulated, and the total number of excitation signals should be equal to the number of branches of the link to be simulated. .
  • the excitation signal generation method for signal integrity simulation may also include:
  • the total number of attack code streams and victim code streams included in each excitation signal is determined.
  • the total number of attack code streams A and victim code streams V included in each excitation signal is greater than or equal to the number of branches.
  • the total number of attack code streams A and victim code streams V included in each excitation signal is the number of items included in the excitation signal.
  • the total number of attack code streams A and victim code streams V included in the excitation signal can be considered as the length of the excitation signal. For example, if the total number of link branches to be simulated is M, then the total number of attack code streams A and victim code streams V included in the excitation signal can be M. In this way, M attack code streams A and victim code streams V are enough to construct different excitation signals for each branch, and each branch includes attack code stream A or victim code stream V. That is to say, each branch The road may be called the victim line.
  • the number of branches is illustrated by examples, as shown in the following content: Can be 4. It should be understood that the examples of the number of branches are only for illustrative purposes. This disclosure is not specifically limited.
  • the excitation signal may include the following:
  • One item of the excitation signal is the victim code stream, and the remaining items are the attack code stream; among the excitation signals corresponding to each branch, the victim code stream appears on different items; or one item of the excitation signal is the attack code stream, and the remaining items are The item is the victim code stream. Between the excitation signals corresponding to each branch, the attack code stream appears on different items.
  • A represents the attack code stream
  • V represents the victim code stream
  • the total number of attack code streams A and victim code streams V of the excitation signal is greater than or equal to 4. If the total number of attack code streams A and victim code streams V is 4, then the four excitation signals corresponding to the four branches can be: the first branch: AAAV, the second branch: AAVA, the third branch: AVAA, The fourth branch: VAAA, can also be: the first branch: VVVA, the second branch: VVAV, the third branch: VAVV, the fourth branch: AVVV.
  • the excitation signal constructed based on the total number of attack code streams A and victim code streams V equal to the number of branches is the most concise excitation signal, and the simulation results obtained based on this excitation signal can more comprehensively reflect Problems with each branch.
  • each excitation signal contains only one attack code stream A or only one victim code stream V
  • each branch has a probability of becoming a victim line.
  • other branches except the victim line are attack lines, which can excite the worst case of each branch at once without the need to determine which branch should be used as the victim line through frequency domain or manual selection, that is, The simulation results formed in this way are not affected by the selection of the victim line.
  • the number of branches as 4 as an example. If the total number of attack code streams A and victim code streams V of the excitation signal is less than 4, for example, 3, then one of the four excitation signals corresponding to the four branches will The following situations are: the first branch: VAA, the second branch: AVA, the third branch: AAV, the fourth branch: VAA.
  • the attack code stream A and the victim code stream V can be formed relative to each other. Corresponding relationship, thereby stimulating odd mode excitation and even mode excitation.
  • the adjacent relationship of each branch is not fixed. The adjacent relationship of the branch becomes the fourth branch-the first branch-the second branch-the third branch.
  • the total number of attack code streams A and victim code streams V of the excitation signals of some branches may be equal to the number of branches, and the total number of attack code streams A and victim code streams V of the excitation signals of the remaining branches
  • the total number can be greater than the number of branches, and adaptive design can be performed according to actual conditions. This disclosure does not specifically limit this.
  • FIG. 5 a schematic flowchart of determining simulation excitation time is provided according to an exemplary embodiment of the present disclosure. As shown in Figure 5, in the method provided by the present disclosure, the following steps are also included after step 230:
  • Step 240 Determine the unit interval time of one symbol in the first code stream sequence.
  • the unit interval (UI) time of one symbol can be recorded as t1.
  • the circuit transmission signal relies on the change of the waveform to identify each bit (unit: bit) of information, then the waveform of this bit of information is called a symbol.
  • symbols with the same time interval are often used to represent a symbol.
  • the waveform representing 0 is one symbol
  • the waveform representing 1 is another symbol.
  • the baud rate represents the number of code elements transmitted per unit time, and is a measure of the symbol transmission rate.
  • One symbol UI is defined as the width of one data bit. For example, in a data stream with a baud rate of 10Gbps, one UI is equal to 100ps; similarly, in a 1.0Gbps data stream, one UI is equal to 1ns.
  • the unit interval time of different symbols in the first code stream sequence is the same.
  • the symbol UI time can be determined as t1.
  • Step 250 Determine the number of symbols contained in the excitation signal.
  • the number of code elements that can be recorded is K.
  • the number of symbols included in an excitation signal specifically depends on the number of the first code stream sequence P, the second code stream sequence P', the third code stream sequence H and the fourth code stream sequence L it includes.
  • Step 260 Determine the simulation excitation time based on the number of symbols and the unit interval time of one symbol; where the simulation excitation time is used to indicate the duration of the excitation signal for simulation.
  • the simulation excitation time be T
  • K represents the number of symbols contained in the excitation signal
  • t1 represents the unit interval time of one symbol.
  • the simulation excitation time can be determined according to step 240 to step 260. In this way, the simulation excitation time is the most efficient time for simulation.
  • the method provided by the present disclosure constructs a first code stream sequence and a second code stream sequence based on a pseudo-random binary sequence, and constructs a third code stream sequence of all 1s and a fourth code stream sequence of all 0s. Based on the first code stream sequence , the second code stream sequence, the third code stream sequence and the fourth code stream sequence to construct the attack code stream and the victim code stream, and then construct an excitation signal for each branch based on the attack code stream and the victim code stream. You can change the maximum number of each branch at one time All bad situations are stimulated, simulation results can be obtained quickly, and the simulation results are highly accurate.
  • the present disclosure in order to verify the accuracy of the victim code stream V and the attack code stream A, can perform the following verification steps: first select three adjacent branches, recorded from top to bottom as Trace1, Trace2 and Trace3. Assign Trace2 to the victim code stream V as an incentive, and assign Trace1 and Trace3 to the attack code stream A as an incentive. In this way, reflection, inter-code interference, general crosstalk and odd mode crosstalk can be formed between the victim code stream V and the attack code stream A. Even-mode crosstalk, etc., by observing the eye diagram results at this time, you can verify the accuracy of the victim code stream V and the attack code stream A.
  • an excitation signal generation device for signal integrity simulation is provided according to an exemplary embodiment of the present disclosure.
  • the device may be a server or a module provided on the server, and is used to implement the foregoing method embodiments. all or part of its functionality.
  • the excitation signal generating device includes: a first building module 501, a second building module 502, and an excitation signal generating module 503.
  • the first building module 501 is used to construct a first code stream sequence and a second code stream sequence, where the first code stream sequence is a pseudo-random binary sequence, and the second code stream sequence is a sequence of each code stream of the first code stream sequence. The sequence obtained by inverting the value of one bit.
  • the second building module 502 is configured to construct a victim code stream and an attack code stream based on the first code stream sequence and the second code stream sequence constructed by the first building module 501 .
  • both the victim code stream and the attack code stream include multiple code stream segments; the first code stream segment of the victim code stream is the first code stream sequence, and the second code stream segment of the victim code stream is the second code stream sequence; the attack code stream The first code stream segment and the second code stream segment of the code stream are both the first code stream sequence or the second code stream sequence; the first code stream segment and the second code stream segment of the victim code stream are multiple parts of the victim code stream.
  • any two of the code stream segments, the first code stream segment and the second code stream segment of the attack code stream are any two of the multiple code stream segments of the attack code stream, and the first code stream segment of the victim code stream is the same as
  • the position of the first code stream segment of the attack code stream corresponds to the position of the second code stream segment of the victim code stream and the position of the second code stream segment of the attack code stream.
  • the excitation signal generation module 503 is used to generate excitation signals corresponding to each branch in the link to be simulated based on the victim code stream and attack code stream constructed by the second building module 502 .
  • generating excitation signals corresponding to each branch in the link to be simulated according to the victim code stream and the attack code stream includes: each branch includes the first branch and the third branch. Two branches.
  • the excitation signal corresponding to the first branch contains the attack code stream, and the excitation signal corresponding to the second branch contains the victim code stream.
  • An odd mode excitation or an even mode is formed between the first branch and the second branch. excitation.
  • FIG. 7 is another excitation signal generation device for signal integrity simulation provided by an exemplary embodiment of the present disclosure.
  • the excitation signal generation device provided by the present disclosure also includes a first calculation module 504.
  • the first calculation module 504 is used to determine the total number of attack code streams and victim code streams included in each excitation signal according to the number of branches.
  • the attack code stream and the victim code stream are used as items of the excitation signal to form an excitation signal.
  • One item of the excitation signal is the victim code stream, and the remaining items are the attack code stream; each branch Between the corresponding excitation signals, the victim code stream appears in different items; or, one item of the excitation signal is the attack code stream, and the remaining items are the victim code stream. Between the corresponding excitation signals of each branch, the attack code stream appears. Now on a different item.
  • the excitation signal generation device also includes a second calculation module 505.
  • the second calculation module 505 Used to: determine the unit interval time of a symbol in the first code stream sequence;
  • the simulation excitation time is determined; where the simulation excitation time is used to indicate the length of time the excitation signal is used for simulation.
  • the first building module 501 is also used to: construct a third code stream sequence and a fourth code stream sequence.
  • the third code stream sequence is an all-1 code stream.
  • sequence, the fourth code stream sequence is an all-0 code stream sequence;
  • the second building module 502 is also used to construct an attack code stream according to the third code stream sequence and the fourth code stream sequence.
  • the third code stream segment of the attack code stream is the third code stream sequence, and the fourth code stream segment of the attack code stream is the fourth code stream sequence; or, the attack code The third code stream segment of the stream is the fourth code stream sequence, and the fourth code stream segment of the attack code stream is the third code stream sequence.
  • the third code stream segment of the victim code stream is the first code stream sequence or the second code stream sequence
  • the fourth code stream segment of the victim code stream is the first code stream. sequence or second stream sequence.
  • the electronic device may be either or both of the first device and the second device, or a stand-alone device independent of them.
  • the stand-alone device may communicate with the first device and the second device to receive the collected information from them. input signal.
  • FIG. 8 illustrates a block diagram of an electronic device according to the present disclosure.
  • the electronic device 11 includes one or more processors 111 and memories 112 .
  • the processor 111 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 11 to perform desired functions.
  • CPU central processing unit
  • the processor 111 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 11 to perform desired functions.
  • Memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory.
  • the volatile memory may include, for example, random access memory (RAM) and/or cache memory (cache).
  • the non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.
  • One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 111 may execute the program instructions to implement the various embodiments of the present disclosure described above for signal integrity simulation. Excitation signal generation methods and/or other desired functionality.
  • Various contents such as input signals, signal components, noise components, etc. may also be stored in the computer-readable storage medium.
  • the electronic device 11 may further include an input device 113 and an output device 114, and these components are interconnected through a bus system and/or other forms of connection mechanisms (not shown).
  • the input device 113 may be the above-mentioned microphone or microphone array, Input signal for capturing sound sources.
  • the input device 113 may be a communication network connector for receiving the collected input signals from the first device and the second device.
  • the input device 13 may also include, for example, a keyboard, a mouse, and the like.
  • the output device 114 can output various information to the outside, including determined distance information, direction information, etc.
  • the output device 14 may include, for example, a display, a speaker, a printer, a communication network and remote output devices connected thereto, and the like.
  • the electronic device 11 may also include any other appropriate components depending on the specific application.
  • embodiments of the present disclosure may also be a computer program product, which includes computer program instructions that, when executed by a processor, cause the processor to perform the “exemplary method” described above in this specification
  • the steps in the excitation signal generation method for signal integrity simulation according to various embodiments of the present disclosure are described in Sec.
  • the computer program product may have program code for performing the operations of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and Includes conventional procedural programming languages, such as the "C" language or similar programming languages.
  • the program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server execute on.
  • embodiments of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon.
  • the computer program instructions when executed by a processor, cause the processor to execute the above-mentioned “example method” part of this specification.
  • the steps in the excitation signal generation method for signal integrity simulation according to various embodiments of the present disclosure are described in .
  • the computer-readable storage medium may be any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may include, for example, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: electrical connection with one or more conductors, portable disk, hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • each component or each step can be decomposed and/or recombined. These decompositions and/or recombinations should be considered equivalent versions of the present disclosure.

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Abstract

公开了一种用于信号完整性仿真的激励信号生成方法及装置，所述方法包括：构建第一码流序列及第二码流序列，根据第一码流序列及第二码流序列，构建受害码流及攻击码流，之后根据受害码流及攻击码流，生成待仿真链路中各支路分别对应的激励信号。本方法以伪随机二进制序列为基础，为待仿真链路构建了激励信号，在将该激励信号输入至待仿真链路后，可以激发奇模串扰、偶模串扰、一般串扰、码间干扰及反射，还可以快速得到每一支路的仿真结果。因此，激励信号包括的干扰信息较为全面，仿真结果准确。

Description

一种用于信号完整性仿真的激励信号生成方法及装置
本公开要求在2022年3月16日提交的、申请号为202210258087.7、发明名称为“一种用于信号完整性仿真的激励信号生成方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及信号仿真领域，尤其涉及一种用于信号完整性仿真的激励信号生成方法及装置。
背景技术
信号完整性(Signal Integrity，SI)是用于评估信号在传输路径上传输质量的度量标准，在构建高速电路时，需要考虑信号完整性的问题。一般的，可以对高速电路进行仿真，观察一个激励信号经过一段传输通道后的时域波形或者眼图，进而判断信号完整性。在构建该激励信号时，需要考虑如何使该激励信号包括多种干扰信息，以激发出传输通道面对不同干扰时的反应。
通常使用PRBS(Pseudo-Random Binary Sequence，伪随机二进制序列)码为传输通道构建激励信号，将激励信号输入至各传输通道进行仿真。但是，使用PRBS码构建的激励信号包括的干扰信息较为片面，受激励信号激发的传输通道面对干扰的反应较少，仿真结果不够准确。
发明内容
本公开提供一种用于信号完整性仿真的激励信号生成方法及装置，以解决传统激励信号仿真结果不准确的问题。
第一方面，本公开提供一种用于信号完整性仿真的激励信号生成方法，包括：
构建第一码流序列及第二码流序列，其中，第一码流序列为伪随机二进制序列，第二码流序列为对第一码流序列的每一位的值取反所得到的序列；
根据第一码流序列及第二码流序列，构建受害码流及攻击码流；其中，受害码流及攻击码流均包括多个码流段；受害码流的第一码流段为第一码流序列，受害码流的第二码流段为第二码流序列；攻击码流的第一码流段及第二码流段均为第一码流序列或第二码流序列；受害码流的第一码流段及第二码流段为受害码流的多个码流段中的任意两个，攻击码流的第一码流段及第二码流段为攻击码流的多个码流段中的任意两个，受害码流的第一码流段与攻击码流的第一码流段的位置相对应，受害码流的第二码流段与攻击码流的第二码流段的位置相对应；
根据受害码流及攻击码流，生成待仿真链路中各支路分别对应的激励信号。
第二方面，本公开还提供一种用于信号完整性仿真的激励信号生成装置，包括：
第一构建模块：用于构建第一码流序列及第二码流序列，其中，第一码流序列为伪随机二进制序列， 第二码流序列为对第一码流序列的每一位的值取反所得到的序列；
第二构建模块：用于根据第一构建模块构建的第一码流序列及第二码流序列，构建受害码流及攻击码流；其中，受害码流及攻击码流均包括多个码流段；受害码流的第一码流段为第一码流序列，受害码流的第二码流段为第二码流序列；攻击码流的第一码流段及第二码流段均为第一码流序列或第二码流序列；受害码流的第一码流段及第二码流段为受害码流的多个码流段中的任意两个，攻击码流的第一码流段及第二码流段为攻击码流的多个码流段中的任意两个，受害码流的第一码流段与攻击码流的第一码流段的位置相对应，受害码流的第二码流段与攻击码流的第二码流段的位置相对应；
激励信号生成模块：用于根据第二构建模块构建的受害码流及攻击码流，生成待仿真链路中各支路分别对应的激励信号。
第三方面，本公开提供一种计算机可读存储介质，存储介质存储有计算机程序，计算机程序用于执行上述第一方面任一实施方式中的用于信号完整性仿真的激励信号生成方法。
第四方面，本公开提供一种电子设备，包括：
处理器；
用于存储处理器可执行指令的存储器；
处理器，用于从存储器中读取可执行指令，并执行可执行指令以实现上述第一方面任一实施方式中的用于信号完整性仿真的激励信号生成方法。
由以上技术方案可知，本公开提供的用于信号完整性仿真的激励信号生成方法及装置，可以构建激励信号，该激励信号是基于伪随机二进制序列构建的，因此可以激发出反射、码间干扰及一般串扰。激励信号中还包括奇模激励及偶模激励，在将激励信号输入至待仿真链路后，能够激发出奇模串扰及偶模串扰效应，生成的干扰信息较为全面。同时，本公开为每一条支路均构建相应的激励信号，可以快速得到每一支路的仿真结果，仿真的准确性大大提高。
附图说明
通过结合附图对本公开进行更详细的描述，本公开的上述以及其他目的、特征和优势将变得更加明显。附图用来提供对本公开的进一步理解，并且构成说明书的一部分，与本公开一起用于解释本公开，并不构成对本公开的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
图1是本公开一示例性实施例提供的传输通道建模方法。
图2是本公开一示例性实施例提供的一种对传输通道建模后形成的模型示意图。
图3是本公开一示例性实施例提供的用于信号完整性仿真的激励信号生成方法的流程示意图。
图4是本公开一示例性实施例提供的构建攻击码流的流程示意图。
图5是本公开一示例性实施例提供的确定仿真激励时间的流程示意图。
图6是本公开一示例性实施例提供的一种用于信号完整性仿真的激励信号生成装置。
图7是本公开一示例性实施例提供的另一种用于信号完整性仿真的激励信号生成装置。
图8是本公开一示例性实施例提供的电子设备的结构图。
具体实施方式
下面，将参考附图详细地描述根据本公开的示例实施例。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是本公开的全部实施例，应理解，本公开不受这里描述的示例实施例的限制。
申请概述
信号完整性问题主要表现为，在激励信号的边沿变化时，传输通道易发生阻抗不连续、相邻通道间容性耦合和感性耦合、以及通道的衰减等情况，会引发激励信号的反射、串扰和码间干扰等问题，从而导致信号质量变差。其中，传输通道是指电路结构中具体用于信号传输的通道。高速电路作为大规模、超大规模集成电路，也是电路的一种，同样存在上述问题。
具体地，反射(reflection)是在传输线上的回波。即信号功率(电压和电流)的其中一部分传输到线上并到达负载处，信号功率的另一部分被反射回源端。反射一般是由传输线上源端与负载端阻抗不匹配引起的。布线的几何形状、不正确的线端接、经过连接器的传输及电源平面的不连续等因素的变化均会导致此类反射。
串扰(Crosstalk)是传输线之间的互感和互容的耦合引起线上的噪声，其中，串扰包括奇模(Odd)串扰和偶模(Even)串扰等。
码间干扰：受系统传输特性影响，相邻码元的脉冲波形之间可能互相重叠，这种相邻码元间的互相重叠称为码间干扰。
为了评估传输通道的信号完整性，可以进行信号完整性仿真，具体仿真步骤可以为：对传输通道进行建模，对建模后的传输通道输入激励信号，观察激励信号经过一段传输通道后的时域波形或者眼图，以确定电路传输通道的质量。其中，时域(Time domain)用于描述物理信号与时间之间关系，例如一个信号的时域波形可以表达信号随着时间的变化，利用累积叠加的方式将每一个码元的波形重叠到一起，叠加后形成的“眼睛”形状的波形图，即为眼图(Eye Diagram)。眼图包含了丰富的信息，从眼图上可以观察出信号干扰的影响，体现了数字信号整体的特征，从而估计系统优劣程度。
当前，信号完整性仿真的激励信号一般由PRBS码构成。但是，PRBS码构成的激励信号虽然能从一定程度上反映出反射、码间干扰和串扰的综合影响，但是对于更为复杂情况，例如，奇模串扰和偶模串扰等情况很难模拟出来，而奇模串扰和偶模串扰是评价眼宽(Eye Width)的重要因素，因此，采用PRBS码构建的激励信号进行仿真，采用PRBS码构建的激励信号包括的干扰信息较为片面，不能准确判断信号完整性，仿真结果不够准确。
本公开提供一种用于信号完整性仿真的激励信号生成方法，通过该方法生成的激励信号，可以覆盖反射、码间干扰、一般串扰、奇模串扰、偶模串扰等较为复杂的场景，将上述方法生成的激励信号应用至信 号完整性仿真过程中，可以提高仿真结果的准确性。
示例性系统
在对高速电路进行信号完整性仿真的过程中，可以采用提取S参数的方式对传输通道进行建模分析。S参数(S parameter，散射参数)是建立在入射波、反射波关系基础上的网络参数。S参数以器件端口的反射信号以及从该端口传向另一端口的信号来反映传输通道的信息，具体信息例如为互连通道的损耗、阻抗连续性、反射、延时、串扰等。在提取S参数时，需要通过对端口施加激励信号来获得入射信号和反射信号。其中，各个端口以及端口间的互连，依靠对传输通道进行建模来实现。
参见图1，为本公开一示例性实施例提供的传输通道建模方法，参见图2，为本公开一示例性实施例提供的一种对传输通道建模后形成的模型示意图。对传输通道进行建模的步骤可以包括：
步骤110：根据传输通道的物理结构进行建模。包括设置模型的物理属性(如堆叠结构、材料属性、长宽高等)。其中，对传输通道进行建模可以包括对整个传输通道中的各种无源元件(passive component)进行建模，在完整的电路结构中，一般按照是否需要电源划分为无源部分和有源部分，针对无源部分形成的通道即为传输通道。无源元件在电路设计中无需连接电源、接收到相应信号即可工作。无源元件可以为封装(Package)、印制电路板(PCB)、连接器(Connector)、分立器件等。其中，分立器件(Discrete device)主要是电阻类、电感类和电容类元件。
步骤120：建立所要提取信号的激励端口。
具体的，步骤120对待仿真的传输通道，设置激励端口，该激励端口用于输入激励信号以及提取S参数。
步骤130：设置电磁场求解参数。其中，求解参数可以包括求解频率、收敛条件以及辐射边界等，本公开对此不做具体限定。
步骤140：电磁场求解。求解后的模型可以以散射参数(S parameter)文件形式存储。
步骤150：对所有模型进行级联，搭建完整的待仿真链路。
步骤160：添加发送端和接收端有源模型。
其中，有源模型可以为IBIS模型(Input/Output Buffer Information Specification，IBIS)或spice模型。
建模完成后，可以在发送端施加由某种码型构成的激励信号进行瞬态电路仿真，之后在接收端查看接收的时域波形或者眼图。
在一些实现方式中，步骤110-步骤160可以依靠EDA(Electronic design automation，电子设计自动化)工具完成。
示例性方法
图3为本公开一示例性实施例提供的用于信号完整性仿真的激励信号生成方法的流程示意图，该方法 包括以下步骤：
步骤210：构建第一码流序列及第二码流序列；
其中，第一码流序列P为伪随机二进制序列，第二码流序列P'为对第一码流序列P的每一位的值取反得到的序列。
在ITU-TV.29规范中，PRBS码(伪随机二进制序列)中包含一定0和1的组合，并且0和1的出现的几率呈现一定的随机性，使用PRBS码可以很好的将反射和码间干扰的情况激发出来，也能反映一定的串扰信息。因此，本公开依靠PRBS码构建的第一码流序列及第二码流序列，可以作为构建激励信号的基础，以利于后续使用激励信号进行信号完整性仿真。
本公开中，第一码流序列可以为PRBS(N)，其中N的数值代表第一码流序列中0以及1的总位数，N可以为除0外的自然数。例如，以PRBS7构建第一码流序列，则N为127，即第一码流序列的长度为127比特。
具体地，记一组N位码流的PRBS(N)为第一码流序列P，对第一码流序列P中的每一位取反得到一组新的码流序列，即第二码流序列P'。取反过程中，第一码流序列P中原始位为1，则取反后变为0，第一码流序列P中原始位为0，则取反后变为1。例如第一码流序列P的其中四位为1011，则取反后得到的第二码流序列P'为0100。
本公开中，在执行步骤210之前，还可以包括建模的步骤。
具体地，对目标电路的结构进行建模，得到目标电路的结构对应的待仿真链路。
其中，待仿真链路可以包括多条支路。
目标电路的结构一般较为复杂，可以包括多条相邻的传输通道，因此对目标电路的结构进行建模后得到的待仿真链路可以包括多条支路，且多条支路之间可以存在相邻的位置关系。在一些实现方式中，对目标电路的结构进行建模的过程可以按照步骤110-步骤160进行，待仿真链路即为建模后形成的仿真模型。
步骤220：根据所述第一码流序列及所述第二码流序列，构建受害码流及攻击码流。
其中，受害码流V及攻击码流A均包括多个码流段；受害码流V的第一码流段为第一码流序列，受害码流V的第二码流段为第二码流序列；攻击码流A的第一码流段及第二码流段均为第一码流序列或第二码流序列；受害码流V的第一码流段及第二码流段为受害码流V的多个码流段中的任意两个，攻击码流A的第一码流段及第二码流段为攻击码流A的多个码流段中的任意两个，受害码流V的第一码流段与攻击码流A的第一码流段的位置相对应，受害码流V的第二码流段与攻击码流A的第二码流段的位置相对应。
在本公开中，受害码流V及攻击码流A可以用于在各自对应的两支路之间形成奇模激励或者偶模激励。
例如，第一码流序列为1011，第二码流序列为0100，以受害码流V的第一码流段为第一码流序列，受害码流V的第二码流段为第二码流序列为例，则受害码流V为10110100，那么攻击码流A可以为10111011或01000100。在攻击码流A为10111011时，攻击码流A与受害码流V之间在第一码流段的位置可以形成 偶模激励，在第二码流段的位置可以形成奇模激励，相应的，在攻击码流A为01000100时，攻击码流A与受害码流V之间在第一码流段的位置可以形成奇模激励，在第二码流段的位置可以形成偶模激励。
其中，受害码流V及攻击码流A包括的码流段的个数，可以根据实际情况进行设计，本公开对此不做具体限定。
应理解的是，上述内容对第一码流序列P及第二码流序列P'进行的举例，仅为示例性描述，并不对第一码流序列P及第二码流序列P'的实际包括的0/1的位数及0/1的分布构成任何限定。
步骤230：根据受害码流及攻击码流，生成待仿真链路中各支路分别对应的激励信号。
也就是说，激励信号中包括受害码流V和/或攻击码流A。
本公开提供的激励信号生成方法中，以PRBS码构建第一码流序列及第二码流序列，之后根据第一码流序列和第二码流序列分别构建攻击码流、受害码流。本公开提供的激励信号生成方法还包括根据受害码流及攻击码流为每一条支路构建激励信号，该激励信号包括的干扰信息较为全面，可以激发出反射、奇模串扰、偶模串扰及码间干扰等问题，可以一次性将每条支路的最差情况激发出来，快速得到每一条支路的仿真结果，并且仿真结果的准确性会有极大提高。
在上述图3所示实施例的基础上，如图4所示，步骤220根据第一码流序列及第二码流序列，构建受害码流及攻击码流之后，本公开提供的方法还可以包括：
步骤310：构建第三码流序列及第四码流序列。
其中，第三码流序列H为全1码流序列，即第三码流序列H的每一位均为1，例如，第三码流序列H可以为1111。第四码流序列L为全0码流序列，即第四码流序列L的每一位均为0，例如第四码流序列L可以为0000。为了与第一码流序列P及第二码流序列P'相匹配，在第一码流序列P及第二码流序列P'均为N位时，第三码流序列H及第四码流序列L也可以均为N位，其中N可以为除0外的自然数。例如，以PRBS7构建第一码流序列P时，N为127，即第一码流序列P的长度为127比特(binary digit,bit)，相应地，对于第三码流序列H及第四码流序列L，N也可以为127，即第三码流序列H及第四码流序列L的长度为127比特。
步骤320：根据第三码流序列及第四码流序列，构建攻击码流。
例如，第三码流序列H为1111，第四码流序列L为0000，第三码流序列H及第四码流序列L的每一位没有状态的变化，即第三码流序列H及第四码流序列L的每一位均为1或者每一位均为0，那么，基于第三码流序列H及第四码流序列L构成的攻击码型A来进一步构建激励信号，该包括攻击码型A的激励信号一直保持在高或者低的状态，不存在状态变化，对于输入有该包括攻击码型A的激励信号的支路的相邻支路，在该相邻支路的激励信号中包含受害码型V时，该包括攻击码型A的激励信号的支路不会对其相邻支路激发出串扰问题，该相邻支路仅会表现出码间干扰和/或反射问题。
应理解的是，上述内容对第三码流序列H及第四码流序列L进行的举例，仅为示例性描述，并不对第 三码流序列H及第四码流序列L实际包括的0/1的位数构成任何限定。
本公开提供的激励信号生成方法中，攻击码流A还可以具体包括以下内容：
攻击码流的第三码流段为第三码流序列，攻击码流的第四码流段为第四码流序列；或者，攻击码流的第三码流段为第四码流序列，攻击码流的第四码流段为第三码流序列。
其中，攻击码流A的第三码流段及第四码流段为攻击码流A的多个码流段中区别于第一码流段及第二码流段的任意两个。也就是说，构成攻击码流A的多个码流段，不局限于第一码流段-第二码流段-第三码流段-第四码流段这一顺序。
由上述内容可知，攻击码流A的构成可以是：第一码流段及第二码流段均为第一码流序列P，或二者均为第二码流序列P'，第三码流段为第三码流序列H，第四码流序列为第四码流序列L，其中，第一码流段、第二码流段、第三码流段及第四码流段为攻击码流的多个码流段中的任意一个。那么，对攻击码流A举例如下：PPHL、P'P'HL、HP'P'L、HPPL等等，此处不再穷举。
本公开提供的激励信号生成方法中，受害码流V还可以具体包括以下内容：
受害码流的第三码流段为第一码流序列或第二码流序列，受害码流的第四码流段为第一码流序列或第二码流序列。
其中，受害码流V的第三码流段及第四码流段为受害码流V的多个码流段中区别于第一码流段及第二码流段的任意两个。也就是说，构成受害码流V的多个码流段，不局限于第一码流段-第二码流段-第三码流段-第四码流段这一顺序。并且，受害码流V的第三码流段与攻击码流A的第三码流段的位置相对应，受害码流V的第四码流段与攻击码流A的第四码流段的位置相对应。
由上述内容可知，受害码流V的构成可以是：第一码流段为第一码流序列P，第二码流段为第二码流序列P'，或者第一码流段为第二码流序列P'，第二码流段为第一码流序列P。第三码流段为第一码流序列P或第二码流序列P'，第四码流段为第一码流序列P或第二码流序列P'。也就是说，受害码流V至少包括一个第一码流序列P及一个第二码流序列P'。那么，受害码流V共有14种组合方式。计算公式为：24-2＝14种。以攻击码流A为基础对受害码流V举例如下：当攻击码流A为PPHL，受害码流V可以为PP'PP、PP'PP'、PP'P'P、PP'P'P'、P'PPP、P'PPP'、P'PP'P、P'PP'P'。此处不再穷举受害码流V的其他情况。
这样，当攻击码流A及受害码流V出现在相邻支路的对应位置时，可以同时激发出奇模串扰、偶模串扰、一般串扰、码间干扰及反射的问题。
可以理解的是，当受害码流V及攻击码流A均包括四个码流段时，受害码流V及攻击码流A的长度为4N，N可以为除0外的自然数。
在一些实现方式中，本公开提供的攻击码流A可以包括四个码流段，这四个码流段可以分别为第一码流序列P、第二码流序列P'、第三码流序列H及第四码流序列L。受害码流V也可以包括四个码流段，这四个码流段中，其中两个分别为第一码流序列及第二码流序列，另两个为第一码流序列和/或第二码流序列。 这样，采用攻击码流A及受害码流V形成的激励信号可以用于激发奇模串扰、偶模串扰、码间干扰及反射等问题。
在另一些实现方式中，本公开提供的攻击码流A还可以只包括两个码流段，这两个码流段可以均为第一码流序列或第二码流序列。受害码型V也可以只包括两个码流段，这两个码流段可以分别为第一码流序列及第二码流序列。这样，采用攻击码流A及受害码流V形成的激励信号可以用于激发奇模串扰及偶模串扰等问题。
在另一些实现方式中，本公开提供的攻击码流A还可以只包括两个码流段，这两个码流段可以为第三码流序列及第四码流序列，受害码流V也可以只包括两个码流段，这两个码流段可以为第一码流序列和/或第二码流序列。这样，采用攻击码流A及受害码流V形成的激励信号可以用于激发码间干扰和反射的问题。例如，由该攻击码流A构建形成一个攻击激励信号，由该受害码流V构建形成一个受害激励信号，选择一条支路作为攻击线(Aggressor)，选择另一条支路作为受害线(Victim)，将攻击激励信号输入至攻击线，将受害激励信号输入至受害线，那么，受害线所表现出来的问题即为码间干扰和反射问题。
本公开中，步骤230具体可以包括：各支路中包括第一支路和第二支路，第一支路对应的激励信号中包含攻击码流，第二支路对应的激励信号中包含受害码流，第一支路和第二支路之间形成奇模激励或者偶模激励。
如果第一激励信号的某一项为受害码流，第二激励信号中与第一激励信号的受害码流相对应的项为攻击码流，即确定第一激励信号的其中一项为受害码流，将第二激励信号中、与第一激励信号的受害码流相对应的项确定为攻击码流。那么，当第一激励信号及第二激励信号输入至相邻的两支路后，可以确保在待仿真链路上激发出奇模串扰和偶模串扰。
可以理解的是，上述第一支路及第二支路为待仿真链路的所有支路中任意两个相邻支路，且激励信号的总个数应当等于待仿真链路的支路数。
具体的，本公开提供的用于信号完整性仿真的激励信号生成方法，还可以包括：
根据支路的条数，确定每一激励信号包括的攻击码流及受害码流的总数量。
其中，每一激励信号包括的攻击码流A及受害码流V的总数量，大于等于支路的条数。每一激励信号包括的攻击码流A及受害码流V的总数量，即为激励信号包含的项的项数。
激励信号包括的攻击码流A及受害码流V的总数量，可以认为是该激励信号的长度。例如，待仿真链路支路的总条数为M，那么激励信号包括的攻击码流A及受害码流V的总数量可以为M。这样，M个攻击码流A及受害码流V足以为每一支路构建出不同的激励信号，且每一支路均包括攻击码流A或受害码流V，也就是说，每一条支路均可能称为受害线。
需要说明的是，在本公开中，为了便于描述支路数与激励信号中攻击码流及受害码流总数量之间的关系，对支路数进行了举例说明，如下述内容中支路数可以为4条。应理解对支路数的举例仅为示意性说明， 不对本公开构成具体限定。
具体的，激励信号具体可以包括以下内容：
激励信号的一项为受害码流，其余项为攻击码流；各支路分别对应的激励信号之间，受害码流出现在不同的项上；或者，激励信号的一项为攻击码流，其余项为受害码流，各支路分别对应的激励信号之间，攻击码流出现在不同的项上。
表1
其中，A表示攻击码流，V表示受害码流。
参见表1，为包括攻击码流A及受害码流V的总数量不同的各激励信号的示例。以支路数为4条为例，激励信号的攻击码流A及受害码流V的总数量大于等于4。如果攻击码流A及受害码流V的总数量为4，那么四条支路对应的四个激励信号可以为：第一支路：AAAV、第二支路：AAVA、第三支路：AVAA、第四支路：VAAA，也可以为：第一支路：VVVA、第二支路：VVAV、第三支路：VAVV、第四支路：AVVV。这样，不论四条支路输入了何种激励信号，也不论四条支路的相邻关系如何变化，在相邻支路之间均能形成攻击码流A与受害码流V的对应关系，均可以激发出奇模串扰、偶模串扰、一般串扰、码间干扰、以及反射的问题。也就是说，根据包括的攻击码流A及受害码流V的总数量等于支路条数构建的激励信号，是最为简洁的激励信号，且基于该激励信号得到的仿真结果能较为全面的反映出各个支路的问题。此外，由于每一激励信号上均仅包含一个攻击码流A或者均仅包含一个受害码流V，在向各个支路输入激励信号的情况下，每一支路均有成为受害线的概率，相应地，除该受害线外的其他支路为攻击线，可以使每条支路的最差情况一次性激发出来，无需通过频域或人工选择、判定将哪条支路作为受害线，即采用该方式形成的仿真结果不受受害线选择的影响。
继续参见表1，以支路数为4条为例，如果激励信号的攻击码流A及受害码流V的总数量小于4，例如为3，那么四条支路对应的四个激励信号的一种情况为：第一支路：VAA、第二支路：AVA、第三支路：AAV、第四支路：VAA，各支路之间可以形成攻击码流A和受害码流V相对的对应关系，进而激发出奇模激励和偶模激励。但是各支路的相邻关系不是固定的，支路相邻关系变为第四支路-第一支路-第二支路-第三支路，那么第四支路与第一支路之间没有A和V相对的对应关系，无法激发出奇模激励，只能激发出偶模激励。因此激励信号的攻击码流A受害码流V总数量小于支路总条数的方案，非最佳选择方案。
继续参见表1，以支路数为4条为例，如果激励信号的攻击码流A及受害码流V的总数量大于4，例如为5，那么四条支路对应的四个激励信号的一种情况为：第一支路：VAAAA、第二支路：AVAAA、第 三支路：AAVAA、第四支路：AAAVA。此时，该激励信号能够全面反映问题，并且每一支路均有机会成为受害线，可以使每条支路的最差情况一次性激发出来，仿真结果全面且准确，是较佳的选择方案。
在一些实现方式中，部分支路的激励信号的攻击码流A及受害码流V的总数量可以等于支路的数量，其余部分支路的激励信号的攻击码流A及受害码流V的总数量可以大于支路数，可以根据实际情况进行适应性设计，本公开对此不作具体限定。
参见图5，为本公开一示例性实施例提供的确定仿真激励时间的流程示意图。如图5所示，本公开提供的方法中，步骤230后还包括以下步骤：
步骤240：确定第一码流序列中一个码元的单位间隔时间。
其中，可以记一个码元的单位间隔(Unit Interval，UI)时间为t1。
电路传输信号是靠波形的变化来识别每一位(单位：bit)信息的，那么这一位信息的波形就叫作码元。在数字通信中，常用时间间隔相同的符号来表示一个码元，例如，当用二进制码0和1表示数据时，代表0的波形是一个码元，代表1的波形是另一个码元。波特率表示单位时间内传送的码元符号的个数，它是对符号传输速率的一种度量。一个码元UI定义为一个数据bit的宽度，例如：在一个波特率为10Gbps的数据流中，一个UI就等于100ps；同理，在一个1.0Gbps的数据流中，一个UI等于1ns。对于第一码流序列这样一个二进制序列，二进制的一位就是一个码元。其中，第一码流序列中不同码元的单位间隔时间相同。根据实际信号的波特率可以确定码元UI时间为t1。
步骤250：确定激励信号中包含的码元的个数。
其中，可以记码元的个数为K。一个激励信号中包括的码元的个数具体取决于其包括的第一码流序列P、第二码流序列P'，第三码流序列H及第四码流序列L的数量。
例如，一个激励信号中包括的攻击码流A及受害码流V的总数量为M个，每个攻击码流A或受害码流V中含有4个码流序列(第一码流序列、第二码流序列、第三码流序列或第四码流序列)，每个码流序列含有N个码元，则码元的个数K＝4*N*M＝4NM。
步骤260：基于码元的个数及一个码元的单位间隔时间，确定仿真激励时间；其中，仿真激励时间用于表示激励信号用于仿真的时长。
其中，记仿真激励时间为T，那么仿真激励时间T的计算公式为：T＝K*t1。其中，K表示激励信号中包含的码元的个数，t1表示一个码元的单位间隔时间。
为了在仿真模型中，将激励信号的每一比特的影响在仿真中激发出来，可以按照步骤240-步骤260确定仿真激励时间。这样，仿真激励时间是进行仿真时效率最高的时间。
本公开提供的方法，基于伪随机二进制序列构建第一码流序列及第二码流序列，并构建全1的第三码流序列及全0的第四码流序列，基于第一码流序列、第二码流序列、第三码流序列及第四码流序列构建攻击码流及受害码流，之后根据攻击码流及受害码流为每一支路构建激励信号。可以一次性将每一支路的最 差情况都激发出来，快速得到仿真结果，且仿真结果准确性高。
在一些实现方式中，本公开为了验证受害码流V及攻击码流A的准确性，可以进行如下验证步骤：首先挑选三条相邻的支路，由上至下记为Trace1、Trace2及Trace3，将Trace2赋予受害码流V作为激励，将Trace1及Trace3赋予攻击码流A作为激励，这样，受害码流V及攻击码流A之间可以形成反射、码间干扰、一般串扰及奇模串扰、偶模串扰等，此时观察眼图结果，即可验证受害码流V及攻击码流A的准确性。
参见图6，为本公开一示例性实施例提供的一种用于信号完整性仿真的激励信号生成装置，该装置可以是一种服务器或者设置在服务器上的模块，用于实现前述方法实施例的全部或部分功能。具体的，该激励信号生成装置包括：第一构建模块501、第二构建模块502及激励信号生成模块503。
具体的，第一构建模块501用于构建第一码流序列及第二码流序列，其中，第一码流序列为伪随机二进制序列，第二码流序列为对第一码流序列的每一位的值取反所得到的序列。
第二构建模块502用于根据第一构建模块501构建的第一码流序列及第二码流序列，构建受害码流及攻击码流。
其中，受害码流及攻击码流均包括多个码流段；受害码流的第一码流段为第一码流序列，受害码流的第二码流段为第二码流序列；攻击码流的第一码流段及第二码流段均为第一码流序列或第二码流序列；受害码流的第一码流段及第二码流段为受害码流的多个码流段中的任意两个，攻击码流的第一码流段及第二码流段为攻击码流的多个码流段中的任意两个，受害码流的第一码流段与攻击码流的第一码流段的位置相对应，受害码流的第二码流段与攻击码流的第二码流段的位置相对应。
激励信号生成模块503用于根据第二构建模块502构建的受害码流及攻击码流，生成待仿真链路中各支路分别对应的激励信号。
可选的，在本公开的一种实现方式中，根据受害码流及攻击码流，生成待仿真链路中各支路分别对应的激励信号包括：各支路中包括第一支路和第二支路，第一支路对应的激励信号中包含攻击码流，第二支路对应的激励信号中包含受害码流，第一支路和第二支路之间形成奇模激励或者偶模激励。
可选的，参见图7，是本公开一示例性实施例提供的另一种用于信号完整性仿真的激励信号生成装置。本公开提供的激励信号生成装置，还包括第一计算模块504，第一计算模块504用于：根据支路的条数，确定每一激励信号包括的攻击码流及受害码流的总数量。
可选的，在本公开的一种实现方式中，攻击码流及受害码流作为激励信号的项形成激励信号，激励信号的一项为受害码流，其余项为攻击码流；各支路分别对应的激励信号之间，受害码流出现在不同的项上；或者，激励信号的一项为攻击码流，其余项为受害码流，各支路分别对应的激励信号之间，攻击码流出现在不同的项上。
可选的，继续参见图7，本公开提供的激励信号生成装置，还包括第二计算模块505，第二计算模块505 用于：确定第一码流序列中一个码元的单位间隔时间；
确定激励信号中包含的码元的个数；
基于码元的个数及一个码元的单位间隔时间，确定仿真激励时间；其中，仿真激励时间用于表示激励信号用于仿真的时长。
可选的，继续参见图7，本公开提供的激励信号生成装置，第一构建模块501还用于：构建第三码流序列及第四码流序列，第三码流序列为全1码流序列，第四码流序列为全0码流序列；
第二构建模块502还用于：根据第三码流序列及第四码流序列，构建攻击码流。
可选的，在本公开的一种实现方式中，攻击码流的第三码流段为第三码流序列，攻击码流的第四码流段为第四码流序列；或者，攻击码流的第三码流段为第四码流序列，攻击码流的第四码流段为第三码流序列。
可选的，在本公开的一种实现方式中，受害码流的第三码流段为第一码流序列或第二码流序列，受害码流的第四码流段为第一码流序列或第二码流序列。
示例性电子设备
下面，参考图8来描述根据本公开的电子设备。该电子设备可以是第一设备和第二设备中的任一个或两者、或与它们独立的单机设备，该单机设备可以与第一设备和第二设备进行通信，以从它们接收所采集到的输入信号。
图8图示了根据本公开的电子设备的框图。
如图8所示，电子设备11包括一个或多个处理器111和存储器112。
处理器111可以是中央处理单元(CPU)或者具有数据处理能力和/或指令执行能力的其他形式的处理单元，并且可以控制电子设备11中的其他组件以执行期望的功能。
存储器112可以包括一个或多个计算机程序产品，所述计算机程序产品可以包括各种形式的计算机可读存储介质，例如易失性存储器和/或非易失性存储器。所述易失性存储器例如可以包括随机存取存储器(RAM)和/或高速缓冲存储器(cache)等。所述非易失性存储器例如可以包括只读存储器(ROM)、硬盘、闪存等。在所述计算机可读存储介质上可以存储一个或多个计算机程序指令，处理器111可以运行所述程序指令，以实现上文所述的本公开的各个实施例的用于信号完整性仿真的激励信号生成方法以及/或者其他期望的功能。在所述计算机可读存储介质中还可以存储诸如输入信号、信号分量、噪声分量等各种内容。
在一个示例中，电子设备11还可以包括：输入装置113和输出装置114，这些组件通过总线系统和/或其他形式的连接机构(未示出)互连。
例如，在该电子设备11是第一设备或第二设备时，该输入装置113可以是上述的麦克风或麦克风阵列， 用于捕捉声源的输入信号。在该电子设备是单机设备时，该输入装置113可以是通信网络连接器，用于从第一设备和第二设备接收所采集的输入信号。
此外，该输入设备13还可以包括例如键盘、鼠标等等。
该输出装置114可以向外部输出各种信息，包括确定出的距离信息、方向信息等。该输出设备14可以包括例如显示器、扬声器、打印机、以及通信网络及其所连接的远程输出设备等等。
当然，为了简化，图8中仅示出了该电子设备11中与本公开有关的组件中的一些，省略了诸如总线、输入/输出接口等等的组件。除此之外，根据具体应用情况，电子设备11还可以包括任何其他适当的组件。
示例性计算机程序产品和计算机可读存储介质
除了上述方法和设备以外，本公开的实施例还可以是计算机程序产品，其包括计算机程序指令，所述计算机程序指令在被处理器运行时使得所述处理器执行本说明书上述“示例性方法”部分中描述的根据本公开各种实施例的用于信号完整性仿真的激励信号生成方法中的步骤。
所述计算机程序产品可以以一种或多种程序设计语言的任意组合来编写用于执行本公开操作的程序代码，所述程序设计语言包括面向对象的程序设计语言，诸如Java、C++等，还包括常规的过程式程序设计语言，诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。
此外，本公开的实施例还可以是计算机可读存储介质，其上存储有计算机程序指令，所述计算机程序指令在被处理器运行时使得所述处理器执行本说明书上述“示例性方法”部分中描述的根据本公开各种实施例的用于信号完整性仿真的激励信号生成方法中的步骤。
所述计算机可读存储介质可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以包括但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
以上结合具体实施例描述了本公开的基本原理，但是，需要指出的是，在本公开中提及的优点、优势、效果等仅是示例而非限制，不能认为这些优点、优势、效果等是本公开的各个实施例必须具备的。另外，上述公开的具体细节仅是为了示例的作用和便于理解的作用，而非限制，上述细节并不限制本公开为必须采用上述具体的细节来实现。
本公开中涉及的器件、装置、设备、系统的方框图仅作为例示性的例子并且不意图要求或暗示必须按照方框图示出的方式进行连接、布置、配置。如本领域技术人员将认识到的，可以按任意方式连接、布置、 配置这些器件、装置、设备、系统。诸如“包括”、“包含”、“具有”等等的词语是开放性词汇，指“包括但不限于”，且可与其互换使用。这里所使用的词汇“或”和“和”指词汇“和/或”，且可与其互换使用，除非上下文明确指示不是如此。这里所使用的词汇“诸如”指词组“诸如但不限于”，且可与其互换使用。
还需要指出的是，在本公开的装置、设备和方法中，各部件或各步骤是可以分解和/或重新组合的。这些分解和/或重新组合应视为本公开的等效方案。
提供所公开的方面的以上描述以使本领域的任何技术人员能够做出或者使用本公开。对这些方面的各种修改对于本领域技术人员而言是非常显而易见的，并且在此定义的一般原理可以应用于其他方面而不脱离本公开的范围。因此，本公开不意图被限制到在此示出的方面，而是按照与在此公开的原理和新颖的特征一致的最宽范围。
为了例示和描述的目的已经给出了以上描述。此外，此描述不意图将本公开的实施例限制到在此公开的形式。尽管以上已经讨论了多个示例方面和实施例，但是本领域技术人员将认识到其某些变型、修改、改变、添加和子组合。

Claims (11)

  1. 一种用于信号完整性仿真的激励信号生成方法，包括：
    构建第一码流序列及第二码流序列，其中，所述第一码流序列为伪随机二进制序列，所述第二码流序列为对所述第一码流序列的每一位的值取反所得到的序列；
    根据所述第一码流序列及所述第二码流序列，构建受害码流及攻击码流；其中，所述受害码流及所述攻击码流均包括多个码流段；所述受害码流的第一码流段为所述第一码流序列，所述受害码流的第二码流段为所述第二码流序列；所述攻击码流的第一码流段及第二码流段均为所述第一码流序列或所述第二码流序列；所述受害码流的第一码流段及第二码流段为所述受害码流的多个码流段中的任意两个，所述攻击码流的第一码流段及第二码流段为所述攻击码流的多个码流段中的任意两个，所述受害码流的第一码流段与所述攻击码流的第一码流段的位置相对应，所述受害码流的第二码流段与所述攻击码流的第二码流段的位置相对应；
    根据所述受害码流及所述攻击码流，生成待仿真链路中各支路分别对应的激励信号。
  2. 根据权利要求1所述的方法，所述根据所述受害码流及所述攻击码流，生成待仿真链路中各支路分别对应的激励信号包括：所述各支路中包括第一支路和第二支路，所述第一支路对应的激励信号中包含所述攻击码流，所述第二支路对应的激励信号中包含所述受害码流，所述第一支路和所述第二支路之间形成奇模激励或者偶模激励。
  3. 根据权利要求1所述的方法，还包括：
    根据所述支路的条数，确定每一所述激励信号包括的所述攻击码流及所述受害码流的总数量。
  4. 根据权利要求3所述的方法，其中，所述攻击码流及所述受害码流作为所述激励信号的项形成所述激励信号，所述方法还包括：
    所述激励信号的一项为所述受害码流，其余项为所述攻击码流；所述各支路分别对应的所述激励信号之间，所述受害码流出现在不同的项上；
    或者，所述激励信号的一项为所述攻击码流，其余项为所述受害码流，所述各支路分别对应的所述激励信号之间，所述攻击码流出现在不同的项上。
  5. 根据权利要求1所述的方法，其中，所述第一码流序列中不同码元的单位间隔时间相同，所述根据所述受害码流及所述攻击码流，生成待仿真链路中各支路分别对应的激励信号之后，所述方法还包括：
    确定所述第一码流序列中一个所述码元的单位间隔时间；
    确定所述激励信号中包含的所述码元的个数；
    基于所述码元的个数及一个所述码元的单位间隔时间，确定仿真激励时间；其中，所述仿真激励时间用于表示所述激励信号用于仿真的时长。
  6. 根据权利要求1-5任一项所述的方法，其中，所述根据所述第一码流序列及所述第二码流序列，构建受害码流及攻击码流之后，所述方法还包括：
    构建第三码流序列及第四码流序列，所述第三码流序列为全1码流序列，所述第四码流序列为全0码流序列；
    根据所述第三码流序列及所述第四码流序列，构建所述攻击码流。
  7. 根据权利要求6所述的方法，还包括：
    所述攻击码流的第三码流段为所述第三码流序列，所述攻击码流的第四码流段为所述第四码流序列；或者，所述攻击码流的第三码流段为所述第四码流序列，所述攻击码流的第四码流段为所述第三码流序列。
  8. 根据权利要求7所述的方法，还包括：
    所述受害码流的第三码流段为所述第一码流序列或所述第二码流序列，所述受害码流的第四码流段为所述第一码流序列或所述第二码流序列。
  9. 一种用于信号完整性仿真的激励信号生成装置，包括：
    第一构建模块：用于构建第一码流序列及第二码流序列，其中，所述第一码流序列为伪随机二进制序列，所述第二码流序列为对所述第一码流序列的每一位的值取反所得到的序列；
    第二构建模块：用于根据所述第一构建模块构建的所述第一码流序列及所述第二码流序列，构建受害码流及攻击码流；其中，所述受害码流及所述攻击码流均包括多个码流段；所述受害码流的第一码流段为所述第一码流序列，所述受害码流的第二码流段为所述第二码流序列；所述攻击码流的第一码流段及第二码流段均为所述第一码流序列或所述第二码流序列；所述受害码流的第一码流段及第二码流段为所述受害码流的多个码流段中的任意两个，所述攻击码流的第一码流段及第二码流段为所述攻击码流的多个码流段中的任意两个，所述受害码流的第一码流段与所述攻击码流的第一码流段的位置相对应，所述受害码流的第二码流段与所述攻击码流的第二码流段的位置相对应；
    激励信号生成模块：用于根据所述第二构建模块构建的所述受害码流及所述攻击码流，生成待仿真链路中各支路分别对应的激励信号。
  10. 一种计算机可读存储介质，所述存储介质存储有计算机程序，所述计算机程序用于执行上述权利要求1-8任一所述的用于信号完整性仿真的激励信号生成方法。
  11. 一种电子设备，所述电子设备包括：
    处理器；
    用于存储所述处理器可执行指令的存储器；
    所述处理器，用于从所述存储器中读取所述可执行指令，并执行所述指令以实现上述权利要求1-8任一所述的用于信号完整性仿真的激励信号生成方法。
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