WO2023162246A1

WO2023162246A1 - Current detection device and motor drive device provided with same

Info

Publication number: WO2023162246A1
Application number: PCT/JP2022/008357
Authority: WO
Inventors: 陽一郎大井
Original assignee: ファナック株式会社
Priority date: 2022-02-28
Filing date: 2022-02-28
Publication date: 2023-08-31
Also published as: TW202337131A

Abstract

This current detection device comprises: a main current detection circuit and an offset correction current detection circuit for detecting the current through a current pathway at the same detection position; a short-circuit unit for short-circuiting between the current input terminals of an AD converter in the offset correction current detection circuit; a first offset correction unit for measuring a first offset of the offset correction current detection circuit while short-circuiting is occurring between the current input terminals, and removing a first offset equivalent from the output of the offset correction current detection circuit; and a second offset correction unit for calculating a second offset amount of the main current detection circuit on the basis of the corrected output of the offset correction current detection circuit and the output of the main current detection circuit obtained at the same detection timing while no short-circuiting is occurring between the current input terminals, and removing a second offset equivalent from the output of the main current detection circuit.

Description

CURRENT DETECTION DEVICE AND MOTOR DRIVE DEVICE INCLUDING THE SAME

The present invention relates to a current detection device and a motor drive device including the same.

A motor drive device is provided with a current detection device that detects the current flowing through the motor in order to control the drive of the motor.

For example, having a main operational amplifier (21) and an offset adjustment circuit (22) connected to the main operational amplifier (21), when the offset adjustment circuit (22) operates, from the main operational amplifier (21), An auto-zero amplifier (2) configured to generate an output voltage (Vo) from which an input offset voltage (ΔVm) of the main operational amplifier (21) is removed, and a voltage measuring section (3) for measuring the output voltage (Vo) and a control circuit section (4) connected to the auto-zero amplifier (2) and the voltage measurement section (3), the control circuit section (4) operating the offset adjustment circuit (22) in an auto-zero mode. and a non-auto-zero mode in which the offset adjustment circuit (22) is not operated, and the control circuit (4) changes the output voltage (Vo) before and after switching from the auto-zero mode to the non-auto-zero mode. respectively, and subtracting the measured value of the output voltage (Voa) in the autozero mode from the measured value of the output voltage (Von) in the non-autozero mode to calculate the input offset voltage (ΔVm), and then and measuring the output voltage (Vo) in the non-autozero mode, and correcting the measured value of the output voltage (Vo) using the calculated value of the input offset voltage (ΔVm). An output voltage measurement system (1) characterized by is known (see, for example, Patent Document 1).

For example, an auto-zero amplifier circuit that corrects an offset of an input differential signal and a comparator circuit that converts an output signal output from the auto-zero amplifier circuit into a digital signal, wherein the auto-zero amplifier circuit and the comparator circuit is known as an arithmetic circuit configured in the same package (see, for example, Patent Document 2).

JP 2016-208308 A JP 2019-062450 A

Conventionally, the offset correction of the current detection circuit is performed by measuring the output value of the current detection circuit as an offset in advance when the current input to the current detection circuit is set to 0 (zero) by stopping the operation of the motor drive device. This is realized by removing (subtracting) the offset equivalent amount from the current detection value by the current detection circuit in the subsequent normal operation. That is, in order to correct the offset, the input of the current detection circuit must be set to 0, so that the normal current detection process must be stopped once, which is inefficient. Further, if the current detection circuit continues to detect current in normal use, the offset of the current detection circuit changes due to temperature drift. Conventionally, since the offset measured in advance has been used as it is for offset correction, offset correction corresponding to the change in offset has not been performed. Therefore, there is a demand for a technique capable of continuously correcting the offset of the current detection circuit without stopping the current detection process.

According to one aspect of the present disclosure, a current detection device includes a main current detection circuit that detects a current on a current path and outputs digital data corresponding to the current, and a current detection circuit at the same detection location as the main current detection circuit. A current detection circuit for offset correction that detects a current on a path and outputs digital data corresponding to the current, a short-circuit section that short-circuits the current input terminals of the AD converter in the current detection circuit for offset correction, and a short-circuit section. measuring the first offset output from the current detection circuit for offset correction when the current input terminals are shorted by the current detection circuit, and performing correction to remove the amount corresponding to the first offset from the output of the current detection circuit for offset correction The output of the main current detection circuit obtained at the same detection timing when the first offset correction unit and the short-circuiting unit do not short-circuit the current input terminals and the output corrected by the first offset correction unit of the current detection circuit for offset correction. and calculating a second offset output from the main current sensing circuit based on the output of and performing a correction to remove an amount corresponding to the second offset from the output of the main current sensing circuit. and

Further, according to one aspect of the present disclosure, a motor drive device includes the current detection device, and controls motor drive using an output corrected by the second offset correction section of the main current detection circuit.

According to one aspect of the present disclosure, it is possible to continuously correct the offset of the current detection circuit without stopping the current detection process.

1 is a circuit diagram showing a current sensing device according to one embodiment of the present disclosure; FIG. FIG. 4 is a block diagram illustrating a method of calculating a second offset output from a main current detection circuit; FIG. [0014] Figure 4 shows a timing chart illustrating the operation of a current sensing device according to an embodiment of the present disclosure; 4 is a flow chart showing an operation flow of a current detection device according to an embodiment of the present disclosure; FIG. 4 is a circuit diagram showing a current detection device according to a modification of an embodiment of the present disclosure; 6 is a timing chart illustrating the operation of the current detection device shown in FIG. 5; FIG. 6 is a flow chart showing an operation flow of the current detection device shown in FIG. 5; 1 illustrates a motor drive device with a current sensing device according to an embodiment of the present disclosure; FIG.

A current detection device and a motor drive device including the same will be described below with reference to the drawings. In each drawing, similar parts are provided with similar reference numerals. Also, to facilitate understanding, the scales of these drawings are appropriately changed. The illustrated forms are examples of implementations and are not limited to these forms. Further, in the following description, the offset of the current detection circuit for offset correction is referred to as "first offset", and the offset of the main current detection circuit is referred to as "second offset".

FIG. 1 is a circuit diagram showing a current detection device according to one embodiment of the present disclosure. Hereinafter, the same reference numerals in different drawings mean components having the same or similar functions.

A current detection device 1 according to an embodiment of the present disclosure includes a main current detection circuit 11, an offset correction current detection circuit 12, a short circuit section 13, a first offset correction section 14, and a second offset correction section 15. and

The main current detection circuit 11 detects the current on the current path 2 and outputs digital data corresponding to the current. The main current detection circuit 11 may be any of a shunt resistor type current detection circuit, a hall element type current detection circuit, or a core type current detection circuit. As an example, FIG. 1 shows a case where the main current detection circuit 11 is configured by a shunt resistor type current detection circuit.

The main current detection circuit 11 includes a current detection resistor (shunt resistor) 21 , an insulated AD converter 22 ,

filter resistors

31 and 32 , and a filter capacitor 33 . Conversion methods of the AD converter 22 include successive approximation type, delta sigma type, double integration type, flash type (parallel comparison type), and pipeline type. A filter composed of

filter resistors

31 and 32 and a filter capacitor 33 is provided on the input side of the AD converter 22 . A filter capacitor 33 is electrically connected between the non-inverting input terminal (+) and the inverting input terminal (-) of the AD converter 22, and

filter resistors

31 and 32 are electrically connected to both terminals of the filter capacitor 33. Connected. When a current flows through the current path 2, a potential difference occurs between both terminals of the current detection resistor 21, and each potential signal is applied to the non-inverting input terminal (+ ) and the inverting input terminal (-). The AD converter 22 outputs digital data corresponding to the current on the current path 2 based on each input potential signal. The digital data output from the AD converter 22 is input to an LSI (Large Scale Integrated Circuit) 40, which is a digital arithmetic circuit, subjected to offset correction, which will be described later, and then output to the outside as current value digital data.

The offset correction current detection circuit 12 detects the current on the current path 2 at the same detection point as the main current detection circuit 11 and outputs digital data corresponding to the current. The offset correction current detection circuit 12 may be a shunt resistor type current detection circuit, a hall element type current detection circuit, or a core type current detection circuit. FIG. 1 shows, as an example, the case where the current detection circuit 12 for offset correction is configured by a shunt resistor type current detection circuit. The offset correction current detection circuit 12 is preferably installed near the main current detection circuit 11 .

The offset correction current detection circuit 12 includes a current detection resistor (shunt resistor) 21 , an insulated AD converter 23 ,

filter resistors

34 and 35 , and a filter capacitor 36 . By sharing the current detection resistor 21 between the main current detection circuit 11 and the offset correction current detection circuit 12, the main current detection circuit 11 and the offset correction current detection circuit 12 are detected at the same detection point on the current path 2. Current can be detected. Conversion methods of the AD converter 23 include successive approximation type, delta sigma type, double integration type, flash type (parallel comparison type), and pipeline type. A filter composed of

filter resistors

34 and 35 and a filter capacitor 36 is provided on the input side of the AD converter 23 . A filter capacitor 36 is electrically connected between the non-inverting input terminal (+) and the inverting input terminal (-) of the AD converter 23, and

filter resistors

34 and 35 are electrically connected to both terminals of the filter capacitor 36. Connected. When a current flows through the current path 2, a potential difference is generated between both terminals of the current detection resistor 21, and each potential signal is applied to the non-inverting input terminal (+ ) and the inverting input terminal (-). The AD converter 23 outputs digital data corresponding to the current on the current path 2 based on each input potential signal. Digital data output from the AD converter 23 is input to an LSI (Large Scale Integrated Circuit) 40, which is a digital arithmetic circuit.

The short-circuit unit 13 is an open/close switch that short-circuits/opens the non-inverting input terminal (+) and the inverting input terminal (-) between the current input terminals of the AD converter 23 in the offset correction current detection circuit 12. . The short circuit portion 13 is composed of a semiconductor switching element such as a unipolar transistor such as an FET, a bipolar transistor, an IGBT, a thyristor, or a GTO. It may be a semiconductor switching element. Under the control of the first offset correction section 14 in the LSI (Large Scale Integrated Circuit) 40, the shorting section 13 periodically repeats shorting and opening.

The first offset correction unit 14 measures the first offset output from the offset correction current detection circuit 12 when the current input terminals of the AD converter 23 are shorted by the short circuit 13, and the offset correction current detection circuit 12 performs a correction that removes an amount corresponding to the first offset from the output of .

When the current input terminals of the AD converter 23 are shorted by the short circuit 13, no current flows from the current path 2 into the AD converter 23 in the offset correction current detection circuit 12. Therefore, the AD in the offset correction current detection circuit 12 is Only the offset (that is, the first offset) of the offset correction current detection circuit 12 is output from the converter 23 . The first offset correction unit 14 measures this first offset when the current input terminals of the AD converter 23 are short-circuited by the short-circuit unit 13, and outputs the first offset correction current detection circuit 12 after the measurement. A correction is performed to remove the amount corresponding to the first offset from the output of the current detection circuit 12 for offset correction so that the offset of is not included.

Thus, the measurement of the first offset by the first offset correction unit 14 and the correction of the output of the current detection circuit 12 for offset correction are performed when the current input terminals of the AD converter 23 are shorted by the short circuit unit 13. . Since the short-circuiting section 13 periodically repeats short-circuiting and opening, the measurement of the first offset by the first offset correction section 14 and the correction of the output of the current detection circuit 12 for offset correction are repeatedly executed at a predetermined cycle. will be Therefore, even if the first offset of the current detection circuit 12 for offset correction changes due to temperature drift, the output of the current detection circuit 12 for offset correction cannot be corrected when the current input terminals of the AD converter 23 are shorted by the short circuit 13. When the current input terminals of the AD converter 23 are opened following the short circuit, the offset correction current detection circuit 12 outputs corrected digital data from which the first offset has been removed. . Therefore, the influence of temperature drift on the output of the offset correction current detection circuit 12 can be minimized.

The second offset correction unit 15 detects the main current obtained at the same detection timing when the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open). A second offset output from the main current detection circuit 11 is calculated based on the plurality of outputs of the circuit 11 and the plurality of outputs corrected by the first offset correction section 14 of the current detection circuit 12 for offset correction. , to remove (subtract) an amount corresponding to the second offset from the output of the main current detection circuit 11 .

As described above, when the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open), the offset correction current detection circuit 12 outputs the first offset corrected digital data from which is removed is output. When the short-circuiting section 13 does not short-circuit the current input terminals of the AD converter 23, the second offset correction section 15 combines a plurality of outputs of the main current detection circuit 11 obtained at the same detection timing with the current detection circuit for offset correction. A second offset output from the main current detection circuit 11 is calculated based on a plurality of corrected outputs from the first offset correction unit 14 of 12 . In order to obtain a plurality of outputs of the main current detection circuit 11 and a plurality of outputs corrected by the first offset correction section 14 of the offset correction current detection circuit 12, the main current detection circuit 11 and the offset correction current detection circuit 12 The simultaneous detection (simultaneous input) of the current on the current path 2 is performed multiple times while the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 .

Here, a method for calculating the second offset output from the main current detection circuit 11 will be described. FIG. 2 is a block diagram illustrating a method of calculating the second offset output from the main current detection circuit.

When the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when it is open), the value of the current on the current path 2 at time t is I(t), and the output of the main current detection circuit 11 is I ₁ (t), and the output corrected by the first offset correction unit 14 of the current detection circuit 12 for offset correction is I ₂ (t).

Assuming that the gain of the main current detection circuit 11 is G ₁ and the second offset of the main current detection circuit 11 is I _of , the output I ₁ (t) of the main current detection circuit 11 at time t is given by Equation 1: expressed.

Assuming that the gain of the offset correction current detection circuit 12 is _G2 , the corrected output _I2 (t) by the first offset correction section 14 of the offset correction current detection circuit 12 at time t is given by Equation 2. is represented by Since the output I ₂ (t) of the current detection circuit 12 for offset correction has already been corrected by the first offset correction unit 14 at the time of the short circuit between the current input terminals of the AD converter 23 before the open time, the output I 2 (t) is An offset of 1 is 0, ie the first offset does not appear in Equation 2.

By substituting formula 2 into formula 1, formula 3 is obtained.

Using Equations 1 to 3, the output of the main current detection circuit 11 and the corrected output of the offset correction current detection circuit 12 obtained at the same detection timing at each of the two times are used to calculate the second An example of calculating the offset is as follows.

In order to obtain two outputs of the main current detection circuit 11 and two outputs corrected by the first offset correction section 14 of the offset correction current detection circuit 12, the main current detection circuit 11 and the offset correction current detection circuit 12 Simultaneous detection (simultaneous input) of the current on the current path 2 in , is performed twice while the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 .

When the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open), the output I ₁ (t ₁ ) of the main current detection circuit 11 at time t ₁ is The output I ₂ (t ₁ ) corrected by the first offset correction unit 14 of the offset correction current detection circuit 12 at time t ₁ is expressed by Equation 5.

When the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open), the output I ₁ (t ₂ ) of the main current detection circuit 11 at time t ₂ is The output I ₂ (t ₂ ) corrected by the first offset correction unit 14 of the offset correction current detection circuit 12 at time t ₂ is expressed by Equation 6.

By subtracting the sides of Equation 4 and Equation 6, Equation 8 is obtained.

By subtracting the sides of Equation 5 and Equation 7, Equation 9 is obtained.

Formula 10 is obtained by substituting formula 9 into formula 8 and arranging it.

Substituting Equation 10 into Equation 3 when t=t ₁ yields Equation 11.

Formula 12 is obtained by rearranging Formula 11.

The second offset correction unit 15 can calculate the second offset I _of according to Equation (12).

In the above-described embodiment, the second offset is calculated based on each output obtained at the same detection timing at each of the two times, but each output obtained at the same detection timing at each of three or more times A second offset may be calculated based on . Several modes for calculating the second offset based on outputs at three or more times are listed below.

The first form is to calculate the second offset based on the average of each output measured at each time. Here, a case is assumed in which the second offset is calculated based on the output of the main current detection circuit 11 and the corrected output of the offset correction current detection circuit 12 obtained at the same detection timing at each of the six times. The first form will be described as an example.

In order to obtain six outputs of the main current detection circuit 11 and six outputs corrected by the first offset correction section 14 of the offset correction current detection circuit 12, the main current detection circuit 11 and the offset correction current detection circuit 12 Simultaneous detection (simultaneous input) of the current on the current path 2 in is performed six times while the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 .

When the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open), the output of the main current detection circuit 11 measured at time t ₁ is I ₁ ( t ₁ ), the output of the main current detection circuit 11 measured at time t ₂ is I ₁ (t ₂ ), the output of the main current detection circuit 11 measured at time t ₃ is I ₁ (t ₃ ), time t ₄ is I ₁ (t ₄ ), I 1 (t 5 ) is the output of the main current detection circuit 11 measured at time t ₅ , and I ₁ (t ₅ ) is the output of the main current detection circuit 11 measured at time t ₆ . Let the output of the current detection circuit 11 be I ₁ (t ₆ ).

The average output I _{' 1} (T ₁ ₎ of I 1 (t 1 ), I ₁ (t ₂ ₎ and I ₁ (t ₃ ) is given by Equation 13.

The average output I _{' 1} (T ₂ ) _of I 1 (t ₄ ), I ₁ (t ₅ ) and I ₁ (t ₆ ) is given by Equation 14.

Similarly, when the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open), the current detection circuit 12 for offset correction measured at time t ₁ The output corrected by the first offset correction unit 14 is I ₂ (t ₁ ), and the output corrected by the first offset correction unit 14 of the offset correction current detection circuit 12 measured at time t ₂ is I _{2 .} (t ₂ ), the output corrected by the first offset correction unit 14 of the offset correction current detection circuit 12 measured at time t ₃ is I ₂ (t ₃ ), the output for offset correction measured at time t ₄ The corrected output by the first offset correction unit 14 of the current detection circuit 12 is I ₂ (t ₄ ), and the corrected output by the first offset correction unit 14 of the current detection circuit 12 for offset correction measured at time t ₅ is is I ₂ (t ₅ ), and the output corrected by the first offset correction unit 14 of the offset correction current detection circuit 12 measured at time t ₆ is I ₂ (t ₆ ).

The average output I _' ₂ (T ₁ ) _of I 2 (t 1 ), I ₂ (t ₂ ) and I ₂ (t ₃ ) is given by Equation 15.

The average output I _{' 2} (T _{2 ) of I 2 (t 4 ), I 2 (t 5 ) and I 2} ₍ _t ₆ ₎ _is _given by Equation 16.

I ₁ (t ₁ ), I ₁ (t ₂ ), I ₂ (t ₁ ) and I ₂ (t ₂ ) in Equation 12 are replaced by I' 1 (T 1 ), I _' ₁ (T ₂ ) and I _' ₂ Substituting (T ₁ ) and I′ ₂ (T ₂ ) yields the second offset I _of as shown in Equation 17. The second offset correction unit 15 can calculate the second offset I _of according to Equation 17.

A second form computes a plurality of interim second offset values calculated based on the output for each of the two times and averages these interim second offset values to compute the final second offset. It is. Here, it is assumed that the second offset is calculated based on the output of the main current detection circuit 11 and the corrected output of the offset correction current detection circuit 12 obtained at the same detection timing at each of the four times. The second form will be described as an example.

In order to obtain the four outputs of the main current detection circuit 11 and the four outputs corrected by the first offset correction section 14 of the offset correction current detection circuit 12, the main current detection circuit 11 and the offset correction current detection circuit 12 Simultaneous detection (simultaneous input) of the current on the current path 2 in is performed four times while the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 .

When the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open), the output of the main current detection circuit 11 measured at time t ₁ is I ₁ ( t ₁ ), the output of the main current detection circuit 11 measured at time t ₂ is I ₁ (t ₂ ), the output of the main current detection circuit 11 measured at time t ₃ is I ₁ (t ₃ ), time t The output of the main current detection circuit 11 measured at ₄ is I ₁ (t ₄ ). Further, when the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (that is, when the current input terminals of the AD converter 23 are open), the offset correction current detection circuit 12 measured at time t ₁ The output corrected by the first offset correction unit 14 is I ₂ (t ₁ ), and the output corrected by the first offset correction unit 14 of the offset correction current detection circuit 12 measured at time t ₂ is I ₂ ( t ₂ ), the output corrected by the first offset correction unit 14 of the offset correction current detection circuit 12 measured at time t ₃ is I ₂ (t ₃ ), the offset correction current measured at time t ₄ Let I ₂ (t ₄ ) be the output corrected by the first offset correction unit 14 of the detection circuit 12 .

Output I ₁ (t ₁ ) of main current detection circuit 11 measured at time t 1 , corrected output I ₂ (t ₁ ) of current _detection circuit 12 for offset correction, and main current detection measured at time t ₂ Substituting the output I ₁ (t ₂ ) of the circuit 11 and the output I ₂ (t ₂ ) corrected by the first offset correction section 14 of the current detection circuit 12 for offset correction into Equation 12, Equation 18 gives: A second provisional offset value I _oft1 is obtained.

Similarly, I ₁ (t ₁ ), I ₁ (t ₂ ), I ₂ (t ₁ ) and I ₂ (t ₂ ) in Equation 12 are replaced by I 1 (t ₃ ), _{I 1} ₍ t ₄ ) and I _{2 .} Substituting (t ₃ ) and I ₂ (t ₄ ) yields the second interim offset value I _oft2 as shown in Equation 19.

By averaging the second interim offset I _oft1 given by Equation 18 and the second interim offset I oft2 given by Equation 19, the final second offset I _oft2 given by Equation 20 is obtained. _of is obtained. The second offset correction unit 15 can calculate the second offset I _of according to Equation (20).

Subsequently, the operation of the current detection device according to the embodiment of the present disclosure will be described with a specific example. FIG. 3 shows a timing chart illustrating operation of a current sensing device according to one embodiment of the present disclosure. In FIG. 3, execution timings of the first offset correction, the second offset correction, the measurement of the first offset by the current detection circuit 12 for offset correction, and the measurement of the current by the main current detection circuit 11 are expressed as " It is indicated by a bar-shaped thick line.

Here, an example of calculating the second offset based on the output of the main current detection circuit 11 and the corrected output of the offset correction current detection circuit 12 obtained at the same detection timing at each of two times will be described. do

As shown in FIG. 3, the short-circuit portion 13 is controlled by a first offset correction portion 14 in an LSI (Large Scale Integrated Circuit) 40 so that the current between the input terminals of the AD converter 23 in the current detection circuit 12 for offset correction is short circuit (ON) and open circuit (OFF) are repeated periodically.

The main current detection circuit 11 detects the current on the current path 2 at a predetermined current detection cycle, regardless of the cycle of shorting (ON) and opening (OFF) by the shorting section 13 . The current detection cycle by the main current detection circuit 11 is preferably shorter than the short-circuit (ON)/open-circuit (OFF) cycle by the short-circuit portion 13 .

When the current input terminals of the AD converter 23 are short-circuited (ON) by the short-circuit unit 13, the first offset correction unit 14 measures the first offset of the current detection circuit 12 for offset correction at time _t1 , At t ₂ , correction is performed by removing (subtracting) the amount corresponding to the first offset from the output of the offset correction current detection circuit 12 . At this time, the main current detection circuit 11 outputs "corrected digital data" from which the amount corresponding to the second offset _Iof1 calculated in the previous cycle is removed. When the current input terminals of the AD converter 23 are opened (OFF) following the short circuit (ON), the offset correction current detection circuit 12 detects the current at time _t3 and time _t4 , which are the detection timings of the main current detection circuit 11. A current on current path 2 is detected. As described above, the main current detection circuit 11 detects the current on the current path 2 at a predetermined current detection cycle. The current detection period of the detection circuit 11 is monitored, and the current detection circuit 12 for offset correction is controlled to detect current at the timing that matches the detection timing of the main current detection circuit 11 . As a result, the main current detection circuit 11 and the offset correction current detection circuit 12 detect the current on the current path 2 at the same detection timing, time _t3 , and detect the current on the current path 2 at the same detection timing, time _t4 . current is detected. The second offset correction unit 15 compares the output of the main current detection circuit 11 obtained at times _t3 and _t4, which are the same detection timing, with the output of the offset correction current detection circuit 12 corrected by the first offset correction unit 14. At time _t5 , the second offset _Iof2 output from the main current detection circuit 11 is calculated based on the output of the main current detection circuit 11 and the amount corresponding to the second offset _Iof2 from the output of the main current detection circuit 11. Perform a correction that removes (subtracts). After time _t5 , the main current detection circuit 11 outputs "corrected digital data" from which the amount corresponding to the second offset _Iof2 calculated at time _t5 is removed.

When the current input terminals of the AD converter 23 are short-circuited (ON) by the short-circuit section 13 subsequent to the opening (OFF), the first offset correction section 14 causes the first offset correction current detection circuit 12 to turn on at time _t6 . is measured, and correction is executed by removing (subtracting) the amount corresponding to the first offset from the output of the current detection circuit 12 for offset correction at time _t7 . When the current input terminals of the AD converter 23 are opened (OFF) following the short circuit (ON), the main current detection circuit 11 and the offset correction current detection circuit 12 open the current path 2 at time _t8 , which is the same detection timing. The upper current is detected, and the current on the current path 2 is detected at the same detection timing, time _t9 . The second offset correction unit 15 compares the output of the main current detection circuit 11 obtained at times _t8 and _t9 , which are the same detection timing, with the output of the offset correction current detection circuit 12 corrected by the first offset correction unit 14. At time _t10 , the second offset _Iof3 output from the main current detection circuit 11 is calculated based on the output of the main current detection circuit 11 and the amount corresponding to the second offset _Iof3 from the output of the main current detection circuit 11. Perform a correction that removes (subtracts). After time _t10 , the main current detection circuit 11 outputs "corrected digital data" from which the amount corresponding to the second offset _Iof3 calculated at time _t10 is removed. After time _t10 , the same processes as described above are repeatedly executed. That is, the first offset correction unit 14 measures the first offset of the offset correction current detection circuit 12 at time _t11 , and the output of the offset correction current detection circuit ₁₂ changes to the first offset at time t12. Perform a correction to remove (subtract) the corresponding amount.

FIG. 4 is a flow chart showing the operation flow of the current detection device according to one embodiment of the present disclosure.

The main current detection circuit 11 continues to detect the current on the current path 2 at a predetermined current detection cycle regardless of the cycle of short-circuiting and opening by the short-circuiting portion 13 (step S200). It is preferable that the current detection cycle by the main current detection circuit 11 is shorter than the short circuit/open cycle by the short circuit portion 13 .

In step S101, the non-inverting input terminal (+) and the inverting input terminal (-) between the current input terminals of the AD converter 23 in the offset correction current detection circuit 12 are short-circuited.

In step S102, the first offset correction unit 14 measures the first offset output from the current detection circuit 12 for offset correction.

In step S103, the first offset correction unit 14 performs correction by removing (subtracting) the amount corresponding to the first offset from the output of the current detection circuit 12 for offset correction.

In step S104, the non-inverting input terminal (+) and the inverting input terminal (-) between the current input terminals of the AD converter 23 in the offset correction current detection circuit 12 are opened.

In step S105, the offset correction current detection circuit 12 detects the current on the current path 2 at a plurality of times of the same detection timing as the main current detection circuit 11.

In step S106, the second offset correction unit 15 compares the output of the main current detection circuit 11 obtained at the same detection timing and the output corrected by the first offset correction unit 14 of the offset correction current detection circuit 12. Based on this, the second offset output from the main current detection circuit 11 is calculated. For the second offset and the second offset provisional value, there is a possibility that the denominators shown in Equations 12 and 17 to 19 will be zero. When the denominators shown in Equations 12 and 17 to 19 become 0, the second offset calculated in step S106 diverges. In order to prevent such divergence, if the second offset calculated in step S106 diverges, the process returns to step S105, and the main current detection circuit 11 and the offset correction current detection circuit 12 detect the same timing again. Perform current sensing and subsequent calculation of a second offset in step S106.

In step S<b>107 , the second offset correction unit 15 executes correction by removing (subtracting) the amount corresponding to the second offset from the output of the main current detection circuit 11 . As a result, the main current detection circuit 11 outputs "corrected digital data" from which the amount corresponding to the second offset is removed (step S200). After that, the process returns to step S101 and the above-described processing is executed again. As described above, the current detection processing of the main current detection circuit 11 continues to be executed at a cycle different from that of the offset correction processing. offset correction can be performed continuously.

In the above-described embodiment, the current input terminals of the AD converter 23 in the offset correction current detection circuit 12 are short-circuited by the short circuit 13, but this short circuit affects the current detection processing of the main current detection circuit 11. The current detection device 1 should be provided with such a configuration as not to Therefore, for example, when each of the main current detection circuit 11 and the offset correction current detection circuit 12 is a shunt resistor type current detection circuit, the filter resistor 31 provided on the input side of the AD converter 22 in the main

current detection circuit

11 and 32, and filter

resistors

34 and 35 provided on the input side of the AD converter 23 of the offset correction current detection circuit 12 are current detection resistors ( shunt resistor) 21. It is preferable that the resistance value of each of the

filter resistors

31, 32, 34 and 35 is set to be about 1000 times higher than the resistance value of the current detection resistor 21, for example. For example, the resistance value of the current detection resistor 21 is 6.4 mΩ, and the resistance values of the

filter resistors

31, 32, 34 and 35 are each set to 22Ω. Note that the numerical values given here are only examples, and other numerical values may be used. The same applies when the main current detection circuit 11 and the offset correction current detection circuit 12 are Hall element type current detection circuits or core type current detection circuits.

Filter resistors

31 and 32 provided on the side and filter

resistors

34 and 35 provided on the input side of the AD converter 23 of the offset correction current detection circuit 12 are used in the main current detection circuit 11 and the offset correction current detection circuit 12. It is set to have a resistance value greater than the resistance value (impedance) of the shared Hall element or core.

Next, a current detection device according to a modification of one embodiment of the present disclosure will be described.

FIG. 5 is a circuit diagram showing a current detection device according to a modification of one embodiment of the present disclosure.

In this modification, the short circuit between the current input terminals of the AD converter 23 in the current detection circuit 12 for offset correction by the short circuit 13 surely does not affect the current detection processing of the main current detection circuit 11. A switch unit 51 is further provided in the current detection device 1 .

When the current input terminals of the AD converter 23 are short-circuited by the short-circuiting part 13, the switch unit 51 is turned off (OFF: open) in order to cut off the inflow of current from the current path 2 to the current input terminals of the AD converter 23. When the short-circuiting part 13 does not short-circuit the current input terminals of the AD converter 23, it is turned on (ON: closed) so as not to cut off the inflow of current from the current path 2 to the current input terminals of the AD converter 23. FIG. The switch unit 51 is composed of semiconductor switching elements such as a unipolar transistor such as an FET, a bipolar transistor, an IGBT, a thyristor, and a GTO. It may be a semiconductor switching element. Under the control of the first offset correction section 14 in the LSI (Large Scale Integrated Circuit) 40, the switch section 51 is periodically turned off (OFF) and on (ON). Circuit components other than the switch unit 51 are the same as those shown in FIG. 1, so the same circuit components are denoted by the same reference numerals, and detailed description of the circuit components is omitted. .

FIG. 6 is a timing chart illustrating the operation of the current detection device shown in FIG. In FIG. 6, execution timings of the first offset correction, the second offset correction, the measurement of the first offset by the current detection circuit 12 for offset correction, and the measurement of the current by the main current detection circuit 11 are expressed as " It is indicated by a bar-shaped thick line. FIG. 6 further adds the operation state of the switch section 51 to the timing chart shown in FIG.

When the current input terminals of the AD converter 23 are short-circuited (ON) by the short-circuiting part 13, the switch part 51 is turned off (OFF) in order to block the inflow of current from the current path 2 to the current input terminals of the AD converter 23. When the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (OFF), it is turned ON so as not to block the inflow of current from the current path 2 to the current input terminals of the AD converter 23 . Note that execution timings of the first offset correction, the second offset correction, the measurement of the first offset by the current detection circuit 12 for offset correction, and the measurement of the current by the main current detection circuit 11 are shown in FIG. , detailed description of each execution timing will be omitted.

FIG. 7 is a flow chart showing the operation flow of the current detection device shown in FIG.

The main current detection circuit 11 continues to detect the current on the current path 2 at a predetermined current detection cycle regardless of the cycle of short-circuiting and opening by the short-circuiting portion 13 (step S200). The current detection cycle of the main current detection circuit 11 is preferably shorter than the short-circuit/open cycle of the short-circuit portion 13 and the open (OFF)/close (ON) cycle of the switch portion 51 .

In step S<b>301 , the switch unit 51 turns off (OFF) in order to block the inflow of current from the current path 2 to the current input terminal of the AD converter 23 .

In step S302, the non-inverting input terminal (+) and the inverting input terminal (-) between the current input terminals of the AD converter 23 in the offset correction current detection circuit 12 are short-circuited.

In step S303, the first offset correction unit 14 measures the first offset output from the current detection circuit 12 for offset correction.

In step S304, the first offset correction unit 14 performs correction by removing (subtracting) the amount corresponding to the first offset from the output of the current detection circuit 12 for offset correction.

In step S305, the non-inverting input terminal (+) and the inverting input terminal (-) between the current input terminals of the AD converter 23 in the offset correction current detection circuit 12 are opened.

In step S306, it is turned on so as not to block the inflow of current from the current path 2 to the current input terminal of the AD converter 23.

In step S307, the offset correction current detection circuit 12 detects the current on the current path 2 at a plurality of times of the same detection timing as the main current detection circuit 11.

In step S308, the second offset correction unit 15 compares the output of the main current detection circuit 11 obtained at the same detection timing and the output corrected by the first offset correction unit 14 of the offset correction current detection circuit 12. Based on this, the second offset output from the main current detection circuit 11 is calculated. For the second offset and the second offset provisional value, there is a possibility that the denominators shown in Equations 12 and 17 to 19 will be zero. When the denominators shown in Equations 12 and 17 to 19 become 0, the second offset calculated in step S308 diverges. In order to prevent such divergence, if the second offset calculated in step S308 diverges, the process returns to step S307, and the main current detection circuit 11 and the offset correction current detection circuit 12 detect the same timing again. Perform current sensing, followed by calculation of a second offset in step S308.

In step S<b>309 , the second offset correction unit 15 executes correction by removing (subtracting) the amount corresponding to the second offset from the output of the main current detection circuit 11 . As a result, the main current detection circuit 11 outputs "corrected digital data" from which the amount corresponding to the second offset is removed (step S200). After that, the process returns to step S301 and the above-described process is executed again. As described above, the current detection processing of the main current detection circuit 11 continues to be executed at a cycle different from that of the offset correction processing. offset correction can be performed continuously.

Using the current detection device 1 according to the embodiment of the present disclosure and its modification described above, it is possible to detect the current flowing through the motor in order to control the driving of the motor.

FIG. 8 is a diagram showing a motor drive device including a current detection device according to one embodiment of the present disclosure.

As an example, a case of controlling a three-phase AC motor 300 by a motor drive device 100 connected to a three-phase AC power supply 200 will be described. In the illustrated example, the number of phases of the AC power supply 200 is three, but the number of phases of the AC power supply 200 does not particularly limit the present invention. It may be a phase AC power supply. Examples of the AC power supply 200 include a three-phase 400V AC power supply, a three-phase 200V AC power supply, a three-phase 600V AC power supply, and a single-phase 100V AC power supply. In the illustrated example, the number of phases of the motor 300 is three, but the number of phases of the motor 300 does not particularly limit the present invention. It may be a motor. Also, the motor 300 may be an induction motor or a synchronous motor. The motor 300 is used, for example, as a drive source for a feed shaft or spindle of a machine tool, or an arm of an industrial machine or an industrial robot.

The motor drive device 100 includes a converter 61 , an inverter 62 , a smoothing capacitor 63 , a motor control section 64 and a current detection device 1 .

The converter 61 converts the AC power supplied from the AC power supply 200 into DC power and outputs it to the DC link. Converter 61 is configured as a three-phase bridge circuit when three-phase AC power is supplied from AC power supply 200 , and is configured as a single-phase bridge circuit when single-phase AC power is supplied from AC power supply 200 . In the illustrated example, since the AC power supply 200 is a three-phase AC power supply, the converter 61 is configured by a three-phase bridge circuit. There is a rectifier circuit of the system.

A smoothing capacitor 63 is provided in the DC link, which is a circuit portion that electrically connects the DC output side of the converter 61 and the DC input side of the inverter 62 . A DC link may be referred to as a "DC link section," "DC link," "DC link section," "DC bus," or "DC intermediate circuit." The smoothing capacitor 63 is sometimes called a "DC link capacitor" or the like. The smoothing capacitor 63 has a function of accumulating energy (DC power) in the DC link and a function of suppressing pulsation of the DC side output of the converter 61 . As the smoothing capacitor 63 is charged, DC power is accumulated in the DC link.

The inverter 62 converts the DC power in the DC link into AC power and outputs it to the motor 300 side. The inverter 62 is composed of a switching element and a bridge circuit of diodes connected in anti-parallel to the switching element. Inverter 62 is composed of a three-phase bridge circuit when motor 300 is a three-phase AC motor, and is composed of a single-phase bridge circuit when motor 300 is a single-phase AC motor. In the illustrated example, the motor 300 is a three-phase AC motor, so the inverter 62 is configured with a three-phase bridge circuit. Examples of the inverter 62 include a PWM inverter including semiconductor switching elements therein. The semiconductor switching element is composed of, for example, a unipolar transistor such as an FET, a bipolar transistor, an IGBT, a thyristor, a GTO, or the like. may be

For example, the current detection device 1 is provided on the power line connecting the inverter 62 and the motor 300 .

The motor control unit 64 generates a drive command for on/off controlling each semiconductor switching element of the inverter 62 and outputs it to the inverter 62 . The motor control unit 64 receives the current value digital data output from the current detection device 1 (corrected by the second offset correction unit 15) and the rotation speed (speed feedback), a predetermined torque command, an operation program for the motor 300, and the like. Motor 300 is controlled in speed, torque, or rotor position based on the AC power supplied from inverter 62 . Note that the configuration of the motor control unit 64 described here is merely an example, and terms such as a position command generation unit, a position control unit, a speed control unit, a current control unit, and a torque command generation unit are included in the motor control unit. A configuration of the portion 64 may be defined. An arithmetic processing unit (processor) is provided in the motor control unit 64 . Examples of arithmetic processing units include ICs, LSIs, CPUs, MPUs, and DSPs. The motor control unit 64 having an arithmetic processing unit is, for example, a functional module implemented by a computer program executed on a processor. For example, when the motor control section 64 is constructed in the form of a computer program, the function of each section can be realized by operating the arithmetic processing unit according to this computer program. A computer program for executing the processing of the motor control unit 64 may be provided in a form recorded in a computer-readable recording medium such as a semiconductor memory, magnetic recording medium, or optical recording medium. Alternatively, the motor control unit 64 may be realized as a semiconductor integrated circuit in which a computer program for realizing the function is written.

It should be noted that the installation location and application of the current detection device 1 shown in FIG. 8 are an example. For example, the current detection device 1 may be provided on the power line on the input side of the converter 61 and used to detect the input current to the motor drive device 100 . Further, for example, the current detection device 1 may be provided in a DC link and used to detect a DC link current. Further, the current detection device 1 may be used to detect various currents in a motor drive device that controls driving of a DC motor. In addition, the current detection device 1 may be used for current detection in various electric devices such as computer products, home electric appliances, trains, automobiles, and aircrafts, as well as motor drive devices. In any of the application examples described above, the current value digital data (corrected by the second offset correction unit 15) output from the current detection device 1 is used as the current detection value in the electrical equipment.

Although preferred embodiments according to the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes can be made within the scope of claims.

Reference Signs List 1 current detection device 2 current path 11 main current detection circuit 12 current detection circuit for offset correction 13 short-circuit portion 14 first offset correction portion 15 second offset correction portion 21

current detection resistor

22, 23

AD converter

31, 32, 34 , 35

filter resistor

33, 36 filter capacitor 40 LSI (Large Scale Integrated Circuit)
51 Switch Unit 61 Converter 62 Inverter 63 Smoothing Capacitor 64 Motor Control Unit 100 Motor Driving Device 200 AC Power Supply 300 Motor

Claims

a main current detection circuit that detects a current on the current path and outputs digital data corresponding to the current;
an offset correction current detection circuit that detects the current on the current path at the same detection location as the main current detection circuit and outputs digital data corresponding to the current;
a short-circuiting portion that short-circuits the current input terminals of the AD converter in the current detection circuit for offset correction;
A first offset output from the offset-correcting current detection circuit when the current input terminals are short-circuited by the short-circuit portion is measured, and an amount equivalent to the first offset is obtained from the output of the offset-correcting current detection circuit. a first offset corrector that performs a correction to remove the
The output of the main current detection circuit and the output corrected by the first offset correction section of the offset correction current detection circuit obtained at the same detection timing when the short-circuiting section does not short-circuit the current input terminals. a second offset correction that calculates a second offset output from the main current detection circuit based on and removes an amount corresponding to the second offset from the output of the main current detection circuit. Department and
A current sensing device comprising:
The current detection device according to claim 1, wherein the first offset correction unit measures the first offset and corrects the output of the current detection circuit for offset correction at a predetermined cycle.
The second offset correction section is adapted to output the output of the main current detection circuit and the current detection circuit for offset correction obtained at the same detection timing at each of a plurality of times when the short-circuiting section does not short-circuit the current input terminals. 3. The current detection device according to claim 1, wherein said second offset is calculated based on the output corrected by said first offset correction unit of .
When the short-circuiting portion does not short-circuit the current input terminals, the output of the main current detection circuit at time t1 is I1 ( t1 ), and the output of the offset correction current detection circuit at time t1 is I1( t1 ). I 2 (t 1 ) is the output corrected by the offset correction unit of , I 1 (t 2 ) is the output of the main current detection circuit at time t 2 , and I 1 (t 2 ) is the output of the offset correction current detection circuit at time t 2 . When the output corrected by the first offset correction section is I 2 (t 2 ), the second offset correction section

4. The current sensing device of claim 3, wherein the second offset Iof is calculated according to:
each of the main current detection circuit and the offset correction current detection circuit is a shunt resistor type current detection circuit,
Each filter resistor provided on the input side of each of the AD converters of the main current detection circuit and the offset correction current detection circuit has a shunt resistor shared by the main current detection circuit and the offset correction current detection circuit. The current detection device according to any one of claims 1 to 4, having a large resistance value.
When the current input terminals are short-circuited by the short-circuit portion, the inflow of current from the current path to the current input terminal is cut off, and when the short-circuit portion does not short-circuit the current input terminals, the current flows from the current path. The current detection device according to any one of claims 1 to 5, further comprising a switch section that does not block the inflow of current to the input terminal.
A current detection device according to any one of claims 1 to 6,
A motor drive device that controls driving of a motor using the output corrected by the second offset correction section of the main current detection circuit.