WO2023159192A2 - Methods and structures to improve the performance of iii-nitride tunnel junctions - Google Patents

Methods and structures to improve the performance of iii-nitride tunnel junctions Download PDF

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WO2023159192A2
WO2023159192A2 PCT/US2023/062837 US2023062837W WO2023159192A2 WO 2023159192 A2 WO2023159192 A2 WO 2023159192A2 US 2023062837 W US2023062837 W US 2023062837W WO 2023159192 A2 WO2023159192 A2 WO 2023159192A2
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nitride
ill
layer
nitride layer
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WO2023159192A3 (en
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Philip Chan
Matthew S. WONG
Shuji Nakamura
Daniel A. Cohen
Emily TRAGESER
Steven P. Denbaars
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The Regents Of The University Of California
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
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    • H01S5/00—Semiconductor lasers
    • H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
    • H01S5/0607—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying physical parameters other than the potential of the electrodes, e.g. by an electric or magnetic field, mechanical deformation, pressure, light, temperature
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
    • H—ELECTRICITY
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/305—Structure or shape of the active region; Materials used for the active region characterised by the doping materials used in the laser structure
    • H01S5/3095—Tunnel junction
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
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    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261—Non-optical elements, e.g. laser driver components, heaters
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    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054—Methods of obtaining the confinement
    • H01S5/2059—Methods of obtaining the confinement by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion
    • H01S5/2063—Methods of obtaining the confinement by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion obtained by particle bombardment
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    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm
    • H01S5/32341—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm blue laser based on GaN or GaP

Definitions

  • the n-type AkGa z N / n-type Al p Ga w N superlattice is comprised of one or more periods of an n-type AkGa z N / n-type Al p Ga w N heterostructure.
  • Each layer of the n-type AkGa z N / n-type Al p Ga w N heterostructure or superlattice has a thickness of at least 2 nm, but the thickness of each layer need not be identical to other layers of the n-type AkIn y Ga z N / n-type Al p In q Ga w N heterostructure or superlattice.
  • FIG. 13 is a schematic of a preferred embodiment for a VCSEL, wherein the device is bonded anode-down to a carrier.
  • Block 801 represents the optional step of growing a Ill-nitride template on or above the substrate.
  • the Ill-nitride template may comprise GaN when fabricating InGaN-based devices.
  • the current density through the junction also depends on the carrier effective masses in the tunneling direction.
  • the hole mass is determined by the curvature of the uppermost valence band, which depends on the strain. It has been shown theoretically that in [0001] -oriented GaN an in-plane tensile strain of only 0.04% can produce a nine-fold reduction in the hole mass for holes traveling in the surface-normal direction, that is, in the direction perpendicular to the tunnel junction.
  • the ITO of the preferred embodiment is replaced with epitaxially-grown compressively-strained n-type (Al,Ga,In)N of a composition and thickness suitable to induce adequate tensile strain in the underlying p-type (Al,Ga,In)N.
  • This embodiment corresponds to the fourth row of the Table in FIG. 12.
  • the strain inducing structure may include an electron-accepting layer.
  • Block 1608 represents the end result of the method, namely, a Ill-nitride device according to the present invention.
  • the Ill-nitride device may comprise, for example, an LED, LD, VCSEL, EELD, or other optoelectronic device.

Abstract

A III-nitride tunnel junction (TJ) is grown on or above a III-nitride device structure, wherein the III-nitride tunnel junction comprises an n-type III-nitride layer grown on or above a p-type III-nitride layer. An n-type AlxGazN / n-type AlpGawN superlattice (SL) is grown on or above the n-type III-nitride layer of the III-nitride tunnel junction to enhance the electrical performance of the tunnel junction, wherein x+z=1, p+w=1, 0≤x≤1, 0≤z≤1, 0≤p≤1, 0≤w≤1. Tensile strain can also be used to improve tunnel junction performance, wherein a variety of methods can be used to induce the required strain, resulting in improved current injection into the devices to increase the output power, emission uniformity and efficiency of the devices.

Description

METHODS AND STRUCTURES TO IMPROVE THE PERFORMANCE OF III-NITRIDE TUNNEL JUNCTIONS
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned applications:
U.S. Provisional Application Serial No. 63/311,583, filed on February 18, 2022, by Philip Chan, Matthew S. Wong, and Shuji Nakamura, entitled “METHOD TO IMPROVE THE PERFORMANCE OF III-NITRIDE TUNNEL JUNCTIONS,” attorneys’ docket number G&C 30794.0814USP1 (UC 2022-779-1); and
U.S. Provisional Application Serial No. 63/319,571, filed on March 14, 2022, by Daniel A. Cohen, Emily Trageser and Steven P. DenBaars, entitled “TUNNEL JUNCTION COMPRISING TENSILE-STRAINED (Al,Ga,In)N,” attorneys’ docket number G&C 30794.0815USP1 (UC 2022-787-1); both of which applications are incorporated by reference herein.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
This invention was made with Government support under Grant No. HR001120C0135 awarded by the Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in this invention.
BACKGROUND OF THE INVENTION
1. Field of the Invention.
This invention relates generally to light-emitting diodes (LEDs) and laser diodes (LDs), and more specifically, to method and structures to improve the performance of III -nitride tunnel junctions (TJs) used in LEDs and LDs. 2. Description of the Related Art.
(Note: This application references a number of different publications as indicated throughout the specification by one or more reference numbers in brackets, e.g., [x] . A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References.” Each of these publications is incorporated by reference herein.)
This invention describes improvements to semiconductor tunnel junctions for use in light emitting diodes (LEDs), laser diodes (LDs), vertical-cavity surfaceemitting lasers (VCSELs) and edge-emitting laser diodes (EELDs) based on III- nitride alloys. [1,2]
In this context, the term “Ill-nitride,” or equivalently, “Group-Ill nitride” or “III-N” or “nitride” refers to any composition or material related to (B, Al, Ga, In, Sc, Y)N semiconductors having the formula BuAlvGawInxScyYzN where 0<u<l, 0<v<l, 0<w<l, 0<x<l, 0<y<l, 0<z<l,and u+v+w+x+y+z=l. The most common Ill-nitride materials in commercial use comprise (Al,Ga,In)N, but this invention is not limited to (Al,Ga,In)N, and encompasses all Ill-nitrides.
Tunnel junctions are used to convert an electron current in an n-type current spreading layer into a hole current prior to injection into the light emitting device’s active region. This improves the uniformity of current injection compared to devices in which the current spreading is done with a semitransparent metal layer or in a p- type (Al,Ga,In)N layer.
Compared to other conventional current spreading layers, including semitransparent metal layers, such as Ni/Au, or transparent conductive oxides (TCOs), such as indium-tin oxide (ITO), tunnel junctions are more optically transparent or less absorbing, which allows more light emitted from the device and enhances the light extraction efficiency of the device.
Tunnel junctions require an electrical bias to operate and introduce some additional voltage beyond the bias needed to operate the light emitting active region junction and the voltage due to bulk resistance in the various device layers. However, a voltage penalty issue hinders the electrical performance of tunnel junctions, particularly in a high current density operating range.
What is needed, then, are methods that improve the electrical performance of tunnel junctions in Ill-nitride devices. The present invention satisfies this need.
SUMMARY OF THE INVENTION
The present invention discloses method and structures to improve the performance of III -nitride tunnel junctions.
In a first embodiment, a III -nitride device includes a Ill-nitride tunnel junction comprising an n-type Ill-nitride layer grown on or above a p-type Ill-nitride layer; with an n-type AlxGazN / n-type AlpGawN superlattice (SL) grown on or above the n- type Ill-nitride layer of the Ill-nitride tunnel junction, wherein x+z=l, p +w=l, 0<x<l, 0<z<l, 0<p<l, 0<w<l. The n-type AkGazN / n-type AlpGawN superlattice is comprised of one or more periods of an n-type AkGazN / n-type AlpGawN heterostructure. Each layer of the n-type AkGazN / n-type AlpGawN heterostructure or superlattice has a thickness of at least 2 nm, but the thickness of each layer need not be identical to other layers of the n-type AkInyGazN / n-type AlpInqGawN heterostructure or superlattice.
In a second embodiment, tensile strain is used to improve tunnel junction performance in Ill-nitride devices, wherein a variety of methods can be used to induce the required strain, resulting in improved current injection into the devices to increase the output power, emission uniformity and efficiency of the devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
FIG. 1 is a schematic illustration of a Ill-nitride tunnel junction structure, according to one embodiment of the present invention. FIG. 2 is a schematic illustration of an epitaxial structure for a Ill-nitride tunnel junction, according to one embodiment of the present invention.
FIG. 3 is a schematic illustration of a Ill-nitride tunnel junction with heterostructures, where i and j are the corresponding thickness in each layer of the superlattice and k is the number of periods in the superlattice.
FIG. 4 is a table of voltage values for various device dimensions at different current densities.
FIG. 5 is a graph of current density (A/cm2) vs. voltage (V) for a Ill-nitride tunnel junction device of the present invention and a reference device, wherein the devices have dimensions of 5x5 pm2.
FIG. 6 is a graph of current density (A/cm2) vs. voltage (V) for a Ill-nitride tunnel junction device of the present invention and a reference device, wherein the devices have dimensions of 20x20 pm2.
FIG. 7 is a graph of current density (A/cm2) vs. voltage (V) for a Ill-nitride tunnel junction device of the present invention and a reference device, wherein the devices have dimensions of 80x80 pm2.
FIG. 8 is a flowchart that illustrates the steps for a process of fabricating a III- nitride device structure, according to the present invention.
FIG. 9(a) is a schematic of a state of the art tunnel junction LED, and FIG. 9(b) is a graph of current density (A/cm2) vs. forward voltage (V) showing Current- Voltage characteristics for state of the art tunnel junction LEDs of various sizes, wherein the minimum equivalent contact resistance extracted from the slope is 5 x 10' 3 Ohm-cm'2.
FIG. 10 is a graph of volts vs. current density (A/cm2) showing simulated IV characteristics for a GaN tunnel junction assuming an unstrained hole effective mass of 1.8 mo and a tensilely strained hole mass of 0.2 mo, wherein verification of the model is by comparison to experimental data on an unstrained blue micro LED.
FIG. 11 shows a calculated strain field below a ring stressor, wherein the stressor thickness is 0.5 pm and the interface stress is 0.5 gigapascals (Gpa). FIG. 12 is a Table that illustrates various embodiments of the invention, showing types, applications and schematics of the structures, wherein details of the structures, such as active region or waveguide designs, have been omitted for clarity, and concentric arcs or arrowheads in the schematics indicate the strain field or direction.
FIG. 13 is a schematic of a preferred embodiment for a VCSEL, wherein the device is bonded anode-down to a carrier.
FIG. 14 is a schematic of a preferred embodiment for an LED, wherein sputtered AIN forms a ring stressor.
FIGS. 15(a) and 15(b) are schematics of a preferred embodiment for an EELD, wherein FIG. 15(a) is an end view of the structure, and FIG. 15(b) is a side view of the structure showing segmentation of an ITO stressor and p-GaN to increase local strain without excessive bowing.
FIG. 8 is a flowchart that illustrates the steps for a process of fabricating a III- nitride device structure, according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
Ill-nitride tunnel junction with an n-type AlGaN / AlGaN superlattice Overview
Due to the electrical resistive characteristics of p-type Ill-nitride layers, current spreading layers, such as ITO, and semi-transparent metal contacts, have been employed to enhance the optoelectrical performances of III -nitride light emitters. However, these current spreading layers are generally more optically absorbing as compared to the Ill-nitride materials, resulting in a reduction in light extraction efficiency.
In contrast, n-type Ill-nitride materials are orders of magnitude more conductive than their p-type III -nitride material counterparts, with excellent transparency as compared to common current spreading layers. Therefore, tunnel junctions, which are comprised of p-type and n-type Ill-nitride layers, can be used as a current spreading layer that offers better optical properties.
However, one main drawback of tunnel junctions is the penalty of excess voltage and the penalty increases significantly with applied current. This invention utilizes an n-type AlpGawN / n-type AkGazN heterostructure and superlattice, where p+w=l, x+z=l, 0<p<l, 0<w<l, 0<x<l, 0<z<l, on the n-side of a Ill-nitride tunnel junction, which reduces the voltage penalty as compared to conventional GaN-based tunnel junctions. Thus, this invention enhances the electrical conductivity of III- nitride tunnel junctions.
Technical Description
As shown in FIG. 1, a Ill-ni tride TJ 100 is comprised of p-type and n-type III- nitride TJ layers 101, 102, with other layers 103, 104, below and above the p-type and n-type Ill-nitride TJ layers 101, 102. In this context, the p-type and n-type Ill-nitride TJ layers 101, 102 comprise an n++-type or n-type AlalnbGacN layer grown on or above a p++-type or p-type AlalnbGacN layer, wherein a+b+c=l, 0<a<l, 0<b<l, 0<c<l. Due to the nature of Ill-nitride TJs 100, the p-type and n-type III -nitride TJ layers 101, 102 should be as thin as possible to yield a narrow tunneling barrier or high tunneling probability. Therefore, additional layers are needed for current spreading purposes.
As shown in FIG. 2, one or more n-type GaN layer(s) 200 (with a thickness of x nm) and/or one or more n-type Ill-nitride layer(s) 201 may be grown on or above the n-type Ill-nitride TJ layers 102 to enhance the current spreading performance before growing subsequent layers. As shown in FIG. 3, this invention describes the use of an n-AlxGazN / n- AlpGawN SL 300, wherein x+z=l, p+w=l, 0<x<l, 0<z<l, 0<p<l, 0<w<l, on the n- side of a Ill-nitride TJ 100, i.e., on or above the n-type Ill-nitride TJ layers 102, to enhance the electrical performance of the TJ 100. In one embodiment, the n-type III- nitride TJ layers 102 comprises an n++-type AlalnbGacN layer 102 grown on or above the p-type Ill-nitride TJ layers 101 that comprises a p++-type or p-type III -nitride layer 101, wherein a+b+c=l, 0<a<l, 0<b<l, 0<c<l, and the n-AkGazN / n-AlPGawN SL 300 is comprised of one or more periods of an n-AlxGazN / n-AlpGawN heterostructure 302, 301, which may be repeated k times (x k), wherein the n- AlpGawN layer 301 has a thickness of j nm and the n-AlxGazN layer 302 has a thickness of i nm. In this embodiment, each layer of the n-AlxGazN / n-AlpGawN heterostructure 302, 301 and SL 300 has a thickness of at least 2 nm, but the thickness of each layer 301, 302 may or may not be identical to other layers of the n-AlxGazN / n-AlpGawN heterostructure 302, 301 and SL 300.
The use of the n-AlxGazN / n-AlpGawN SL 300 provides additional electrical benefits from strain-related effects, two-dimensional electron gas (2DEG), and/or two-dimensional hole gas (2DHG). As shown in the table of FIG. 4 and the graphs of FIGS. 5, 6, and 7, the cause of the strain-related effects, 2DEG, or 2DHG, is attributed to the presence of the AlxGazN / AlpGawN heterostructure 302. 301 in the SL 300, where the resulting impact is the increase in carrier concentration.
Specifically, FIG. 4 is a table of voltage values for various device dimensions at different current densities;
FIG. 5 is a graph of current density (A/cm2) vs. voltage (V) for a Ill-nitride tunnel junction device of the present invention and a reference device, wherein the devices have dimensions of 5x5 pm2;
FIG. 6 is a graph of current density (A/cm2) vs. voltage (V) for a Ill-nitride tunnel junction device of the present invention and a reference device, wherein the devices have dimensions of 20x20 pm2; and FIG. 7 is a graph of current density (A/cm2) vs. voltage (V) for a Ill-nitride tunnel junction device of the present invention and a reference device, wherein the devices have dimensions of 80x80 pm2.
Method of Fabrication
FIG. 8 is a flowchart that illustrates the steps for a process of fabricating a III- nitride device according to the present invention. Specifically, the flowchart illustrates the steps for a method comprising fabricating a Ill-nitride device structure including a Ill-nitride TJ according to the present invention.
Block 800 represents the step of loading a substrate into a chamber of a metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) reactor. The substrate may comprise sapphire, silicon (Si), silicon carbide (SiC), glass, Ill-nitride materials such as GaN and AIN with any crystal orientation such as nonpolar and semipolar, or other materials.
Block 801 represents the optional step of growing a Ill-nitride template on or above the substrate. The Ill-nitride template may comprise GaN when fabricating InGaN-based devices.
Block 802 represents the step of epitaxially growing a III -nitride device structure on or above the Ill-nitride template and/or substrate.
Block 803 represents the step of epitaxially growing a III -nitride tunnel junction on or above an n-type Ill-nitride layer of the Ill-nitride device structure, wherein the Ill-nitride tunnel junction comprises an n-type Ill-nitride layer on or above a p-type Ill-nitride layer. Generally, the n-type Ill-nitride layer of the III- nitride tunnel junction comprises an n++-type Ill-nitride and the p-type Ill-nitride layer of the Ill-nitride tunnel junction comprises a p++-type Ill-nitride layer
Block 804 represents the step of epitaxially growing an n-type AkGazN / n- type AlpGawN superlattice on or above the n-type Ill-nitride layer of the Ill-nitride tunnel junction, wherein x+z=l, p+w=l, 0<x<l, 0<z<l, 0<p<l, 0<w<l. The n-type AkGazN / n-type AlpGawN superlattice is comprised of one or more periods of an n-type AkGazN / n-type AlpGawN heterostructure.
In one embodiment, each layer of the n-type AkGazN / n-type AlpGawN heterostructure has a thickness of at least 2 nm. However, the thickness of each layer of the n-type AkGazN / n-type AlpGawN heterostructure need not be identical to other layers of the n-type AkGazN / n-type AlpGawN heterostructure.
Block 805 represents the step of processing the Ill-nitride device structure into a III -nitride device, and then packaging the device. This may include, but is not limited to, depositing TCO layers, sub-mounting, etching mesas or ridge waveguides, passivating sidewalls, depositing electrodes, etc.
Block 806 represents the end result of the method, namely, a Ill-nitride device. The Ill-nitride device may comprise, for example, an LED, LD, solar cell, or other optoelectronic device.
The above steps may be modified, eliminated, repeated, or completed in any desired order, without departing from the scope of the present invention.
Ill-nitride tunnel junction with tensile strained n-type (Al.GaJn)N Overview
A state-of-the-art LED example including a Ill-nitride TJ is shown schematically in FIG. 9(a), along with its current-voltage (IV) characteristics in FIG. 9(b). [3] The LED includes an n-GaN template on a patterned sapphire substrate (PSS) 900, active region 901, p-GaN layer 902, p+ GaN layer 903, n-InGaN layer 904, n+ GaN layer 905, n-GaN layer 906, omnidirectional reflector (ODR) 907, SiCh passivation layer 908, and Al/Ni/Au n-type contacts 909. A TJ 910 is formed by the p+ GaN layer 903, n-InGaN layer 904 and n+ GaN layer 905.
By careful control of the doping and thickness of the n-type and p-type TJ layers 903, 904, 905, the device tum-on voltage is only a small fraction of a volt above the tum-on voltage of the light emitting active region 901. However, the slope resistance is still significant and, at a current density of 100 A/cm2, the excess voltage approaches one volt, with an equivalent contact resistivity of 5 x 10'3 Ohm-cm2. Tunnel junctions do not achieve contact resistivities below 1 x 10'4 Ohm-cm2, comparable to that for metallic contacts, but it is still a limitation on the power and efficiency of high-brightness LEDs and LDs.
In most cases, the tunnel junctions are homojunctions fabricated in GaN, but (Al,Ga,In)N heterojunctions have also been demonstrated, and InGaN-GaN or GaN- InGaN-GaN tunnel junctions presently provide the best performance. [3] In these cases, the n-type InGaN is compressively strained and induces a very small tensile strain in the adjacent GaN, but the InGaN composition, thickness, and extended geometry is such that the strain induced in the adjacent GaN is inadequate to reduce the hole mass.
ITO tunneling contacts to p-type GaN or p-type InGaN are commonplace and are also limited to contact resistivities higher than 1 x 10'4 Ohm-cm2. [4,5] In these contacts, the vapor-deposited ITO is amorphous or poly crystalline, and induces insignificant strain on the underlying GaN.
There are reports of metallic anode contacts to p-type GaN with contact resistivities below 1 x 10'5 Ohm-cm2 [6], although such values are controversial and have not been achieved in commercial devices. In these reports, the metal is diffused into the GaN, forming microscopic islands of an intermediate composition. The unexpectedly high performance of these contacts has sometimes been attributed to strain effects, but also to lowered heterobarriers and without theoretical or experimental justification. Furthermore, even very thin “semitransparent” metallic contacts introduce significant optical loss into LEDs and an unacceptable loss into VCSELs.
This invention describes innovations to semiconductor tunnel junctions for use in LEDs, LDs, VCSELs and EELDs based on (Al,Ga,In)N alloys. Such tunnel junctions are used to convert an electron current in an n-type current spreading layer into a hole current prior to injection into the light emitting device’s active region. This improves the uniformity of current injection and reduces the optical loss compared to devices in which the current spreading is done with a semitransparent metal layer or in a p-type (Al,Ga,In)N layer. In many (Al,Ga,In)N light emitters, the anode contact is formed with an n-type transparent conducting oxide, such as nickel oxide or ITO, deposited upon a p-type (Al,Ga,In) layer. These anode contacts are also semiconductor tunnel junctions. Indeed, even so-called Ohmic contacts formed between a metal layer and p-type (Al,Ga,In)N depend to some extent on tunneling and will benefit from the innovations described below.
Tunnel junctions require an electrical bias to operate and introduce some additional voltage beyond the bias needed to operate the light emitting active region junction and the voltage due to bulk resistance in the various device layers. The key innovation of this invention is to induce in-plane tensile strain in the p-type (Al,Ga,In)N portion of the tunnel junction, thereby lowering the hole effective mass and reducing the voltage needed to drive current through the tunnel junction. This leads to a significant improvement in the power conversion efficiency of the device and enables operation at higher power and brightness. This, in turn, provides significant commercial advantage over the present state of the art.
Principles of Operation
A semiconductor tunnel junction is a highly doped pn junction operated in reverse bias such that the valence band on the p-side aligns with the conduction band on the n-side. Electrons in the p-side valence band may tunnel across the band gap to unfilled conduction band states on the n-side, leaving behind holes in the p-side valence band. In this way, an electron current at the reverse biased anode produces a hole current that can travel to the device active region. The tunneling probability depends on the depletion width at the tunnel junction, which in turn depends on the doping profiles on each side of the junction and on the voltage applied across the tunnel junction. High and abrupt doping leads to a low turn-on voltage. The current density through the junction also depends on the carrier effective masses in the tunneling direction. [7,8] The hole mass is determined by the curvature of the uppermost valence band, which depends on the strain. It has been shown theoretically that in [0001] -oriented GaN an in-plane tensile strain of only 0.04% can produce a nine-fold reduction in the hole mass for holes traveling in the surface-normal direction, that is, in the direction perpendicular to the tunnel junction. [9] The impact on the IV characteristic is shown in FIG. 10, which compares the case of an (unstrained) hole mass m =1.8 mo to the (strained) case of m =0.2 mo. At a current density of Ik A/cm2, the reduction in voltage is a full 1 Volt, 20% of the operating voltage of a typical high brightness LED, producing a 20% improvement in the power conversion efficiency.
The required strain may be produced in many ways and the preferred embodiment depends on the structure of the device into which the tunnel junction is incorporated. In most cases, a patterned film of a material under internal strain, hereafter referred to as a stressor, is disposed upon the p-type (Al,Ga,In)N surface. The interface bond limits the relaxation of the stressor and the reaction force applies an opposite stress to the underlying (Al,Ga,In)N. If the stressor is directly above the tunnel junction, then a compressive stressor induces tension in the underlying (Al,Ga,In)N and tension in the (Al,Ga,In)N below and to the side of the stressor. Conversely, a stressor under tensile internal stress will induce compression directly below, and tension below and to the side. The stressor’s internal strain may be controlled by choice of material, deposition technique and thickness, and the induced strain in the underlying material may be further controlled by the stressor geometry. FIG. 11 shows the calculated displacement fields below a ring stressor suitable for use with an LED or VCSEL.
Some representative preferred and alternative embodiments are described below.
Preferred and Alternative Embodiments
Various embodiments are shown schematically in the Table of FIG. 12, which has columns for a type of stressor, an application of the stressor, and a general schematic of the resulting device, and rows for a tensile metal or dielectric ring stressor used in LED or VCSEL applications, an AlGaN TJ on p-GaN used in LED or VCSEL applications, a compressively stressed ITO on p-GaN used in LED or LD applications, a thick n-InGaN / p-GaN TJ used in LD applications, and a metal / p- AlGaN / p-GaN used in LD applications. Details of the structures such as the design of the active region or waveguide layers are omitted from the general schematics, because this invention is versatile and does not depend significantly on those details.
1. Preferred Embodiment for a VCSEL
FIG. 13 shows schematically a preferred embodiment for a VCSEL, based on a previously reported VCSEL [10], but applicable to other cavity designs. This embodiment corresponds to the first row of the Table in FIG. 12.
The VCSEL includes a submount 1300, bonding metal 1301, distributed Bragg reflector (DBR) 1302, ring stressor 1303, n-GaN layer 1304, TJ 1305, ion implantation 1306, p-GaN layer 1307, p-AlGaN layer 1308, active region 1309, n- GaN layer 1310, n-GaN contact layer 1311, cathode contact 1312, and DBR 1313.
Ion implantation 1306 and/or the buried tunnel junction 1305 are used to define a current aperture of some diameter. A tensile stressor 1303 in the shape of a ring is disposed upon the n-type GaN current spreading layer 1304 such that tensile strain is induced in the n-type and p-type (Al,Ga,In)N layers 1304, 1305, 1307, 1308 within the current aperture. The magnitude of the induced strain decreases with depth below the surface and may be designed to be sufficient to reduce the hole mass at the tunnel junction 1305 but negligible at the depth of the active region 1309. In this embodiment, the ring stressor 1303 is metallic and also serves as the anode contact. A suitable stressor material is tungsten, which is known to support internal stress above +1 GPa, the sign dependent upon the deposition parameters, and is stiff enough to effectively induce strain in the less-stiff underlying (Al,Ga,In)N layers 1304, 1305, 1307, 1308. Other suitable materials include, but are not limited to, platinum, palladium, molybdenum, nickel, and ITO. 2. Preferred Embodiment for an LED
FIG. 14 shows schematically a preferred embodiment for an LED, based on a previously reported LED [11], but applicable to other LED designs. This embodiment also corresponds to the first row of the Table in FIG. 12.
The LED includes a substrate 1400, n-GaN layer 1401, active region 1402, p- AlGaN layer 1403, p-GaN layer 1404, TJ 1405, n-GaN layer 1406, ion implantation 1407, ring stressor 1408, AIN 1409, anode 1410 and cathode 1411.
The embodiment is similar to the VCSEL in FIG. 11, but the resonator cavity and distributed Bragg reflectors (DBRs) are omitted. The ring stressor 1408 is electrically inactive but is in the path of light extraction, so an optically absorbing metallic stressor would limit the light extraction efficiency. Instead, a tensile stressed transparent film is used. Sputter-deposited AIN 1409 is shown in this example, but other dielectric materials such as silicon dioxide, silicon nitride, and aluminum oxide, are among many suitable alternatives.
3. Alternative Embodiment for a VCSEL or LED
As shown in the second row of the Table in FIG. 12, the tunnel junction is fabricated entirely within epitaxially-grown tensile-strained (Al,Ga,In)N. In the case of a VCSEL or LED with an InGaN active region designed to emit visible light, a suitable strained tunnel junction may be formed from n-type AlGaN grown upon p- type AlGaN, both layers tensile-strained to GaN.
4. Preferred Embodiment for an EELD
FIG. 15(a) shows schematically a preferred embodiment for an EELD, based on a previously reported laser [4], but applicable to other edge-emitting laser designs. This embodiment corresponds to the third row of the Table in FIG. 12.
The EELD includes a cathode 1500, n-GaN layer 1501, n-GaN cladding 1502, n-InGaN waveguide 1503, InGaN/GaN active region 1504, p- Al GaN EBL 1505, p- GaN waveguide 1506, p-GaN cladding 1507, p++ GaN 1508, ITO 1509, SiO2 1510, and anode 1511.
In this case, there is no need for a current spreading layer or tunnel junction to convert an electron current to a hole current. Instead, the ITO 1509 and anode 1511, which also serve as the laser waveguide’s upper cladding layer, form the n-side of a tunnel junction with p++ GaN 1508. In this case, the ITO 1509 is deposited with compressive internal stress such that tensile stress 1512 is induced in the (Al,Ga,In)N layers 1508, 1507 directly below. Because the EELD is long and thin, rather than circular or nearly square as in the case of VCSELs or LEDs, continuous stress along the length of the laser would lead to unacceptable bowing. To avoid this, the ITO 1509 is interrupted intermittently along the length of the laser and the underlying (Al,Ga,In)N 1508 is etched shallowly to allow some relaxation of the material below the ITO-(Al,Ga,In)N tunnel junction 1509, 1508 at the surface, as shown in FIG. 15(b)
5. Alternative Embodiment for an EELD
In this embodiment, the ITO of the preferred embodiment is replaced with epitaxially-grown compressively-strained n-type (Al,Ga,In)N of a composition and thickness suitable to induce adequate tensile strain in the underlying p-type (Al,Ga,In)N. This embodiment corresponds to the fourth row of the Table in FIG. 12.
6. Alternative Embodiment for an EELD
In this embodiment, which corresponds to the fifth row of the Table in FIG. 12, the ITO and (Al,Ga,In)N segments are periodic with a period equal to a multiple of a half wavelength of the laser light in the waveguide, with a duty cycle and depth chosen to produce a coupling coefficient K of approximately 1/L where L is the length of the laser. [12] In this case, a single-frequency distributed feedback (DFB) laser results. Method of Fabrication
FIG. 16 is a flowchart that illustrates the steps for a process of fabricating a Ill-nitride device according to the present invention. Specifically, the flowchart illustrates the steps for a method comprising fabricating a III -nitride device structure including a Ill-nitride TJ according to the present invention.
Block 1600 represents the step of loading a substrate into a chamber of a metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) reactor. The substrate may comprise sapphire, silicon (Si), silicon carbide (SiC), glass, Ill-nitride materials such as GaN and AIN with any crystal orientation such as nonpolar and semipolar, or other materials.
Block 1601 represents the optional step of growing a Ill-nitride template on or above the substrate. The Ill-nitride template may comprise GaN when fabricating InGaN-based devices.
Block 1602 represents the step of epitaxially growing a III -nitride device structure comprised of one or more (Al,Ga,In)N layers on or above the Ill-nitride template and/or substrate.
Block 1603 represents the step of epitaxially growing a III -nitride tunnel junction on or above the Ill-nitride device structure. Specifically, this Block represents the step of growing a p-type Ill-nitride layer of the III -nitride tunnel junction on or above the III -nitride device structure.
Block 1604 represents the step of activating the p-type III -nitride layer of the Ill-nitride tunnel junction by annealing, and then epitaxially growing an n-type III- nitride layer of the III -nitride tunnel junction on or above of the p-type Ill-nitride layer of the Ill-nitride tunnel junction, wherein the n-type Ill-nitride layer is an electron-accepting layer disposed on or above the p-type Ill-nitride layer.
Block 1605 represents the step of etching a mesa for the Ill-nitride device structure.
Block 1606 represents the step of depositing the anode and cathode contacts for the III -nitride device structure. Block 1607 represents the step of depositing a stressor for the III -nitride device structure, wherein the stressor is a strain inducing structure to induce in-plane tensile strain in the p-type Ill-nitride layers. Moreover, both the p-type Ill-nitride layer of the tunnel junction and the n-type Ill-nitride layer of the III -nitride tunnel junction may be in a state of in-plane tensile strain as compared to an unstrained state of the p-type Ill-nitride layer and/or the n-type Ill-nitride layer.
The strain inducing structure may include an electron-accepting layer.
The strain inducing structure may comprise tensile strained or compressively strained transparent conducting oxide or nitride on, above and/or to the side of the tunnel junction, wherein the transparent conducting oxide is ITO.
The strain inducing structure may comprise tensile strained or compressively strained metal or dielectric disposed on, above and/or to the side of the tunnel junction, wherein the metal is tungsten, molybdenum, palladium, platinum, nickel or alloys of these metals, and the dielectric is AIN.
The strain inducing structure may comprise tensile strained or compressively strained Ill-nitride layers disposed on, above and/or to the side of the tunnel junction.
The strain inducing structure may comprise a mechanical element incorporated into the device structure that presses or bends the p-type Ill-nitride layers.
Preferably, the in-plane tensile strain induced in the p-type III -nitride layers equals or exceeds 0.04%.
Alternatively, the III -nitride device structure may be strained such that it is unstrained relative to the p-type Ill-nitride layer.
In one embodiment, the Ill-nitride device structure is an EELD and the stressor is interrupted intermittently along a length of the EELD and the Ill-nitride layers underlying the stressor are etched shallowly to increase the strain in the remaining material below the stressor. For example, the stressor and the Ill-nitride layers underlying the stressor are etched and the etching is periodic with a period equal to a multiple of a half wavelength of the EELD’s light in a waveguide, with a duty cycle and depth chosen to produce a coupling coefficient K of approximately 1/L where L is a length of the EELD, resulting in a single frequency distributed feedback (DFB) laser.
Block 1608 represents the end result of the method, namely, a Ill-nitride device according to the present invention. The Ill-nitride device may comprise, for example, an LED, LD, VCSEL, EELD, or other optoelectronic device.
The above steps may be modified, eliminated, repeated, or completed in any desired order, without departing from the scope of the present invention.
Benefits and Advantages
Output power and power conversion efficiency are key metrics for many applications based on (Al,Ga,In)N LEDs or laser diodes, including solid state lighting, fixed and mobile displays, and mobile or remote sensing. Both the power and efficiency are limited by excess voltage needed to drive electrical current through the LEDs or lasers. The excess voltage at tunnel junctions used to aid current spreading or at tunnel junction contacts is a major source of this excess voltage. This invention reduces the excess voltage by more than 20%, producing an equivalent improvement in efficiency. This provides significant commercial advantage in mass markets that utilize these LEDs or laser diodes.
References
The following publications are incorporated by reference herein:
[1] A. Alhassan, “Reduced-droop green Ill-nitride light emitting diodes utilizing GaN tunnel junctions,” Appl. Phys. Express 11, 042101 (2018).
[2] C. A. Foreman, “Continuous-wave operation of m plane GaN based vertical cavity surface emitting lasers with a tunnel junction intracavity contact,” Appl. Phys. Letts. 112, 111106 (2018). [3] P. Li “Metalorganic chemical vapor deposition grown n InGaN/n GaN tunnel junctions for micro light emitting diodes with very low forward voltage,” Semicond. Sci. Technol. 35, 125023 (2020).
[4] S. Mehari, “Demonstration of enhanced continuous wave operation of blue laser diodes on a semipolar (20-2-1) GaN substrate using indium tin oxide / thin p-GaN cladding layers,” Optics Express 26, 1564 (2018).
[5] B. Yonkee, “Demonstration of low resistance ohmic contacts to p-type (20-2-1) GaN,” Semicond. Sci. Technol. 30, 075007 (2015).
[6] G. Greco, “Ohmic contacts to GaN materials,” Appl. Surface Sci. 383, 324-345 (2016).
[7] G. Hurkx, “A new recombination model for device simulation including tunneling,” IEEE Transactions on Electron Devices 39, 331-338 (1992).
[8] Silvaco Inc., ATLAS User’s Manual, Section 3.6.6 eqns. 3-480 through 3-484 (2016).
[9] Y. Kuroiwa, “Theoretical prediction of strain induced carrier effective mass modulation in 4H SiC and GaN,” Appl. Phys. Lett. 115, 112102 (2019).
[10] Keams, J., “Demonstration of blue semipolar (20-2-1) GaN based vertical cavity surface emitting lasers,” Optics Express 27, 23707 (2019).
[11] A. Alhassan, “Reduced droop green III -nitride light emitting diodes utilizing GaN tunnel junctions,” Appl. Phys. Express 11, 042101 (2018).
[12] L. Coldren, Diode Lasers and Photonic Integrated Circuits Ed. 2, Wiley & Sons, Hoboken N. J., (2012), section 3.7.
Conclusion
This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:
1. A device, comprising: a III -nitride tunnel junction (TJ) grown on or above a Ill-nitride device structure, wherein the Ill-nitride TJ comprises an n-type Ill-nitride layer on or above a p-type Ill-nitride layer; and an n-type AkGazN / n-type AlpGawN superlattice (SL) grown on or above the n-type Ill-nitride layer of the Ill-nitride TJ, wherein x+z=l, p+w=l, 0<x<l, 0<z<l, 0<p<l, 0<w<l.
2. The device of claim 1, wherein the n-type AkGazN / n-type AlpGawN SL is comprised of one or more periods of an n-type AkGazN / n-type AlpGawN heterostructure.
3. The device of claim 2, wherein each layer of the n-type AkGazN / n- type AlpGawN heterostructure has a thickness of at least 2 nm.
4. The device of claim 3, wherein the thickness of each layer of the n- type AkGazN / n-type AlpGawN heterostructure need not be identical to other layers of the n-type AkGazN / n-type AlpGawN heterostructure.
5. A method, comprising: fabricating a Ill-nitride tunnel junction (TJ) on or above a Ill-ni tride device structure, wherein the Ill-nitride TJ comprises an n-type Ill-nitride layer on or above a p-type Ill-nitride layer; and fabricating an n-type AkGazN / n-type AlpGawN superlattice (SL) on or above the n-type Ill-nitride layer of the Ill-nitride TJ, wherein x+z=l, p+w=l, 0<x<l, 0<z<l, 0<p<l, 0<w<l.
6. A device, comprising: an epitaxial device structure comprised of one or more Ill-nitride layers; and a tunnel junction (TJ) on or above the epitaxial device structure, wherein the TJ is comprised of a p-type Ill-nitride layer in a state of in-plane tensile strain as compared to an unstrained state of the p-type Ill-nitride layer, and an electronaccepting layer disposed on or above the p-type Ill-nitride layer.
7. The device of claim 6, wherein the electron-accepting layer is an n- type Ill-nitride layer.
8. The device of claim 6, wherein the electron-accepting layer is a transparent conducting oxide or nitride.
9. The device of claim 6, wherein the electron-accepting layer is a metal.
10. The device of claim 6, further comprising a strain inducing structure to induce the in-plane tensile strain in the p-type Ill-nitride layer.
11. The device of claim 10, wherein the electron-accepting layer is the strain inducing structure.
12. The device of claim 10, wherein the strain inducing structure is tensile strained or compressively strained Ill-nitride disposed on, above or to one or more sides of the TJ.
13. The device of claim 10, wherein the strain inducing structure is tensile strained or compressively strained metal or dielectric disposed on, above or to one or more sides of the TJ.
14. The device of claim 10, wherein the strain inducing structure is tensile strained or compressively strained conducting oxide or nitride other than Ill-nitride, disposed on, above or to one or more sides of the TJ.
15. The device of claim 10, wherein the strain inducing structure is a mechanical element incorporated in the device that presses or bends the p-type III- nitride layer.
16. The device of claim 6, wherein the in-plane tensile strain induced in the p-type Ill-nitride layer equals or exceeds 0.04%.
17. The device of claim 6, wherein the epitaxial device structure is strained such that it is unstrained relative to the p-type Ill-nitride layer.
18. The device of claim 17, wherein the stressor is interrupted intermittently along a length and the Ill-nitride layers underlying the stressor are etched shallowly to increase the strain in material below the stressor.
19. The device of claim 18, wherein the stressor and the Ill-nitride layers underlying the stressor are etched and the etching is periodic with a period equal to a multiple of a half wavelength of the device’s emitted light in a waveguide, with a duty cycle and depth chosen to produce a coupling coefficient K of approximately 1/L where L is the length of the device, resulting in a single frequency distributed feedback (DFB) laser.
20. A method, comprising: fabricating an epitaxial device structure comprised of one or more Ill-nitride layers; and fabricating a tunnel junction (TJ) on or above the epitaxial device structure, wherein the TJ is comprised of a p-type Ill-nitride layer in a state of in-plane tensile strain as compared to an unstrained state of the p-type Ill-nitride layer, and an electron-accepting layer disposed on or above the p-type Ill-nitride layer.
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