WO2023153509A1

WO2023153509A1 - Thin-film transistor and method for manufacturing thin-film transistor

Info

Publication number: WO2023153509A1
Application number: PCT/JP2023/004745
Authority: WO
Inventors: ちひろ今村; 学伊藤
Original assignee: 凸版印刷株式会社
Priority date: 2022-02-14
Filing date: 2023-02-13
Publication date: 2023-08-17
Also published as: JP7369340B2; JP2023117705A

Abstract

The present invention comprises: first gate insulation layer 21 which is provided with a flat part that follows a flat surface of a flexible base 11 and a step part 22 that covers a gate electrode layer 12 and that protrudes from the flat part, and which includes an organic atomic group; a second gate insulation layer 23 which is an inorganic compound that is positioned within the upper surface of the step part 22; and a semiconductor layer 13 which is positioned within the upper surface of the second gate insulation layer 23. Each electrode layer 14, 15 has a stepped shape that follows the end face of the step part 22 and the end face of the second gate insulation layer 23 from the flat part to the semiconductor layer 13. The thickness DA of the step part 22 and the thickness DB of the flat part satisfy 0.30≤DB/DA≤0.94. Thus, the electric durability of a thin-film transistor with respect to bending of a flexible base is improved.

Description

Thin film transistor and method for manufacturing thin film transistor

The present disclosure relates to a thin film transistor including a semiconductor layer and a method for manufacturing the thin film transistor.

A thin film transistor comprising a semiconductor layer formed on a flexible base material is mounted in various devices such as display devices, mobile devices, and image sensors. A semiconductor layer that achieves high field-effect mobility and low leakage current enables device miniaturization and low power consumption. On the other hand, applying an external stress to the thin film transistor, such as bending the flexible substrate, changes the mobility of the semiconductor layer.

In the first example of suppressing the mobility change due to bending, the semiconductor layer is arranged in a range where the thickness in the stacking direction is relatively thick. For example, a gate insulating layer covers the gate electrode layer. The stacked region of the gate insulating layer overlapping the gate electrode layer is thicker than the single layer region of the gate insulating layer not covering the gate electrode layer by the thickness of the gate electrode layer. Such laminated areas are less prone to bending than single layer areas. In the first suppression example, the stacking range is extended in the channel width direction, and the entire semiconductor layer is arranged in a part of the stacking range in the channel width direction. Alternatively, in the first suppression example, the stacking range is extended in the channel length direction, and the entire semiconductor layer is arranged in a part of the stacking range in the channel length direction. As a result, bending of the semiconductor layer is suppressed in the entire channel width direction of the semiconductor layer or in the entire channel length direction of the metal oxide layer (see

Patent Documents

1 and 2, for example).

A second example of suppression of mobility change due to bending includes a reinforcing layer for suppressing film stress acting on the semiconductor layer. For example, the semiconductor layer is located between the first reinforcing layer and the second reinforcing layer. The first reinforcing layer is a silicide layer having an area larger than that of the semiconductor layer and a Young's modulus higher than that of the semiconductor layer, and supports the entire semiconductor layer. The second reinforcing layer is a silicide layer having an area larger than that of the semiconductor layer and a Young's modulus higher than that of the semiconductor layer, and covers the entire semiconductor layer. As described above, in the second suppression example, the semiconductor layer is arranged on the neutral plane on which tensile stress does not easily act, or on the neutral plane on which compressive stress does not easily act. This suppresses film stress acting on the semiconductor layer (see, for example, Patent Document 3).

JP 2021-77751 A Japanese Patent Application Laid-Open No. 2020-080430 JP 2018-195843 A

By the way, a gate insulating layer in which an inorganic compound layer is laminated on an organic compound layer achieves both high pressure resistance and high bending resistance. On the other hand, structural differences between the organic compound layer and the inorganic compound layer may form various steps inside the thin film transistor.

For example, the positional difference between the organic compound layer and the inorganic compound layer, the positional difference between the inorganic compound layer and the semiconductor layer, and the positional difference between the organic compound layer and the semiconductor layer are such that a step corresponding to the thickness of one layer is can be formed in layers of Dimensional differences between two layers and shape differences between two layers can also create a step corresponding to the thickness of one layer in the other layer. When the organic compound layer itself has a step as in the first suppression example, or when the inorganic compound layer itself has a step, the above step is further complicated.

Differences in internal stress between layers, such as tensile stress and compressive stress, promote film peeling at the steps between layers. Application of external stress by bending the flexible substrate further promotes such film detachment. If it is a structure in which simple planes are stacked, it is possible to form a neutral plane as in the second suppression example. make it difficult. As a result, whether in the first suppression example or the second suppression example, the configuration in which the difference in structure between the organic compound layer and the inorganic compound layer is not taken into consideration suppresses the mobility change caused by the step. There is still room for improvement.

A thin film transistor for solving the above problems is a thin film transistor comprising a flexible base material having a flat surface and an element structure located on the flat surface. The device structure includes a gate electrode layer located on a part of the flat surface, a flat part located on the other part of the flat surface and following the flat surface, and a flat part covering the gate electrode layer. a first gate insulating layer containing an organic atomic group; a second gate insulating layer, which is an inorganic compound, located within the upper surface of the stepped portion; a semiconductor layer that is an oxide semiconductor, a source electrode layer that is connected to a first end of the semiconductor layer, and a drain electrode layer that is connected to a second end of the semiconductor layer; Prepare. The source electrode layer and the drain electrode layer each have a stepped shape that follows an end face of the stepped portion and an end face of the second gate insulating layer from the flat portion to the semiconductor layer, and As for the thickness, the thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.

In the thin film transistor, the area SD occupied by the second gate insulating layer on the upper surface of the step portion and the area SC occupied by the semiconductor layer on the upper surface of the second gate insulating layer are 1.0 μm or less, and 1≦ SD/SC≦9 may be satisfied.

In the thin film transistor described above, the step portion may have a thickness of 0.6 μm or less.
In the thin film transistor described above, the difference between the thickness DA of the step portion and the thickness DB of the flat portion may be larger than the thickness of the gate electrode layer.

A thin film transistor for solving the above problems is a thin film transistor comprising a flexible base material having a flat surface and an element structure located on the flat surface. The device structure includes a gate electrode layer located on a part of the flat surface, a flat part located on the other part of the flat surface and following the flat surface, and a flat part covering the gate electrode layer. a first gate insulating layer containing an organic atomic group; a second gate insulating layer, which is an inorganic compound, located within the upper surface of the stepped portion; a semiconductor layer that is an oxide semiconductor, a source electrode layer that is connected to a first end of the semiconductor layer, and a drain electrode layer that is connected to a second end of the semiconductor layer; Prepare. The thickness of the step portion is 0.6 μm or less, and the thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.

In the thin film transistor, the difference between the thickness DA of the step portion and the thickness DB of the flat portion is larger than the thickness of the gate electrode layer, and the area SD occupied by the second gate insulating layer on the upper surface of the step portion. and the area SC occupied by the semiconductor layer on the upper surface of the second gate insulating layer may satisfy 1≦SD/SC≦9.

In the thin film transistor, the inorganic compound may be any one selected from the group consisting of silicon oxide, silicon nitride and silicon oxynitride.
In the thin film transistor described above, the oxide semiconductor may contain indium.

A method of manufacturing a thin film transistor for solving the above problems includes forming a gate electrode layer on a part of a flat surface of a flexible base material, and forming a first gate insulator containing an organic atomic group so as to cover the gate electrode layer. A layer is formed on the flat surface, thereby comprising a flat portion located on the other part of the flat surface and following the flat surface, and a stepped portion covering the gate electrode layer and protruding from the flat portion. forming a first gate insulating layer; forming a second gate insulating layer, which is an inorganic compound, in the upper surface of the stepped portion; forming a semiconductor layer, which is an oxide semiconductor, in the upper surface of the second gate insulating layer; forming a source electrode layer from the flat portion to the first end of the semiconductor layer so as to have a stepped shape that follows the end face of the stepped portion and the end face of the second gate insulating layer; Forming a drain electrode layer from the flat portion to the second end of the semiconductor layer so as to have a stepped shape that follows the end face of the stepped portion and the end face of the second gate insulating layer. The thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.

A method of manufacturing a thin film transistor for solving the above problems includes forming a gate electrode layer on a part of a flat surface of a flexible base material, and forming a first gate insulator containing an organic atomic group so as to cover the gate electrode layer. A layer is formed on the flat surface, thereby comprising a flat portion located on the other part of the flat surface and following the flat surface, and a stepped portion covering the gate electrode layer and protruding from the flat portion. forming a first gate insulating layer; forming a second gate insulating layer, which is an inorganic compound, in the upper surface of the stepped portion; forming a semiconductor layer, which is an oxide semiconductor, in the upper surface of the second gate insulating layer; forming a source electrode layer connected to a first end of the semiconductor layer; and forming a drain electrode layer connected to a second end of the semiconductor layer. The thickness of the step portion is 0.6 μm or less, and the thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.

According to the above configuration, it is possible to suppress a decrease in the mobility of the thin film transistor due to bending of the flexible base material.

FIG. 1 is a plan view showing a planar structure of a thin film transistor. FIG. 2 is a cross-sectional view showing a cross-sectional structure of a thin film transistor. FIG. 3 is a table showing mobility reduction rates of Examples and Comparative Examples.

An embodiment of a thin film transistor and a method for manufacturing a thin film transistor will be described below. First, the layer structure of the thin film transistor will be described, and then the method for manufacturing the thin film transistor will be described.

FIG. 1 shows an example of a planar structure of a thin film transistor. FIG. 2 shows an example of a cross-sectional structure of a thin film transistor. 1 and 2 omit wiring connected to various electrodes for convenience of explaining the layer structure of the thin film transistor.

Below, top and bottom surfaces of the components of the thin film transistor will be described with reference to FIG. Further, the source and the drain of the thin film transistor are determined by the operation of the driver circuit in which the thin film transistor is mounted. Therefore, in a thin film transistor, one electrode layer may change function from source to drain, and another electrode layer may change function from drain to source. A thin film transistor is a bottom-gate top-contact transistor.
Further, the fact that the upper surface of the upper layer follows the upper surface of the underlying layer means that the upper surface shape of the upper layer follows the upper surface shape of the underlying layer. The top surface shape of the upper layer conforms to the top surface shape of the underlying layer, which means that the position of the step on the top surface of the upper layer follows the position of the step on the top surface of the underlying layer, or the relative size of the step on the top surface of the upper layer depends on the shape of the underlying layer. It follows the relative size of the step on the top surface.

[Device planar structure]
As shown in FIG. 1, a thin film transistor includes a flexible substrate 11, a gate electrode layer 12 (see FIG. 2), a first gate insulating layer 21, a second gate insulating layer 23, a semiconductor layer 13, and a source electrode layer 14. , and a drain electrode layer 15 . The gate electrode layer 12, the first gate insulating layer 21, the second gate insulating layer 23, the semiconductor layer 13, the source electrode layer 14, and the drain electrode layer 15 are examples of the element structure. The first gate insulating layer 21 and the second gate insulating layer 23 are examples of gate insulating layers.

The flexible base material 11 and the gate electrode layer 12 are arranged in the channel depth direction, which is the thickness direction of the flexible base material 11 . The source electrode layer 14 and the drain electrode layer 15 are arranged in the channel length direction, which is the horizontal direction in FIG. The channel width direction is orthogonal to the channel length direction and the channel depth direction.

The upper surface of the flexible base material 11 is a flat surface extending in the channel length direction and the channel width direction. The top surface of flexible substrate 11 comprises a first portion and a second portion. The area of the first portion is sufficiently smaller than the area of the second portion. A first portion of the flexible base 11 contacts the lower surface of the gate electrode layer 12 . The second portion contacts a portion of the bottom surface of the first gate insulating layer 21 .

The first gate insulating layer 21 is in contact with the top surface of the gate electrode layer 12 and the end surfaces of the gate electrode layer 12 . The first gate insulating layer 21 may cover a portion of the upper surface of the flexible substrate 11 or may cover the entire upper surface of the flexible substrate 11 .

The first gate insulating layer 21 has a flat portion in contact with the upper surface of the flexible base material 11 . The upper surface of the flat portion of the first gate insulating layer 21 follows the flat surface of the flexible base material 11 . The first gate insulating layer 21 further includes a step portion 22 . The step portion 22 is surrounded by the flat portion of the first gate insulating layer 21 . The stepped portion 22 covers the upper surface of the gate electrode layer 12 and the end face of the gate electrode layer 12 and protrudes from the flat portion adjacent to the stepped portion 22 . The stepped portion 22 may rise sharply from the flat portion via a plane orthogonal to the top surface of the flat portion, or may gently rise from the flat portion via a slope with respect to the top surface of the flat portion. The upper surface of the stepped portion 22 follows the flat surface of the flexible base material 11 .

The outer shape of each layer seen from the viewpoint facing the upper surface of the first gate insulating layer 21 is the planar shape of the layer. The planar shape of the stepped portion 22 has, for example, a rectangular shape. The planar shape of the step portion 22 may follow the planar shape of the gate electrode layer 12 or may differ from the planar shape of the gate electrode layer 12 . The planar shape of the stepped portion 22 may be a shape having a portion that follows the planar shape of the wiring connected to the gate electrode layer 12, or may not have a portion that follows the planar shape of the wiring.

The bottom surface of the second gate insulating layer 23 is in contact with the top surface of the step portion 22 . The second gate insulating layer 23 covers the upper surface of the gate electrode layer 12 so that the first gate insulating layer 21 is sandwiched between the second gate insulating layer 23 and the gate electrode layer 12 in the channel depth direction. The second gate insulating layer 23 is positioned within the upper surface of the step portion 22 when viewed from the viewpoint facing the upper surface of the first gate insulating layer 21 . When viewed from the viewpoint facing the upper surface of the first gate insulating layer 21 , the end face of the second gate insulating layer 23 may be located inside the end face of the stepped portion 22 or may be aligned with the end face of the stepped portion 22 . may The planar shape of the second gate insulating layer 23 may follow the planar shape of the stepped portion 22 or may differ from the planar shape of the stepped portion 22 .

The bottom surface of the semiconductor layer 13 is in contact with the top surface of the second gate insulating layer 23 . The semiconductor layer 13 covers the upper surface of the gate electrode layer 12 so that the semiconductor layer 13 and the gate electrode layer 12 sandwich the first gate insulating layer 21 and the second gate insulating layer 23 in the channel depth direction. The semiconductor layer 13 is positioned within the upper surface of the step portion 22 and within the upper surface of the second gate insulating layer 23 when viewed from the viewpoint facing the upper surface of the first gate insulating layer 21 . When viewed from the viewpoint facing the upper surface of the first gate insulating layer 21, the end surface of the semiconductor layer 13 may be located inside the end surface of the second gate insulating layer 23, or may be positioned inside the end surface of the second gate insulating layer 23. may match. The planar shape of the second gate insulating layer 23 may follow the planar shape of the second gate insulating layer 23 or may differ from the planar shape of the second gate insulating layer 23 .

The lower surface of the source electrode layer 14 is in contact with the upper surface of the semiconductor layer 13 and the flat portion of the first gate insulating layer 21 . The source electrode layer 14 covers the first end of the semiconductor layer 13 so as to be connected to the first end, which is the end of the semiconductor layer 13 in the channel length direction. The source electrode layer 14 is in contact with the end face of the semiconductor layer 13, the end face of the second gate insulating layer 23, and the end face of the step portion 22, and extends in the channel length direction from the upper surface of the flat portion of the first gate insulating layer 21 to the semiconductor layer 13. extends to the first end of the

The lower surface of the drain electrode layer 15 is in contact with the upper surface of the semiconductor layer 13 and the flat portion of the first gate insulating layer 21 . The drain electrode layer 15 covers the second end of the semiconductor layer 13 so as to be connected to the second end, which is the end of the semiconductor layer 13 in the channel length direction. The first end and the second end of the semiconductor layer 13 are both ends of the semiconductor layer 13 in the channel length direction. The drain electrode layer 15 is in contact with the end face of the semiconductor layer 13, the end face of the second gate insulating layer 23, and the end face of the step portion 22, and extends from the upper surface of the flat portion of the first gate insulating layer 21 to the semiconductor layer 13 in the channel length direction. extending to the second end of the

The source electrode layer 14 and the drain electrode layer 15 are separated from each other. The length between the source electrode layer 14 and the drain electrode layer 15 is smaller than the length of the gate electrode layer 12 in the channel length direction. A region between the source electrode layer 14 and the drain electrode layer 15 in the semiconductor layer 13 is a channel region. The length of the channel region in the channel length direction, that is, the length between the source electrode layer 14 and the drain electrode layer 15 is the channel length. The length of the channel region in the channel width direction is the channel width.

If the channel length at each position in the channel width direction in one thin film transistor is not constant, the average value of all channel lengths is the channel length in one thin film transistor. When the channel length is longer than the length of the gate electrode layer 12, the region of the semiconductor layer 13 overlapping the gate electrode layer 12 in the channel depth direction is the channel region.

[Flexible base material 11]
The flexible base material 11 has an insulating upper surface. The flexible substrate 11 may be a transparent substrate or an opaque substrate. The flexible base material 11 may be a film having an insulating property, a metal foil provided with an insulating property on the top surface of the flexible base material 11 , or an insulating film on the top surface of the flexible base material 11 . It may be an alloy foil imparted with or may be a thin plate glass having flexibility. The flexible substrate 11 may be a single layer structure or a multilayer structure.

When the flexible substrate 11 has a single-layer structure, examples of materials constituting the flexible substrate 11 include organic polymer compounds, composite materials of organic and inorganic materials, metals, alloys, and inorganic materials. It is at least one selected from the group consisting of polymer compounds. When the flexible base material 11 is a multi-layer structure, examples of constituent materials of each layer constituting the flexible base material 11 are organic polymer compounds, composite materials, metals, alloys, and inorganic polymer compounds. Any one selected from the group.

When the flexible base material 11 is a multi-layer structure, the flexible base material 11 may include a base substrate and a release layer configured to be peelable from the base substrate. The release layer is stripped from the underlying substrate together with the device structure. A release layer comprising device structures may be applied to another flexible substrate. Examples of flexible substrates include low heat resistant papers, cellophane substrates, cloths, recycled fibers, leathers, nylon substrates, and polyurethane substrates. In this case, the release layer and the flexible base constitute another flexible base 11 .

Examples of organic polymer compounds include polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone, polyolefin, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, polyethersulphene, triacetylcellulose, polyvinylfluoride. It is at least one selected from the group consisting of ride films, ethylene-tetrafluoroethylene copolymers, polyimides, fluorine-based polymers, and cyclic polyolefin-based polymers.

An example of a composite material is glass fiber reinforced acrylic polymer or glass fiber reinforced polycarbonate. An example metal is aluminum or copper. An example of an alloy is an iron-chromium alloy, an iron-nickel alloy, or an iron-nickel-chromium alloy. An example of an inorganic polymer compound is alkali-free glass containing silicon oxide, boron oxide and aluminum oxide, or alkali glass containing silicon oxide, sodium oxide and calcium oxide.

When the flexible base material 11 is a film made of an organic polymer compound, the flexible base material 11 may have a multilayer structure including a gas barrier layer. Examples of materials constituting the gas barrier layer are aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and diamond-like carbon. The gas barrier layer may have a single layer structure or a multilayer structure. The flexible substrate 11 may have a gas barrier layer on only one side of the film, or may have gas barrier layers on both sides of the film.

[Gate insulating layers 21 and 23]
The material forming the first gate insulating layer 21 contains an organic atomic group that contributes to the flexibility of the first gate insulating layer 21 . The material forming the first gate insulating layer 21 may be an organic polymer compound. Examples of organic polymer compounds include polyvinylphenol, polyimide, polyvinyl alcohol, acrylic polymers, epoxy polymers, fluoropolymers including amorphous fluoropolymers, melamine polymers, furan polymers, xylene polymers, polyamideimide polymers, silicone polymers, and parylene. It is at least one selected from the group consisting of When the heat resistance of the first gate insulating layer 21 is required to be improved, the organic polymer compound is preferably at least one selected from the group consisting of polyimide, acrylic polymer, and fluorine-based polymer.

The material forming the first gate insulating layer 21 may be an organic-inorganic composite material. An organic-inorganic composite material has a molecular structure that includes an organic atomic group that has the properties of an organic compound and an atomic group that has the properties of an inorganic compound. An example of an organic-inorganic composite is silsesquioxane. A silsesquioxane has a skeleton composed of silicon and oxygen as an atomic group having the properties of an inorganic compound, and an organic group as an atomic group having the properties of an organic compound.

The material constituting the first gate insulating layer 21 may contain particles composed of inorganic compounds in compounds containing organic atomic groups. The particles are nanoparticles having an average particle diameter of several nanometers or more and several hundreds of nanometers or less.

The first gate insulating layer 21 may be a single layer film or a multilayer film. When the first gate insulating layer 21 is a multilayer film, the constituent material of each layer forming the first gate insulating layer 21 contains an organic atomic group.

When it is required to improve the withstand voltage of the gate insulating layer, the resistivity of the first gate insulating layer 21 is preferably 1×10 ¹¹ Ω·cm or more. Furthermore, when thinning of the first gate insulating layer 21 is required, the resistivity of the first gate insulating layer 21 is preferably 1×10 ¹³ Ω·cm or more. Further, when it is required to suppress current leakage between the gate electrode layer 12 and the other electrode layers 14 and 15, the dielectric constant of the first gate insulating layer 21 is 2.0 or more and 5.0 or less. Preferably.

The material forming the second gate insulating layer 23 contains an inorganic compound that does not have long-range order. The inorganic compound is at least one selected from the group consisting of silicon compounds such as silicon oxides, silicon nitrides, and silicon oxynitrides, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, and zirconium oxide. The material forming the second gate insulating layer 23 may be a mixture containing an inorganic compound having no long-range order and an organic compound.

The second gate insulating layer 23 may be a single layer film or a multilayer film. When the second gate insulating layer 23 is a multilayer film, the constituent material of each layer constituting the second gate insulating layer 23 contains the inorganic compound described above.

If it is required to improve the withstand voltage of the gate insulating layer, the second gate insulating layer 23 preferably has a resistivity of 1×10 ¹¹ Ω·cm or more. Furthermore, when the thickness of the second gate insulating layer 23 is required to be reduced, the resistivity of the second gate insulating layer 23 is preferably 1×10 ¹³ Ω·cm or more. Further, when it is required to suppress current leakage between the gate electrode layer 12 and the other electrode layers 14 and 15, the dielectric constant of the second gate insulating layer 23 is 2.0 or more and 5.0 or less. Preferably.

[Electrode layers 12, 14, 15]
Each

electrode layer

12, 14, 15 may be a single-layer structure or a multilayer structure. When each

electrode layer

12, 14, 15 is a multi-layer structure, each

electrode layer

12, 14, 15 includes the bottom layer that enhances the adhesion with the lower layer of the electrode layer and the adhesion with the upper layer of the electrode layer. It is preferred to have a top layer that enhances.

The material constituting each

electrode layer

12, 14, 15 may be a metal, an alloy, a conductive metal oxide, or a conductive organic polymer compound. The materials forming each

electrode layer

12, 14, 15 may be different from each other or may be the same.

Examples of metals are at least one of transition metals, alkali metals, and alkaline earth metals. The transition metal is at least one selected from the group consisting of indium, aluminum, gold, silver, platinum, titanium, copper, nickel and tungsten. The alkali metal is lithium or cesium. Alkaline earth metal is at least one of magnesium and calcium. The alloy is one selected from the group consisting of molybdenum niobium, iron chromium, aluminum lithium, magnesium silver, aluminum neodymium alloy, and aluminum neodymium zirconia alloy.

An example of the metal oxide is any one selected from the group consisting of indium oxide, tin oxide, zinc oxide, cadmium oxide, indium cadmium oxide, cadmium tin oxide, and zinc tin oxide. The metal oxide may contain impurities. The metal oxide containing impurities is indium oxide containing at least one impurity selected from the group consisting of tin, zinc, titanium, cerium, hafnium, zirconium and molybdenum. The metal oxide containing impurities may be antimony or tin oxide containing fluorine. The metal oxide containing impurities may be zinc oxide containing at least one impurity selected from the group consisting of gallium, aluminum and boron.

An example of a conductive organic polymer compound is poly(ethylenedioxythiophene)/polystyrene sulfonate (PEDOT/PSS) or polyaniline.
Each of the electrode layers 14 and 15 may be a layer composed of the same constituent elements as the semiconductor layer 13 and having an impurity concentration sufficiently higher than that of the semiconductor layer 13 .

When it is required to expand the range of materials that can be applied to each

electrode layer

12, 14, 15, the electrical resistivity of each

electrode layer

12, 14, 15 should be 5.0×10 ⁻⁵ Ω·cm or more. Preferably. If it is required to suppress the power consumption of the thin film transistor, the electric resistivity of each

electrode layer

12, 14, 15 is preferably 1.0×10 ⁻² Ω·cm or less.

[Semiconductor layer 13]
A material forming the semiconductor layer 13 is an oxide semiconductor. The oxide semiconductor contains at least one metal element selected from the group consisting of indium, gallium, zinc, and tin.

The oxide semiconductor may be a one-component oxide semiconductor composed of one metal element, a binary oxide semiconductor composed of two metal elements, or composed of three or more metal elements. may be a multi-component oxide semiconductor. The oxide semiconductor may be an amorphous semiconductor, a microcrystalline semiconductor including many microcrystals, or a polycrystalline semiconductor including many microcrystals.

When the light transmittance and field effect mobility (hereinafter also referred to as mobility) of the semiconductor layer 13 are required to be increased, the semiconductor layer 13 is preferably a semiconductor layer containing indium.

Single-component oxide semiconductors are, for example, indium oxide, zinc oxide, gallium oxide, and tin oxide. Binary oxide semiconductors are, for example, indium zinc oxide and indium gallium oxide. A ternary oxide semiconductor is a ternary oxide semiconductor containing indium. Ternary oxide semiconductors are, for example, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, and indium hafnium zinc oxide. The oxide semiconductor contains, in addition to the metal elements constituting the metal oxide, at least other metal elements selected from the group consisting of titanium, germanium, yttrium, zirconium, lanthanum, cerium, tungsten, and magnesium, for example. One element may be included.

An example of an oxide semiconductor is an In-M-Zn-based oxide. In-M-Zn-based oxides include indium (In) and zinc (Zn). The In-M-Zn oxide contains at least one metal element (M) selected from the group consisting of aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, hafnium, and tin.

[Element cross-sectional structure]
As shown in FIG. 2 , the source electrode layer 14 has a stepped shape with steps corresponding to the thickness of the semiconductor layer 13 , the thickness of the second gate insulating layer 23 , and the thickness of the stepped portion 22 . Each stepped surface forming source electrode layer 14 is in contact with an end surface of semiconductor layer 13 , an end surface of second gate insulating layer 23 , and an end surface of stepped portion 22 . The source electrode layer 14 is formed on the upper surface of the semiconductor layer 13 so that the first end of the semiconductor layer 13 is in close contact with the second gate insulating layer 23 and the end of the second gate insulating layer 23 is in close contact with the step portion 22 . , to the flat portion of the first gate insulating layer 21 .

The drain electrode layer 15 has a stepped shape with steps corresponding to the thickness of the semiconductor layer 13 , the thickness of the second gate insulating layer 23 , and the thickness of the stepped portion 22 . Each stepped surface forming the drain electrode layer 15 is in contact with the end surface of the semiconductor layer 13 , the end surface of the second gate insulating layer 23 , and the end surface of the stepped portion 22 . The drain electrode layer 15 is formed on the upper surface of the semiconductor layer 13 so that the second end of the semiconductor layer 13 is in close contact with the second gate insulating layer 23 and the end of the second gate insulating layer 23 is in close contact with the step portion 22 . , to the flat portion of the first gate insulating layer 21 .

The upper surface of the flat portion of the first gate insulating layer 21 and the upper surface of the step portion 22 follow the flat surface of the flexible base material 11 . The thickness DA of the step portion 22 and the thickness DB of the flat portion are obtained by measurement using a scanning electron microscope (SEM) or a contact-type profilometer. The thickness DA of the stepped portion 22 and the thickness DB of the flat portion were measured at 10 points arranged at intervals of 1 μm in the channel length direction and at 10 points arranged at intervals of 1 μm in the channel width direction. Calculated as the average thickness.

As described above, the second gate insulating layer 23 is positioned within the upper surface of the stepped portion 22 . The area SD occupied by the second gate insulating layer 23 on the upper surface of the step portion 22 is obtained from an SEM image of the second gate insulating layer 23 photographed from a viewpoint facing the first gate insulating layer 21 . The semiconductor layer 13 is located within the upper surface of the second gate insulating layer 23 . The area SC occupied by the semiconductor layer 13 on the upper surface of the second gate insulating layer 23 is obtained from an SEM image of the semiconductor layer 13 taken from a viewpoint facing the first gate insulating layer 21 . When the planar shape of the second gate insulating layer 23 is irregular or the planar shape of the semiconductor layer 13 is irregular, image processing may be used to measure the areas SD and SC. Indefinite shapes are shapes that are not geometric, such as quadrilaterals, trapezoids, and combinations thereof, and are surrounded by complex curves. Area SD is greater than or equal to area SC. The length DL of the second gate insulating layer 23 in the channel length direction is equal to or greater than the length CL of the semiconductor layer 13 in the channel length direction. The length of the second gate insulating layer 23 in the channel width direction is greater than or equal to the length of the semiconductor layer 13 in the channel width direction.

The thickness DA of the stepped portion 22 and the thickness DB of the flat portion satisfy Condition 1 below.
At this time, if there is a demand for enhancing the effectiveness of the effect of suppressing the decrease in mobility in the thin film transistor, the thickness DA of the stepped portion 22 may satisfy Condition 2 below. Further, the area SD occupied by the second gate insulating layer 23 on the upper surface of the step portion 22 and the area SC occupied by the semiconductor layer 13 on the upper surface of the second gate insulating layer 23 may satisfy Condition 3 below. Further, when there is a demand for enhancing the effectiveness of the effect of suppressing the decrease in mobility, the thickness DA, the thickness DB, and the thickness of the gate electrode layer 12 may satisfy Condition 5 below.

[Condition 1] 0.30≦DB/DA≦0.94 is satisfied.
[Condition 2] The thickness DA of the step portion 22 is 1.0 μm or less.
[Condition 3] 1≦SD/SC≦9 is satisfied.
[Condition 4] The thickness DA of the step portion 22 is 0.6 μm or less.
[Condition 5] The difference between the thickness DB and the thickness DA is larger than the thickness of the gate electrode layer 12 .

The stepped portion 22 in the first gate insulating layer 21 acts as a charge injection layer of the thin film transistor. The thickness DA of the stepped portion 22 has a size that (i) suppresses deterioration due to voltage for injecting charges. Providing a flat portion thinner than the stepped portion 22 in the first gate insulating layer 21 allows (i) the first gate insulating layer 21 to withstand charge injection, and (ii) flatness other than the stepped portion 22 . Increase flexibility by part. The flexibility of the first gate insulating layer 21 due to the flat portion of the first gate insulating layer 21 causes deterioration of the interface between the stepped portion 22 and the second gate insulating layer 23, Deterioration of the interface with the semiconductor layer 13 and cracking of the second gate insulating layer 23 are suppressed.

Satisfying DA/DB≤0.94 (i) provides resistance to charge injection and (ii) increases the flexibility of the first gate insulating layer 21, while maintaining 0.94<DB/DA. and (iii) a reduction in the mobility of the thin film transistor due to bending of the flexible substrate 11 is greatly suppressed. Satisfying 0.30≦DB/DA suppresses the occurrence of cracks and film peeling in the electrode layers 14 and 15 extending to the flat portion of the first gate insulating layer 21 . DB/DA, which is the ratio of the thickness DA to the thickness DB, may be 0.33 or more and 0.94 or less, or may be 0.67 or more and 0.94 or less. DB/DA, which is the ratio of the thickness DA to the thickness DB, may be 0.3 or more and 0.75 or less, or may be 0.3 or more and 0.67 or less.

Note that the source electrode layer 14 has a step difference corresponding to the thickness of the semiconductor layer 13 and the thickness of the second gate insulating layer 23 and does not have a step difference corresponding to the thickness of the step portion 22, and has two steps. You may have one stepped shape consisting of. That is, the source electrode layer 14 may have a structure that extends from the upper surface of the semiconductor layer 13 to the stepped portion 22 . Further, the source electrode layer 14 has a step corresponding to the thickness of the semiconductor layer 13 and has a single step without a step corresponding to the thickness of the second gate insulating layer 23 and the thickness of the step portion 22 . It may have a shape. That is, the source electrode layer 14 may be configured to extend from the upper surface of the semiconductor layer 13 to the second gate insulating layer 23 .

In addition, the drain electrode layer 15 has two steps having a step corresponding to the thickness of the semiconductor layer 13 and the thickness of the second gate insulating layer 23 and not having a step corresponding to the thickness of the step portion 22. You may have one stepped shape consisting of. In other words, the drain electrode layer 15 may be configured to extend from the upper surface of the semiconductor layer 13 to the stepped portion 22 . In addition, the drain electrode layer 15 has a step corresponding to the thickness of the semiconductor layer 13 and has a single step without a step corresponding to the thickness of the second gate insulating layer 23 and the thickness of the step portion 22 . It may have a shape. In other words, the drain electrode layer 15 may be configured to extend from the upper surface of the semiconductor layer 13 to the second gate insulating layer 23 .

As described above, when the source electrode layer 14 and the drain electrode layer 15 have a single stepped shape consisting of two steps or a single stepped shape, the thickness DA of the stepped portion 22 is , satisfy

conditions

1 and 4 above. When the thickness DA of the stepped portion 22 is 0.6 μm or less, (ii) the flexibility is improved compared to the case where the thickness DA of the stepped portion 22 is 1.0 μm or more, such as 0.6 μm. and (iii) suppression and improvement of mobility decrease. In this case, the area SD and the area SC may satisfy the above condition 3 when there is a demand for enhancing the effectiveness of the effect of suppressing the decrease in mobility in the thin film transistor. Further, when there is a demand for enhancing the effectiveness of the effect of suppressing the decrease in mobility, the thickness DA, the thickness DB, and the thickness of the gate electrode layer 12 may satisfy Condition 5 above.

When it is required to suppress current leakage between the gate electrode layer 12 and the other electrode layers 14 and 15, the thickness DB of the flat portion of the first gate insulating layer 21 should be 0.2 μm or more. preferable. When it is required to suppress the gate voltage for driving the thin film transistor, the thickness DA of the step portion 22 is preferably 1.2 μm or less. When suppression of current leakage and suppression of gate voltage are required, the thickness DB of the flat portion in the first gate insulating layer 21 is 0.4 μm or more, and the thickness DA of the stepped portion 22 is 1.0 μm or less. is preferably The thickness DA of the step portion 22 may be 0.4 μm or more and 1.2 μm or less, or may be 0.4 μm or more and 1.0 μm or less. The thickness DB may be 0.2 μm or more and 0.94 μm or less, or may be 0.4 μm or more and 0.94 μm or less.

When high durability due to bending of the flexible base material 11 and high workability of the membrane structure are required, the area of the upper surface of the stepped portion 22 is 30 μm ² or more and 5×10 ⁴ μm. It is preferably ² or less. The area SD of the upper surface of the second gate insulating layer 23 is preferably 30 μm ² or more and 5×10 ⁴ μm ² or less. The area SC of the upper surface of the semiconductor layer 13 is preferably 30 μm ² or more and 5×10 ⁴ μm ² or less. The channel length is preferably 4 μm or more and 50 μm or less. The channel width is preferably 4 μm or more and 500 μm or less.

When it is required to suppress the occurrence of cracks caused by the gate electrode layer 12, the thickness of the second gate insulating layer 23 is preferably 50 nm or less. When current leakage between the gate electrode layer 12 and the other electrode layers 14 and 15 is required, and the second gate insulating layer 23 itself is required to be a continuous film without being scattered like islands. In this case, the thickness of the second gate insulating layer 23 is preferably 2 nm or more. When it is required to improve the flexibility of the gate electrode layer 12 and suppress current leakage, the thickness of the first gate insulating layer 21 is preferably 2 nm or more and 50 nm or less. Further, when it is required to suppress current leakage between the gate electrode layer 12 and the other electrode layers 14 and 15, the dielectric constant of the second gate insulating layer 23 should be 3.5 or more and 10 or less. is preferred.

When it is required to suppress the electrical resistance value of each

electrode layer

12, 14, 15, the thickness of each

electrode layer

12, 14, 15 is preferably 50 nm or more. If it is required to increase the flexibility of the thin film transistor, the thickness of each

electrode layer

12, 14, 15 is preferably 300 nm or less.

When it is required to improve the uniformity of the thickness of the semiconductor layer 13, the thickness of the semiconductor layer 13 is preferably 10 nm or more. When it is required to reduce the amount of material used in the semiconductor layer 13, the thickness of the semiconductor layer 13 is preferably 100 nm or less. If both improvement in thickness uniformity and suppression of material usage are required, the thickness of the semiconductor layer 13 is preferably 10 nm or more and 100 nm or less. Furthermore, when it is required to improve the effectiveness of obtaining these effects, the thickness of the semiconductor layer 13 is preferably 15 nm or more and 50 nm or less. When the mobility of the thin film transistor is required to be improved, the conductivity of the semiconductor layer 13 is preferably 1.0×10 ⁻⁷ S/cm or more and 1.0×10 ⁻¹ S/cm or less.

(Manufacturing method of thin film transistor)
A method for manufacturing a thin film transistor includes a first step of forming a gate electrode layer 12 on a flexible base material 11 . The method of manufacturing a thin film transistor includes a second step of forming a first gate insulating layer 21 and a third step of stacking a second gate insulating layer 23 on the first gate insulating layer 21 . The method of manufacturing the thin film transistor also includes a fourth step of stacking the semiconductor layer 13 on the second gate insulating layer 23 and a fifth step of stacking the source electrode layer 14 and the drain electrode layer 15 on the semiconductor layer 13 .

In the first step, the gate electrode layer 12 may be formed by a film formation method using a mask that follows the outline of the gate electrode layer 12 . Alternatively, the gate electrode layer 12 may be formed by forming an electrode film to form the gate electrode layer 12 and then processing the electrode film into the shape of the gate electrode layer 12 using an etching method.

The film formation method used to form the gate electrode layer 12 is at least one selected from the group consisting of vacuum deposition, ion plating, sputtering, laser ablation, spin coating, dip coating, and slit die coating. be. Alternatively, the film formation method used to form the gate electrode layer 12 is at least one selected from the group consisting of screen printing, letterpress printing, intaglio printing, planographic printing, and inkjet.

In the second step, the first gate insulating layer 21 may be formed by processing the coating film for forming the first gate insulating layer 21 . At this time, a stepped portion 22 and a flat portion are formed in the first gate insulating layer 21 by an etching method using a mask that follows the planar shape of the first gate insulating layer 21 and a mask that follows the planar shape of the stepped portion 22 . You may Alternatively, the first gate insulating layer 21 may be formed by applying a photolithographic method to the photosensitive coating film to form the stepped portion 22 and the flat portion of the first gate insulating layer 21 from the photosensitive coating film. . The step of forming the stepped portion 22 and the flat portion of the first gate insulating layer 21 may be a single etching step in which the thickness of the resist covering the stepped portion 22 and the thickness of the resist covering the flat portion are made different from each other. , may be separate etching steps. The steps of forming the stepped portion 22 and the flat portion of the first gate insulating layer 21 are carried out by a single method in which the exposure dose applied to the region corresponding to the stepped portion 22 and the exposure dose applied to the flat portion are different from each other. A photolithography process may be used, or separate photolithography processes may be used.

The coating method used to form the first gate insulating layer 21 is selected from the group consisting of a spin coating method, a dip coating method, a slit die coating method, a screen printing method, and an inkjet method using a coating liquid containing an organic polymer compound. at least one. In the coating method, a coating film is formed by baking a liquid film made of a coating liquid. When the photolithography method is used to form the first gate insulating layer 21, the coating liquid contains a photosensitive polymer.

In the third step, the second gate insulating layer 23 may be formed by a film forming method using a mask that follows the shape of the second gate insulating layer 23 . Alternatively, the second gate insulating layer 23 may be formed by forming an insulating layer to be the second gate insulating layer 23 and then processing the insulating layer into the shape of the second gate insulating layer 23 using an etching method. good. The shape processing of the second gate insulating layer 23 may be performed by etching using the pattern of the semiconductor layer 13 as a mask in the fourth step.

The film formation method used to form the second gate insulating layer 23 is at least one selected from the group consisting of laser ablation, plasma CVD, optical CVD, thermal CVD, sputtering, and sol-gel. Alternatively, the film forming method used to form the second gate insulating layer 23 is a group consisting of a spin coating method using a coating liquid containing an inorganic compound precursor, a dip coating method, a slit die coating method, a screen printing method, and an inkjet method. is at least one coating method selected from

In the fourth step, the semiconductor layer 13 may be formed by a film forming method using a mask that follows the shape of the semiconductor layer 13 . Alternatively, the semiconductor layer 13 may be formed by forming a semiconductor film to be the semiconductor layer 13 and then processing the semiconductor film into the shape of the semiconductor layer 13 using an etching method.

The semiconductor layer 13 is formed by a sputtering method, an atomic layer deposition method which is an ALD method, a pulse laser deposition method which is a PLD method, a CVD method, or a wet film formation method including a sol-gel method. The sputtering method includes a DC sputtering method in which a DC voltage is applied to the flexible base material 11, or an RF sputtering method in which a high frequency is applied to the film forming space. The semiconductor layer 13 may be subjected to heat treatment for microcrystallization or polycrystallization. Impurity addition methods include a plasma processing method, an ion implantation method, an ion doping method, and a plasma immersion ion implantation method.

The carrier concentration of the semiconductor layer 13 can be changed by changing the oxygen concentration in the atmosphere when the semiconductor layer 13 is formed. The carrier concentration of the semiconductor layer 13 can also be changed by changing the hydrogen concentration in the atmosphere when the semiconductor layer 13 is formed. The carrier concentration of the semiconductor layer 13 can also be changed by changing the metal composition ratio in the oxide semiconductor. The carrier concentration of the semiconductor layer 13 can also be changed by the temperature of the heat treatment applied to the semiconductor layer 13 and the atmosphere.

In the fifth step, the source electrode layer 14 and the drain electrode layer 15 may be formed by a film formation method using a mask following the shape of the electrode layers. Alternatively, the source electrode layer 14 and the drain electrode layer 15 are formed by forming electrode films to be the electrode layers 14 and 15, and then etching the electrode films into the shapes of the source electrode layer 14 and the drain electrode layer 15. It may be formed by a method of processing.

The film forming method used for forming the electrode layers 14 and 15 is at least one selected from the group consisting of vacuum deposition, ion plating, sputtering, laser ablation, spin coating, dip coating, and slit die coating. is. Alternatively, the film formation method used to form the gate electrode layer 12 is at least one selected from the group consisting of screen printing, letterpress printing, intaglio printing, planographic printing, and inkjet.

[Example 1]
As the thin film transistor of Example 1, a bottom gate/top contact type transistor having the following structure was formed.
・Semiconductor layer 13 area SC: 800 μm ²
・Area SD of the second gate insulating layer 23: 1500 μm ²
・Area SD/Area SC: 1.9
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 0.6 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.4 μm
・Thickness DB/thickness DA: 0.67
・Thickness DB-thickness DA: 0.2 μm
・Thickness of gate electrode layer 12: 80 nm
・Thickness of the second gate insulating layer 23: 10 nm
・Thickness of semiconductor layer 13: 30 nm
・Channel length: 30 μm
・Channel width: 200 μm

In the thin film transistor of Example 1, a polyimide film having a thickness of 20 μm was used as the flexible base material 11 . In the thin film transistor of Example 1, an aluminum neodymium film, which is an aluminum alloy film, was used as the gate electrode layer 12 . The gate electrode layer 12 was obtained by patterning an aluminum alloy film formed on the flexible base material 11 . The aluminum alloy film was obtained by a DC magnetron sputtering method using the flexible substrate 11 as a film formation target under the following film formation conditions. The gate electrode layer 12 was obtained by forming a resist mask from a photosensitive polyresist film laminated on an aluminum alloy film, wet-etching the aluminum alloy film using the resist mask, and then removing the resist mask. . The thickness of the gate electrode layer 12 was 80 nm.

[Film Formation Conditions for Gate Electrode Layer 12]
・Target composition ratio: Al (at%): Nd (at%) = 98:2
・Sputter gas: Argon ・Sputter gas flow rate: 100 sccm
・Deposition pressure: 1.0 Pa
・Target power: 200W
・Substrate temperature: 23°C

The thin film transistor of Example 1 used an acrylic resin film for the first gate insulating layer 21 . The first gate insulating layer 21 was obtained by patterning a coating film containing a photosensitive acrylic resin formed to cover the gate electrode layer 12 . The photosensitive coating film was obtained by a slit coating method of a photosensitive acrylic resin using the flexible base material 11 laminated with the gate electrode layer 12 as a film formation target and setting the rotation speed of the base material to 2400 rpm. The first gate insulating layer 21 is formed by exposing the photosensitive coating film using a mask for forming the first gate insulating layer 21, developing the coating film, and baking the developed coating film at 220°C. Got. The thickness of the first gate insulating layer 21 was 0.6 μm.

The thin film transistor of Example 1 used a silicon oxide film for the second gate insulating layer 23 . The second gate insulating layer 23 was obtained by patterning a silicon oxide film formed to cover the first gate insulating layer 21 . The silicon oxide film was obtained by the CVD method under the following film forming conditions, using the flexible base material 11 laminated with the first gate insulating layer 21 as a film forming object.

[Film Formation Conditions for Second Gate Insulating Layer 23]
・Reactive gas: silane and dinitrogen monoxide ・Silane flow rate: 80 sccm
・Dinitrogen monoxide flow rate: 800 sccm
・Deposition pressure: 200 Pa
・High frequency power: 600W
・High frequency power frequency: 13.56MHz
・Substrate temperature: 200°C

The second gate insulating layer 23 was obtained by dry etching the silicon oxide film using a resist pattern formed on the silicon oxide film as a mask and using the following etching conditions for the second gate insulating layer 23 . The formation of the step portion 22 was obtained by dry etching the first gate insulating layer 21 under the following etching conditions for the first gate insulating layer 21 .

[Etching Conditions for Second Gate Insulating Layer 23]
・Reactive gas: Tetrafluoromethane ・Reactive gas flow rate: 30 sccm
・Deposition pressure: 10 Pa
・High frequency power: 300W
・Etching time: 20 seconds

[Etching Conditions for First Gate Insulating Layer 21]
・Reactive gas: methane tetrafluoride ・Reactive gas flow rate: 40 sccm
・Deposition pressure: 20 Pa
・High frequency power: 300W
・Etching time: 20 seconds

In the thin film transistor of Example 1, an indium gallium zinc oxide (InGaZnO) film having a thickness of 30 nm was used as the semiconductor layer 13 . The semiconductor layer 13 was obtained by wet etching an oxide semiconductor film formed so as to cover the second gate insulating layer 23 . The oxide semiconductor film was obtained by a DC magnetron sputtering method under the following film formation conditions, using the flexible base material 11 laminated with the second gate insulating layer 23 as a film formation target.

[Film Formation Conditions for Semiconductor Layer 13]
・Target composition ratio: atomic mass % In:Ga:Zn:O = 1:1:1:4
・Supply gas: argon and oxygen ・Argon flow rate: 100 sccm
・Oxygen flow rate: 0.1 sccm
・Deposition pressure: 1.0 Pa
・Target power: 300W
・Target frequency: 13.56MHz
・Substrate temperature: room temperature

In the thin film transistor of Example 1, an aluminum neodymium film, which is an aluminum alloy film having a thickness of 80 nm, was used for the source electrode layer 14 and the drain electrode layer 15 . The source electrode layer 14 and the drain electrode layer 15 were obtained by a lift-off method using a DC magnetron sputtering method under the following deposition conditions. For the formation of the source electrode layer 14 and the drain electrode layer 15, first, a lift-off resist having a hole shape following the contours of the electrode layers 14 and 15 was formed. Next, a source electrode layer 14 and a drain electrode layer 15 were obtained by forming an aluminum neodymium film and peeling off the inverted pattern deposited on the lift-off resist together with the resist.

[Formation Conditions for Source Electrode Layer 14 and Drain Electrode Layer 15]
・Target composition ratio: Al (at%): Nd (at%) = 98:2
・Sputter gas: Argon ・Sputter gas flow rate: 100 sccm
・Deposition pressure: 1.0 Pa
・Target power: 200W
・Substrate temperature: 23°C

[Example 2]
The thin film transistor of Example 2 is a bottom-gate/top-contact transistor having the following structure. For the convenience of describing the thin film transistor of Example 2, dimensions related to structural items that are the same as the dimensions of the thin film transistor of Example 1 among the dimensions of the thin film transistor of Example 2 are omitted. A thin film transistor of Example 2 was obtained in the same manner as in Example 1 except that the etching time of the first gate insulating layer 21 for forming the step portion 22 was changed to 40 seconds.
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 0.6 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.4 μm
・Thickness DB/thickness DA: 0.67
・Thickness DB-thickness DA: 0.2 μm

[Example 3]
The thin film transistor of Example 3 is a bottom-gate/top-contact transistor having the following structure. For the convenience of describing the thin film transistor of Example 2, dimensions related to structural items that are the same as the dimensions of the thin film transistor of Example 1 among the dimensions of the thin film transistor of Example 2 are omitted. A thin film transistor of Example 2 was obtained in the same manner as in Example 1 except that the etching time of the first gate insulating layer 21 for forming the step portion 22 was changed to 8 seconds.
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 0.6 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.55 μm
・Thickness DB/thickness DA: 0.92
・Thickness DB-thickness DA: 0.05 μm

[Example 4]
The thin film transistor of Example 4 is a bottom-gate/top-contact transistor having the following structure. For the convenience of describing the thin film transistor of Example 4, dimensions related to structural items that are the same as the dimensions of the thin film transistor of Example 1 among the dimensions of the thin film transistor of Example 4 are omitted. In the thin film transistor of Example 4, the rotation speed of the substrate for forming the first gate insulating layer 21 was changed to 890 rpm, and the etching time of the first gate insulating layer 21 for forming the step portion 22 was set to 6 seconds. It was obtained in the same manner as in Example 1 except for the above.
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 1.0 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.94 μm
・Thickness DB/thickness DA: 0.94
・ Thickness DB-thickness DA: 0.06 μm

[Example 5]
The thin film transistor of Example 5 is a bottom-gate/top-contact transistor having the following structure. For the sake of convenience in describing the thin film transistor of Example 5, the dimensions of the thin film transistor of Example 5 that relate to structural items that are the same as the dimensions of the thin film transistor of Example 1 are omitted. In the thin film transistor of Example 4, the rotation speed of the substrate for forming the first gate insulating layer 21 was changed to 4800 rpm, and the etching time of the first gate insulating layer 21 for forming the step portion 22 was set to 14 seconds. It was obtained in the same manner as in Example 1 except for the above.
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 0.4 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.3 μm
・Thickness DB/thickness DA: 0.75
・Thickness DB-thickness DA: 0.1 μm

[Example 6]
In the thin film transistor of Example 6, the constituent material of the first gate insulating layer 21, the constituent material of the second gate insulating layer 23, the forming conditions of the first gate insulating layer 21, and the forming conditions of the second gate insulating layer 23 were changed. , was obtained in the same manner as in Example 1 except for the above.

The material for forming the first gate insulating layer 21 of Example 6 is photosensitive polymethylsilsesquioxane. The rotation speed of the substrate for forming the first gate insulating layer 21 of Example 6 is 1000 rpm, and the firing temperature of the coating film is 200.degree.

The second gate insulating layer 23 of Example 6 is a silicon oxynitride film formed using the following film formation conditions. The etching time for forming the step portion 22 in the first gate insulating layer 21 in Example 6 was 30 seconds, and the etching time for forming the second gate insulating layer 23 in Example 6 was 30 seconds. be.

[Film Formation Conditions for Second Gate Insulating Layer 23]
・Reactive gas: silane, ammonia, hydrogen, and dinitrogen monoxide ・Silane flow rate: 50 sccm
・Ammonia flow rate: 100sccm
・Hydrogen flow rate: 1000sccm
・Dinitrogen monoxide flow rate: 500sccm
・Deposition pressure: 300 Pa
・High frequency power: 900W
・High frequency power frequency: 13.56MHz
・Substrate temperature: 200°C

[Example 7]
In the thin film transistor of Example 7, the material for forming the first gate insulating layer 21, the material for forming the second gate insulating layer 23, the conditions for forming the first gate insulating layer 21, and the conditions for forming the second gate insulating layer 23 were changed. , was obtained in the same manner as in Example 1 except for the above.

The material for forming the first gate insulating layer 21 of Example 7 is a material in which nanoparticles made of silicon oxide are dispersed in an acrylic resin. The first gate insulating layer 21 of Example 7 was obtained by baking the coating film formed on the upper surfaces of the flexible base material 11 and the gate electrode layer 12 at 250° C. using the gravure offset printing method. . The coating liquid is a solution in which nanoparticles made of silicon oxide are dispersed in a solution containing an acrylic resin.

The second gate insulating layer 23 of Example 7 is a silicon nitride film formed using the following film formation conditions. The etching time for forming the step portion 22 in the first gate insulating layer 21 in Example 7 was 40 seconds, and the etching time for forming the second gate insulating layer 23 in Example 7 was 40 seconds. be.

[Film Formation Conditions for Second Gate Insulating Layer 23]
・Reactive gases: silane, ammonia, hydrogen, and nitrogen ・Silane flow rate: 10 sccm
・Ammonia flow rate: 70 sccm
・Hydrogen flow rate: 5000sccm
・Nitrogen flow rate: 2000sccm
・Deposition pressure: 200 Pa
・High frequency power: 1000W
・High frequency power frequency: 13.56MHz
・Substrate temperature: 200°C

[Example 8]
The thin film transistor of Example 8 is a bottom-gate/top-contact transistor having the following structure. For the sake of convenience in describing the thin film transistor of Example 8, dimensions related to structural items that are the same as those of the thin film transistor of Example 1 among the dimensions of the thin film transistor of Example 8 are omitted. A thin film transistor of Example 8 was obtained in the same manner as in Example 1 except that the size of the resist mask for forming the second gate insulating layer 23 was changed.
・Semiconductor layer 13 area SC: 800 μm ²
・Area SD of the second gate insulating layer 23: 800 μm ²
・Area SD/Area SC: 1.0

[Example 9]
The thin film transistor of Example 9 is a bottom-gate/top-contact transistor having the following structure. For the sake of convenience in describing the thin film transistor of Example 9, dimensions related to structural items that are the same as those of the thin film transistor of Example 1 among the dimensions of the thin film transistor of Example 9 are omitted. A thin film transistor of Example 9 was obtained in the same manner as in Example 1 except that the size of the resist mask for forming the second gate insulating layer 23 was changed.
・Semiconductor layer 13 area SC: 800 μm ²
・Area SD of the second gate insulating layer 23: 7200 μm ²
・Area SD/Area SC: 9.0

[Example 10]
The thin film transistor of Example 10 is a bottom-gate/top-contact transistor having the following structure. For the sake of convenience in describing the thin film transistor of Example 10, dimensions related to structural items that are the same as the dimensions of the thin film transistor of Example 4 among the dimensions of the thin film transistor of Example 10 are omitted. A thin film transistor of Example 10 was obtained in the same manner as in Example 4 except that the etching time of the first gate insulating layer 21 for forming the step portion 22 was changed to 70 seconds.
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 1.0 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.3 μm
・Thickness DB/thickness DA: 0.3
・Thickness DB-thickness DA: 0.7 μm

[Comparative Example 1]
The thin film transistor of Comparative Example 1 is a bottom-gate/top-contact transistor having the following structure. For the convenience of describing the thin film transistor of Comparative Example 1, dimensions related to structural items that are the same as the dimensions of the thin film transistor of Example 1 among the dimensions of the thin film transistor of Comparative Example 1 are omitted. A thin film transistor of Comparative Example 1 was obtained in the same manner as in Example 1 except that the etching time of the first gate insulating layer 21 for forming the step portion 22 was changed to 0 seconds.
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 0.6 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.6 μm
・Thickness DB/thickness DA: 1.0
・Thickness DB-thickness DA: 0.0 μm

[Comparative Example 2]
The thin film transistor of Comparative Example 2 is a bottom-gate/top-contact transistor having the following structure. For the convenience of describing the thin film transistor of Comparative Example 2, the dimensions related to structural items that are the same as the dimensions of the thin film transistor of Example 4 among the dimensions of the thin film transistor of Comparative Example 2 are omitted. A thin film transistor of Comparative Example 2 was obtained in the same manner as in Example 4 except that the etching time of the first gate insulating layer 21 for forming the step portion 22 was changed to 5 seconds.
・Thickness DA of stepped portion 22 of first gate insulating layer 21: 1.0 μm
・Thickness DB of the flat portion of the first gate insulating layer 21: 0.95 μm
・Thickness DB/thickness DA: 0.95
・Thickness DB-thickness DA: 0.05 μm

[evaluation]
For the thin film transistors of Examples 1 to 10 and Comparative Examples 1 and 2, mobilities were calculated from transfer characteristics using a semiconductor parameter analyzer (B1500A: manufactured by Agilent Technologies).

To calculate the mobility, first, the voltage of the source electrode layer 14 was set to 0 V, and the source-drain voltage was set to 10 V, and the transfer characteristic, which is the relationship between the gate voltage and the drain current Id, was obtained. The source-drain voltage is the voltage between source electrode layer 14 and drain electrode layer 15 . A gate voltage is the voltage between the source electrode layer 14 and the gate electrode layer 12 . A drain current is a current that flows through the drain electrode layer 15 . At this time, the gate voltage was changed by changing the voltage of the gate electrode layer 12 from -20V to +20V.

Next, using the transfer characteristics of the gate voltage and the drain current, the mutual conductance (A/V), which is the change in the drain current with respect to the change in the gate voltage, was calculated. Then, the relative dielectric constant and thickness of the first gate insulating layer 21, the relative dielectric constant and thickness of the second gate insulating layer 23, the channel length, the channel Width, source-drain voltage were applied and the mobility was calculated.

Next, while winding the flexible base material 11 around a metal rod with a radius of 1 mm, the transfer characteristic, which is the relationship between the gate voltage and the drain current Id, was obtained as described above. Then, the difference in mobility before and after the load test with respect to the mobility before the load test was measured as the mobility decrease rate.

FIG. 3 shows, for Examples 1 to 10 and Comparative Examples 1 and 2, the thickness DA of the stepped portion 22 of the first gate insulating layer 21, the thickness DB of the flat portion, the constituent material of the first gate insulating layer 21, The constituent material, area SD/area SC, pre-test mobility, and mobility reduction rate of the second gate insulating layer 23 are shown.

As shown in FIG. 3, the mobilities before the bending test of the thin film transistors of Examples 1 to 10 and the thin film transistors of Comparative Examples 1 and 2 are all 10.0 cm ² /Vs or more and 10.6 cm ² /Vs or less. was recognized. On the other hand, it was found that the thin film transistors of Examples 1 to 10 had a mobility reduction rate of 2.0% or less. On the other hand, it was found that the mobility reduction rate in the thin film transistor of the comparative example exceeded 70%. In particular, Example 3, Example 4, Comparative Example 1, and Comparative Example 2 all have a thickness DB/thickness DA of 0.9 or more and 1.0 or less, but the mobility of Comparative Examples 1 and 2 It was found that the mobility reduction rates of Examples 3 and 4 were significantly smaller than the reduction rates. Accordingly, it can be said that the ratio of thickness DB/thickness DA of 0.94 or less, that is, the thin film transistor satisfies the upper limit of Condition 1, significantly suppresses the rate of decrease in mobility of the thin film transistor.

In addition, the thin film transistor of Example 2 and the thin film transistor of Example 10 both have a thickness DB/thickness DA of about 0.3, while the thin film transistor of Example 2 has a better mobility reduction. It was also accepted to show the rate. Similarly, the thin film transistor of Example 3 and the thin film transistor of Example 4 both have a thickness DB/thickness DA of about 0.9, while the thin film transistor of Example 3 has better mobility reduction. It was also accepted to show the rate. Accordingly, the thickness DB/thickness DA is 0.94 or less and the thickness DA is 0.6 μm or less, that is, the thin film transistor satisfies the upper limit of Condition 1 and Condition 4. It can be said that the mobility decrease rate of is brought closer to 0.

In addition, in the thin film transistor of Example 10, after the bending test, minute cracks were generated on the surfaces of the source electrode layer 14 and the drain electrode layer 15 covering the end face of the stepped portion 22 so as not to cause disconnection. was confirmed by microscopic observation. In the thin film transistor of Example 2, no minute cracks were observed on the surfaces of the source electrode layer 14 and the drain electrode layer 15 covering the end face of the stepped portion 22 even after the bending test. Accordingly, it can be said that the thickness DB/thickness DA of 0.30 or more, particularly the thickness DA of 0.6 μm or less, enhances the effectiveness of the effect of suppressing the mobility decrease rate.

According to the above embodiment, the following effects can be obtained.
(1) A thin film transistor that satisfies Condition 1 and includes the electrode layers 14 and 15 covering from the semiconductor layer 13 to the flat portion of the first gate insulating layer 21 does not reduce mobility due to bending of the flexible base material 11. suppress.

(2) A thin film transistor that satisfies Condition 1 and Condition 4 suppresses a decrease in mobility due to bending of the flexible base material 11 compared to a thin film transistor that does not satisfy Condition 1 or Condition 4.

(3) If the thin film transistor satisfies at least one of the

conditions

2, 3, and 5, the effectiveness of obtaining the effects according to the above (1) and (2) is enhanced.

The above embodiment can also be implemented with the following modifications.
[Oxide semiconductor]
If it is required to improve the accuracy of suppressing the threshold variation ΔVth in the bent state, the oxide semiconductor forming the semiconductor layer 13 is preferably a ternary oxide semiconductor that is the same type as InGaZnO. Further, in the case where it is required to improve the accuracy of suppressing the threshold variation ΔVth in the bent state, the oxide semiconductor forming the semiconductor layer 13 should be a ternary semiconductor containing indium and gallium or containing indium and zinc. An oxide semiconductor is more preferable.

[Protective layer]
- The device structure may further include a protective layer that protects the back channel portion of the semiconductor layer 13 . The back channel portion of the semiconductor layer 13 is the surface of the semiconductor layer 13 opposite to the surface in contact with the second gate insulating layer 23 . The protective layer is positioned to cover the back channel portion of the semiconductor layer 13 .

The layer structure of the protective layer may be a single layer structure or a multilayer structure. The protective layer may cover only the back channel portion, or may cover the gate electrode layer 12, the first gate insulating layer 21, the second gate insulating layer 23, the source electrode layer 14, the drain electrode layer 15, and the semiconductor layer 13. may The back channel portion of the semiconductor layer 13 changes the electronic state of the semiconductor layer 13 by being exposed to chemical substances used in manufacturing the thin film transistor or by adsorbing gases in the atmosphere. The protective layer protects the back channel portion of the semiconductor layer 13 from chemicals during manufacturing and the atmosphere, thereby stabilizing the electrical characteristics of the thin film transistor.

An example of the material forming the protective layer is at least one of an inorganic insulating compound and an organic insulating compound. An example of an inorganic insulating compound is at least one selected from the group consisting of silicon oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, zirconium oxide, silicon nitride, and silicon oxynitride. An example of the organic insulating compound is at least one selected from the group consisting of acrylic resin such as polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, epoxy resin, polyimide, and parylene.

When the protection layer is required to suppress leakage current, the electrical resistance value of the protection layer is preferably 10 ¹¹ Ωcm or more, more preferably 10 ¹⁴ Ωcm or more. When the material forming the protective layer contains an organic insulating compound, the thickness of the layer made of the organic insulating compound is preferably 0.3 μm or more and 3 μm or less. When the material forming the protective layer contains an inorganic insulating compound, the thickness of the layer made of the inorganic insulating compound is preferably 5 nm or more and 100 nm or less. When the source electrode layer 14 and the drain electrode layer 15 are required to be formed as upper layers of the protective layer, the end face shape of the protective layer may be a forward tapered shape. A protective layer having a forward tapered end face shape suppresses disconnection and unstable shape of electrode layers stacked on the protective layer.

A protective layer composed of an inorganic insulating compound is formed by a sputtering method, an atomic layer deposition method, a pulse laser deposition method, or a CVD method. A protective layer composed of an organic insulating compound is formed by a wet film formation method such as a spin coating method, a slit coating method, or various printing methods.

CL... Length of semiconductor layer DL... Length of second insulating layer 11... Flexible base material 12... Gate electrode layer 13... Semiconductor layer 14... Source electrode layer 15... Drain electrode layer 21... First gate insulating layer 22... Step Part 23... Second gate insulating layer

Claims

a flexible substrate comprising a flat surface;
a device structure located on the flat surface, the thin film transistor comprising:
The element structure is
a gate electrode layer positioned on a portion of the flat surface;
a first gate insulating layer including an organic atomic group, comprising a flat portion positioned on the other portion of the flat surface and following the flat surface, and a stepped portion covering the gate electrode layer and protruding from the flat portion; and,
a second gate insulating layer, which is an inorganic compound, positioned within the upper surface of the stepped portion;
a semiconductor layer, which is an oxide semiconductor, located within the upper surface of the second gate insulating layer;
a source electrode layer connected to a first end of the semiconductor layer;
a drain electrode layer connected to the second end of the semiconductor layer;
The source electrode layer and the drain electrode layer are
having a stepped shape that follows the end surface of the stepped portion and the end surface of the second gate insulating layer from the flat portion to the semiconductor layer;
A thin film transistor, wherein the thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.
The stepped portion has a thickness of 1.0 μm or less,
2. An area SD occupied by the second gate insulating layer on the upper surface of the step portion and an area SC occupied by the semiconductor layer on the upper surface of the second gate insulating layer satisfy 1≦SD/SC≦9. The thin film transistor described.
3. The thin film transistor according to claim 1, wherein the step portion has a thickness of 0.6 [mu]m or less.
The thin film transistor according to any one of claims 1 to 3, wherein a difference between a thickness DA of the step portion and a thickness DB of the flat portion is larger than a thickness of the gate electrode layer.
a flexible substrate comprising a flat surface;
a device structure located on the flat surface, the thin film transistor comprising:
The element structure is
a gate electrode layer positioned on a portion of the flat surface;
a first gate insulating layer including an organic atomic group, comprising a flat portion positioned on the other portion of the flat surface and following the flat surface, and a stepped portion covering the gate electrode layer and protruding from the flat portion; and,
a second gate insulating layer, which is an inorganic compound, positioned within the upper surface of the stepped portion;
a semiconductor layer, which is an oxide semiconductor, located within the upper surface of the second gate insulating layer;
a source electrode layer connected to a first end of the semiconductor layer;
a drain electrode layer connected to the second end of the semiconductor layer;
The stepped portion has a thickness of 0.6 μm or less,
A thin film transistor, wherein the thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.
a difference between a thickness DA of the step portion and a thickness DB of the flat portion is larger than a thickness of the gate electrode layer;
an area SD occupied by the second gate insulating layer on the upper surface of the step portion and an area SC occupied by the semiconductor layer on the upper surface of the second gate insulating layer satisfy 1≦SD/SC≦9,
6. The thin film transistor according to claim 5.
The thin film transistor according to any one of Claims 1 to 5, wherein the inorganic compound is one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.
The thin film transistor according to any one of claims 1 to 6, wherein the oxide semiconductor contains indium.
forming a gate electrode layer on a portion of the flat surface of the flexible substrate;
forming a first gate insulating layer containing an organic atomic group on the flat surface so as to cover the gate electrode layer, thereby forming a flat portion located on another portion of the flat surface and following the flat surface; forming a first gate insulating layer covering the electrode layer and comprising a stepped portion protruding from the flat portion;
forming a second gate insulating layer made of an inorganic compound in the upper surface of the stepped portion;
forming a semiconductor layer that is an oxide semiconductor in the upper surface of the second gate insulating layer;
forming a source electrode layer from the flat portion to the first end of the semiconductor layer so as to have a stepped shape that follows the end face of the stepped portion and the end face of the second gate insulating layer;
forming a drain electrode layer from the flat portion to a second end of the semiconductor layer so as to have a stepped shape that follows the end face of the stepped portion and the end face of the second gate insulating layer;
A method of manufacturing a thin film transistor, wherein the thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.
forming a gate electrode layer on a portion of the flat surface of the flexible substrate;
forming a first gate insulating layer containing an organic atomic group on the flat surface so as to cover the gate electrode layer, thereby forming a flat portion located on another portion of the flat surface and following the flat surface; forming a first gate insulating layer covering the electrode layer and comprising a stepped portion protruding from the flat portion;
forming a second gate insulating layer made of an inorganic compound in the upper surface of the stepped portion;
forming a semiconductor layer that is an oxide semiconductor in the upper surface of the second gate insulating layer;
forming a source electrode layer connected to a first end of the semiconductor layer;
forming a drain electrode layer connected to a second end of the semiconductor layer;
The stepped portion has a thickness of 0.6 μm or less,
A method of manufacturing a thin film transistor, wherein the thickness DA of the step portion and the thickness DB of the flat portion satisfy 0.30≦DB/DA≦0.94.