WO2023145558A1 - Substrate-processing device and substrate-processing method - Google Patents

Abstract

This substrate-processing device comprises: a pick-up unit; a removal unit; and a mounting unit. The pick-up unit separates a chip from a tape in a state where a plurality of the chips are fitted to a frame via the tape and a protective film is formed on a first main surface of each of the chips on the side that is opposite from the tape. After the chip is separated from the tape by the pick-up unit, the removal unit removes the protective film from the chip. After the removal unit has removed the protective film, the mounting unit mounts the chip on a substrate with the first main surface of the chip facing the substrate.

Description

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

The present disclosure relates to a substrate processing apparatus and a substrate processing method.

The chip mounting system described in Patent Document 1 includes a chip supply device, a bonding device, a surface treatment device, a loading/unloading section, and a transport section (paragraph [0225] of Patent Document 1). The chip supply device holds a plurality of chips and individually supplies the chips to be joined. The bonding device attaches the chips supplied from the chip supply device onto the substrate. The surface treatment apparatus performs surface activation treatment and hydrophilization treatment on the bonding surfaces of the plurality of chips and the substrate. The loading/unloading section loads a chip and a substrate to be bonded from the outside of the chip mounting system into the inside thereof, and carries out the substrate on which the chip is attached (the structure including the chip and the substrate) to the outside. The transport unit transports a plurality of chips, substrates, and a structure including chips and substrates between the loading/unloading unit, the chip supply device, the bonding device, and the surface treatment device. Inside the chip feeder, a dicing process is performed to generate a plurality of chips (paragraph [0248] of Patent Document 1). Also, inside the chip supply device, a plurality of diced chips are placed on a dicing tape (paragraph [0250] of Patent Document 1).

Japanese Patent No. 6337400

One aspect of the present disclosure provides a technique for improving the quality of substrates with chips.

A substrate processing apparatus according to one aspect of the present disclosure includes a pickup section, a removal section, and a mount section. The pickup part separates the chips from the tape in a state in which a plurality of chips are attached to the frame via a tape and a protective film is formed on the first main surface of the chips opposite to the tape. The removal unit removes the protective film from the chip after the chip is separated from the tape by the pickup unit. The mounting section mounts the chip on the substrate with the first main surface of the chip facing the substrate after the protective film is removed by the removing portion.

According to one aspect of the present disclosure, it is possible to improve the quality of the chip-equipped substrate.

FIG. 1 is a plan view showing a substrate processing apparatus according to one embodiment. 2A is a cross-sectional view showing an example of a substrate, FIG. 2B is a cross-sectional view showing an example of a chip, and FIG. 2C is a cross-sectional view showing an example of chip pick-up, FIG. 2D is a cross-sectional view showing an example of a substrate with a chip. FIG. 3 is a flowchart illustrating a substrate processing method according to one embodiment. 4A is a plan view showing an example of the motion of the first frame transfer arm, and FIG. 4B is a plan view showing an example of the motion of the first frame transfer arm following FIG. 4A. be. FIG. 5 is a cross-sectional view showing an example of the tip cleaning section. FIG. 6 is a cross-sectional view showing an example of an expanded portion. FIG. 7 is a cross-sectional view showing an example of a second processing station. FIG. 8 is a cross-sectional view showing an example of lamination of dummy chips. FIG. 9 is a cross-sectional view showing an example of an inspection unit. FIG. 10 is a cross-sectional view showing an example of the chip peeling portion. FIG. 11A is a cross-sectional view showing an example of a blade, and FIG. 11B is a cross-sectional view showing an example of a heater and a cooler. FIG. 12(A) is a cross-sectional view showing an example of a seal and a nozzle, and FIG. 12(B) is a cross-sectional view showing an example of a push-up pin. FIG. 13 is a cross-sectional view showing an example of a rework portion. FIG. 14 is a plan view showing a substrate processing apparatus according to the first modified example. FIG. 15 is a plan view showing a substrate processing apparatus according to a second modified example. 16A is a cross-sectional view showing a modification of the substrate shown in FIG. 2A, FIG. 16B is a cross-sectional view showing an example of the second chip, and FIG. FIG. 16D is a cross-sectional view showing an example of picking up a chip, and FIG. 16D is a cross-sectional view showing a modification of the chip-attached substrate shown in FIG. 2D. FIG. 17A is a cross-sectional view showing another modification of the substrate with chips shown in FIG. 2D, and FIG. 17C is a cross-sectional view showing an example of post-processing following FIG. 17B, and FIG. 17D is a cross-sectional view showing an example of post-processing following FIG. It is a sectional view showing. FIG. 18 is a plan view showing a substrate processing apparatus according to a third modified example. 19A is a cross-sectional view showing an example of a chip protected by a protective film, and FIG. 19B is a cross-sectional view showing an example of pickup of the chip shown in FIG. 19A. 19C is a cross-sectional view showing an example of mounting the chip shown in FIG. 19B; FIG. 20 is a cross-sectional view showing an example of the second processing station shown in FIG. 18. FIG. 21A is a cross-sectional view showing an example of particles, FIG. 21B is a cross-sectional view showing an example of supply of stripping solution, and FIG. 21C is a cross-sectional view showing an example of stripping of a protective film. FIG. 21D is a cross-sectional view showing an example of dissolution of the protective film. FIG. 22 is a cross-sectional view showing an example of the application section.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In addition, in each drawing, the same reference numerals are given to the same or corresponding configurations, and explanations thereof may be omitted. In this specification, the X-axis direction, the Y-axis direction, and the Z-axis direction are directions perpendicular to each other. The X-axis direction and Y-axis direction are horizontal directions, and the Z-axis direction is vertical direction.

A substrate processing apparatus 1 according to one embodiment will be described with reference to FIGS. As shown in FIGS. 2A to 2D, the substrate processing apparatus 1 bonds a plurality of chips CP1 to different bonding regions on the main surface W1c of the substrate W1, thereby forming a substrate CW1 with chips. manufacture. The pasting area is set in advance.

A substrate CW1 with chips includes a substrate W1 and a plurality of chips CP1 bonded to the substrate W1. Although not shown, another chip may be stacked on each chip CP1.

A substrate W1 shown in FIG. 2(A) is loaded into the substrate processing apparatus 1. The substrate W1 has an underlying substrate W1a and a plurality of devices W1b formed on the underlying substrate W1a. The underlying substrate W1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. Device W1b includes a semiconductor element, a circuit, a terminal, or the like. The device W1b is formed on the main surface W1c.

Also, a plurality of chips CP1 shown in FIG. A plurality of chips CP1 are adhered to a tape TP1, and the outer circumference of the tape TP1 is attached to the frame FR1. A plurality of chips CP1 are arranged in the opening of the frame FR1. The plurality of chips CP1 can be obtained, for example, by dicing the substrate while the substrate is adhered to the tape TP1.

The chip CP1 has a base substrate CP1a and a device CP1b formed on the base substrate CP1a. The underlying substrate CP1a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. Device CP1b includes a semiconductor element, a circuit, a terminal, or the like. The device CP1b is arranged on the side opposite to the tape TP1 with respect to the base substrate CP1a.

As shown in FIG. 2(C), the pickup unit 53 separates the plurality of chips CP1 individually from the tape TP1. After that, the chip CP1 is turned upside down and then bonded to the substrate W1 as shown in FIG. 2(D). The device W1b on the substrate W1 and the device CP1b on the chip CP1 are electrically connected. Thus, a chip-equipped substrate CW1 is obtained.

It should be noted that, as shown in FIG. 17A, the substrate W1 that constitutes the chip-equipped substrate CW1 may not have the device W1b. That is, the substrate W1 does not have to have an electric circuit. For example, the substrate W1 consists of only a silicon wafer, a compound semiconductor wafer, or a glass substrate. When the substrate W1 does not have the device W1b, as shown in FIG. 17B, the substrate W1 and the substrate W2 are bonded with the plurality of chips CP1 interposed therebetween. Next, as shown in FIG. 17C, the plurality of chips CP1 and substrate W1 are separated, and finally, as shown in FIG. spliced. The substrate W3 has an underlying substrate W3a and a plurality of devices W3b formed on the underlying substrate W3a. The device W3b on the substrate W3 and the device CP1b on the chip CP1 are electrically connected.

As shown in FIG. 1, the substrate processing apparatus 1 includes a loading/unloading station 2, a first processing station 3, an interface block 4, a second processing station 5, and a controller 9. The loading/unloading station 2, the first processing station 3, the interface block 4, and the second processing station 5 are arranged in this order from the X-axis negative direction side to the X-axis positive direction side.

The loading/unloading station 2 includes a mounting table 20 . Cassettes C1 to C4 are mounted on the mounting table 20. As shown in FIG. The cassette C1 accommodates the substrate W1 shown in FIG. 2(A). The cassette C2 accommodates the chip-attached substrate CW1 shown in FIG. 2(D). The cassette C3 accommodates a plurality of chips CP1 together with the frame FR1 shown in FIG. 2(B). A cassette C4 accommodates a used frame FR1 (not shown). The used frame FR1 is the frame FR1 remaining after the plurality of chips CP1 are separated from the tape TP1. A chip CP1 may remain in the used frame FR1.

The loading/unloading station 2 includes a transport area 21 , a third substrate transport arm 22 and a third frame transport arm 23 . The transport area 21 is adjacent to the mounting table 20 . The third substrate transport arm 22 holds and transports the substrate W1 in the transport area 21 . The third frame transport arm 23 holds and transports the frame FR1 in the transport area 21 . The third substrate transfer arm 22 and the third frame transfer arm 23 are each capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.

The loading/unloading station 2 has a drive section (not shown) that moves or rotates the third substrate transfer arm 22 and the third frame transfer arm 23 . The third substrate transfer arm 22 and the third frame transfer arm 23 may be mounted on the same Y-axis slider and moved in the Y-axis direction at the same time, or may be mounted on different Y-axis sliders and moved in the Y-axis direction independently. may be The third substrate transfer arm 22 and the third frame transfer arm 23 are stacked in the Z-axis direction when mounted on the same Y-axis slider. When the third substrate transfer arm 22 and the third frame transfer arm 23 are mounted on different Y-axis sliders, the Y-axis sliders are shifted in the Z-axis direction.

The third substrate transport arm 22 takes out the substrate W1 before bonding the chip CP1 from the cassette C1 and transports it to the substrate platform 24 . Further, the third substrate transport arm 22 takes out the substrate CW1 with chips from the substrate mounting portion 24 and stores it in the cassette C2. The third substrate transfer arm 22 that transfers the substrate W1 before bonding the chip CP1 thereto and the third substrate transfer arm 22 that transfers the substrate CW1 with the chip may be provided separately.

The third frame transport arm 23 takes out the plurality of chips CP1 together with the frame FR1 from the cassette C3 and transports them to the frame mounting section 25. Also, the third frame transfer arm 23 takes out the used frame FR1 from the frame placing portion 25 and stores it in the cassette C4. The third frame transfer arm 23 that transfers the plurality of chips CP1 together with the frame FR1 and the third frame transfer arm 23 that transfers the used frame FR1 may be provided separately.

The loading/unloading station 2 includes a substrate loading section 24 and a frame loading section 25 . The substrate rest 24 and the frame rest 25 are arranged between the transport area 21 of the loading/unloading station 2 and the transport area 30 of the first processing station 3 and are adjacent to both transport areas 21 , 30 . The substrate rest 24 and the frame rest 25 may be vertically stacked to reduce the footprint of the loading/unloading station 2 .

The substrate W1 before bonding the chip CP1 is mounted on the substrate mounting portion 24. A substrate CW<b>1 with a chip may be placed on the substrate placement part 24 . The substrate mounting portion 24 on which the substrate W1 before bonding the chip CP1 is mounted and the substrate mounting portion 24 on which the substrate CW1 with chips is mounted may be provided separately, or a plurality of each may be provided. may be

A plurality of chips CP1 are mounted on the frame mounting portion 25 together with the frame FR1. A used frame FR<b>1 may be placed on the frame placement portion 25 . The frame mounting portion 25 on which the plurality of chips CP1 are mounted together with the frame FR1 and the frame mounting portion 25 on which the used frames FR1 are mounted may be provided separately, or a plurality of each may be provided. good too.

The first processing station 3 includes a transfer area 30 , a first substrate transfer arm 31 and a first frame transfer arm 32 . The transport area 30 extends in the X-axis direction. The first substrate transport arm 31 holds and transports the substrate W<b>1 in the transport area 30 . The first frame transport arm 32 holds and transports the frame FR1 in the transport area 30 . The first substrate transfer arm 31 and the first frame transfer arm 32 are each capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis.

The first processing station 3 has a drive section (not shown) that moves or rotates the first substrate transfer arm 31 and the first frame transfer arm 32 . The first substrate transfer arm 31 and the first frame transfer arm 32 may be mounted on the same X-axis slider and moved in the X-axis direction at the same time, or may be mounted on different X-axis sliders and moved in the X-axis direction independently. may be The first substrate transfer arm 31 and the first frame transfer arm 32 are stacked in the Z-axis direction when mounted on the same X-axis slider. When the first substrate transfer arm 31 and the first frame transfer arm 32 are mounted on different X-axis sliders, the plurality of X-axis sliders are shifted in the Z-axis direction.

The first substrate transport arm 31 takes out the substrate W1 before bonding the chip CP1 from the substrate mounting part 24, passes through the surface modification part 34 and the substrate cleaning part 35, and transfers it to the first buffer part of the interface block 4. Transport to 41. The first substrate transport arm 31 also takes out the substrate CW1 with chips from the first buffer unit 41 and places it on the substrate placement unit 24 of the loading/unloading station 2 via the inspection unit 36 and the like. The first substrate transfer arm 31 that transfers the substrate W1 before bonding the chip CP1 thereto and the first substrate transfer arm 31 that transfers the substrate CW1 with the chip may be provided separately.

The first frame transport arm 32 takes out the plurality of chips CP1 together with the frame FR1 from the frame mounting part 25 and transports them to the second buffer part 42 of the interface block 4 via the chip cleaning part 33 . Also, the first frame transfer arm 32 takes out the used frame FR1 from the second buffer section 42 and places it on the frame placement section 25 of the loading/unloading station 2 . The first frame transfer arm 32 that transfers the plurality of chips CP1 together with the frame FR1 and the first frame transfer arm 32 that transfers the used frame FR1 may be provided separately.

The first processing station 3 includes a chip cleaning section 33 , a surface modification section 34 , a substrate cleaning section 35 , an inspection section 36 , a chip peeling section 37 , a rework section 38 and an annealing section 39 . The chip cleaning section 33, the surface modification section 34, the substrate cleaning section 35, the inspection section 36, the chip peeling section 37, the rework section 38, and the annealing section 39 are adjacent to the transfer area 30, It is arranged on the Y-axis positive direction side or the Y-axis negative direction side of the transport area 30 .

The chip cleaning unit 33 cleans the plurality of chips CP1 in a state in which the plurality of chips CP1 are adhered to the tape TP1 and the outer periphery of the tape TP1 is attached to the frame FR1. By bonding the chip CP1 to the substrate W1 after cleaning the chip CP1, it is possible to prevent foreign matter from entering. The details of the chip cleaning unit 33 will be described later.

The surface modification unit 34 plasma-processes the main surface W1c of the substrate W1. In the surface modification section 34, for example, the oxygen gas, which is the processing gas, is excited under reduced pressure to be plasmatized and ionized. By irradiating the main surface W1c of the substrate W1 with oxygen ions, the main surface W1c is modified. The processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.

The substrate cleaning section 35 cleans the main surface W1c of the substrate W1. For example, the substrate cleaning unit 35 supplies pure water (for example, deionized water) onto the substrate W1 while rotating the substrate W1 held by the spin chuck. The pure water spreads over the entire main surface W1c due to centrifugal force and washes the main surface W1c. Pure water imparts OH groups to the main surface W1c that has been modified in advance. The substrate W1 and the chip CP1 can be bonded using hydrogen bonding between OH groups.

The inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad. The inspection items include at least one of presence/absence of foreign matter such as air bubbles and presence/absence of misalignment. For example, if a bubble exists at the interface between the substrate W1 and the chip CP1, the bubble bursts when the chip-attached substrate CW1 is vacuum-processed. Due to the bursting of the air bubbles, even the chip CP1, which is in a good state of bonding, may cause problems, or the vacuum chamber may be contaminated. Alternatively, if air bubbles or particles exist at the interface between the substrate W1 and the chip CP1, the height of the chip CP1 increases, chipping occurs during grinding or polishing, and the resulting impact causes problems even for the chip CP1, which is in a good state of bonding. Details of the inspection unit 36 will be described later.

The chip peeling unit 37 peels off the chip CP1, which was found to be in a defective bonding state in the inspection by the inspection unit 36, from the substrate W1. By peeling off the chip CP1, which is in a poorly bonded state, from the substrate W1, the problem caused when air bubbles or particles are present at the interface between the substrate W1 and the chip CP1 can be solved, and the quality of the substrate CW1 with the chip can be improved. The chip CP1 separated from the substrate W1 may be reused or discarded. Details of the chip peeling portion 37 will be described later.

The rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off by the chip peeling unit 37 on the main surface W1c of the substrate W1. This process is a process of returning the bonding region from which the chip CP1 has been peeled off to the state immediately before bonding the chip CP1. For example, the rework unit 38 selectively supplies at least one of plasma and water to the bonding region from which the chip CP1 has been removed. Details of the rework unit 38 will be described later.

The annealing section 39 heats the chip-equipped substrate CW1. Before heat treatment, the chip CP1 and the substrate W1 are bonded by hydrogen bonding between OH groups. The heat treatment causes a dehydration-condensation reaction and a covalent bond, thereby improving the bonding strength between the chip CP1 and the substrate W1. Note that the chip CP<b>1 is peeled off by the chip peeling unit 37 before the chip-attached substrate CW<b>1 is heat-treated by the annealing unit 39 .

The interface block 4 is adjacent to the transport area 30 of the first processing station 3 . The interface block 4 includes a first buffer section 41 , a second buffer section 42 , a second substrate transfer arm 43 and a second frame transfer arm 44 . The first buffer section 41 and the second buffer section 42 are adjacent to the transport area 30 of the first processing station 3 . The first buffer section 41 and the second buffer section 42 may be vertically stacked to reduce the footprint of the interface block 4 .

The first buffer unit 41 stores the substrate W1 before bonding the chip CP1. The first buffer section 41 may store the chip-equipped substrate CW1. The first buffer section 41 that stores the substrate W1 before bonding the chip CP1 thereto and the first buffer section 41 that stores the substrate CW1 with the chip may be provided separately, or a plurality of each may be provided. .

The second buffer unit 42 stores a plurality of chips CP1 together with the frame FR1. The second buffer section 42 may store the used frame FR1. The second buffer section 42 that stores the plurality of chips CP1 together with the frame FR1 and the second buffer section 42 that stores the used frame FR1 may be provided separately, or a plurality of each may be provided.

The second substrate transport arm 43 takes out the substrate W1 before bonding the chip CP1 from the first buffer unit 41 and transports it to the substrate holding unit 51 of the second processing station 5 . The second substrate transport arm 43 may transport the substrate CW1 with chips from the substrate holding section 51 to the first buffer section 41 . The second substrate transfer arm 43 is capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis. The second substrate transport arm 43 that transports the substrate W1 before bonding the chip CP1 thereto and the second substrate transport arm 43 that transports the substrate CW1 with the chip may be provided separately.

The second frame transport arm 44 takes out the plurality of chips CP1 together with the frame FR1 from the second buffer section 42 and transports them to the chip holding section 52 of the second processing station 5 . The second frame transport arm 44 may transport the used frame FR1 from the chip holding section 52 to the second buffer section 42 . The second frame transfer arm 44 is capable of horizontal (both X-axis and Y-axis) and vertical movement and rotation about a vertical axis. The second frame transfer arm 44 that transfers the plurality of chips CP1 together with the frame FR1 and the second frame transfer arm 44 that transfers the used frame FR1 may be provided separately.

The interface block 4 has a drive section (not shown) that moves or rotates the second substrate transfer arm 43 and the second frame transfer arm 44 . The second substrate transfer arm 43 and the second frame transfer arm 44 may be moved simultaneously in a predetermined direction, or may be moved independently in a predetermined direction. Although the second substrate transfer arm 43 and the second frame transfer arm 44 are not stacked in the Z-axis direction in FIGS. 1 and 2, they may be stacked in the Z-axis direction.

The interface block 4 stores a substrate W1 that has undergone pretreatment (for example, surface modification and cleaning) and a plurality of chips CP1 that have undergone pretreatment (for example, cleaning). As a result, the operating rate of the second processing station 5 can be improved, and the production efficiency of the substrates CW1 with chips can be improved.

The interface block 4 may be omitted, and the first processing station 3 and the second processing station 5 may be adjacent to each other. In this case, the first substrate transport arm 31 of the first processing station 3 transports the substrate W1 before bonding the chip CP1 to the substrate holding unit 51 of the second processing station 5, and the substrate CW1 with chips is transferred to the substrate holding unit. Received from 51. Also, in this case, the first frame transport arm 32 of the first processing station 3 transports the plurality of chips CP1 together with the frame FR1 to the chip holding section 52 of the second processing station 5, and transfers the used frame FR1 to the chip holding section. Received from 52.

The second processing station 5 is arranged on the opposite side of the transfer area 30 of the first processing station 3 with respect to the interface block 4 . The second processing station 5 includes a substrate holding section 51 , a chip holding section 52 , a pickup section 53 and a mounting section 54 . The substrate holding part 51 holds the substrate W1. The chip holding unit 52 holds the plurality of chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1. The substrate holding part 51 and the chip holding part 52 are each capable of horizontal movement (both the X-axis direction and the Y-axis direction) and rotation about the vertical axis. The pickup unit 53 separates the chip CP1 held by the chip holding unit 52 from the tape TP1. The mounting unit 54 mounts the chip CP1 separated from the tape TP1 by the pickup unit 53 onto the main surface W1c of the substrate W1. Details of the second processing station 5 will be described later.

A chip bonding section 6 is composed of the interface block 4 and the second processing station 5 . The chip bonding section 6 is adjacent to the transfer area 30 of the first processing station 3 . As described above, the interface block 4 may be omitted, and the chip bonding section 6 may be composed of only the second processing station 5 .

The control unit 9 is, for example, a computer, and includes a CPU (Central Processing Unit) 91 and a storage medium 92 such as a memory. The storage medium 92 stores programs for controlling various processes executed in the substrate processing apparatus 1 . The control unit 9 controls the operation of the substrate processing apparatus 1 by causing the CPU 91 to execute programs stored in the storage medium 92 . A unit controller for controlling the operation of each unit constituting the substrate processing apparatus 1 may be provided, and a system controller for integrally controlling a plurality of unit controllers may be provided. The control section 9 may be configured by the unit control section and the system control section.

Next, a substrate processing method according to one embodiment will be described with reference to FIG. The processing in FIG. 3 is performed under the control of the control unit 9 .

First, the third substrate transfer arm 22 of the loading/unloading station 2 takes out the substrate W1 from the cassette C1 and transfers it to the substrate platform 24 . Next, the first substrate transport arm 31 of the first processing station 3 takes out the substrate W1 from the substrate platform 24 and transports it to the surface modification unit 34 . Next, the surface modification unit 34 plasma-processes the main surface W1c of the substrate W1 (step S101). After that, the first substrate transfer arm 31 takes out the substrate W<b>1 from the surface modification section 34 and transfers it to the substrate cleaning section 35 . Next, the substrate cleaning section 35 cleans the main surface W1c of the substrate W1 (step S102). After that, the first substrate transport arm 31 takes out the substrate W1 from the substrate cleaning section 35 and transports it to the first buffer section 41 of the interface block 4 . Next, the second substrate transfer arm 43 takes out the substrate W1 from the first buffer section 41 and transfers it to the substrate holding section 51 of the second processing station 5 .

In parallel with the above processing, the following processing is performed. First, the third frame transfer arm 23 of the loading/unloading station 2 takes out a plurality of chips CP1 together with the frame FR1 from the cassette C3, and transfers them to the frame mounting section 25. As shown in FIG. Next, the first frame transfer arm 32 of the first processing station 3 takes out the plurality of chips CP1 together with the frame FR1 from the frame mounting section 25 and transfers them to the chip cleaning section 33 . Next, the chip cleaning unit 33 cleans the multiple chips CP1 (step S103). After that, the first frame transport arm 32 takes out the plurality of chips CP1 together with the frame FR1 from the chip cleaning section 33 and transports them to the second buffer section 42 of the interface block 4 . Next, the second frame transport arm 44 takes out the plurality of chips CP1 together with the frame FR1 from the second buffer section 42 and transports them to the chip holding section 52 of the second processing station 5 .

Next, the chip bonding section 6 bonds a plurality of chips CP1 to different bonding regions on the main surface W1c of the substrate W1 (step S104). Thus, a chip-equipped substrate CW1 is obtained. After that, the second substrate transport arm 43 takes out the substrate CW1 with chips from the substrate holding section 51 and transports it to the first buffer section 41 . Next, the first substrate transfer arm 31 of the first processing station 3 takes out the chip-attached substrate CW1 from the first buffer section 41 and transfers it to the inspection section 36 .

Next, the inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad (step S105). The inspection unit 36 transmits inspection results to the control unit 9 . The control unit 9 checks whether there is a defect (step S106). The control unit 9 performs control to sort the transfer destination of the substrate CW1 with chips between the annealing unit 39 and the chip peeling unit 37 according to the inspection result by the inspection unit 36 .

When there is a defect in the bonding state of the chip CP1 (step S106, NO), the destination of the chip-attached substrate CW1 is the chip peeling section 37. The first substrate transport arm 31 takes out the substrate CW1 with chips from the inspection section 36 and transports it to the chip peeling section 37 . Next, the chip peeling unit 37 peels off the chip CP1, which was in a defective bonding state, from the substrate W1 (step S107). After that, the first substrate transport arm 31 takes out the substrate CW1 with chips from the chip peeling section 37 and transports it to the rework section 38 . Next, the rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off (step S108). After that, the first substrate transfer arm 31 takes out the chip-attached substrate CW1 from the rework section 38 and transfers it to the chip bonding section 6 .

Next, the chip bonding unit 6 either bonds the chip CP1 again to the bonding region where the chip CP1 has been peeled off, or the dummy chip DC1 prepared separately from the chip CP1 without bonding the chip CP1 again. (see FIG. 8) are pasted together (step S109). Unlike chip CP1, dummy chip DC1 does not have a device, that is, an electric circuit. For example, the dummy chip DC1 consists of only a silicon wafer, a compound semiconductor wafer, or a glass substrate. Note that the chip bonding unit 6 may bond neither the chip CP1 nor the dummy chip DC1, or bond anything on the bonding region from which the chip CP1 has been peeled off.

When the chip CP1 is separated from the substrate W1, the device W1b on the substrate W1 may be damaged. Bonding the chip CP1 again to the damaged device W1b is a waste of the chip CP1. Waste of the chip CP1 can be prevented by not bonding the chip CP1 to the damaged device W1b. This effect is obtained even when nothing is attached to the damaged device W1b.

Note that when the substrate W1 does not have the device W1b as shown in FIG. 17A, it is preferable to bond the chip CP1 again to the bonding region from which the chip CP1 has been peeled off. This is because if the chip CP1 is not bonded again (including the case that the dummy chip DC1 is bonded again without bonding the chip CP1 again), the device W3b on the substrate W3 shown in FIG. 17D is wasted. .

As described above, the chip bonding unit 6 bonds the chip CP1 again or bonds the dummy chip DC1 to the bonding region from which the chip CP1 has been peeled off (step S109). In this case, unlike the case where nothing is bonded to the bonding area from which the chip CP1 has been peeled off, it is possible to prevent the substrate CW1 with the chip from being subjected to post-processing while leaving a space for mounting the chip CP1. The quality of post-processing can be improved. Uniform processing is possible, for example when grinding or polishing.

After step S<b>109 , the first substrate transfer arm 31 of the first processing station 3 takes out the chip-attached substrate CW<b>1 from the chip bonding section 6 and transfers it to the inspection section 36 . After that, the processing after step S105 is performed again. After step S<b>109 , the first substrate transfer arm 31 may take out the chip-attached substrate CW<b>1 from the chip bonding section 6 and transfer it to the annealing section 39 . After that, the processing after step S110 is performed.

On the other hand, if there is no defect in the bonded state of all the chips CP1 (step S106, YES), the annealing unit 39 is the transfer destination of the substrate CW1 with chips. The first substrate transfer arm 31 takes out the chip-attached substrate CW1 from the inspection section 36 and transfers it to the annealing section 39 . Next, the annealing section 39 heats the substrate CW1 with chips (step S110). The heat treatment improves the bonding strength between the chip CP1 and the substrate W1.

After that, the first substrate transfer arm 31 takes out the substrate CW1 with chips from the annealing section 39 and places it on the substrate mounting section 24 of the loading/unloading station 2 . Finally, the third substrate transfer arm 22 of the loading/unloading station 2 takes out the substrate CW1 with chips from the substrate mounting section 24 and stores it in the cassette C2. The chip-equipped substrate CW1 is unloaded from the substrate processing apparatus 1 while being accommodated in the cassette C2.

After step S104, the first frame transfer arm 32 of the first processing station 3 takes out the used frame FR1 from the chip bonding section 6 and places it on the frame mounting section 25 of the loading/unloading station 2. Next, the third frame transfer arm 23 of the loading/unloading station 2 takes out the used frame FR1 from the frame mounting section 25 and stores it in the cassette C4.

Next, an example of the first frame transfer arm 32 of the first processing station 3 will be described with reference to FIG. The first frame transport arm 32 has a pair of guide rails 321 on which the frame FR1 is placed, a gripping portion 322 that grips the frame FR1, and a driving portion 323 that moves the gripping portion 322 in the longitudinal direction of the pair of guide rails 321. .

The third frame transfer arm 23 of the loading/unloading station 2 and the second frame transfer arm 44 of the interface block 4 may be configured similarly to the first frame transfer arm 32 of the first processing station 3. a pair of guide rails on which the frame FR1 is placed, a gripping portion that grips the frame FR1, and a driving portion that moves the gripping portion in the longitudinal direction of the pair of guide rails.

Each of the pair of guide rails 321 has an L-shaped cross section and includes a horizontal plate 321a and a vertical plate 321b. When viewed from above, a pair of vertical plates 321b are arranged to sandwich the frame FR1, and restrict movement of the frame FR1 in a direction perpendicular to the vertical plates 321b. The frame FR1 is placed on a pair of horizontal plates 321a.

The first frame transfer arm 32 has a pair of guide rails 321 in addition to the grip portion 322, so that the frame FR1 can be stably supported. Further, the driving section 323 moves the gripping section 322 in the longitudinal direction of the pair of guide rails 321, so that the frame FR1 can be smoothly transferred to and from a desired device (for example, the tip cleaning section 33).

As shown in FIG. 4, the tip cleaning section 33 may have a pair of guide rails 338 . By continuously arranging the pair of guide rails 338 and the pair of guide rails 321, the frame FR1 can be transferred smoothly. The pair of guide rails 338 may be horizontally and vertically movable.

Each of the pair of guide rails 338 has an L-shaped cross section and includes a horizontal plate 338a and a vertical plate 338b. When viewed from above, a pair of vertical plates 338b are arranged to sandwich the frame FR1 and restrict movement of the frame FR1 in a direction perpendicular to the vertical plates 338b. The frame FR1 is placed on a pair of horizontal plates 338a.

The tip cleaning section 33 may have an internal transport section 339 . As shown in FIG. 4B, inside the chip cleaning section 33, the internal transport section 339 holds and transports the frame FR1 from above. The internal transport section 339 transports the frame FR1 between the pair of guide rails 338 and the frame holding section 332, which will be described later.

The internal transport section 339 has, for example, a plurality of arms 339a. When viewed from above, each of the plurality of arms 339a traverses the opening of the frame FR1, and both ends in the longitudinal direction attract and transport the frame FR1 from above. The internal transport section 339 is capable of horizontal (both X-axis and Y-axis) and vertical movement.

Next, an example of the tip cleaning section 33 will be described with reference to FIGS. 5 and 6. FIG. The chip cleaning section 33 has, for example, a chip holding section 331 and a frame holding section 332 . The chip holding part 331 horizontally holds the plurality of chips CP1 from below via the tape TP1. When the later-described expanding section 333 expands the tape TP1 radially, the chip holding section 331 slidably mounts the tape TP1. Note that the chip holding portion 331 may have a vacuum chuck mechanism to fix the tape TP1.

The frame holding portion 332 horizontally holds the frame FR1 from below. The frame holder 332 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1. A rotation drive unit 334, which will be described later, rotates the frame holding unit 332, thereby rotating the plurality of chips CP1 together with the frame FR1.

The tip cleaning section 33 may have an expanding section 333 . As shown in FIG. 6, the expanding section 333 widens the interval between the adjacent chips CP1 by radially expanding the tape TP1. For example, the expanding section 333 radially expands the tape TP1 by raising the chip holding section 331 relative to the frame holding section 332 . By widening the interval between the adjacent chips CP1, the side surfaces of the chips CP1 can be efficiently cleaned.

The tip cleaning section 33 may have a rotary drive section 334 , a nozzle 335 and a cup 336 . The rotation driving unit 334 rotates the frame holding unit 332 to rotate the plurality of chips CP1 together with the frame FR1. The rotation driving section 334 rotates the chip holding section 331 together with the frame holding section 332 . The nozzle 335 supplies cleaning liquid to the multiple chips CP1. The cleaning liquid is a chemical liquid, a rinse liquid, or the like. The rinse liquid is pure water such as DIW (deionized water). The nozzle 335 may move in a direction perpendicular to the rotation centerline of the tip holder 331 or the like. A cup 336 collects the cleaning fluid.

The tip cleaning section 33 may have a cleaning head 337 . The cleaning head 337 is a brush, sponge, or the like, and scrubs and cleans the chips CP1. The cleaning head 337 may apply ultrasonic waves to the liquid film formed between the plurality of chips CP1. The liquid film is formed by supplying the cleaning liquid from the nozzle 335 .

Next, an example of the second processing station 5 will be described with reference to FIG. The second processing station 5 includes a substrate holding section 51, a chip holding section 52, a pickup section 53, and a mounting section 54, as described above.

The substrate holding part 51 holds the substrate W1. The substrate holding unit 51 holds the substrate W1 horizontally, for example, with the main surface W1c of the substrate W1 facing upward. The main surface W1c of the substrate W1 may have a device W1b for each bonding region, and the substrate holding section 51 may hold the substrate W1 horizontally with the device W1b facing upward.

The chip holding unit 52 holds the plurality of chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1. The chip holding unit 52 horizontally holds the plurality of chips CP1, for example, with the devices CP1b of the plurality of chips CP1 facing upward.

The pickup unit 53 separates the plurality of chips CP1 individually from the tape TP1. The pickup section 53 has a first suction head 531 . The first suction head 531 sucks the chip CP1 from the side opposite to the tape TP1. For example, the first suction head 531 sucks the chip CP1 from above.

The first suction head 531 removes the chip CP1 from the tape TP1 by moving upward while sucking the chip CP1. The first suction head 531 may be upside down. By turning the chip CP1 upside down, the chip CP1 can be mounted on the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1.

The tip holding part 52 may have a push-up pin 532 . The push-up pin 532 pushes up the chip CP1 from below via the tape TP1. The first suction head 531 sucks the chip CP<b>1 pushed up by the push-up pin 532 . Thereby, it is possible to prevent the adjacent chips CP1 from rubbing against each other.

Although not shown, the pick-up section 53 may have an expanding section similar to the tip cleaning section 33 . The expanding section widens the interval between adjacent chips CP1 by radially expanding the tape TP1. Thereby, it is possible to prevent the adjacent chips CP1 from rubbing against each other.

The mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the device CP1b of the chip CP1 facing the substrate W1. The mount section 54 has a second suction head 541 . The second suction head 541 sucks the upside-down chip CP1 from above and moves downward in that state to mount the chip CP1 on the main surface W1c of the substrate W1.

In this embodiment, the second suction head 541 of the mount section 54 directly receives the chip CP1 from the first suction head 531 of the pickup section 53, but it may be received via a transport section (not shown). The transport unit transports the chip CP<b>1 from the pickup unit 53 to the mount unit 54 . The transport section may turn the chip CP1 upside down.

As shown in FIG. 7, when the main surface W1c of the substrate W1 has a device W1b for each bonding region, the control section 9 may have an information acquisition section 93. The information acquisition unit 93 acquires information indicating whether the state of the device W1b is good or bad for each bonding region. Whether the device W1b is in good condition or not is inspected by an external inspection device. The inspection device performs, for example, an appearance inspection or an operation inspection of the device W1b, and transmits the inspection result to the control unit 9. FIG.

Under the control of the control unit 9, the chip bonding unit 6 bonds the chip CP1 to the device W1b in good condition, and bonds the dummy chip DC1 (see FIG. 8) to the device W1b in poor condition. match. Note that the chip bonding unit 6 may bond neither the chip CP1 nor the dummy chip DC1, or bond anything on the device W1b in the defective state.

Bonding the chip CP1 to the device W1b in a bad state is a waste of the chip CP1. Waste of the chip CP1 can be prevented by not bonding the chip CP1 to the device W1b in a defective state. This effect can be obtained even when nothing is attached to the device W1b which is in a bad state.

Also, if the dummy chip DC1 is bonded without bonding the chip CP1 to the device W1b that is in a defective state, unlike the case where nothing is bonded, the space for mounting the chip CP1 remains empty. The attached substrate CW1 can be prevented from being subjected to post-processing, and the quality of the post-processing can be improved.

Next, an example of the inspection unit 36 will be described with reference to FIG. The inspection unit 36 inspects whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad. The inspection items include at least one of presence/absence of foreign matter such as air bubbles and presence/absence of misalignment. The inspection unit 36 has, for example, a substrate holding unit 361 and an inspection head 362 .

The substrate holding part 361 holds the chip-equipped substrate CW1. The substrate holder 361 can move in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holder 361 may be rotatable around the vertical axis. The inspection position can be changed by moving or rotating the substrate holder 361 . The substrate holder 361 may be vertically movable.

The inspection head 362 has, for example, a CT scanner, an infrared scanner, a confocal laser scanner, an ultrasonic scanner, or the like, acquires an image of the interface between the chip CP1 and the substrate W1, and detects the presence or absence of air bubbles. Alternatively, the inspection head 362 may have a height measuring device such as a laser displacement gauge and detect the presence or absence of air bubbles by detecting the height of the chip CP1. If there is a bubble, the height of the chip CP1 increases by the thickness of the bubble.

Based on the information acquired by the inspection head 362, the inspection unit 36 determines whether the bonding state of each of the plurality of chips CP1 bonded to different bonding regions of the main surface W1c of the substrate W1 is good or bad. It may have a determination unit (not shown). The determination unit is composed of a computer. The determination unit may be part of the control unit 9 .

Next, an example of the chip peeling portion 37 will be described with reference to FIG. The chip peeling unit 37 peels off the chip CP1, which was found to be poorly bonded in the inspection by the inspection unit 36, from the substrate W1. The chip peeling section 37 has, for example, a substrate holding section 371 , a peeling head 372 , and a recovery box 373 .

The substrate holding part 371 holds the chip-equipped substrate CW1. The substrate holding part 371 can move in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holder 371 may be rotatable around the vertical axis. The peeling position can be changed by moving or rotating the substrate holder 371 . The substrate holder 371 may be vertically movable.

The stripping head 372 includes, for example, a suction head 372a. The suction head 372a sucks the chip CP1 from above and moves upward in this state to separate the chip CP1 from the substrate W1. The first suction head 531 may be movable not only in the vertical direction but also in the horizontal direction. The suction head 372 a drops the chips CP<b>1 separated from the substrate W<b>1 into the recovery box 373 .

Next, with reference to FIGS. 11 and 12, a modified example of the chip peeling portion 37 will be described. As shown in FIG. 11A, the separation head 372 may include a blade 372b in addition to the suction head 372a. The blade 372b separates the chip CP1 from the substrate W1 by being inserted into the interface between the chip CP1 and the substrate W1.

As shown in FIG. 11(B), the separation head 372 may include a heater 372c and a cooler 372d in addition to the suction head 372a. The heater 372c and the cooler 372d are provided inside the suction head 372a, form a temperature gradient in the chip CP1, and separate the chip CP1 from the substrate W1 by thermal stress.

The cooler 372d is arranged to surround the heater 372c. This can suppress lateral leakage of heat from the heater 372c, and can suppress heating of the chip CP1, which is not to be peeled off. Note that even if the arrangement of the cooler 372d and the heater 372c is reversed, it is possible to separate the chip CP1 from the substrate W1 by thermal stress. Note that the cooler 372d may be provided in the substrate holder 371 (see FIG. 10) instead of being provided inside the suction head 372a.

As shown in FIG. 12(A), the stripping head 372 may include a tubular seal 372e and a nozzle 372f in addition to the suction head 372a. The seal 372e collects a peeling liquid that reduces the bonding strength between the chip CP1 and the substrate W1 around the chip CP1 to be peeled. The nozzle 372f discharges the stripping liquid inside the seal 372e.

The stripper penetrates into the interface between the chip CP1 and the substrate W1 to be stripped, and reduces the bonding strength between the chip CP1 and the substrate W1. The stripping liquid contains, for example, pure water such as DIW. Pure water reduces the bonding strength between the chip CP1 and the substrate W1 by hydrolysis. The stripping solution may contain pure water and components other than pure water.

The seal 372e is pressed against the main surface W1c of the substrate W1. The material of the seal 372e is, for example, resin or rubber. The inner peripheral surface of the seal 372e may be a tapered surface that tapers downward. The stripping liquid can be guided inward by the tapered surface.

The nozzle 372f may suck up the stripping liquid accumulated inside the seal 372e before separating the seal 372e from the substrate W1. The nozzle 372f for discharging the stripping liquid and the nozzle 372f for sucking the stripping liquid may be provided separately.

As shown in FIG. 12(B), the chip peeling section 37 may have a plurality of push-up pins 374 inside the substrate holding section 371 . The plurality of push-up pins 374 are raised and lowered individually. With the substrate holding part 371 sucking the substrate CW1 with chips, the push-up pins 374 locally push up the substrate W1, so that the substrate W1 is locally bent and deformed, and the chips CP1 are separated from the substrate W1.

Next, an example of the rework section 38 will be described with reference to FIG. The rework unit 38 selectively processes the bonding region from which the chip CP1 has been peeled off by the chip peeling unit 37 on the main surface W1c of the substrate W1. The rework section 38 has, for example, a substrate holding section 381 and a processing head 382 .

The substrate holding part 381 holds the chip-equipped substrate CW1. The substrate holder 381 can move in the horizontal direction (both the X-axis direction and the Y-axis direction). The substrate holder 381 may be rotatable around the vertical axis. The processing position can be changed by moving or rotating the substrate holder 381 . The substrate holder 381 may be vertically movable.

The processing head 382 has, for example, a plasma head, and selectively supplies plasma to the bonding area where the chip CP1 is separated from the plasma head. The processing head 382 may have a cover surrounding the plasma head in order to narrow the plasma supply area, and the pressure inside the cover may be reduced.

The processing head 382 may have a cleaning head, and selectively supplies water to the bonding region where the chip CP1 is separated from the cleaning head. The cleaning head may supply water in either liquid or gaseous form, preferably in gaseous form. The treatment head 382 may have a cover surrounding the cleaning head to restrict the water supply area and may also have a vacuum inside the cover.

The processing head 382 may be movable in the horizontal direction (both the X-axis direction and the Y-axis direction). By moving the processing head 382, the processing position can be changed. The processing head 382 may be vertically movable.

Next, with reference to FIG. 14, the substrate processing apparatus 1 according to the first modified example will be described mainly about the differences from the above-described embodiment. In the substrate processing apparatus 1 , the second processing station 5 has an inspection section 36 instead of the first processing station 3 . It is also possible to simultaneously perform the bonding of the substrate W1 and the chip CP1 (step S104) and the inspection of the bonding state (step S105). The second processing station 5 may also include a chip peeling section 37 in addition to the inspection section 36 instead of the first processing station 3 .

Next, with reference to FIGS. 15 and 16, the substrate processing apparatus 1 according to the second modified example will be described mainly with respect to differences from the above embodiment and the first modified example. As shown in FIGS. 16A to 16D, the substrate processing apparatus 1 attaches a second chip different from the chip CP1 to a second bonding region different from the bonding region of the main surface W1c of the substrate W1. A substrate CW1 with a chip is manufactured by laminating CP2. The substrate with chips CW1 includes a substrate W1, a plurality of chips CP1 bonded to the substrate W1, and a plurality of second chips CP2 bonded to the substrate W1.

A plurality of second chips CP2 shown in FIG. 16(B) are loaded into the substrate processing apparatus 1 . A plurality of second chips CP2 are adhered to a second tape TP2, and the outer periphery of the second tape TP2 is attached to the second frame FR2. A plurality of second chips CP2 are arranged in the opening of the second frame FR2. The plurality of second chips CP2 can be obtained, for example, by dicing the substrate while the substrate is adhered to the second tape TP2.

The second chip CP2 has a base substrate CP2a and a device CP2b formed on the base substrate CP2a. The underlying substrate CP2a is, for example, a silicon wafer, a compound semiconductor wafer, or a glass substrate. The device CP2b includes semiconductor elements, circuits, terminals, or the like. The device CP2b is arranged on the side opposite to the second tape TP2 with respect to the base substrate CP2a.

As shown in FIG. 16(C), the pickup unit 53 separates the plurality of second chips CP2 individually from the second tape TP2. After that, the second chip CP2 is turned upside down and then bonded to the substrate W1 as shown in FIG. 16(D). The device W1b of the substrate W1, the device CP1b of the chip CP1, and the device CP2b of the second chip CP2 are electrically connected. Thus, a chip-equipped substrate CW1 is obtained.

As shown in FIG. 15, the interface block 4 may include a third buffer section 45. The third buffer section 45 is adjacent to the transport area 30 of the first processing station 3 . The first buffer section 41 , the second buffer section 42 and the third buffer section 45 may be vertically stacked to reduce the footprint of the interface block 4 .

The third buffer unit 45 stores a plurality of second chips CP2 together with the second frame FR2. The third buffer unit 45 stores a plurality of second chips CP2 that have undergone pretreatment (for example, cleaning). As a result, the operating rate of the second processing station 5 can be improved, and the production efficiency of the substrates CW1 with chips can be improved.

The transportation and cleaning of the second chip CP2 are performed in the same manner as the transportation and cleaning of the chip CP1, so description thereof will be omitted. The device used for transporting and cleaning the second chip CP2 and the device used for transporting and cleaning the chip CP1 may be a common device or may be separate devices.

Also, since the pickup and mounting of the second chip CP2 are performed in the same manner as the pickup and mounting of the chip CP1, the description thereof will be omitted. The device used to pick up and mount the second chip CP2 and the device used to pick up and mount the chip CP1 may be a common device or may be separate devices.

Next, with reference to FIGS. 18 to 22, the substrate processing apparatus 1 according to the third modified example will be described mainly with respect to differences from the above embodiment, the first modified example, and the second modified example. As shown in FIGS. 19A to 19C, the substrate processing apparatus 1 peels off the chip CP1 protected by the protective film PF1 from the tape TP1, and then mounts the chip CP1 on the substrate W1. On the way, the substrate processing apparatus 1 removes the protective film PF1 from the chip CP1.

As shown in FIG. 20, the second processing station 5 includes a substrate holding section 51, a chip holding section 52, a pickup section 53, and a mounting section . The second processing station 5 also comprises a remover 55 (see FIG. 18). Hereinafter, the pickup section 53, the mounting section 54, and the removing section 55 will be described in this order.

The pickup unit 53 picks up the chips CP1 in a state in which the plurality of chips CP1 are attached to the frame FR1 via the tape TP1 and the protective film PF1 is formed on the first main surface CP1c of the chips CP1 opposite to the tape TP1. Peel off from tape TP1. The protective film PF1 covers the first main surface CP1c of the chip CP1.

The pickup section 53 has a first suction head 531 . The first suction head 531 suctions the chip CP1 via the protective film PF1. The protective film PF1 suppresses damage to the device CP1b by preventing contact between the first suction head 531 and the device CP1b of the chip CP1.

The first suction head 531 separates the chip CP1 from the tape TP1 by moving upward while sucking the chip CP1. At this time, the protective film PF1 is torn off and divided. Note that the protective film PF1 may be divided in advance by laser processing, blade processing, or the like.

The first suction head 531 may be capable of being turned upside down. The chip CP1 can be turned upside down, and the first main surface CP1c of the chip CP1 can face the substrate W1. Note that, as described above, a transporting unit (not shown) may transport the chip CP1 from the pickup unit 53 to the mounting unit 54, and the transporting unit may turn the chip CP1 upside down on the way.

The mounting unit 54 mounts the chip CP1 on the main surface W1c of the substrate W1 with the first main surface CP1c of the chip CP1 facing the substrate W1. The mount section 54 has a second suction head 541 . The second suction head 541 suctions the second main surface CP1d of the chip CP1. The second main surface CP1d is a surface opposite to the first main surface CP1c and is a surface separated from the tape TP1.

The second suction head 541 picks up the chip CP1 from above and moves downward in that state to mount the chip CP1 on the main surface W1c of the substrate W1. The protective film PF1 is removed in advance so that the chip CP1 and the substrate W1 are in contact with each other. The device CP1b of the chip CP1 and the device W1b of the substrate W1 are electrically connected.

According to this modification, the pickup unit 53 peels off the chip CP1 from the tape TP1 while the protective film PF1 covers the first main surface CP1c of the chip CP1. Therefore, contact between the pickup portion 53 and the chip CP1 can be prevented, and damage to the chip CP1 can be suppressed. This is particularly effective when the first main surface CP1c of the chip CP1 has the device CP1b.

After that, after removing the protective film PF1, the chip CP1 is bonded to the substrate W1 with the first main surface CP1c of the chip CP1 facing the substrate W1. By removing the protective film PF1 in advance, the chip CP1 can be brought into contact with the substrate W1, and the device CP1b of the chip CP1 and the device W1b of the substrate W1 can be electrically connected.

Next, an example of the removal unit 55 will be described with reference to FIG. As shown in FIG. 21A, the protective film PF1 may cover not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1. Although the details will be described later, the protective film PF1 is formed by coating and solidifying a liquid material for the protective film PF1 on a plurality of chips CP1 divided in advance by dicing, and is also formed in the gaps between the adjacent chips CP1. It is formed.

As shown in FIG. 21(B), the removal section 55 may have a first supply section 551 . The first supply unit 551 supplies the stripping liquid L1 for stripping the protective film PF1 from the chip CP1 to the protective film PF1. The peeling liquid L1 peels the protective film PF1 from the chip CP1, for example, without dissolving the protective film PF1. The protective film PF1 is peeled off from the chip CP1 in the form of a film.

For example, the first supply unit 551 has a storage tank for storing the stripping liquid L1, and the protective film PF1 is immersed in the stripping liquid L1 stored in the storage tank together with the chip CP1. At this time, for example, the second suction head 541 of the mount section 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the stripping liquid L1. Note that the suction head that holds the chip CP1 is not limited to the second suction head 541 of the mount section 54 .

As shown in FIG. 21(C), the peeling liquid L1 permeates into the protective film PF1 and reaches the interface between the protective film PF1 and the chip CP1, thereby peeling the protective film PF1 from the chip CP1. As a result, the particles PC attached to the chip CP1 before the protective film PF1 is formed are separated from the chip CP1 together with the protective film PF1.

The protective film PF1 preferably covers not only the first main surface CP1c of the chip CP1 but also the side surface CP1e of the chip CP1 in order to improve the removal efficiency of the particles PC. Particles PC adhering to side surface CP1e of chip CP1 can also be peeled off from chip CP1.

The stripping liquid L1 is appropriately selected according to the material of the protective film PF1, and is, for example, pure water such as DIW. The protective film PF1 is, for example, an organic film. Pure water can permeate the interior of the organic film. Although the material of the organic film is not particularly limited, it is, for example, an acrylic resin or an epoxy resin, preferably an acrylic resin. The pure water may be heated to improve the peelability between the protective film PF1 and the chip CP1.

As shown in FIG. 21(D), the removal section 55 may have a second supply section 552 . The second supply unit 552 supplies the stripping liquid L1 to the protective film PF1 by the first supply unit 551, and then supplies the dissolving liquid L2 for dissolving the protective film PF1.

For example, the second supply unit 552 has a reservoir for storing the solution L2, and the protective film PF1 is immersed in the solution L2 stored in the reservoir together with the chip CP1. At this time, for example, the second suction head 541 of the mount section 54 holds the chip CP1 with the first main surface CP1c of the chip CP1 facing downward so that the protective film PF1 is easily immersed in the solution L2. Note that the suction head that holds the chip CP1 is not limited to the second suction head 541 of the mount section 54 .

For example, an alkaline developer is used as the dissolving liquid L2. When an alkaline developer is used, the zeta potential of the same polarity can be generated in the chips CP1 and the particles PC, and the reattachment of the particles PC to the chips CP1 can be suppressed. Note that when an alkaline developer is used as the dissolving liquid L2, an alkaline developing liquid having a concentration lower than that of the dissolving liquid L2 may be used as the stripping liquid L1.

The storage tank for storing the dissolving liquid L2 and the storage tank for storing the stripping liquid L1 may be common. Moreover, although the removal unit 55 has both the first supply unit 551 and the second supply unit 552 , it may have only the first supply unit 551 or only the second supply unit 552 . The removal unit 55 may have a drying unit that dries the chip CP1. If the removing unit 55 does not use liquid such as the stripping liquid L1 or the dissolving liquid L2, the drying unit is unnecessary.

Next, an example of the application unit 70 will be described with reference to FIGS. 18 and 22. FIG. The coating section 70 is provided in the first processing station 3 as shown in FIG. The coating section 70 is adjacent to the transport area 30 . The plurality of chips CP<b>1 are cleaned by the chip cleaning section 33 , processed by the coating section 70 , and then transported to the chip bonding section 6 by the first frame transport arm 32 . Although the application unit 70 and the tip cleaning unit 33 are provided separately in this modification, the application unit 70 may have the function of the tip cleaning unit 33 .

As shown in FIG. 22, the application section 70 has, for example, a tip holding section 701 and a frame holding section 702. The chip holding unit 701 horizontally holds the plurality of chips CP1 from below via the tape TP1. The chip holding portion 701 slidably mounts the tape TP1. Note that the tip holding unit 701 may have a vacuum chuck mechanism to fix the tape TP1.

The frame holding portion 702 horizontally holds the frame FR1 from below. The frame holder 702 has a vacuum chuck mechanism or a mechanical chuck mechanism and fixes the frame FR1. A rotation drive unit 704, which will be described later, rotates the frame holding unit 702, thereby rotating the plurality of chips CP1 together with the frame FR1.

The application unit 70 has a rotary drive unit 704 , a nozzle 705 and a cup 706 . The rotation driving unit 704 rotates the frame holding unit 702 to rotate the plurality of chips CP1 together with the frame FR1. The rotation driving section 704 rotates the tip holding section 701 as well as the frame holding section 702 . The nozzle 705 supplies the liquid material L3 of the protective film PF1 to the plurality of chips CP1. Cup 706 collects liquid material L3.

The applicator 70 forms the protective film PF1 by applying and solidifying the liquid material of the protective film PF1 on the plurality of chips CP1 divided in advance by dicing. The protective film PF1 can also be formed in the gap between the adjacent chips CP1, and the protective film PF1 can also be formed on the side surface CP1e of the chip CP1. In addition, in this specification, "hardening" includes "hardening." “Curing” means that molecules are linked together to form a polymer (for example, cross-linking or polymerization).

With the plurality of chips CP1 attached to the frame FR1 via the tape TP1, the coating unit 70 applies the liquid material L3 of the protective film PF1 to the chips CP1 from the opposite side of the tape TP1 with respect to the chips CP1. Then, the protective film PF1 is formed. Since the plurality of chips CP1 are adhered to the tape TP1, it is easy to handle.

The liquid material L3 is supplied near the rotation center line of the plurality of chips CP1, spreads radially in a direction away from the rotation center line due to centrifugal force, and forms a liquid film. The protective film PF1 is formed by solidifying the liquid film of the liquid material L3. After forming the liquid film, the rotation of the chip CP1 may be stopped before the liquid film is solidified.

The liquid material L3 contains, for example, a volatile component, and is solidified by volatilization of the volatile component. The particles PC can be peeled off from the chip CP1 by utilizing the volume shrinkage associated with volatilization of the volatile components. The liquid material L3 may contain acrylic resin. The particles PC can also be separated from the chip CP1 by curing shrinkage of the acrylic resin.

Although the embodiments and the like of the substrate processing apparatus and the substrate processing method according to the present disclosure have been described above, the present disclosure is not limited to the above embodiments and the like. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope of the claims. These also naturally belong to the technical scope of the present disclosure.

This application claims priority based on Japanese Patent Application No. 2022-011239 filed with the Japan Patent Office on January 27, 2022, and the entire contents of Japanese Patent Application No. 2022-011239 are incorporated into this application. .

1 Substrate Processing Apparatus 6 Chip Bonding Part 53 Pickup Part 54 Mounting Part 55 Removal Part CP1 Chip CP1c First Main Surface FR1 Frame TP1 Tape PF1 Protective Film W1 Substrate W1c Main Surface

Claims (17)

1. a pick-up unit that removes the chips from the tape in a state in which a plurality of chips are attached to a frame via a tape and a protective film is formed on a first main surface of the chips opposite to the tape;
   a removal unit that removes the protective film from the chip after the chip is separated from the tape by the pickup unit;
   a mounting unit that mounts the chip on the substrate with the first main surface of the chip facing the substrate after the protective film is removed by the removing unit;
   A substrate processing apparatus comprising:
2. wherein said pickup section includes a first suction head that suctions said chip via said protective film, and said mounting section includes a second suction head that suctions a second main surface of said chip separated from said tape. Item 1. The substrate processing apparatus according to item 1.
3. 3. The substrate processing apparatus according to claim 1, wherein said removal section includes a first supply section that supplies a stripping liquid for stripping said protective film from said chip to said protective film.
4. The substrate processing apparatus according to claim 3, wherein the stripping liquid is pure water.
5. 4. The removing section according to claim 3, wherein the removal section includes a second supply section that supplies a dissolving liquid for dissolving the protective film after supplying the stripping liquid from the first supply section to the protective film. Substrate processing equipment.
6. 3. The substrate processing apparatus according to claim 1, further comprising a coating unit that forms the protective film by coating and solidifying the liquid material for the protective film on the plurality of chips divided in advance by dicing. .
7. The application unit applies the liquid material of the protective film to the chips from the side opposite to the tape with respect to the chips in a state where the chips are attached to the frame via the tape. 7. The substrate processing apparatus according to claim 6, wherein said protective film is formed by solidifying said protective film.
8. a chip bonding section having the pickup section, the removing section, and the mounting section;
   a transport area adjacent to the coating unit and the chip bonding unit; and a first frame transport arm that holds the frame in the transport area and transports the plurality of chips together with the frame,
   7. The substrate processing apparatus according to claim 6, wherein said first frame transport arm transports said plurality of chips together with said frame from said coating section to said chip bonding section.
9. The chip bonding section includes an interface section adjacent to the transfer area, and a second processing station disposed on the opposite side of the interface section to the transfer area,
   The second processing station includes a substrate holding section that holds the substrate, a chip holding section that holds the plurality of chips while the plurality of chips are mounted on the frame via the tape, and the pickup section. , the removing section, and the mounting section,
   The interface section includes a first buffer section that stores the substrate, a second substrate transfer arm that transfers the substrate from the first buffer section to the substrate holding section, and a first frame transfer arm that transfers the substrate together with the frame. and a second frame transport arm for transporting the plurality of chips together with the frame from the second buffer to the chip holding part. A substrate processing apparatus as described.
10. The second processing station includes an inspection unit for inspecting whether the bonding state of each of the plurality of chips bonded to different bonding regions on the main surface of the substrate is good or bad, and an inspection by the inspection unit. 10. The substrate processing apparatus according to claim 9, further comprising a chip peeling unit for peeling said chip whose bonding state is defective from said substrate.
11. an inspection unit that inspects whether the bonding state of each of the plurality of chips bonded to different bonding regions on the main surface of the substrate is good or bad; a chip peeling unit for peeling the chip from the substrate,
    9. The substrate processing apparatus according to claim 8, wherein said inspection section and said chip peeling section are adjacent to said transfer area.
12. removing the chips from the tape in a state in which a plurality of chips are attached to a frame via tape and a protective film is formed on a first main surface of the chips opposite to the tape;
    removing the protective film from the chip after peeling the chip from the tape;
    After removing the protective film, mounting the chip on the substrate with the first main surface of the chip facing the substrate;
    A substrate processing method comprising:
13. 13. The substrate processing method according to claim 12, wherein removing the protective film includes supplying a peeling liquid for peeling the protective film from the chip to the protective film.
14. The substrate processing method according to claim 13, wherein the stripping liquid is pure water.
15. 15. The method according to claim 13 or 14, wherein removing the protective film includes supplying the stripping solution to the protective film and then supplying the protective film with a dissolving solution for dissolving the protective film. The substrate processing method described.
16. 15. The method according to any one of claims 12 to 14, comprising forming the protective film by coating and solidifying the liquid material of the protective film on the plurality of chips divided in advance by dicing. substrate processing method.
17. Forming the protective film is performed by applying the liquid material of the protective film from the side opposite to the tape with respect to the chips in a state in which the plurality of chips are attached to the frame via the tape. 17. The substrate processing method according to claim 16, comprising forming the protective film by coating the chip and solidifying it.

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