WO2023139990A1 - ニューラルネットワーク回路およびニューラルネットワーク演算方法 - Google Patents

ニューラルネットワーク回路およびニューラルネットワーク演算方法 Download PDF

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WO2023139990A1
WO2023139990A1 PCT/JP2022/046214 JP2022046214W WO2023139990A1 WO 2023139990 A1 WO2023139990 A1 WO 2023139990A1 JP 2022046214 W JP2022046214 W JP 2022046214W WO 2023139990 A1 WO2023139990 A1 WO 2023139990A1
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circuit
core
quantization
neural network
memory
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賢治 渡邊
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Leap Mind Inc
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Leap Mind Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present invention relates to a neural network circuit and a neural network operation method.
  • This application claims priority based on Japanese Patent Application No. 2022-008692 filed in Japan on January 24, 2022, the content of which is incorporated herein.
  • CNN convolutional neural networks
  • a convolutional neural network has a multilayer structure having convolution layers and pooling layers, and requires a large number of operations such as convolution operations.
  • Various calculation methods have been devised for speeding up calculation by a convolutional neural network (Patent Document 1, etc.).
  • the object of the present invention is to provide a high-performance neural network circuit and neural network operation method that can be incorporated into embedded devices such as IoT devices.
  • a neural network circuit has a plurality of neural network operation cores each having a convolution operation circuit that performs a convolution operation and a quantization operation circuit that performs a quantization operation, and the plurality of neural network operation cores are connected so as to be capable of inputting and outputting data.
  • a neural network operation method is a neural network operation method using a first neural network operation core and a second neural network operation core, wherein output data of the first neural network operation core is switched between loopback data flow for looping back to the first neural network and bypass data flow for bypassing the second neural network operation core.
  • the neural network circuit and neural network operation method of the present invention can be incorporated into embedded devices such as IoT devices and have high performance.
  • FIG. 2 illustrates a convolutional neural network
  • FIG. 4 is a diagram for explaining convolution operations performed by a convolution layer
  • FIG. 4 is a diagram for explaining expansion of data in a convolution operation
  • 1 is a diagram showing the overall configuration of a neural network circuit according to a first embodiment
  • FIG. It is a figure which shows the whole structure of NN arithmetic core.
  • 4 is a timing chart showing an operation example of the same NN arithmetic core
  • 4 is a timing chart showing another operation example of the same NN operation core
  • It is a figure which shows NN arithmetic multi-core.
  • It is a timing chart showing an operation example of the same NN calculation multi-core.
  • FIG. 4 is a timing chart showing another operation example of the same NN arithmetic multi-core; 4 is a timing chart showing another operation example of the same NN arithmetic multi-core; 3 is an internal block diagram of the DMAC of the same neural network circuit; FIG. 4 is a state transition diagram of a control circuit of the same DMAC; FIG. 4 is an internal block diagram of a convolution operation circuit of the same neural network circuit; FIG. FIG. 4 is an internal block diagram of a multiplier of the convolution arithmetic circuit; 3 is an internal block diagram of a sum-of-products operation unit of the same multiplier; FIG. FIG.
  • FIG. 4 is an internal block diagram of an accumulator circuit of the same convolution arithmetic circuit; It is an internal block diagram of the accumulator unit of the same accumulator circuit. 4 is an internal block diagram of a quantization arithmetic circuit of the same neural network circuit; FIG. 3 is an internal block diagram of a vector operation circuit and a quantization circuit of the same quantization operation circuit; FIG. 4 is a block diagram of an arithmetic unit; FIG. 4 is an internal block diagram of a vector quantization unit of the same quantization circuit; FIG. It is a figure explaining control of the same neural network circuit by a semaphore. It is a timing chart of the first data flow. It is a timing chart of the second data flow.
  • FIG. 8 is an internal block diagram of a convolution circuit of the neural network circuit according to the second embodiment
  • FIG. 4 is an internal block diagram of a multiplier of the convolution arithmetic circuit
  • FIG. 4 is an internal block diagram of a sum-of-products operation unit array of the same multiplier
  • FIG. 4 is an internal block diagram of a sum-of-products operation unit of the same sum-of-products operation unit array
  • It is a figure which shows the whole structure of the neural-network circuit which concerns on 3rd embodiment.
  • 4 is an internal block diagram of the first DMAC of the same neural network circuit;
  • FIG. 8 is an internal block diagram of a convolution circuit of the neural network circuit according to the second embodiment
  • FIG. 4 is an internal block diagram of a multiplier of the convolution arithmetic circuit
  • FIG. 4 is an internal block diagram of a sum-of-products operation unit array of the same multiplier
  • FIG. 4 is an internal block diagram of a sum-of-products operation
  • FIG. 4 is a timing chart showing the operation of a clock control unit such as the first DMAC; 4 is an internal block diagram of a convolution operation circuit of the same neural network circuit; FIG. 4 is an internal block diagram of a quantization arithmetic circuit of the same neural network circuit; FIG. It is a figure which shows the whole structure of the neural-network circuit which concerns on 4th embodiment.
  • FIG. 1 is a diagram showing a convolutional neural network 200 (hereinafter referred to as "CNN 200").
  • CNN 200 convolutional neural network
  • the computations performed by the neural network circuit 100 (hereinafter referred to as "NN circuit 100") according to the first embodiment are at least part of the trained CNN 200 used during inference.
  • the CNN 200 is a multi-layered network including a convolution layer 210 that performs convolution operations, a quantization operation layer 220 that performs quantization operations, and an output layer 230 .
  • convolutional layers 210 and quantization operation layers 220 are interleaved.
  • CNN200 is a model widely used for image recognition and moving image recognition.
  • the CNN 200 may further have layers with other functions, such as fully connected layers.
  • FIG. 2 is a diagram for explaining the convolution operation performed by the convolution layer 210.
  • the convolution layer 210 performs a convolution operation on input data a using weight w.
  • the convolution layer 210 performs a sum-of-products operation with input data a and weight w as inputs.
  • Input data a (also called activation data or feature map) to the convolution layer 210 is multidimensional data such as image data.
  • the input data a is a three-dimensional tensor consisting of elements (x, y, c).
  • the convolution layer 210 of the CNN 200 performs a convolution operation on low-bit input data a.
  • the elements of the input data a are 2-bit unsigned integers (0, 1, 2, 3).
  • Elements of input data a may be, for example, 4-bit or 8-bit unsigned integers.
  • the CNN 200 may further have an input layer that performs type conversion and quantization before the convolutional layer 210.
  • the weights w (also called filters or kernels) of the convolutional layer 210 are multidimensional data whose elements are learnable parameters.
  • the weight w is a 4-dimensional tensor consisting of elements (i,j,c,d).
  • the weight w has d three-dimensional tensors (hereinafter referred to as “weight wo”) each having elements (i, j, c).
  • the weight w in the learned CNN 200 is learned data.
  • Convolutional layer 210 of CNN 200 performs a convolution operation using low-bit weights w.
  • the elements of the weight w are 1-bit signed integers (0,1), where the value '0' represents +1 and the value '1' represents -1.
  • the convolution layer 210 performs the convolution operation shown in Equation 1 and outputs output data f.
  • s indicates stride.
  • the area indicated by the dotted line in FIG. 2 indicates one of the areas ao (hereinafter referred to as “applied area ao”) to which the weight wo is applied to the input data a.
  • Elements of the application area ao are represented by (x+i, y+j, c).
  • the quantization operation layer 220 performs quantization and the like on the convolution operation output from the convolution layer 210 .
  • the quantization operation layer 220 has a pooling layer 221 , a batch normalization layer 222 , an activation function layer 223 and a quantization layer 224 .
  • the pooling layer 221 compresses the output data f of the convolution layer 210 by performing calculations such as average pooling (formula 2) and MAX pooling (formula 3) on the convolutional calculation output data f output by the convolution layer 210 .
  • u indicates the input tensor
  • v indicates the output tensor
  • T indicates the size of the pooling region.
  • max is a function that outputs the maximum value of u for combinations of i and j contained in T.
  • the Batch normalization layer 222 normalizes the data distribution of the output data of the quantization operation layer 220 and the pooling layer 221 by, for example, the operation shown in Equation 4.
  • Equation 4 u denotes the input tensor, v the output tensor, ⁇ the scale, and ⁇ the bias.
  • ⁇ and ⁇ are trained constant vectors.
  • the activation function layer 223 computes an activation function such as ReLU (equation 5) on the outputs of the quantization computation layer 220, the pooling layer 221, and the batch normalization layer 222.
  • ReLU activation function
  • u is the input tensor
  • v is the output tensor.
  • max is a function that outputs the largest numerical value among the arguments.
  • the quantization layer 224 quantizes the output of the pooling layer 221 and the activation function layer 223 based on the quantization parameter, as shown in Equation 6, for example.
  • the quantization shown in Equation 6 reduces the input tensor u to 2 bits.
  • q(c) is the vector of quantization parameters.
  • q(c) is a trained constant vector.
  • the inequality sign “ ⁇ ” in Equation 6 may be “ ⁇ ”.
  • the output layer 230 is a layer that outputs the results of the CNN 200 using the identity function, softmax function, and the like.
  • a layer preceding the output layer 230 may be the convolution layer 210 or the quantization operation layer 220 .
  • the quantized output data of the quantization layer 224 is input to the convolution layer 210, so the convolution operation load of the convolution layer 210 is small compared to other convolutional neural networks that do not perform quantization.
  • the NN circuit 100 divides the input data for the convolution operation (Equation 1) of the convolution layer 210 into partial tensors and performs the operation.
  • the method of division into partial tensors and the number of divisions are not particularly limited.
  • a partial tensor is formed, for example, by splitting the input data a(x+i, y+j, c) into a(x+i, y+j, co).
  • the NN circuit 100 can also perform computation without dividing the input data for the convolution computation (equation 1) of the convolution layer 210 .
  • the variable c in Equation 1 is divided into blocks of size Bc as shown in Equation 7.
  • the variable d in Equation 1 is divided into blocks of size Bd, as shown in Equation 8.
  • co is the offset and ci is the index from 0 to (Bc-1).
  • do is the offset and di is the index from 0 to (Bd-1). Note that the size Bc and the size Bd may be the same.
  • the input data a(x+i, y+j, c) in Equation 1 is divided by the size Bc in the c-axis direction and represented by the divided input data a(x+i, y+j, co).
  • the divided input data a is also referred to as "divided input data a".
  • the weight w (i, j, c, d) in Equation 1 is divided by the size Bc in the c-axis direction and the size Bd in the d-axis direction, and is represented by the divided weight w (i, j, co, do).
  • the divided weight w is also referred to as "divided weight w".
  • the output data f(x, y, do) divided by the size Bd is obtained by Equation 9.
  • the final output data f(x, y, d) can be calculated.
  • the NN circuit 100 develops the input data a and the weight w in the convolution operation of the convolution layer 210 and performs the convolution operation.
  • FIG. 3 is a diagram for explaining expansion of data in a convolution operation.
  • Divided input data a(x+i, y+j, co) is developed into vector data having Bc elements. Elements of the divided input data a are indexed by ci (0 ⁇ ci ⁇ Bc).
  • divided input data a developed into vector data for each i and j is also referred to as "input vector A".
  • Input vector A has elements from divided input data a(x+i, y+j, co ⁇ Bc) to divided input data a(x+i, y+j, co ⁇ Bc+(Bc ⁇ 1)).
  • the division weight w (i, j, co, do) is developed into matrix data with Bc ⁇ Bd elements.
  • the elements of the division weight w developed into matrix data are indexed by ci and di (0 ⁇ di ⁇ Bd).
  • the divided weight w developed into matrix data for each i and j is also referred to as "weight matrix W".
  • the weight matrix W has division weights w (i, j, co ⁇ Bc, do ⁇ Bd) to division weights w (i, j, co ⁇ Bc+(Bc ⁇ 1), do ⁇ Bd+(Bd ⁇ 1)) as elements.
  • Output data f(x, y, do) can be obtained by shaping the vector data calculated for each of i, j, and co into a three-dimensional tensor.
  • the convolution operation of the convolution layer 210 can be performed by multiplying the vector data and the matrix data.
  • FIG. 4 is a diagram showing the overall configuration of the NN circuit 100 according to this embodiment.
  • the NN circuit 100 includes a first DMA controller 3 (hereinafter also referred to as “first DMAC 3”), a controller 6, an IFU 7, a shared memory 8, a second DMA controller 9 (hereinafter also referred to as “second DMAC 9”), and at least one neural network operation core 10 (hereinafter also referred to as "NN operation core 10").
  • the NN circuit 100 can implement a plurality of NN operation cores 10.
  • the NN circuit 100 illustrated in FIG. 4 can implement up to four NN operation cores 10 .
  • the plurality of NN operation cores 10 constitute a "neural network operation multi-core 10M (hereinafter also referred to as "NN operation multi-core 10M")" that cooperates to execute at least part of the operation of the NN 200.
  • FIG. A plurality of NN operation cores 10 are daisy-chained in this embodiment. Note that the number of NN operation cores 10 that can be implemented in the NN circuit 100 may be five or more.
  • the first DMAC 3 is connected to the external bus EB and performs data transfer between the external memory 120 such as DRAM and the NN operation core 10 .
  • the first DMAC 3 transfers data read from the external memory 120 to one of the NN operation cores 10 .
  • the first DMAC 3 may be capable of transferring the same data read from the external memory 120 to a plurality of NN operation cores 10, or may be capable of broadcasting.
  • the first DMAC 3 also transfers data between an external memory such as a DRAM and the shared memory 8 .
  • the controller 6 is connected to the external bus EB and operates as a slave of the external host CPU 110 .
  • the controller 6 has a bus bridge 60 and a register 61 .
  • the bus bridge 60 relays bus access from the external bus EB to the internal bus IB.
  • the bus bridge 60 also relays write requests and read requests from the external host CPU 110 to the register 61 .
  • the register 61 has a parameter register and a status register.
  • a parameter register is a register that controls the operation of the NN circuit 100 .
  • the status register is a register that indicates the status of the NN circuit 100, including a pointer to the instruction sequence of each module, the number of instructions, and the like. Also, the status register may be configured to include a semaphore S.
  • FIG. The external host CPU 110 can access the register 61 via the bus bridge 60 of the controller 6 .
  • the controller 6 is connected to each block of the NN circuit 100 (first DMAC 3, IFU 7, second DMAC 9, NN arithmetic core 10) via an internal bus IB.
  • the external host CPU 110 can access each block of the NN circuit 100 via the controller 6 .
  • the external host CPU 110 can issue instructions to the NN arithmetic core 10 via the controller 6 .
  • each block can update the status register (which may include the semaphore S) of the controller 6 via the internal bus IB.
  • the status register may be configured to be updated via dedicated wiring connected to each block.
  • the IFU (Instruction Fetch Unit) 7 reads from the external memory 120 instructions for each block of the NN circuit 100 (the first DMAC 3, the second DMAC 9, and the NN arithmetic core 10) via the external bus EB based on instructions from the external host CPU 110. Also, the IFU 7 transfers the read instruction command to each corresponding block of the NN circuit 100 (the first DMAC 3, the second DMAC 9, and the NN operation core 10).
  • the shared memory 8 is a rewritable memory such as a volatile memory composed of, for example, SRAM (Static RAM).
  • the shared memory 8 is a memory for temporarily recording data used by the NN operation core 10 and for recording data shared by a plurality of NN operation cores.
  • the second DMAC 9 connects the shared memory 8 and the NN operation core 10 and performs data transfer between the shared memory 8 and the NN operation core 10 .
  • the second DMAC 9 may be capable of broadcasting data read from the shared memory 8 to the multiple NN operation cores 10 .
  • the NN circuit 100 can temporarily save data and the like shared by a plurality of NN calculation cores to the shared memory 8 using the second DMAC 9 without saving it to the external memory 120 using the first DMAC 3, thereby speeding up the data transfer between the NN calculation cores. Note that the NN circuit 100 does not have to have the shared memory 8 and the second DMAC 9 .
  • FIG. 5 is a diagram showing the overall configuration of the NN operation core 10. As shown in FIG.
  • the NN operation core 10 includes a first memory 1 , a second memory 2 , a convolution operation circuit 4 and a quantization operation circuit 5 .
  • the NN operation core 10 is characterized in that a convolution operation circuit 4 and a quantization operation circuit 5 are formed in a loop via a first memory 1 and a second memory 2 .
  • the first memory 1 is a rewritable memory such as a volatile memory composed of, for example, SRAM (Static RAM). Data is written to and read from the first memory 1 via the first DMAC 3, the second DMAC 9, and the internal bus IB.
  • the external host CPU 110 can input/output data to/from the NN operation core 10 by writing/reading data to/from the first memory 1 .
  • the first memory 1 is connected to the input port of the convolution operation circuit 4 , and the convolution operation circuit 4 can read data from the first memory 1 . Also, the first memory 1 is loop-connected (C1) to the output port of the quantization operation circuit 5 , and the quantization operation circuit 5 can write data to the first memory 1 . In addition, the first memory 1 can transfer data through the inter-core connection (C2) with another NN operation core 10, and the other NN operation core 10 connected between the cores (C2) can write data to the first memory 1. In this embodiment, daisy chain connection is used as an example of inter-core connection (C2).
  • the second memory 2 is a rewritable memory such as a volatile memory composed of, for example, SRAM (Static RAM). Data is written to and read from the second memory 2 via the first DMAC 3, the second DMAC 9, and the internal bus IB.
  • the external host CPU 110 can input/output data to/from the NN operation core 10 by writing/reading data to/from the second memory 2 .
  • the second memory 2 is connected to the input port of the quantization arithmetic circuit 5, and the quantization arithmetic circuit 5 can read data from the second memory 2.
  • the second memory 2 is also connected to the output port of the convolution circuit 4 , and the convolution circuit 4 can write data to the second memory 2 .
  • the convolution operation circuit 4 is a circuit that performs convolution operations in the convolution layer 210 of the trained CNN 200 .
  • the convolution operation circuit 4 reads the input data a stored in the first memory 1 and performs a convolution operation on the input data a.
  • the convolution operation circuit 4 writes output data f of the convolution operation (hereinafter also referred to as “convolution operation output data”) to the second memory 2 .
  • the quantization operation circuit 5 is a circuit that performs at least part of the quantization operation in the quantization operation layer 220 of the trained CNN 200.
  • the quantization operation circuit 5 reads out the output data f of the convolution operation stored in the second memory 2, and performs a quantization operation on the output data f of the convolution operation (operation including at least quantization among pooling, batch normalization, activation function, and quantization).
  • the quantization operation circuit 5 writes the output data of the quantization operation (hereinafter also referred to as "quantization operation output data") to the loop-connected (C1) first memory 1 . Further, the quantization operation circuit 5 can transfer data to another NN operation core 10 via the inter-core connection (C2), and the quantization operation circuit 5 can output the quantization operation output data to the other NN operation core 10 connected to the inter-core connection (C2).
  • the NN operation core 10 Since the NN operation core 10 has the first memory 1, the second memory 2, etc., it is possible to reduce the number of data transfers of overlapping data in the data transfer by the first DMAC 3 from the external memory such as DRAM. As a result, the power consumption or processing load caused by memory access can be greatly reduced.
  • FIG. 6 is a timing chart showing an operation example of the NN arithmetic core 10.
  • the first DMAC 3 stores the layer 1 input data a in the first memory 1 .
  • the first DMAC 3 may divide the input data a of the layer 1 according to the order of the convolution operation performed by the convolution operation circuit 4 and transfer the divided data to the first memory 1 .
  • the convolution operation circuit 4 reads the layer 1 input data a stored in the first memory 1 .
  • the convolution operation circuit 4 performs the layer 1 convolution operation shown in FIG. 1 on the layer 1 input data a.
  • the output data f of the layer 1 convolution operation is stored in the second memory 2 .
  • the quantization arithmetic circuit 5 reads the layer 1 output data f stored in the second memory 2 .
  • a quantization operation circuit 5 performs a layer 2 quantization operation on layer 1 output data f.
  • the output data of the layer 2 quantization operation is stored in the first memory 1 .
  • the convolution operation circuit 4 reads the output data of the layer 2 quantization operation stored in the first memory 1 .
  • the convolution operation circuit 4 performs a layer 3 convolution operation using the output data of the layer 2 quantization operation as input data a.
  • the output data f of the layer 3 convolution operation is stored in the second memory 2 .
  • the convolution operation circuit 4 reads the output data of the quantization operation of the layer 2M-2 (M is a natural number) stored in the first memory 1.
  • the convolution operation circuit 4 performs the convolution operation of the layer 2M-1 using the output data of the quantization operation of the layer 2M-2 as the input data a.
  • the output data f of the layer 2M-1 convolution operation is stored in the second memory 2.
  • the quantization arithmetic circuit 5 reads the layer 2M-1 output data f stored in the second memory 2 .
  • the quantization operation circuit 5 performs a layer 2M quantization operation on the output data f of the 2M ⁇ 1 layer.
  • the output data of the layer 2M quantization operation are stored in the first memory 1 .
  • the convolution operation circuit 4 reads the output data of the layer 2M quantization operation stored in the first memory 1 .
  • the convolution operation circuit 4 performs a layer 2M+1 convolution operation using the output data of the layer 2M quantization operation as input data a.
  • the output data f of the layer 2M+1 convolution operation are stored in the second memory 2 .
  • the convolution operation circuit 4 and the quantization operation circuit 5 alternately perform operations to advance the operation of the CNN 200 shown in FIG.
  • the convolution operation circuit 4 performs the convolution operation of layer 2M-1 and layer 2M+1 by time division.
  • the quantization operation circuit 5 performs the quantization operation of layer 2M-2 and layer 2M by time division. Therefore, the NN operation core 10 has a significantly smaller circuit scale compared to the case where separate convolution operation circuits 4 and quantization operation circuits 5 are implemented for each layer.
  • the NN operation core 10 performs operations of the CNN 200, which has a multilayer structure of multiple layers, using circuits formed in a loop.
  • the NN operation core 10 can efficiently use hardware resources due to its looped circuit configuration. Since the NN operation core 10 forms a circuit in a loop, parameters in the convolution operation circuit 4 and the quantization operation circuit 5 that change in each layer are updated as appropriate.
  • the NN computation core 10 transfers intermediate data to an external computation device such as the external host CPU 110. After the external arithmetic device performs arithmetic on the intermediate data, the arithmetic result by the external arithmetic device is input to the first memory 1 and the second memory 2 . The NN operation core 10 resumes operation on the operation result by the external operation device.
  • FIG. 7 is a timing chart showing another operation example of the NN arithmetic core 10.
  • the NN operation core 10 may divide the input data a into partial tensors and perform operations on the partial tensors by time division.
  • the method of division into partial tensors and the number of divisions are not particularly limited.
  • FIG. 7 shows an operation example when the input data a is decomposed into two partial tensors.
  • the decomposed partial tensors be “first partial tensor a 1 ” and “second partial tensor a 2 ”.
  • the convolution operation of layer 2M-1 is decomposed into a convolution operation corresponding to the first partial tensor a 1 (denoted as “layer 2M-1 (a 1 )” in FIG. 7) and a convolution operation corresponding to the second partial tensor a 2 (denoted “layer 2M-1 (a 2 )” in FIG. 7).
  • the convolution and quantization operations corresponding to the first partial tensor a 1 and the convolution and quantization operations corresponding to the second partial tensor a 2 can be performed independently, as shown in FIG.
  • the convolution operation circuit 4 performs a layer 2M-1 convolution operation (operation indicated by layer 2M-1 (a 1 ) in FIG. 7) corresponding to the first partial tensor a 1 . After that, the convolution operation circuit 4 performs a layer 2M-1 convolution operation (operation indicated by layer 2M-1 (a 2 ) in FIG. 7) corresponding to the second partial tensor a 2 .
  • the quantization operation circuit 5 also performs a layer 2M quantization operation (operation indicated by layer 2M(a 1 ) in FIG. 7) corresponding to the first partial tensor a 1 . In this way, the NN operation core 10 can perform the layer 2M-1 convolution operation corresponding to the second partial tensor a 2 and the layer 2M quantization operation corresponding to the first partial tensor a 1 in parallel.
  • the convolution operation circuit 4 performs a layer 2M+1 convolution operation (operation indicated by layer 2M+1 (a 1 ) in FIG. 7) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 also performs a layer 2M quantization operation (operation indicated by layer 2M (a 2 ) in FIG. 7) corresponding to the second partial tensor a2.
  • the NN operation core 10 can perform the layer 2M+ 1 convolution operation corresponding to the first partial tensor a1 and the layer 2M quantization operation corresponding to the second partial tensor a2 in parallel.
  • the convolution and quantization operations corresponding to the first partial tensor a 1 and the convolution and quantization operations corresponding to the second partial tensor a 2 can be performed independently. Therefore, the NN operation core 10 may perform, for example, a layer 2M ⁇ 1 convolution operation corresponding to the first partial tensor a 1 and a layer 2M+2 quantization operation corresponding to the second partial tensor a 2 in parallel. That is, the convolution operation and quantization operation that the NN operation core 10 performs in parallel are not limited to the operation of successive layers.
  • the NN operation core 10 can operate the convolution operation circuit 4 and the quantization operation circuit 5 in parallel. As a result, the waiting time of the convolution operation circuit 4 and the quantization operation circuit 5 is reduced, and the operation processing efficiency of the NN operation core 10 is improved.
  • the number of divisions is 2 in the operation example shown in FIG. 7, the NN operation core 10 can operate the convolution operation circuit 4 and the quantization operation circuit 5 in parallel even when the number of divisions is greater than 2.
  • the NN operation core 10 may perform the layer 2M-1 convolution operation corresponding to the second partial tensor a 2 and the layer 2M quantization operation corresponding to the third partial tensor a 3 in parallel.
  • the order of operations is appropriately changed according to the storage conditions of the input data a in the first memory 1 and the second memory 2 .
  • Method 1 As a calculation method for partial tensors, an example (Method 1) is shown in which partial tensors in the same layer are calculated in the convolution calculation circuit 4 or quantization calculation circuit 5, and then partial tensors in the next layer are calculated.
  • Method 1 As shown in FIG. 7, in the convolution operation circuit 4, after performing the layer 2M-1 convolution operation corresponding to the first partial tensor a 1 and the second partial tensor a 2 (in FIG.
  • the calculation method for partial tensors is not limited to this.
  • the calculation method for the partial tensors may be a method of calculating partial tensors in multiple layers and then calculating remaining partial tensors (Method 2). For example, in the convolution operation circuit 4, after performing the layer 2M ⁇ 1 corresponding to the first partial tensor a 1 and the layer 2M+ 1 corresponding to the first partial tensor a 1 , the layer 2M ⁇ 1 corresponding to the second partial tensor a2 and the layer 2M+ 1 corresponding to the second partial tensor a2 may be carried out.
  • the method of computing partial tensors may be a method of computing partial tensors by combining method 1 and method 2. However, when method 2 is used, it is necessary to perform operations in accordance with the dependency regarding the operation order of partial tensors.
  • FIG. 8 is a diagram showing the NN arithmetic multicore 10M.
  • the NN operation multi-core 10M illustrated in FIG. 8 includes two NN operation cores 10 that are daisy-chained. When distinguishing between the two NN operation cores 10, the two NN operation cores 10 are referred to as "first NN operation core 10A” and "second NN operation core 10B".
  • the first memory 1 is abbreviated as "A”
  • the convolution operation circuit 4 as "C”
  • the second memory 2 as "F”
  • the quantization operation circuit 5 as "Q”.
  • the quantization arithmetic circuit 5 of the first NN arithmetic core 10A and the first memory 1 of the second NN arithmetic core 10B are daisy chain connected (C2).
  • the quantization operation circuit 5 of the first NN operation core 10A can write quantization operation output data to the first memory 1 of the loop-connected (C1) first NN operation core 10A and/or the first memory 1 of the daisy-chain-connected (C2) second NN operation core 10B.
  • the quantization arithmetic circuit 5 of the second NN arithmetic core 10B and the first memory 1 of the first NN arithmetic core 10A are daisy chain connected (C2).
  • the quantization operation circuit 5 of the second NN operation core 10B can write the quantization operation output data to the first memory 1 of the loop-connected (C1) second NN operation core 10B and/or the first memory 1 of the daisy-chain-connected (C2) first NN operation core 10A.
  • the NN operation multi-core 10M includes three or more NN operation cores 10
  • the plurality of NN operation cores 10 are daisy-chained.
  • the quantization operation circuits 5 of the NN operation cores 10 other than the NN operation core 10 at the final stage are daisy-chain connected (C2) to the first memory 1 of the NN operation core 10B at the subsequent stage.
  • the quantization operation circuit 5 of the NN operation core 10 at the final stage is daisy-chain connected (C2) to the first memory 1 of the NN operation core 10 at the first stage.
  • a plurality of NN operation cores 10 are characterized in that they are formed in a daisy chain loop.
  • the first memory (A) 1, the convolution operation circuit (C) 4, the second memory (F) 2, and the quantization operation circuit (Q) 5 are connected in a loop.
  • the first memory (A) 1, the convolution operation circuit (C) 4, the second memory (F) 2, and the quantization operation circuit (Q) 5 are connected in a daisy chain loop so that the first memory (A) 1, the convolution operation circuit (C) 4, the second memory (F) 2, and the quantization operation circuit (Q) 5 are repeatedly arranged in the same order.
  • the multiple NN operation cores 10 that make up the NN operation multi-core 10M do not have to have the same hardware configuration.
  • the capacity/configuration of the first memory 1 of the first NN operation core 10A may be different from the capacity/configuration of the first memory 1 of the second NN operation core 10B.
  • the configuration of the quantization operation circuit 5 of the first NN operation core 10A may be different from the configuration of the quantization operation circuit 5 of the second NN operation core 10B.
  • FIG. 9 is a timing chart showing operation example 1 of the NN arithmetic multi-core 10M.
  • the convolution operation and quantization operation corresponding to the first partial tensor a 1 and the convolution operation and quantization operation corresponding to the second partial tensor a 2 are performed independently by different NN operation cores 10, as shown in FIG.
  • the convolution operation circuit 4 of the first NN operation core 10A performs a layer 2M- 1 convolution operation (operation indicated by layer 2M-1 (a 1 ) in FIG. 9) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 of the first NN operation core 10A performs a layer 2M quantization operation (operation indicated by layer 2M(a 1 ) in FIG. 9) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 of the first NN operation core 10A stores the layer 2M quantization operation output data corresponding to the first partial tensor a 1 in the first memory 1 of the first NN operation core 10A.
  • the convolution operation circuit 4 of the second NN operation core 10B performs a layer 2M-1 convolution operation (operation indicated by layer 2M-1 (a 2 ) in FIG. 9) corresponding to the second partial tensor a 2 .
  • the quantization operation circuit 5 of the second NN operation core 10B performs a layer 2M quantization operation (operation indicated by layer 2M(a 2 ) in FIG. 9) corresponding to the second partial tensor a2.
  • the quantization operation circuit 5 of the second NN operation core 10B stores the layer 2M quantization operation output data corresponding to the second partial tensor a2 in the first memory 1 of the second NN operation core 10B.
  • the second DMAC 9 DMA-transfers the layer 2M quantization operation output data corresponding to the first partial tensor a 1 stored in the first memory 1 of the first NN operation core 10A to the shared memory 8 (transfer indicated by DMA1 in FIG. 9).
  • the second DMAC 9 DMA-transfers the layer 2M quantization calculation output data corresponding to the second partial tensor a2 stored in the first memory 1 of the second NN calculation core 10B to the shared memory 8 (transfer indicated by DMA2 in FIG. 9).
  • the first DMAC 3 DMA-transfers the layer 2M quantization operation output data corresponding to the first partial tensor a 1 and the second partial tensor a 2 stored in the shared memory 8 to the external memory 120 (transfer indicated by DMA 3 in FIG. 9).
  • the NN operation multi-core 10M can, for example, independently perform operations on the same layer using different NN operation cores 10 to shorten the time required for the operation.
  • the shared memory 8 and the second DMAC 9 can organize the calculation results of the NN calculation cores 10 .
  • FIG. 10 is a timing chart showing operation example 2 of the NN arithmetic multi-core 10M. Convolution and quantization operations corresponding to the first partial tensor a 1 are performed cooperatively by different NN operation cores 10 .
  • the convolution operation circuit 4 of the first NN operation core 10A performs the layer 2M-1 convolution operation (the operation indicated by layer 2M-1 (a 1 ) in FIG. 10) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 of the first NN operation core 10A performs a layer 2M quantization operation (operation indicated by layer 2M(a 1 ) in FIG. 10) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 of the first NN operation core 10A stores the layer 2M quantization operation output data corresponding to the first partial tensor a 1 in the first memory 1 of the second NN operation core 10B.
  • the convolution operation circuit 4 of the second NN operation core 10B performs the layer 2M+1 convolution operation (the operation indicated by layer 2M+1 (a 1 ) in FIG. 10) corresponding to the first partial tensor a 1 . Thereafter, the quantization operation circuit 5 of the second NN operation core 10B performs a layer 2M+2 quantization operation (operation indicated by layer 2M+2 (a 1 ) in FIG. 10) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 of the second NN operation core 10B stores the quantization operation output data of layer 2M+ 2 corresponding to the second partial tensor a2 in the first memory 1 of the second NN operation core 10B.
  • the first DMAC 3 DMA-transfers the layer 2M+2 quantization operation output data corresponding to the first partial tensor a 1 stored in the first memory 1 of the second NN operation core 10B to the external memory 120 (transfer indicated by DMA in FIG. 10).
  • the NN computation multi-core 10M can reduce the time required for computation by successively performing computations corresponding to the same partial tensor by different NN computation cores 10, for example.
  • FIG. 11 is a timing chart showing operation example 3 of the NN arithmetic multi-core 10M.
  • operation example 3 the configuration of the partial tensor is changed in the layer 2M ⁇ 1 convolution operation and the layer 2M+1 convolution operation.
  • the second DMAC 9 DMA-transfers the first partial tensor a 1 to the first memory 1 of the first NN operation core 10A (transfer indicated by DMA1 in FIG. 11).
  • the second DMAC 9 DMA-transfers the second partial tensor a2 to the first memory 1 of the second NN operation core 10B (transfer indicated by DMA2 in FIG. 11).
  • the convolution operation circuit 4 of the first NN operation core 10A performs the layer 2M-1 convolution operation (the operation indicated by layer 2M-1 (a 1 ) in FIG. 11) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 of the first NN operation core 10A performs a layer 2M quantization operation (operation indicated by layer 2M(a 1 ) in FIG. 11) corresponding to the first partial tensor a 1 .
  • the quantization operation circuit 5 of the first NN operation core 10A stores the layer 2M quantization operation output data corresponding to the first partial tensor a 1 in the first memory 1 of the first NN operation core 10A.
  • the second DMAC 9 DMA-transfers the layer 2M quantization operation output data corresponding to the first partial tensor a 1 stored in the first memory 1 of the first NN operation core 10A to the shared memory 8 (transfer indicated by DMA3 in FIG. 11).
  • the convolution operation circuit 4 of the second NN operation core 10B performs a layer 2M-1 convolution operation (operation indicated by layer 2M-1 (a 2 ) in FIG. 11) corresponding to the second partial tensor a 2 .
  • the start of the convolution operation by the convolution operation circuit 4 of the second NN operation core 10B is later than the start of the convolution operation by the convolution operation circuit 4 of the first NN operation core 10A.
  • the quantization operation circuit 5 of the second NN operation core 10B performs a layer 2M quantization operation corresponding to the second partial tensor a2 (the operation indicated by layer 2M( a2 ) in FIG. 11).
  • the quantization operation circuit 5 of the second NN operation core 10B stores the layer 2M quantization operation output data corresponding to the second partial tensor a2 in the first memory 1 of the second NN operation core 10B.
  • the second DMAC 9 DMA-transfers the layer 2M quantization operation output data corresponding to the second partial tensor a 2 stored in the first memory 1 of the second NN operation core 10B to the shared memory 8 (transfer indicated by DMA4 in FIG. 11).
  • each NN operation core 10 is optimized to perform parallel operations on input data a with 32 channels in the c-axis direction, and performs a layer 2M+1 convolution operation in which input data a has 64 channels in the c-axis direction.
  • the manner in which the input data a is divided into partial tensors may be changed so that the convolution operation circuit 4 of the NN operation core 10A operates on the input data a of channels 0 to 31, and the convolution operation circuit 4 of the NN operation core 10B operates on the input data a of channels 32 to 63.
  • Two of the subdivided partial tensors are called “third partial tensor a 3 ” and “fourth partial tensor a 4 ”.
  • the second DMAC 9 DMA-transfers the third partial tensor a3 to the first memory 1 of the first NN operation core 10A (transfer indicated by DMA5 in FIG. 11).
  • the second DMAC 9 DMA-transfers the fourth partial tensor a4 to the first memory 1 of the second NN operation core 10B (transfer indicated by DMA6 in FIG. 11).
  • the convolution operation circuit 4 of the first NN operation core 10A performs a layer 2M+1 convolution operation (operation indicated by layer 2M+1 (a 3 ) in FIG. 11) corresponding to the third partial tensor a 3 .
  • the quantization operation circuit 5 of the first NN operation core 10A performs a layer 2M+2 quantization operation (operation indicated by layer 2M+2 (a 3 ) in FIG. 11) corresponding to the third partial tensor a3 .
  • the quantization operation circuit 5 of the first NN operation core 10A stores the quantization operation output data of layer 2M+2 corresponding to the third partial tensor a3 in the first memory 1 of the first NN operation core 10A.
  • the convolution operation circuit 4 of the second NN operation core 10B performs a layer 2M+1 convolution operation (operation indicated by layer 2M+1 (a 4 ) in FIG. 11) corresponding to the fourth partial tensor a 4 .
  • the quantization operation circuit 5 of the second NN operation core 10B performs a layer 2M+2 quantization operation (operation indicated by layer 2M+2 (a 4 ) in FIG. 11) corresponding to the fourth partial tensor a 4 .
  • the quantization operation circuit 5 of the second NN operation core 10B stores the quantization operation output data of layer 2M+2 corresponding to the fourth partial tensor a4 in the first memory 1 of the second NN operation core 10B.
  • the NN circuit 100 uses the second DMAC 9 and the shared memory 8 to change the division mode of the partial tensor assigned to the NN operation core 10.
  • the NN circuit 100 can reduce the number of times the input data a is saved in the external memory 120 by DMA transfer using the first DMAC 3 even when changing the division mode of the partial tensor.
  • FIG. 12 is an internal block diagram of the first DMAC3.
  • the first DMAC 3 has a data transfer circuit 31 and a state controller 32 .
  • the first DMAC 3 has a dedicated state controller 32 for the data transfer circuit 31, and when an instruction command is input, DMA data transfer can be performed without the need for an external controller.
  • the data transfer circuit 31 is connected to the external bus EB and performs DMA data transfer between the external memory 120 such as DRAM and the NN operation core 10 .
  • the data transfer circuit 31 also performs DMA data transfer between the external memory 120 such as a DRAM and the shared memory 8 .
  • the number of DMA channels of the data transfer circuit 31 is not limited.
  • each of the first NN operation core 10A and the second NN operation core 10B may have a dedicated DMA channel.
  • the state controller 32 controls the state of the data transfer circuit 31 . Also, the state controller 32 is connected to the controller 6 via an internal bus IB. The state controller 32 has an instruction queue 33 and a control circuit 34 .
  • the instruction queue 33 is a queue in which the instruction command C3 for the first DMAC 3 is stored, and is composed of a FIFO memory, for example.
  • One or more instruction commands C3 are written into the instruction queue 33 via the IFU 7 or via the internal bus IB.
  • the control circuit 34 is a state machine that decodes the instruction command C3 and sequentially controls the data transfer circuit 31 based on the instruction command C3.
  • the control circuit 34 may be implemented by a logic circuit or by a CPU controlled by software.
  • FIG. 13 is a state transition diagram of the control circuit 34. As shown in FIG. When the instruction command C3 is input to the instruction queue 33 (Not empty), the control circuit 34 transitions from the idle state ST1 to the decode state ST2.
  • the control circuit 34 decodes the instruction command C3 output from the instruction queue 33 in the decode state ST2. Also, the control circuit 34 reads the semaphore S stored in the register 61 of the controller 6 and determines whether the operation of the data transfer circuit 31 instructed by the instruction command C3 can be executed. If it is not executable (Not ready), the control circuit 34 waits until it becomes executable (Wait). If it is executable (ready), the control circuit 34 transitions from the decode state ST2 to the execution state ST3.
  • the control circuit 34 controls the data transfer circuit 31 to perform the operation instructed by the instruction command C3.
  • the control circuit 34 removes the executed instruction command C3 from the instruction queue 33 and updates the semaphore S stored in the register 61 of the controller 6 .
  • the control circuit 34 transitions from the execution state ST3 to the decode state ST2.
  • the control circuit 34 transitions from the execution state ST3 to the idle state ST1.
  • FIG. 14 is an internal block diagram of the convolution operation circuit 4. As shown in FIG.
  • the convolution circuit 4 has a weight memory 41 , a multiplier 42 , an accumulator circuit 43 and a state controller 44 .
  • the convolution operation circuit 4 has a dedicated state controller 44 for the multiplier 42 and the accumulator circuit 43, and when an instruction command is input, the convolution operation can be performed without the need for an external controller.
  • the weight memory 41 is a memory that stores the weight w used in the convolution operation, and is a rewritable memory such as a volatile memory configured with SRAM (Static RAM), for example.
  • the first DMAC 3 writes the weight w required for the convolution operation into the weight memory 41 by DMA transfer.
  • FIG. 15 is an internal block diagram of the multiplier 42.
  • Multiplier 42 multiplies input vector A and weight matrix W.
  • the input vector A is vector data having Bc elements obtained by expanding divided input data a(x+i, y+j, co) for each i and j, as described above.
  • the weight matrix W is matrix data having Bc ⁇ Bd elements in which divided weights w(i, j, co, do) are expanded for each i and j.
  • the multiplier 42 has Bc ⁇ Bd product-sum operation units 47, and can perform multiplication of the input vector A and the weight matrix W in parallel.
  • the multiplier 42 reads out the input vector A and the weight matrix W required for multiplication from the first memory 1 and the weight memory 41 to carry out the multiplication.
  • the multiplier 42 outputs Bd sum-of-products operation results O(di).
  • FIG. 16 is an internal block diagram of the sum-of-products operation unit 47.
  • Sum-of-products unit 47 performs multiplication of input vector A element A(ci) with weight matrix W element W(ci, di). Further, the sum-of-products operation unit 47 adds the multiplication result and the multiplication result S(ci, di) of another sum-of-products operation unit 47 .
  • the sum-of-products operation unit 47 outputs the addition result S(ci+1, di).
  • Element A(ci) is a 2-bit unsigned integer (0, 1, 2, 3).
  • the element W(ci,di) is a 1-bit signed integer (0,1), where the value "0" represents +1 and the value "1" represents -1.
  • the sum-of-products operation unit 47 has an inverter (inverter) 47a, a selector 47b, and an adder 47c.
  • the sum-of-products operation unit 47 performs multiplication using only the inverter 47a and the selector 47b without using a multiplier.
  • the selector 47b selects the input of the element A(ci) when the element W(ci, di) is "0". When the element W(ci, di) is "1", the selector 47b selects the complement of the element A(ci) inverted by the inverter. Element W(ci, di) is also input to Carry-in of adder 47c.
  • the adder 47c outputs a value obtained by adding the element A(ci) to S(ci, di) when the element W(ci, di) is "0".
  • the adder 47c outputs a value obtained by subtracting the element A(ci) from S(ci, di) when W(ci, di) is "1".
  • FIG. 17 is an internal block diagram of the accumulator circuit 43. As shown in FIG. The accumulator circuit 43 accumulates the sum-of-products operation result O(di) of the multiplier 42 in the second memory 2 .
  • the accumulator circuit 43 has Bd accumulator units 48 and can accumulate Bd product-sum operation results O(di) in parallel in the second memory 2 .
  • FIG. 18 is an internal block diagram of the accumulator unit 48.
  • the accumulator unit 48 has an adder 48a and a mask portion 48b.
  • the adder 48 a adds the element O(di) of the sum-of-products operation result O and the partial sum, which is the intermediate progress of the convolution operation shown in Equation 1, stored in the second memory 2 .
  • the addition result is 16 bits per element.
  • the addition result is not limited to 16 bits per element, and may be, for example, 15 bits or 17 bits per element.
  • the adder 48a writes the addition result to the same address in the second memory 2.
  • the mask unit 48b masks the output from the second memory 2 and zeros the addition target for the element O(di) when the initialization signal clear is asserted.
  • the initialization signal clear is asserted when the intermediate partial sum is not stored in the second memory 2 .
  • the second memory 2 stores the output data f(x, y, do).
  • a state controller 44 controls the states of the multiplier 42 and the accumulator circuit 43 . Also, the state controller 44 is connected to the controller 6 via an internal bus IB. The state controller 44 has an instruction queue 45 and a control circuit 46 .
  • the instruction queue 45 is a queue in which the instruction command C4 for the convolution operation circuit 4 is stored, and is composed of, for example, a FIFO memory. An instruction command C4 is written into the instruction queue 45 via the IFU 7 or via the internal bus IB.
  • the control circuit 46 is a state machine that decodes the instruction command C4 and controls the multiplier 42 and the accumulator circuit 43 based on the instruction command C4.
  • the control circuit 46 has the same configuration as the control circuit 34 of the state controller 32 of the first DMAC3.
  • FIG. 19 is an internal block diagram of the quantization arithmetic circuit 5.
  • the quantization arithmetic circuit 5 has a quantization parameter memory 51 , a vector arithmetic circuit 52 , a quantization circuit 53 and a state controller 54 .
  • the quantization operation circuit 5 has a dedicated state controller 54 for the vector operation circuit 52 and the quantization circuit 53, and when an instruction command is input, the quantization operation can be performed without requiring an external controller.
  • the quantization parameter memory 51 is a memory that stores the quantization parameter q used in the quantization calculation, and is a rewritable memory such as a volatile memory configured with SRAM (Static RAM), for example.
  • the first DMAC 3 writes the quantization parameter q required for the quantization calculation into the quantization parameter memory 51 by DMA transfer.
  • FIG. 20 is an internal block diagram of the vector operation circuit 52 and the quantization circuit 53. As shown in FIG. The vector computation circuit 52 computes the output data f(x, y, do) stored in the second memory 2 . The vector operation circuit 52 has Bd number of operation units 57 and performs SIMD operations on the output data f(x, y, do) in parallel.
  • FIG. 21 is a block diagram of the arithmetic unit 57.
  • the arithmetic unit 57 has, for example, an ALU 57a, a first selector 57b, a second selector 57c, a register 57d, and a shifter 57e.
  • the arithmetic unit 57 may further include other calculators and the like that a known general-purpose SIMD arithmetic circuit has.
  • the vector operation circuit 52 performs at least one of the operations of the pooling layer 221 in the quantization operation layer 220, the batch normalization layer 222, and the activation function layer 223 on the output data f(x, y, do) by combining the operation units of the operation unit 57.
  • the arithmetic unit 57 can add the data stored in the register 57d and the element f(di) of the output data f(x, y, do) read from the second memory 2 by the ALU 57a.
  • the arithmetic unit 57 can store the addition result by the ALU 57a in the register 57d.
  • the arithmetic unit 57 can initialize the addition result by inputting "0" to the ALU 57a instead of the data stored in the register 57d by selecting the first selector 57b. For example, when the pooling area is 2 ⁇ 2, the shifter 57e can output the average value of the addition result by shifting the output of the ALU 57a to the right by 2 bits.
  • the vector operation circuit 52 can perform the average pooling operation shown in Equation 2 by repeating the above operations and the like by the Bd number of operation units 57 .
  • the arithmetic unit 57 can compare the data stored in the register 57d with the element f(di) of the output data f(x, y, do) read from the second memory 2 by the ALU 57a.
  • the arithmetic unit 57 can control the second selector 57c according to the comparison result by the ALU 57a to select the larger one of the data stored in the register 57d and the element f(di).
  • the arithmetic unit 57 can initialize the comparison target to the minimum value by inputting the minimum value of the possible values of the element f(di) to the ALU 57a by selecting the first selector 57b.
  • the vector operation circuit 52 can implement the MAX pooling operation of Equation 3 by repeating the above operations and the like by the Bd number of operation units 57 . Note that the shifter 57e does not shift the output of the second selector 57c in the MAX pooling calculation.
  • the arithmetic unit 57 can subtract the data stored in the register 57d and the element f(di) of the output data f(x, y, do) read from the second memory 2 by the ALU 57a.
  • Shifter 57e can left shift (ie, multiply) or right shift (ie, divide) the output of ALU 57a.
  • the vector operation circuit 52 can perform the operation of Batch Normalization of Equation 4 by repeating the above operation and the like by the Bd number of operation units 57 .
  • the arithmetic unit 57 can use the ALU 57a to compare the element f(di) of the output data f(x, y, do) read from the second memory 2 and "0" selected by the first selector 57b.
  • the arithmetic unit 57 can select and output either the element f(di) or the constant value "0" previously stored in the register 57d according to the comparison result by the ALU 57a.
  • the vector operation circuit 52 can perform the ReLU operation of Equation 5 by repeating the above operations and the like by the Bd number of operation units 57 .
  • the vector operation circuit 52 can implement average pooling, MAX pooling, batch normalization, activation function operations, and combinations of these operations. Since vector arithmetic circuit 52 is capable of performing general-purpose SIMD operations, it may also perform other operations required for operations in quantization operations layer 220 . Also, the vector operation circuit 52 may perform operations other than the operations in the quantization operation layer 220 .
  • the quantization arithmetic circuit 5 does not have to have the vector arithmetic circuit 52 . If the quantization operation circuit 5 does not have the vector operation circuit 52 , the output data f(x, y, do) are input to the quantization circuit 53 .
  • the quantization circuit 53 quantizes the output data of the vector operation circuit 52 . As shown in FIG. 20, the quantization circuit 53 has Bd quantization units 58 and performs operations on the output data of the vector operation circuit 52 in parallel.
  • FIG. 22 is an internal block diagram of quantization unit 58.
  • a quantization unit 58 quantizes the element in(di) of the output data of the vector operation circuit 52 .
  • Quantization unit 58 comprises a comparator 58a and an encoder 58b.
  • the quantization unit 58 performs the operation (formula 6) of the quantization layer 224 in the quantization operation layer 220 on the output data (16 bits/element) of the vector operation circuit 52 .
  • the quantization unit 58 reads the necessary quantization parameters q (th0, th1, th2) from the quantization parameter memory 51, and the comparator 58a compares the input in(di) with the quantization parameter q.
  • Quantization unit 58 quantizes the result of comparison by comparator 58a to 2 bits/element by encoder 58b. Since ⁇ (c) and ⁇ (c) in Equation 4 are different parameters for each variable c, the quantization parameters q(th0, th1, th2) reflecting ⁇ (c) and ⁇ (c) are different parameters for each in(di).
  • the quantization unit 58 classifies the input in(di) into four regions (for example, in ⁇ th0, th0 ⁇ in ⁇ th1, th1 ⁇ in ⁇ th2, th2 ⁇ in) by comparing the input in(di) with three thresholds th0, th1, and th2, encodes the classification result into 2 bits, and outputs it.
  • the quantization unit 58 can also perform Batch Normalization and calculation of an activation function together with quantization by setting quantization parameters q (th0, th1, th2).
  • the quantization unit 58 performs quantization by setting the threshold th0 as ⁇ (c) in Equation 4 and the threshold difference (th1 ⁇ th0) and (th2 ⁇ th1) as ⁇ (c) in Equation 4, thereby performing the Batch Normalization operation shown in Equation 4 together with quantization.
  • ⁇ (c) can be reduced by increasing (th1-th0) and (th2-th1).
  • ⁇ (c) can be increased by decreasing (th1-th0) and (th2-th1).
  • Quantization unit 58 can implement an activation function in conjunction with quantization of input in(di). For example, quantization unit 58 saturates the output values in regions where in(di) ⁇ th0 and th2 ⁇ in(di). Quantization unit 58 may perform activation function computation in conjunction with quantization by setting the quantization parameter q such that the output is non-linear.
  • the state controller 54 controls the states of the vector operation circuit 52 and the quantization circuit 53. Also, the state controller 54 is connected to the controller 6 via an internal bus IB.
  • the state controller 54 has an instruction queue 55 and a control circuit 56 .
  • the instruction queue 55 is a queue in which the instruction command C5 for the quantization arithmetic circuit 5 is stored, and is composed of a FIFO memory, for example. An instruction command C5 is written into the instruction queue 55 via the IFU 7 or via the internal bus IB.
  • the control circuit 56 is a state machine that decodes the instruction command C5 and controls the vector operation circuit 52 and the quantization circuit 53 based on the instruction command C5.
  • the control circuit 56 has the same configuration as the control circuit 34 of the state controller 32 of the first DMAC3.
  • the quantization operation circuit 5 writes quantization operation output data having Bd elements to the first memory 1 .
  • Formula 10 shows a suitable relationship between Bd and Bc.
  • n is an integer.
  • the controller 6 transfers instruction commands transferred from the external host CPU 110 to the instruction queues of the first DMAC 3, the second DMAC 9, the convolution operation circuit 4 and the quantization operation circuit 5 via the internal bus IB.
  • the controller 6 may have an instruction memory that stores instruction commands for each circuit.
  • the controller 6 is connected to the external bus EB and operates as a slave of the external host CPU 110 .
  • the controller 6 has registers 61 including parameter registers and status registers.
  • a parameter register is a register that controls the operation of the NN circuit 100 .
  • the status register is a register that indicates the status of the NN circuit 100 including the semaphore S.
  • the semaphore S is decremented by the P operation and incremented by the V operation.
  • the P operation and V operation by the first DMAC 3, the convolution operation circuit 4 and the quantization operation circuit 5 update the semaphore S of the controller 6 via the internal bus IB.
  • FIG. 23A and 23B are diagrams for explaining control of the NN circuit 100 by the semaphore S.
  • FIG. A semaphore S is provided for each data flow F via the memories (first memory 1, second memory 2) in the NN circuit 100.
  • FIG. 23 and the following description semaphores related to data flow related to the second DMAC 9 are omitted for simplicity of description. Since the NN circuit 100 in this embodiment includes a plurality of NN operation cores 10, there are a plurality of data flows. Which data flow is used to perform operations on CNN 200 is controlled by the corresponding instruction command.
  • the semaphore S has a first semaphore S11, a second semaphore S12, a third semaphore S13, and a fourth semaphore S14 for the first NN operation core 10A.
  • the first semaphore S11 is used to control the first data flow F11 of the first NN operation core 10A.
  • the first data flow F11 is a data flow in which the first DMAC 3 (Producer) writes the input data a to the first memory 1 of the first NN operation core 10A, and the convolution operation circuit 4 (Consumer) of the first NN operation core 10A reads the input data a.
  • the first semaphore S11 has a first write semaphore S11W and a first read semaphore S11R.
  • the second semaphore S12 is used to control the second data flow F12 of the first NN operation core 10A.
  • the second data flow F12 is a data flow in which the convolution operation circuit 4 (Producer) of the first NN operation core 10A writes the output data f to the second memory 2 of the first NN operation core 10A, and the quantization operation circuit 5 (Consumer) of the first NN operation core 10A reads the output data f.
  • the second semaphore S12 has a second write semaphore S12W and a second read semaphore S12R.
  • the third semaphore S13 is used to control the third data flow F13 of the first NN arithmetic core 10A.
  • the third data flow F13 is a data flow in which the quantization operation circuit 5 (Producer) of the first NN operation core 10A writes the quantization operation output data to the first memory 1 of the first NN operation core 10A, and the convolution operation circuit 4 (Consumer) of the first NN operation core 10A reads the quantization operation output data.
  • the third semaphore S13 has a third write semaphore S13W and a third read semaphore S13R.
  • the fourth semaphore S14 is used to control the fourth data flow F14 of the first NN operation core 10A.
  • the fourth data flow F14 is a data flow in which the quantization operation circuit 5 (Producer) of the second NN operation core 10B writes the quantization operation output data to the first memory 1 of the first NN operation core 10A, and the convolution operation circuit 4 (Consumer) of the first NN operation core 10A reads out the quantization operation output data.
  • the fourth semaphore S14 has a fourth write semaphore S14W and a fourth read semaphore S14R.
  • the semaphore S has a first semaphore S21, a second semaphore S22, a third semaphore S23, and a fourth semaphore S24 for the second NN operation core 10B.
  • the first semaphore S21 is used to control the first data flow F21 of the second NN operation core 10B.
  • the first data flow F21 is a data flow in which the first DMAC 3 (Producer) writes the input data a to the first memory 1 of the second NN operation core 10B, and the convolution operation circuit 4 (Consumer) of the second NN operation core 10B reads the input data a.
  • the first semaphore S21 has a first write semaphore S21W and a first read semaphore S21R.
  • the second semaphore S22 is used to control the second data flow F22 of the second NN operation core 10B.
  • the second data flow F22 is a data flow in which the convolution operation circuit 4 (Producer) of the second NN operation core 10B writes the output data f to the second memory 2 of the second NN operation core 10B, and the quantization operation circuit 5 (Consumer) of the second NN operation core 10B reads the output data f.
  • the second semaphore S22 has a second write semaphore S22W and a second read semaphore S22R.
  • the third semaphore S23 is used to control the third data flow F23 of the second NN arithmetic core 10B.
  • the third data flow F23 is a data flow in which the quantization operation circuit 5 (Producer) of the second NN operation core 10B writes the quantization operation output data to the first memory 1 of the second NN operation core 10B, and the convolution operation circuit 4 (Consumer) of the second NN operation core 10B reads out the quantization operation output data.
  • the third semaphore S23 has a third write semaphore S23W and a third read semaphore S23R.
  • the fourth semaphore S24 is used to control the fourth data flow F24 of the second NN operation core 10B.
  • the fourth data flow F24 is a data flow in which the quantization operation circuit 5 (Producer) of the first NN operation core 10A writes the quantization operation output data to the first memory 1 of the second NN operation core 10B, and the convolution operation circuit 4 (Consumer) of the second NN operation core 10B reads the quantization operation output data.
  • the fourth semaphore S24 has a fourth write semaphore S24W and a fourth read semaphore S24R.
  • FIG. 24 is a timing chart of the first data flow F11.
  • the first write semaphore S11W is a semaphore that restricts writing to the first memory 1 of the first NN operation core 10A by the first DMAC 3 in the first data flow F11 of the first NN operation core 10A.
  • the first write semaphore S11W indicates the number of memory areas in the first memory 1 that can store data of a predetermined size, such as the input vector A, in which data has already been read and other data can be written.
  • the first write semaphore S11W is "0"
  • the first DMAC 3 cannot write to the first memory 1 in the first data flow F11, and has to wait until the first write semaphore S11W becomes "1" or more.
  • the first read semaphore S11R is a semaphore that restricts reading from the first memory 1 of the first NN operation core 10A by the convolution circuit 4 of the first NN operation core 10A in the first data flow F1 of the first NN operation core 10A.
  • the first read semaphore S11R indicates the number of memory areas in which data has been written and can be read out of the memory areas in which data of a predetermined size such as the input vector A can be stored in the first memory 1 .
  • the convolution circuit 4 cannot read from the first memory 1 in the first data flow F11, and is kept waiting until the first read semaphore S11R becomes "1" or more.
  • the first DMAC 3 starts DMA transfer when the instruction command C3 is stored in the instruction queue 33 . As shown in FIG. 24, since the first write semaphore S11W is not "0", the first DMAC 3 starts DMA transfer (DMA transfer 1). The first DMAC 3 performs a P operation on the first write semaphore S11W when starting DMA transfer. After completing the DMA transfer, the first DMAC 3 performs the V operation on the first read semaphore S11R.
  • the convolution operation circuit 4 of the first NN operation core 10A starts the convolution operation.
  • the convolution circuit 4 is kept waiting until the first read semaphore S11R becomes "1" or more (Wait in decode state ST2).
  • the convolution operation circuit 4 starts the convolution operation (convolution operation 1).
  • the convolution operation circuit 4 performs the P operation on the first read semaphore S11R.
  • the convolution operation circuit 4 performs the V operation on the first write semaphore S11W.
  • the first DMAC 3 starts the DMA transfer described as "DMA transfer 3" in FIG. 24, the first write semaphore S11W is "0", so the first DMAC 3 waits until the first write semaphore S11W becomes "1" or more (Wait in decode state ST2). When the first write semaphore S11W becomes "1" or more by V operation by the convolution operation circuit 4, the first DMAC 3 starts DMA transfer.
  • the first DMAC 3 and the convolution operation circuit 4 of the first NN operation core 10A can prevent access contention to the first memory 1 in the first data flow F11.
  • the first DMAC 3 and the convolution circuit 4 of the first NN operation core 10A can operate independently and in parallel while synchronizing the data transfer in the first data flow F11 of the first NN operation core 10A by using the first semaphore S11.
  • FIG. 25 is a timing chart of the second data flow F12.
  • the second write semaphore S12W is a semaphore that restricts writing to the second memory 2 of the first NN operation core 10A by the convolution circuit 4 of the first NN operation core 10A in the second data flow F12 of the first NN operation core 10A.
  • the second write semaphore S12W indicates the number of memory areas in which data has been read and other data can be written, among memory areas in which data of a predetermined size such as output data f can be stored in the second memory 2 .
  • the convolution circuit 4 cannot write to the second memory 2 in the second data flow F12, and is kept waiting until the second write semaphore S12W becomes "1" or more.
  • the second read semaphore S12R is a semaphore that restricts reading from the second memory 2 of the first NN operation core 10A by the quantization operation circuit 5 of the first NN operation core 10A in the second data flow F2 of the first NN operation core 10A.
  • the second read semaphore S12R indicates the number of memory areas in which data has been written and can be read out of memory areas in which data of a predetermined size, such as output data f, can be stored in the second memory 2 .
  • the quantization arithmetic circuit 5 cannot read from the second memory 2 in the second data flow F12, and is kept waiting until the second read semaphore S12R becomes "1" or more.
  • the convolution operation circuit 4 of the first NN operation core 10A performs the P operation on the second write semaphore S12W when starting the convolution operation. After completing the convolution operation, the convolution operation circuit 4 performs V operation on the second read semaphore S12R.
  • the quantization operation circuit 5 of the first NN operation core 10A starts the quantization operation when the instruction command C5 is stored in the instruction queue 55. As shown in FIG. 25, since the second read semaphore S12R is "0", the quantization arithmetic circuit 5 is kept waiting until the second read semaphore S12R becomes "1" or more (Wait in decode state ST2). When the second read semaphore S12R becomes "1" by V operation by the convolution operation circuit 4, the quantization operation circuit 5 starts the quantization operation (quantization operation 1). When starting the quantization operation, the quantization operation circuit 5 performs the P operation on the second read semaphore S12R. After completing the quantization operation, the quantization operation circuit 5 performs V operation on the second write semaphore S12W.
  • the quantization operation circuit 5 starts the quantization operation described as "quantization operation 2" in FIG. 25, since the second read semaphore S12R is "0", the quantization operation circuit 5 is kept waiting until the second read semaphore S12R becomes "1" or more (Wait in decode state ST2). When the second read semaphore S12R becomes "1" or more by V operation by the convolution operation circuit 4, the quantization operation circuit 5 starts the quantization operation.
  • the convolution operation circuit 4 of the first NN operation core 10A and the quantization operation circuit 5 of the first NN operation core 10A can prevent access conflicts for the second memory 2 in the second data flow F12 by using the second semaphore S12. Further, the convolution operation circuit 4 of the first NN operation core 10A and the quantization operation circuit 5 of the first NN operation core 10A can operate independently and in parallel while synchronizing data transfer in the second data flow F12 by using the second semaphore S12.
  • FIG. 26 is a timing chart of the third data flow F13.
  • the third write semaphore S13W is a semaphore that restricts writing to the first memory 1 of the first NN operation core 10A by the quantization operation circuit 5 of the first NN operation core 10A in the third data flow F13 of the first NN operation core 10A.
  • the third write semaphore S13W indicates the number of memory areas in the first memory 1 that can store data of a predetermined size, such as the quantization operation output data of the quantization operation circuit 5, to which data has already been read and other data can be written.
  • the quantization arithmetic circuit 5 cannot write to the first memory 1 in the third data flow F13, and is kept waiting until the third write semaphore S13W becomes "1" or more.
  • the third read semaphore S13R is a semaphore that restricts reading from the first memory 1 of the first NN operation core 10A by the convolution operation circuit 4 of the first NN operation core 10A in the third data flow F13 of the first NN operation core 10A.
  • the third read semaphore S13R indicates the number of memory areas in which data has been written and can be read out of memory areas in which data of a predetermined size, such as quantization operation output data of the quantization operation circuit 5, can be stored in the first memory 1.
  • the third read semaphore S13R is "0"
  • the convolution circuit 4 cannot read from the first memory 1 in the third data flow F13, and is kept waiting until the third read semaphore S13R becomes "1" or more.
  • the quantization operation circuit 5 of the first NN operation core 10A performs the P operation on the third write semaphore S13W when starting the quantization operation. After completing the convolution operation, the quantization operation circuit 5 performs V operation on the third read semaphore S13R.
  • the convolution operation circuit 4 of the first NN operation core 10A starts the convolution operation.
  • the convolution operation circuit 4 is kept waiting until the third read semaphore S13R becomes "1" or more (Wait in decode state ST2).
  • the convolution operation circuit 4 starts the convolution operation (convolution operation 5).
  • the convolution operation circuit 4 performs the P operation on the third read semaphore S13R.
  • the convolution operation circuit 4 performs the V operation on the third write semaphore S13W.
  • the convolution operation circuit 4 starts the convolution operation described as "convolution operation 7" in FIG. 26, since the third read semaphore S13R is "0", the convolution operation circuit 4 waits until the third read semaphore S13R becomes "1" or more (Wait in decode state ST2). When the third read semaphore S13R becomes "1" or more by V operation by the quantization operation circuit 5, the convolution operation circuit 4 starts the convolution operation.
  • the quantization operation circuit 5 of the first NN operation core 10A and the convolution operation circuit 4 of the first NN operation core 10A can prevent access contention to the first memory 1 in the third data flow F13. Also, the quantization operation circuit 5 of the first NN operation core 10A and the convolution operation circuit 4 of the first NN operation core 10A can operate independently and in parallel while synchronizing the data transfer in the third data flow F13 by using the third semaphore S13.
  • FIG. 27 is a timing chart of the fourth data flow F14.
  • the fourth write semaphore S14W is a semaphore that restricts writing to the first memory 1 of the first NN operation core 10A by the quantization operation circuit 5 of the second NN operation core 10B in the fourth data flow F14 of the first NN operation core 10A.
  • the fourth write semaphore S14W indicates the number of memory areas in the first memory 1 that can store data of a predetermined size, such as the quantization operation output data of the quantization operation circuit 5, in which data has already been read and other data can be written.
  • the quantization arithmetic circuit 5 cannot write to the first memory 1 in the fourth data flow F14, and is kept waiting until the fourth write semaphore S14W becomes "1" or more.
  • the fourth read semaphore S14R is a semaphore that restricts reading from the first memory 1 of the first NN operation core 10A by the convolution operation circuit 4 of the first NN operation core 10A in the fourth data flow F14 of the first NN operation core 10A.
  • the fourth read semaphore S14R indicates the number of memory areas in which data has been written and can be read out of memory areas in which data of a predetermined size, such as quantization operation output data of the quantization operation circuit 5, can be stored in the first memory 1.
  • the fourth read semaphore S14R is "0"
  • the convolution circuit 4 cannot read from the first memory 1 in the fourth data flow F14, and is kept waiting until the fourth read semaphore S14R becomes "1" or more.
  • the quantization operation circuit 5 of the second NN operation core 10B performs the P operation on the fourth write semaphore S14W when starting the quantization operation. After completing the convolution operation, the quantization operation circuit 5 performs V operation on the fourth read semaphore S14R.
  • the convolution operation circuit 4 of the first NN operation core 10A starts the convolution operation.
  • the convolution circuit 4 is kept waiting until the fourth read semaphore S14R becomes "1" or more (Wait in decode state ST2).
  • the convolution operation circuit 4 starts the convolution operation (convolution operation 9).
  • the convolution operation circuit 4 performs the P operation on the fourth read semaphore S14R.
  • the convolution operation circuit 4 performs the V operation on the fourth write semaphore S14W.
  • the convolution operation circuit 4 starts the convolution operation described as "convolution operation 10" in FIG. 27, the fourth read semaphore S14R is "0", so the convolution operation circuit 4 waits until the fourth read semaphore S14R becomes "1" or more (Wait in decode state ST2). When the fourth read semaphore S14R becomes "1" or more by V operation by the quantization operation circuit 5, the convolution operation circuit 4 starts the convolution operation.
  • the quantization operation circuit 5 of the second NN operation core 10B and the convolution operation circuit 4 of the first NN operation core 10A can prevent access conflicts for the first memory 1 in the fourth data flow F14 by using the fourth semaphore S14. Further, the quantization operation circuit 5 of the second NN operation core 10B and the convolution operation circuit 4 of the first NN operation core 10A can operate independently and in parallel while synchronizing the data transfer between the plurality of NN operation cores 10 in the fourth data flow F14 by using the fourth semaphore S14.
  • the first memory 1 of the first NN operation core 10A is shared by three data flows (first data flow F11, third data flow F13 and fourth data flow F14).
  • first data flow F11 third data flow F13
  • fourth data flow F14 fourth data flow F14
  • the first data flow F21 of the second NN operation core 10B is equivalent to the first data flow F11 of the first NN operation core 10A.
  • the first DMAC 3 and the convolution operation circuit 4 of the second NN operation core 10B can prevent access contention to the first memory 1 in the first data flow F21 by using the first semaphore S21.
  • the first DMAC 3 and the convolution operation circuit 4 of the second NN operation core 10B can operate independently and in parallel while synchronizing the data transfer in the first data flow F21 of the second NN operation core 10B by using the first semaphore S21.
  • the second data flow F22 of the second NN operation core 10B is equivalent to the second data flow F12 of the first NN operation core 10A.
  • the convolution operation circuit 4 of the second NN operation core 10B and the quantization operation circuit 5 of the second NN operation core 10B can prevent access conflicts with respect to the second memory 2 in the second data flow F22 by using the second semaphore S22.
  • the convolution operation circuit 4 of the second NN operation core 10B and the quantization operation circuit 5 of the second NN operation core 10B can operate independently and in parallel while synchronizing data transfer in the second data flow F22 by using the second semaphore S22.
  • the third data flow F23 of the second NN operation core 10B is equivalent to the third data flow F13 of the first NN operation core 10A.
  • the quantization operation circuit 5 of the second NN operation core 10B and the convolution operation circuit 4 of the second NN operation core 10B can prevent access conflicts with respect to the first memory 1 in the third data flow F23 by using the third semaphore S23. Further, the quantization operation circuit 5 of the second NN operation core 10B and the convolution operation circuit 4 of the second NN operation core 10B can operate independently and in parallel while synchronizing data transfer in the third data flow F23 by using the third semaphore S23.
  • the fourth data flow F24 of the second NN operation core 10B is equivalent to the fourth data flow F14 of the first NN operation core 10A.
  • the quantization operation circuit 5 of the first NN operation core 10A and the convolution operation circuit 4 of the second NN operation core 10B can prevent access conflicts for the first memory 1 in the fourth data flow F24 by using the fourth semaphore S24. Further, the quantization operation circuit 5 of the first NN operation core 10A and the convolution operation circuit 4 of the second NN operation core 10B can operate independently and in parallel while synchronizing the data transfer between the plurality of NN operation cores 10 in the fourth data flow F24 by using the fourth semaphore S24.
  • the convolution operation circuit 4 of the first NN operation core 10A performs the convolution operation, it reads from the first memory 1 of the first NN operation core 10A and writes to the second memory 2 of the first NN operation core 10A. That is, the convolution operation circuit 4 is the Consumer in the three data flows (the first data flow F11, the third data flow F13, and the fourth data flow F14) and the Producer in the second data flow F12.
  • the convolution operation circuit 4 when starting the convolution operation, performs the P operation on the read semaphore (first read semaphore S11R, third read semaphore S13R, or fourth read semaphore S14R) corresponding to the data flow (see FIGS. 24, 26, and 27), and performs the P operation on the second write semaphore S12W (see FIG. 24).
  • the convolution operation circuit 4 After completing the convolution operation, the convolution operation circuit 4 performs V operation on the write semaphore corresponding to the data flow (first write semaphore S11W, third write semaphore S13W, fourth write semaphore S14W) (see FIGS. 24, 26, and 27), and performs V operation on the second read semaphore S12R (see FIG. 25).
  • the convolution operation circuit 4 of the first NN operation core 10A waits until the read semaphore (first read semaphore S11R, third read semaphore S13R, or fourth read semaphore S14R) corresponding to the data flow becomes "1" or more and the second write semaphore S12W becomes “1" or more (Wait in decode state ST2).
  • the quantization operation circuit 5 of the first NN operation core 10A reads from the second memory 2 of the first NN operation core 10A and writes to the first memory 1 of the first NN operation core 10A or the first memory 1 of the second NN operation core 10B. That is, the quantization arithmetic circuit 5 is the Consumer in the second data flow F12 and the Producer in the two data flows (the third data flow F13 and the fourth data flow F24). Therefore, when starting the quantization operation, the quantization operation circuit 5 performs the P operation on the second read semaphore S12R (see FIG.
  • the quantization operation circuit 5 performs V operation on the second write semaphore S12W (see FIG. 25), and performs V operation on the read semaphore (third read semaphore S13R or fourth read semaphore S24R) corresponding to the data flow (see FIG. 26).
  • the quantization operation circuit 5 of the first NN operation core 10A waits until the second read semaphore S12R becomes “1" or more and the write semaphore (third write semaphore S13W or fourth write semaphore S24W) corresponding to the data flow becomes "1" or more (Wait in decode state ST2).
  • the quantization operation circuit 5 of the first NN operation core 10A can switch between the third data flow F13 and the fourth data flow F24 to change the first memory 1 that stores the quantization operation output data.
  • the quantization operation circuit 5 of the second NN operation core 10B can switch between the third data flow F23 and the fourth data flow F14 to change the first memory 1 storing the quantization operation output data.
  • the NN circuit 100 that can be embedded in embedded equipment such as IoT equipment can be operated with high performance.
  • IoT equipment such as IoT equipment
  • a second embodiment of the present invention will be described with reference to FIGS. 28 to 31.
  • FIG. In the following description, the same reference numerals are given to the same configurations as those already described, and redundant descriptions will be omitted.
  • a neural network circuit 100B (hereinafter referred to as “NN circuit 100B”) according to the second embodiment differs from the neural network circuit 100 according to the first embodiment in the convolution operation circuit 4 .
  • the NN circuit 100B includes a first DMAC 3, a controller 6, an IFU 7, a shared memory 8, a second DMAC 9, and at least one neural network operation core 10E (hereinafter also referred to as "NN operation core 10E").
  • the NN operation core 10E includes a first memory 1, a second memory 2, a convolution operation circuit 4B, and a quantization operation circuit 5.
  • the convolution operation circuit 4B is a circuit that performs a convolution operation in the convolution layer 210 of the trained CNN 200.
  • the convolution operation circuit 4B reads the input data a stored in the first memory 1 and performs a convolution operation on the input data a.
  • the convolution operation circuit 4B writes the convolution operation output data to the second memory 2.
  • FIG. 28 is an internal block diagram of the convolution operation circuit 4B.
  • the convolution circuit 4B has a weight memory 41, a multiplier 42B, an accumulator circuit 43, and a state controller 44.
  • FIG. 29 is an internal block diagram of the multiplier 42.
  • a multiplier (arithmetic unit array) 42B multiplies each element a(x+i, y+j, ci) of the divided input data a(x+i, y+j, co) and each element w(i, j, ci, di) of the divided weight w(i, j, co, do).
  • the multiplier 42 has a Bc ⁇ Bd sum-of-products operation unit array 42A, and can perform parallel multiplication of the element a(x+i, y+j, ci) of the divided input data a(x+i, y+j, co) and the element w(i, j, ci, di) of the divided weight w(i, j, co, do).
  • the multiplier (arithmetic unit array) 42B reads out the elements a and w necessary for multiplication from the first memory 1 and the weight memory 41 and performs multiplication.
  • the multiplier 42 outputs Bd sum-of-products operation results O(x+i, y+j, di).
  • the number of product-sum operation unit arrays 42A included in the multiplier 42 is not limited to Bc ⁇ Bd.
  • the number of sum-of-products operation unit arrays 42A may be (Bc/P) ⁇ Bd (P is Bc or a divisor of Bc).
  • the sum-of-products operation unit array 42A divides the divided input data a(x+i, y+j, co) into P pieces in the c-axis direction.
  • the multiplier (arithmetic unit array) 42B reads the element a (x+i, y+j, ci), the element a (x+i, y+y1+j, ci), and the element a (x+i, y+y2+j, ci) from the first memory 1 (0 ⁇ y1 ⁇ y2).
  • the three sets of elements a are line data separated by a predetermined number of lines ST in the y-axis direction (ST is the stride in the y-axis direction).
  • the multiplier (arithmetic unit array) 42B may have a line memory that stores the element a.
  • the first memory 1 is preferably a multi-bank memory.
  • elements a(x+i, y+j, ci), elements a(x+i, y+y1+j, ci), and elements a(x+i, y+y2+j, ci) are stored in different banks, and each element is read independently at high speed.
  • FIG. 30 is an internal block diagram of the sum-of-products operation unit array 42A.
  • the sum-of-products operation unit array 42A multiplies the element a and the element w.
  • the sum-of-products operation unit array 42A has three sum-of-products operation units 47B.
  • the three sum-of-products operation units 47B are referred to as a first sum-of-products operation unit 471, a second sum-of-products operation unit 472, and a third sum-of-products operation unit 473.
  • FIG. 31 is an internal block diagram of the sum-of-products operation unit 47B.
  • the sum-of-products operation unit 47B multiplies the element A(ci) of the input vector A by the element W(ci, di) of the weight matrix W.
  • FIG. The sum-of-products operation unit 47 outputs the multiplication result s(ci).
  • Element A(ci) is a 2-bit unsigned integer (0, 1, 2, 3).
  • the element W(ci,di) is a 1-bit signed integer (0,1), where the value "0" represents +1 and the value "1" represents -1.
  • the sum-of-products operation unit 47B has an inverter (inverter) 47a, a selector 47b, and an adder 47c.
  • the sum-of-products operation unit 47 performs multiplication using only the inverter 47a and the selector 47b without using a multiplier.
  • the selector 47b selects the input of the element A(ci) when the element W(ci, di) is "0". When the element W(ci, di) is "1", the selector 47b selects the complement of the element A(ci) inverted by the inverter. Element W(ci, di) is also input to Carry-in of adder 47c.
  • the adder 47c outputs a value obtained by adding the element A(ci) to m(ci, di) when the element W(ci, di) is "0".
  • the adder 47c outputs a value obtained by subtracting the element A(ci) from m(ci, di) when W(ci, di) is "1".
  • the first sum-of-products operation unit 471 multiplies the element a (X, Y, ci) and the element w (i, j, ci, di) (X is an arbitrary x-coordinate included in the input data a, Y is an arbitrary y-coordinate included in the input data a).
  • the first sum-of-products operation unit 471 outputs the output m(i, j, ci, di) to the adder 47A.
  • the second sum-of-products operation unit 472 multiplies the element a (X, Y+y1, ci) and the element w (i, j+1, ci, di).
  • the second sum-of-products operation unit 472 outputs the output m(i, j+1, ci, di) to the adder 47A.
  • the third sum-of-products operation unit 473 multiplies the element a (X, Y+y2, ci) and the element w (i, j+2, ci, di).
  • the third sum-of-products operation unit 473 outputs the output m(i, j+2, ci, di) to the adder 47A.
  • the adder 47A adds the output m (i, j, ci, di), the output m (i, j+1, ci, di), the output m (i, j+2, ci, di), and the multiplication result S (x+i, y+j, ci, di) of the other product-sum operation unit 47B, and outputs the addition result S (x+i, y+j, ci+1, di).
  • operations can be parallelized by the sum-of-products operation unit array 42A, and convolution operations can be speeded up.
  • the neural network circuit 100B can suitably perform the convolution operation even if the stride ST in the y-axis direction in the convolution operation is 2 or more.
  • a third embodiment of the present invention will be described with reference to FIGS. 32 to 36.
  • FIG. In the following description, the same reference numerals are given to the same configurations as those already described, and redundant descriptions will be omitted.
  • a neural network circuit 100G (hereinafter referred to as "NN circuit 100G") according to the third embodiment further has a clock gating function and a power gating function compared to the neural network circuit 100 according to the first embodiment.
  • FIG. 32 is a diagram showing the overall configuration of the NN circuit 100G according to this embodiment.
  • the NN circuit 100G includes a first DMAC 3G, a controller 6, an IFU 7, a shared memory 8, a second DMAC 9, and at least one neural network operation core 10G (hereinafter also referred to as "NN operation core 10G"). Note that the NN circuit 100G may not have the shared memory 8 and the second DMAC 9.
  • FIG. 10G is a diagram showing the overall configuration of the NN circuit 100G according to this embodiment.
  • the NN circuit 100G includes a first DMAC 3G, a controller 6, an IFU 7, a shared memory 8, a second DMAC 9, and at least one neural network operation core 10G (hereinafter also referred to as "NN operation core 10G"). Note that the NN circuit 100G may not have the shared memory 8 and the second DMAC 9.
  • FIG. 10G neural network operation core 10G
  • the NN circuit 100G can implement a plurality of NN operation cores 10G.
  • the NN circuit 100G illustrated in FIG. 32 can implement up to four NN operation cores 10G.
  • a plurality of NN operation cores 10G constitute an "NN operation multi-core 10M" that cooperates to execute at least part of operations of the NN 200, like the NN operation cores 10 of the first embodiment.
  • a plurality of NN operation cores 10G are daisy-chained as in the first embodiment. Note that the number of NN operation cores 10 that can be implemented in the NN circuit 100G is not limited to four.
  • FIG. 33 is an internal block diagram of the first DMAC3G.
  • the first DMAC 3G like the first DMAC 3 of the first embodiment, is connected to the external bus EB and performs data transfer between the external memory 120 such as DRAM and the NN operation core 10G.
  • the first DMAC 3G has a data transfer circuit 31, a state controller 32, and a clock control section 39.
  • FIG. 34 is a timing chart showing the operation of the clock control section 39.
  • the clock control unit 39 generates a gated clock (third clock) GC3 from the clock CK supplied to the NN circuit 100G based on the clock enable signal CE3.
  • the clock enable signal CE3 is negated and set to disabled (Low in FIG. 34)
  • the toggling of the gated clock GC3 is stopped.
  • the clock enable signal CE3 is asserted and set to Enable (High in FIG. 34)
  • the gated clock GC3 starts toggling.
  • a circuit for generating the gated clock GC3 is a circuit appropriately selected from known clock gating circuits.
  • the clock enable signal CE3 is controlled by the state controller 32.
  • the control circuit 34 of the state controller 32 determines in the decode state ST2 that the operation of the data transfer circuit 31 instructed by the instruction command C3 cannot be executed, it waits until it becomes executable (Wait).
  • the control circuit 34 negates the clock enable signal CE3 to disable it during the waiting period until the above operation becomes executable. As a result, the toggling of the gated clock GC3 is stopped.
  • the control circuit 34 of the state controller 32 asserts and enables the clock enable signal CE3 when the above operation becomes executable and the decode state ST2 transitions to the execution state ST3. As a result, when the control circuit 34 is in the run state ST3, the toggling of the gated clock GC3 is resumed.
  • the generated gated clock GC3 is output to part of the state controller 32 and the data transfer circuit 31, as shown in FIG. 33, and used as an operating clock.
  • the clock control unit 39 may negate the clock enable signal CE3 to disable it in the idle state ST1. Furthermore, in the idle state ST1, the control circuit 34 may stop power supply (power gating) to the circuit to which the gated clock GC3 is supplied, and transition to the power saving mode.
  • the NN operation core 10G includes a first memory 1, a second memory 2, a convolution operation circuit 4G, and a quantization operation circuit 5G.
  • FIG. 35 is an internal block diagram of the convolution operation circuit 4G.
  • the convolution circuit 4G has a weight memory 41, a multiplier 42, an accumulator circuit 43, a state controller 44, and a clock control section 49.
  • the clock control unit 49 generates a gated clock (first clock) GC4 from the clock CK supplied to the NN circuit 100G based on the clock enable signal CE4. As shown in FIG. 34, when the clock enable signal CE4 is negated and set to disabled, the toggling of the gated clock GC4 is stopped. When the clock enable signal CE4 is asserted and set to enable, the gated clock GC4 starts toggling.
  • the clock control unit 49 has the same configuration as the clock control unit 39 of the first DMAC 3G.
  • the clock enable signal CE4 is controlled by the state controller 44.
  • the control circuit 46 of the state controller 44 determines in the decode state ST2 that the operation of the multiplier 42, the accumulator circuit 43, etc. indicated by the instruction command C4 cannot be executed, it waits until it becomes executable (Wait).
  • the control circuit 46 negates the clock enable signal CE4 to disable it during the period of waiting until the above operation becomes executable. As a result, the toggling of the gated clock GC4 is stopped.
  • the control circuit 46 of the state controller 44 asserts and enables the clock enable signal CE4 when the above operation becomes executable and the decode state ST2 transitions to the execution state ST3. As a result, when the control circuit 46 is in the run state ST3, the toggling of the gated clock GC4 is resumed.
  • the generated gated clock GC4 is output to part of the state controller 44, the weight memory 41, the multiplier 42, and the accumulator circuit 43, as shown in FIG. 35, and used as an operation clock.
  • the clock control unit 49 may negate the clock enable signal CE4 to disable it in the idle state ST1. Furthermore, in the idle state ST1, the control circuit 46 may stop power supply (power gating) to the circuit to which the gated clock GC4 is supplied, and transition to the power saving mode.
  • FIG. 36 is an internal block diagram of the quantization arithmetic circuit 5G.
  • the quantization operation circuit 5G has a quantization parameter memory 51, a vector operation circuit 52, a quantization circuit 53, a state controller 54, and a clock control section 59.
  • the clock control unit 59 generates a gated clock (third clock) GC5 from the clock CK supplied to the NN circuit 100G based on the clock enable signal CE5. As shown in FIG. 34, when the clock enable signal CE5 is negated and set to disabled, the toggling of the gated clock GC5 is stopped. When the clock enable signal CE5 is asserted and set to enable, the gated clock GC5 starts toggling.
  • the clock control section 59 has the same configuration as the clock control section 39 of the first DMAC 3G.
  • the clock enable signal CE5 is controlled by the state controller 54.
  • the control circuit 56 of the state controller 54 determines in the decode state ST2 that the operation of the vector operation circuit 52, the quantization circuit 53, etc., instructed by the instruction command C5 is not executable, it waits until it becomes executable (Wait).
  • the control circuit 56 negates the clock enable signal CE5 to disable it during the period of waiting until the above operation becomes executable.
  • the toggling of the gated clock GC5 is stopped.
  • the control circuit 56 of the state controller 54 asserts and enables the clock enable signal CE5 when the above operation becomes executable and the decode state ST2 transitions to the execution state ST3.
  • the control circuit 56 is in the run state ST3, the toggling of the gated clock GC5 is resumed.
  • the generated gated clock GC5 is output to part of the state controller 54, the quantization parameter memory 51, the vector operation circuit 52, and the quantization circuit 53, as shown in FIG. 36, and used as an operation clock.
  • the clock control unit 59 may negate the clock enable signal CE5 to disable it in the idle state ST1. Furthermore, in the idle state ST1, the control circuit 56 may stop supplying power (power gating) to the circuit to which the gated clock GC5 is supplied, and transition to the power saving mode.
  • power consumption can be reduced by clock gating and power gating.
  • the first DMAC 3G, the convolution operation circuit 4G, and the quantization operation circuit 5G independently perform clock gating and power gating.
  • a fourth embodiment of the present invention will be described with reference to FIG. In the following description, the same reference numerals are given to the same configurations as those already described, and redundant descriptions will be omitted.
  • a neural network circuit 100H (hereinafter referred to as "NN circuit 100H") according to the fourth embodiment further includes a multi-core manager 11 compared to the neural network circuit 100 according to the first embodiment.
  • FIG. 37 is a diagram showing the overall configuration of the NN circuit 100H according to this embodiment.
  • the NN circuit 100 ⁇ /b>H includes a first DMAC 3 , a controller 6 , an IFU 7 , a shared memory 8 , a second DMAC 9 , at least one NN operation core 10 and a multicore manager 11 .
  • the multi-core management unit 11 monitors the state of the NN calculation multi-core 10M and manages the clock and power supplied to the NN calculation core 10.
  • the clock and power are supplied to the operating NN operation cores 10 of the NN operation multi-core 10M, and the clock and power are not supplied to at least some of the NN operation cores 10 that are not operating. That is, the multi-core management unit 11 performs at least one of clock gating and power gating for each NN operation core 10 according to the operation status of the NN operation core 10 .
  • the NN circuit 100H can improve the arithmetic performance by mounting a plurality of the NN arithmetic cores 10, and can suitably suppress an increase in power consumption accompanying an increase in circuit scale.
  • the multi-core management unit 11 may be able to forcibly select an operable NN operation core 10. For example, the multi-core management unit 11 sets some NN operation cores 10 to be operable and other NN operation cores 10 to be inoperable. The multi-core management unit 11 stops providing clocks and power to the NN operation cores 10 set to be inoperable. By limiting the NN operation cores 10 that can operate, the multi-core management unit 11 can reduce the power consumption although the operation performance is degraded. In addition, the multi-core management unit 11 sets all the NN operation cores 10 to be operable, thereby improving the operation performance although the power consumption is increased.
  • power consumption can be reduced by clock gating and power gating.
  • the multi-core management unit 11 independently performs clock gating and power gating for each NN operation core 10 .
  • the NN circuit 100H may also perform the clock gating and power gating performed by the first DMAC 3G, the convolution operation circuit 4G and the quantization operation circuit 5G in the third embodiment.
  • the plurality of NN operation cores 10 are daisy-chained, but the manner of connection of the plurality of NN operation cores 10 is not limited to this.
  • the NN operation core 10 may be connected to at least one other NN operation core 10 so that data can be input/output.
  • the NN circuit 100 is controlled using a semaphore S provided for each data flow even when the connection modes of the plurality of NN operation cores 10 are different.
  • the first memory 1 and the second memory 2 are different memories, but the aspect of the first memory 1 and the second memory 2 is not limited to this.
  • the first memory 1 and the second memory 2 may be, for example, a first memory area and a second memory area in the same memory.
  • the semaphore S is provided for the first data flow (F11, F21), the second data flow (F12, F22), the third data flow (F13, F23), and the fourth data flow (F14, F24), but the aspect of the semaphore S is not limited to this.
  • the semaphore S may, for example, be provided in a data flow in which the first DMAC 3 writes the weight w to the weight memory 41 and the multiplier 42 reads the weight w.
  • the semaphore S may be provided, for example, in a data flow in which the first DMAC 3 writes the quantization parameter q to the quantization parameter memory 51 and the quantization circuit 53 reads the quantization parameter q.
  • the data input to the NN circuit 100 described in the above embodiments is not limited to a single format, and can consist of still images, moving images, voices, characters, numerical values, and combinations thereof.
  • the data input to the NN circuit 100 is not limited to the measurement results of a physical quantity measuring instrument such as an optical sensor, a thermometer, a Global Positioning System (GPS) measuring instrument, an angular velocity measuring instrument, and an anemometer that can be mounted on an edge device provided with the NN circuit 100.
  • Peripheral information such as base station information, vehicle/vessel information, weather information, and congestion information received from peripheral devices via wired or wireless communication, and different information such as financial information and personal information may be combined.
  • Edge devices provided with the NN circuit 100 are assumed to be communication devices such as mobile phones driven by batteries, smart devices such as personal computers, mobile devices such as digital cameras, game devices, and robot products, but are not limited to these. Unprecedented effects can also be obtained by using power on Ethernet (PoE), etc., to limit the peak power that can be supplied, reduce product heat generation, or use it for products that require long-time operation. For example, by applying it to in-vehicle cameras installed in vehicles and ships, surveillance cameras installed in public facilities and roads, etc., it is possible not only to realize long-time shooting, but also to contribute to weight reduction and durability. Similar effects can be obtained by applying the present invention to display devices such as televisions and displays, medical equipment such as medical cameras and surgical robots, and work robots used at manufacturing sites and construction sites.
  • PoE power on Ethernet
  • NN circuit 100 may implement part or all of NN circuit 100 using one or more processors.
  • the NN circuit 100 may implement part or all of the input layer or the output layer by software processing by a processor.
  • a part of the input layer or output layer realized by software processing is, for example, data normalization and transformation. This allows for various input or output formats.
  • the software executed by the processor may be rewritable using communication means or external media.
  • the NN circuit 100 may implement part of the processing in the CNN 200 by combining a graphics processing unit (GPU) on the cloud.
  • the NN circuit 100 performs further processing on the cloud in addition to the processing performed by the edge device provided with the NN circuit 100, or performs processing on the edge device in addition to the processing on the cloud, thereby realizing more complicated processing with less resources.
  • the NN circuit 100 can reduce the amount of communication between the edge device and the cloud due to processing distribution.
  • the present invention can be applied to neural network operations.

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