WO2023138449A1 - 核间中断执行方法、处理方法及装置、设备和存储介质 - Google Patents

核间中断执行方法、处理方法及装置、设备和存储介质 Download PDF

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WO2023138449A1
WO2023138449A1 PCT/CN2023/071686 CN2023071686W WO2023138449A1 WO 2023138449 A1 WO2023138449 A1 WO 2023138449A1 CN 2023071686 W CN2023071686 W CN 2023071686W WO 2023138449 A1 WO2023138449 A1 WO 2023138449A1
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interrupt
core
inter
hardware
interrupt processing
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PCT/CN2023/071686
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English (en)
French (fr)
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先凤新
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科东(广州)软件科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Definitions

  • the invention relates to the field of computer technology, in particular to an inter-core interrupt execution method, a processing method, a device, a device and a storage medium.
  • the polling method means that the receiver starts a process, and uses this process to continuously query whether there is data in the shared memory. Where data is available, data processing is performed immediately.
  • the interrupt method means that the sender notifies the receiver through the inter-core interrupt signal, and then the receiver wakes up the processing process in the interrupt processing function.
  • the real-time performance of the above polling method depends on the polling frequency. If the polling frequency is too high, a large amount of central processing unit (CPU) resources will be wasted. Therefore, inter-core communication is usually implemented in an interrupt manner. In the interrupt mode, it is necessary to modify the kernel code of the operating system to handle inter-core interrupts. This method needs to recompile the kernel, which cannot be realized in the scenario where the third party does not open source the kernel development.
  • the embodiments of the present application provide an inter-core interrupt execution method, processing method and device, equipment, and storage medium, which actually use the interrupt processing resources originally allocated for input and output interrupts in the interrupt processing system for inter-core interrupts, and realize the inter-core interrupt function without modifying the kernel code.
  • the third party does not open source the kernel development, the development convenience of the inter-core communication function is enhanced.
  • the first aspect of the present application provides an inter-core interrupt execution method, including:
  • the member function is preset as an inter-core interrupt processing function, so as to use the pre-allocated interrupt number for input and output interrupts for inter-core interrupts.
  • determining a structure associated with the hardware interrupt number for describing interrupt information includes:
  • executing a member function for interrupt processing in the structure includes:
  • the member function used for interrupt processing in the structure is called in the general interrupt handler.
  • the second aspect of the present application provides an inter-core interrupt processing method, including:
  • Allocate a structure for describing interrupt information in the interrupt processing system of the multi-core operating system
  • the member function used for interrupt processing in the structure is set as an inter-core interrupt processing function.
  • the allocating a hardware interrupt number for input and output interrupts in the interrupt domain of the interrupt processing system includes:
  • the hardware interrupt number is allocated in the interrupt field.
  • the associating the hardware interrupt number with the structure includes:
  • the setting is an inter-core interrupt processing function, it also includes:
  • the inter-core interrupt processing module is loaded into the kernel of the multi-core operating system by using a load module command.
  • the third aspect of the present application provides an inter-core interrupt execution device, including:
  • An acquisition unit configured to: acquire a hardware interrupt number from the received interrupt signal, where the hardware interrupt number is a pre-assigned interrupt number for input and output interrupts;
  • a determining unit configured to: determine a structure associated with the hardware interrupt number for describing interrupt information
  • the execution unit is configured to: execute a member function for interrupt processing in the structure, the member function is preset as an inter-core interrupt processing function, so as to use the pre-assigned interrupt number for input and output interrupts for inter-core interrupts.
  • the determining unit is configured to:
  • the execution unit is used for:
  • the member function used for interrupt processing in the structure is called in the general interrupt handler.
  • the fourth aspect of the present application provides an inter-core interrupt processing device, including:
  • the first allocation unit is configured to: allocate a structure for describing interrupt information in the interrupt processing system of the multi-core operating system;
  • the second allocating unit is used for: allocating a hardware interrupt number used for input and output interrupts in the interrupt domain of the interrupt processing system;
  • an associating unit configured to: associate the hardware interrupt number with the structure
  • the setting unit is configured to: set the member function used for interrupt processing in the structure as an inter-core interrupt processing function.
  • the second allocating unit is configured to:
  • the hardware interrupt number is allocated in the interrupt field.
  • the associating unit is configured to:
  • the above device further includes a loading unit, where the loading unit is used for:
  • an inter-core interrupt processing module is generated
  • the inter-core interrupt processing module is loaded into the kernel of the multi-core operating system by using a load module command.
  • the fifth aspect of the present application provides a computing device, including:
  • At least one memory which is connected to the processor and stores program instructions, and the program instructions, when executed by the at least one processor, cause the at least one processor to perform the method described in any one of the above first aspects.
  • a sixth aspect of the present application provides a computer-readable storage medium, on which program instructions are stored, and when the program instructions are executed by a computer, the computer executes the method described in any one of the above-mentioned first aspects.
  • Fig. 1 is a flow diagram of implementing inter-core communication in an interrupt mode
  • FIG. 2 is a schematic diagram of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of an execution flow of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application
  • FIG. 6 is a schematic diagram of an embodiment of an inter-core interrupt processing method provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an embodiment of an inter-core interrupt execution device provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of an embodiment of an inter-core interrupt processing device provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an embodiment of an inter-core interrupt processing device provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a computing device provided by an embodiment of the present application.
  • first, second, third, etc. or similar terms such as module A, module B, and module C in the description and claims are only used to distinguish similar objects, and do not represent a specific ordering of objects. It is understandable that the specific order or sequence can be interchanged if permitted, so that the embodiments of the application described here can be implemented in an order other than those illustrated or described here.
  • Asymmetric Multi-Processing (AMP) architecture Currently, there are two types of real-time operating system architectures that support multi-core processor platforms: Symmetric Multi-Processing (SMP) architecture and asymmetric multi-processing AM architecture. All CPUs in the SMP-based system share system memory and peripheral resources, and the operating system is responsible for inter-processor cooperation and maintains the consistency of data structures.
  • SMP Symmetric Multi-Processing
  • AM asymmetric multi-processing
  • users need to divide the hardware resources used by each operating system, and the cooperation between CPUs is limited to the use of shared memory. Due to the different degrees of cooperation between CPUs, AMP is called a loosely coupled multi-CPU system, and an SMP system is called a tightly coupled multi-CPU system.
  • X86 platform is a general term for a microprocessor architecture first developed by Intel. The hardware system built based on this microprocessor is called the X86 platform. For example, most PC devices are based on the X86 platform.
  • Interrupt Request (Interrupt ReQuest, IRQ): Since the CPU is continuously busy during the operation of the computer, when the hardware interface device starts or ends sending and receiving information, and the CPU needs to process the information calculation, it will send an interrupt request signal to the CPU through the IRQ, let the CPU store the work in progress, and then suspend the work at hand, and first process the needs of the peripheral hardware. This is what interrupt requests do. Because each component in the computer will have an independent IRQ, except for PCI cards that use the Peripheral Component Interconnect (PCI) bus, each component will occupy a separate IRQ and cannot be reused.
  • PCI Peripheral Component Interconnect
  • APIC Advanced Programmable Interrupt Controller
  • Interrupt Descriptor Table (Interrupt Descriptor Table, IDT): The interrupt descriptor table IDT is also called the interrupt vector table. Each of these entries is called an interrupt descriptor. When an interrupt occurs, pass the interrupt descriptor first, and then enter the corresponding processing program.
  • Load module command (install module, insmod): The insmod command is used to load the specified module into the kernel. Many functions in the Linux system are loaded into the kernel (kernel) when needed through modules.
  • Step 1 Core 1 (core 1) writes data to the shared memory.
  • Step 2 Core 1 (core 1) sends an inter-core interrupt signal to core 2 (core 2).
  • Step 3 Core 2 (core 2) wakes up the data processing process in the interrupt processing function.
  • the data processing process reads data from the shared memory.
  • the prior art has the following defects: currently, the inter-core communication is implemented in an interrupt mode, and the inter-core interrupt processing needs to be realized by modifying the kernel code of the operating system.
  • the linux kernel code is modified to handle inter-core interrupts. This method needs to recompile the kernel, which cannot be realized in the scenario where the third party does not open source the kernel development.
  • the present application provides a method for inter-core interrupt execution and inter-core interrupt processing.
  • the originally allocated hardware interrupt number for input and output interrupt (IO interrupt) is used to process the inter-core interrupt, and the member function of the structure associated with the hardware interrupt number is set as the inter-core interrupt processing function.
  • the interrupt processing resources originally allocated for IO interrupts in the interrupt processing system are actually used for inter-core interrupts. Therefore, the inter-core interrupt function can be realized without modifying the kernel code. Solved the problem that the inter-core communication function cannot be realized in the scenario where the third party does not open source the kernel development.
  • FIG. 2 is a schematic diagram of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application. As shown in Figure 2, the inter-core interrupt execution method may include:
  • Step S210 obtaining a hardware interrupt number from the received interrupt signal, where the hardware interrupt number is a pre-assigned interrupt number for input and output interrupts;
  • Step S220 determining a structure associated with the hardware interrupt number for describing interrupt information
  • Step S230 execute the member function for interrupt processing in the structure, the member function is preset as an inter-core interrupt processing function, so as to use the pre-assigned interrupt number for I/O interrupt for inter-core interrupt.
  • the local interrupt controller transmits the interrupt signal to the processor after receiving the interrupt signal.
  • the CPU suspends the current program that is running and transfers to execute the processing function corresponding to the interrupt signal, and then returns to the original suspended program to continue running after the execution is completed.
  • the hardware interrupt number of the interrupt signal is used as the offset of the interrupt descriptor table (IDT table) to determine the descriptor item (IDT item).
  • the IDT items in the IDT table can be divided into hardware reservations, IO interrupts, and inter-core interrupts. Among them, the hardware reserved part is not used, the IO interrupt part is provided to the interrupt request (IRQ) subsystem, and the inter-core interrupt part is used internally by the kernel.
  • the IRQ subsystem uses the structure irq_desc used to describe the interrupt information as an abstraction of the IDT item. That is to say, one IDT item corresponds to one irq_desc structure.
  • the irq_desc corresponding to the IDT item can be found through the offset of the IDT item, that is, through the hardware interrupt number.
  • the IO interrupt part in the IDT table is used to implement the inter-core interrupt function.
  • a hardware interrupt number for input and output interrupts is allocated in advance in the IRQ subsystem of the multi-core operating system, and a structure for describing interrupt information is allocated in the IRQ subsystem. Associate the above-mentioned hardware interrupt number with the above-mentioned structure. Since the above structure is a structure originally used to describe IO interrupt information, the member function in this structure may be a default IO interrupt processing function. In the embodiment of the present application, the member function in the structure is set as an inter-core interrupt processing function. Based on the above processing steps, the function of using the hardware interrupt number originally used for IO interrupts to process inter-core interrupts can be realized.
  • the hardware interrupt number allocated in the above processing steps may be used when inter-core communication is performed.
  • the core 1 sends an interrupt signal to the core 2, requesting the core 2 to suspend the current running program, and turn to execute the processing function corresponding to the interrupt signal.
  • the core receiving the interrupt signal can obtain the hardware interrupt number from the interrupt signal.
  • the hardware interrupt number was originally used for IO interrupts, and it is used here for inter-core interrupts.
  • the hardware interrupt number can be used as the offset of the interrupt descriptor table, and the structure associated with the hardware interrupt number is determined according to the offset.
  • the member functions in the structure are executed. This member function has been pre-set as an inter-core interrupt processing function, so executing this member function can realize the function of inter-core communication.
  • the interrupt processing resources originally allocated for input and output interrupts in the interrupt processing system are actually used for inter-core interrupts, and the inter-core interrupt function can be realized without modifying the kernel code.
  • the third party does not open source the kernel development, the development convenience of the inter-core communication function is enhanced.
  • FIG. 3 is a schematic diagram of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application. As shown in FIG. 3, in one implementation, step S220 in FIG. 2 determines the structure associated with the hardware interrupt number used to describe the interrupt information, which may specifically include:
  • Step S310 using the hardware interrupt number as an offset of an interrupt descriptor table, and determining a descriptor item corresponding to the hardware interrupt number in the interrupt descriptor table according to the offset;
  • Step S320 acquiring a structure corresponding to the descriptor item for describing interrupt information.
  • the hardware interrupt number can be used as the offset of the interrupt descriptor table. Different IDT entries have different offsets in the interrupt descriptor table. In addition, different IDT entries correspond to different interrupt requests. Each IDT item corresponds to an irq_desc structure used to describe the interrupt information. Therefore, you can first obtain the IDT item corresponding to the hardware interrupt number, and then obtain the irq_desc structure corresponding to the IDT item.
  • FIG. 4 is a schematic diagram of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application. As shown in FIG. 4, in one embodiment, step S230 in FIG. 2 executes the member function for interrupt processing in the structure, which may specifically include:
  • Step S410 executing the general interrupt handler pointed to by the descriptor item
  • Step S420 call the member function used for interrupt processing in the structure in the general interrupt handler.
  • the IDT table can be represented by an array.
  • Each item in this array is the address of a function to be executed.
  • the address of the function of each item in the array is the address of the common interrupt handler common_handler.
  • Each interrupt request corresponds to an IDT item. After receiving the interrupt request, find the address of the function in the corresponding IDT item. Therefore, all IO interrupts are executed from common_handler. That is, the generic interrupt handler pointed to by the descriptor item is executed.
  • transfer is performed according to the hardware interrupt number, that is, according to the offset, to execute the specific interrupt processing function corresponding to the hardware interrupt number.
  • the hardware interrupt number stored in the register can be read, and the corresponding IDT item can be judged by using the hardware interrupt number as an index, so as to find the structure corresponding to the IDT item, and then call the member function used for interrupt processing in the structure.
  • each IO interrupt corresponds to a specific interrupt processing function.
  • the address of each processing function is stored in the corresponding structure irg_desc.
  • These structures form an array irg_desc[IRQ]. That is to say, the address of the member function used for interrupt processing in the structure can be stored in an array.
  • Each element in the array is a structure irg_desc, which stores the address of the member function of each IDT item originally used for IO interrupt in the IDT table.
  • the array can be expressed as irg_desc[IRQ]; the member functions in the array can be expressed as irg_desc[IRQ]->handler().
  • the corresponding member function can be found in the array according to the hardware interrupt number.
  • FIG. 5 is a schematic diagram of an execution flow of an embodiment of an inter-core interrupt execution method provided by an embodiment of the present application. As shown in Figure 5, in an example, the interrupt processing flow of the X86 platform is:
  • the local APIC receives an interrupt signal and interrupts the current processing program of the CPU
  • the CPU determines the IDT item according to the hardware interrupt number of the interrupt signal as the offset of the IDT table. Start execution from the function address given in the IDT item.
  • the Linux system is based on the above-mentioned interrupt execution flow of the X86 platform.
  • the IDT items in the IDT table can be divided into hardware reservation, IO interrupt, and inter-core interrupt.
  • the hardware reserved part is not used
  • the IO interrupt part is provided to the interrupt request (IRQ) subsystem
  • the inter-core interrupt part is used internally by the kernel.
  • the last two IDT entries shown in Figure 5 are part of the inter-core interrupt.
  • the reserved parts of the hardware are not used and are not shown in FIG. 5 .
  • An IDT item corresponds to an irq_desc structure.
  • the irq_desc corresponding to the IDT item can be found through the offset of the IDT item, that is, through the hardware interrupt number.
  • the member function irq_desc[IRQ]->handler in the structure originally used for IO interrupts is replaced with the inter-core interrupt processing function ipi_handler.
  • the purpose of using the IO interrupt processing flow to process inter-core interrupts can be achieved.
  • FIG. 6 is a schematic diagram of an embodiment of an inter-core interrupt processing method provided by an embodiment of the present application. As shown in Figure 6, the inter-core interrupt processing method may include:
  • Step S610 allocating a structure for describing interrupt information in the interrupt processing system of the multi-core operating system
  • Step S620 allocating hardware interrupt numbers for input and output interrupts in the interrupt field of the interrupt processing system
  • Step S630 associating the hardware interrupt number with the structure
  • Step S640 setting the member function used for interrupt handling in the structure as an inter-core interrupt handling function.
  • the multi-core operating system in this embodiment of the present application may include a linux operating system.
  • the interrupt processing system of the multi-core operating system may include the IRQ subsystem of the linux kernel.
  • IRQ subsystem In the linux kernel IRQ subsystem, inter-core interrupts are not open to external use by default, and are only used as a function of the kernel's own internal process synchronization. However, on the X86 architecture, most of the interrupt processing resources can be allocated for different purposes, so this feature can be used to actually use the interrupt processing resources originally allocated for IO interrupts in the Linux kernel for inter-core interrupts.
  • the interrupt processing function corresponding to the interrupt request is registered with the kernel to realize the interrupt processing of the interrupt request.
  • the member function irq_desc[IRQ]->handler in the structure originally used for IO interrupts is replaced with the inter-core interrupt processing function ipi_handler.
  • the purpose of using the IO interrupt processing flow to process inter-core interrupts can be achieved.
  • an irq_desc structure needs to be used to make the IRQ subsystem identifiable.
  • An irq_desc structure can be allocated in the IRQ subsystem of the linux kernel, and then the irq_desc structure can be associated with specific entries in the IDT table.
  • the corresponding inter-core interrupt processing function ipi_handler can be found correctly according to the flow in FIG. 5 .
  • the embodiment of the present application may include the following steps:
  • step S610 a new irq_desc structure is allocated in the IRQ subsystem, and the structure is initialized.
  • empty elements in the irg_desc[IRQ] array can be assigned. For example, you can assign an array with a preset default value.
  • step S620 a hardware interrupt number (hardware irq number) originally used for IO is newly allocated in the interrupt domain (IRQ domain) of the IRQ subsystem.
  • IRQ domain can describe an interrupt source managed by an interrupt controller (IRQ Controller).
  • IRQ Domain can be regarded as the software abstraction of IRQ Controller.
  • the interrupt controller not only refers to the actual interrupt controller on the hardware, but also can be a "virtual" interrupt controller.
  • the so-called domain means domain and scope.
  • all interrupt controllers in the system can form a tree structure, and each interrupt controller can be connected with interrupt requests from several peripherals.
  • An interrupt request can be called an interrupt source.
  • the interrupt controller can number the interrupt sources connected to it according to their physical characteristics in the interrupt controller, that is, the hardware interrupt number. This number is limited only within the scope of the interrupt controller.
  • step S630 associate the hardware irq number with irq_desc.
  • step S640 the handler member function of the irq_desc is reset to the inter-core interrupt handler function ipi_handler.
  • the handler member function is the member function used for interrupt processing in the structure.
  • the interrupt processing resources originally allocated for input and output interrupts in the interrupt processing system can be actually used for inter-core interrupts, and the inter-core interrupt function can be realized without modifying the kernel code.
  • the third party does not open source the kernel development, the development convenience of the inter-core communication function is enhanced.
  • step S620 in FIG. 6, the allocation of hardware interrupt numbers for input and output interrupts in the interrupt field of the interrupt processing system may specifically include:
  • the hardware interrupt number is allocated in the interrupt field.
  • the interrupt number detection program can be used to detect whether the hardware interrupt number of each IO interrupt in the interrupt domain is occupied. If the hardware interrupt number is already occupied by a device, the interrupt number cannot be allocated. If the hardware interrupt number is not occupied, the interrupt number is allocated for inter-core interrupt. In the embodiment of the present application, through interrupt number detection, repeated allocation of interrupt numbers can be avoided, normal operation of the system can be ensured, and reliability and stability of the system can be improved.
  • step S630 in FIG. 6, associating the hardware interrupt number with the structure may specifically include:
  • a pointer array can be used to store the addresses of the structures corresponding to the hardware interrupt numbers. Each element of this array is a pointer variable.
  • the hardware interrupt number can be used to locate in the array and find the array element corresponding to the hardware interrupt number. Then assign the array element to the address of the structure corresponding to the hardware interrupt number, so that the array element points to the corresponding structure.
  • the setting is an inter-core interrupt processing function, it also includes:
  • the inter-core interrupt processing module is loaded into the kernel of the multi-core operating system by using a load module command.
  • a Linux module is a collection of functions and data types that can be compiled as a stand-alone program.
  • Linux's kernel module mechanism allows developers to dynamically add functionality to the kernel.
  • the processing procedure from step S610 to step S640 may be written as a module.
  • the inter-core interrupt function can be realized in the form of a module without modifying the kernel code. When you need to realize this function, you can use the insmod command to load the module into the kernel and use it.
  • the inter-core interrupt processing function is modularized, and the interrupt processing function irq_desc[IRQ]->handler in the structure originally used for IO interrupts is replaced by the inter-core interrupt processing function ipi_handler, and the interrupt processing resources originally allocated for input and output interrupts in the interrupt processing system are actually used for inter-core interrupts.
  • the inter-core interrupt processing function ipi_handler
  • the interrupt processing resources originally allocated for input and output interrupts in the interrupt processing system are actually used for inter-core interrupts.
  • the present application also provides an embodiment of a corresponding inter-core interrupt execution device.
  • the device includes:
  • the obtaining unit 710 is configured to: obtain a hardware interrupt number from the received interrupt signal, where the hardware interrupt number is a pre-assigned interrupt number for input and output interrupts;
  • a determining unit 720 configured to: determine a structure associated with the hardware interrupt number for describing interrupt information
  • the execution unit 730 is configured to: execute a member function for interrupt processing in the structure, the member function is preset as an inter-core interrupt processing function, so as to use the pre-assigned interrupt number for input and output interrupts for inter-core interrupts.
  • the determining unit 720 is used to:
  • the executing unit 730 is used to:
  • the member function used for interrupt processing in the structure is called in the general interrupt handler.
  • the present application also provides an embodiment of a corresponding inter-core interrupt processing device.
  • a corresponding inter-core interrupt processing device As shown in FIG. 8 , the present application also provides an embodiment of a corresponding inter-core interrupt processing device.
  • the device includes:
  • the first allocation unit 810 is configured to: allocate a structure used to describe interrupt information in the interrupt processing system of the multi-core operating system;
  • the second allocation unit 820 is configured to: allocate a hardware interrupt number used for input and output interrupts in the interrupt field of the interrupt processing system;
  • An associating unit 830 configured to: associate the hardware interrupt number with the structure
  • the setting unit 840 is configured to: set the member function used for interrupt processing in the structure as an inter-core interrupt processing function.
  • the second distribution unit 820 is used for:
  • the hardware interrupt number is allocated in the interrupt field.
  • the associating unit 830 is used to:
  • the above-mentioned device further includes a loading unit 850, and the loading unit 850 is used for:
  • an inter-core interrupt processing module is generated
  • the inter-core interrupt processing module is loaded into the kernel of the multi-core operating system by using a load module command.
  • FIG. 10 is a schematic structural diagram of a computing device 900 provided by an embodiment of the present application.
  • the computing device 900 includes: a processor 910 , a memory 920 , and a communication interface 930 .
  • the communication interface 930 in the computing device 900 shown in FIG. 10 can be used to communicate with other devices.
  • the processor 910 may be connected to the memory 920 .
  • the memory 920 can be used to store the program codes and data. Therefore, the memory 920 may be a storage unit inside the processor 910 , or an external storage unit independent of the processor 910 , or a component including a storage unit inside the processor 910 and an external storage unit independent of the processor 910 .
  • computing device 900 may further include a bus.
  • the memory 920 and the communication interface 930 may be connected to the processor 910 through a bus.
  • the bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (Extended Industry Standard Architecture, EISA) bus or the like.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • the bus can be divided into address bus, data bus, control bus and so on.
  • the processor 910 may be a central processing unit (central processing unit, CPU).
  • the processor can also be other general processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (Application specific integrated circuit, ASIC), off-the-shelf programmable gate matrix (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
  • the processor 910 adopts one or more integrated circuits for executing related programs, so as to implement the technical solutions provided by the embodiments of the present application.
  • the memory 920 may include read-only memory and random-access memory, and provides instructions and data to the processor 910 .
  • a portion of processor 910 may also include non-volatile random access memory.
  • processor 910 may also store device type information.
  • the processor 910 executes the computer-executed instructions in the memory 920 to perform the operation steps of the above method.
  • the computing device 900 may correspond to a corresponding subject executing the method according to each embodiment of the present application, and the above-mentioned and other operations and/or functions of each module in the computing device 900 are respectively for realizing the corresponding process of each method of the present embodiment, and for the sake of brevity, details are not repeated here.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art or a part of the technical solution.
  • the computer software product is stored in a storage medium and includes several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the application.
  • the aforementioned storage media include: various media that can store program codes such as U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc.
  • the embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored.
  • the program When the program is executed by a processor, it is used to execute a method for generating a variety of questions, and the method includes at least one of the solutions described in the above-mentioned embodiments.
  • the computer storage medium in the embodiments of the present application may use any combination of one or more computer-readable media.
  • the computer readable medium may be a computer readable signal medium or a computer readable storage medium.
  • a computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • a computer readable signal medium may include a data signal carrying computer readable program code in baseband or as part of a carrier wave. Such propagated data signals may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer readable signal medium may also be any computer readable medium other than a computer readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
  • Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • Computer program code for carrying out the operations of the present application may be written in one or more programming languages, or combinations thereof, including object-oriented programming languages—such as Java, Smalltalk, C++, and conventional procedural programming languages—such as the “C” language or similar programming languages.
  • the program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
  • the remote computer can be connected to the user computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or, alternatively, can be connected to an external computer (e.g., through an Internet connection using an Internet service provider).
  • LAN local area network
  • WAN wide area network
  • Internet service provider e.g., AT&T, MCI, Sprint, EarthLink, MSN, GTE, etc.

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Abstract

本申请实施例涉及计算机技术领域，且涉及一种核间中断执行方法、处理方法及装置、设备和存储介质。其中，核间中断执行方法的具体实现方案为：从接收到的中断信号中获取硬件中断号，所述硬件中断号是预先分配的用于输入输出中断的中断号；确定与所述硬件中断号关联的用于描述中断信息的结构体；执行所述结构体中用于中断处理的成员函数，所述成员函数被预先设置为核间中断处理函数。本申请实施例将中断处理系统中原分配用于输入输出中断的中断处理资源实际用于核间中断，在不修改内核代码的情况下，即可实现核间中断功能。尤其在第三方不开源内核开发的场景下，增强了核间通信功能的开发便利性。

Description

核间中断执行方法、处理方法及装置、设备和存储介质 技术领域
本发明涉及计算机技术领域，尤其涉及核间中断执行方法、处理方法及装置、设备和存储介质。
背景技术
现有多核操作系统的非对称多处理(Asymmetric Multi-Processing，AMP)架构下，共享内存核间通信的实现方式一般分为轮询方式和中断方式。轮询方式即接收方启动一个进程，利用该进程一直查询共享内存是否有数据。在有数据的情况下，立即进行数据处理。中断方式即发送方通过核间中断信号通知接收方，然后接收方在中断处理函数里唤醒处理进程。
上述轮询方式的实时性取决于轮询频率。如果轮询频率太高，会浪费中央处理器(central processing unit，CPU)大量资源。因此，通常以中断方式实现核间通信。在中断方式中，需要通过修改操作系统内核代码实现对核间中断的处理。这种方式需要重新编译内核，在第三方不开源内核开发的场景下，无法实现该功能。
发明内容
鉴于现有技术的以上问题，本申请实施例提供一种核间中断执行方法、处理方法及装置、设备和存储介质，将中断处理系统中原分配用于输入输出中断的中断处理资源实际用于核间中断，在不修改内核代码的情况下，即可实现核间中断功能。尤其在第三方不开源内核开发的场景下，增强了核间通信功能的开发便利性。
为达到上述目的，本申请第一方面提供了一种核间中断执行方法，包括：
从接收到的中断信号中获取硬件中断号，所述硬件中断号是预先分配的用于输入输出中断的中断号；
确定与所述硬件中断号关联的用于描述中断信息的结构体；
执行所述结构体中用于中断处理的成员函数，所述成员函数被预先设置为核间中断处理函数，以将所述预先分配的用于输入输出中断的中断号用于核间中断。
作为第一方面的一种可能的实现方式，确定与所述硬件中断号关联的用于描述中断信息的结构体，包括：
将所述硬件中断号作为中断描述符表的偏移量，根据所述偏移量在所述中断描述符表中确定所述硬件中断号对应的描述符项；
获取所述描述符项对应的用于描述中断信息的结构体。
作为第一方面的一种可能的实现方式，执行所述结构体中用于中断处理的成员函数，包括：
执行所述描述符项指向的通用中断处理程序；
在所述通用中断处理程序中调用所述结构体中用于中断处理的成员函数。
本申请第二方面提供了一种核间中断处理方法，包括：
在多核操作系统的中断处理系统中分配用于描述中断信息的结构体；
在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号；
将所述硬件中断号与所述结构体进行关联；
将所述结构体中用于中断处理的成员函数设置为核间中断处理函数。
作为第二方面的一种可能的实现方式，所述在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号，包括：
检测所述中断域中用于输入输出中断的硬件中断号是否被占用；
在所述硬件中断号没有被占用的情况下，在所述中断域中分配所述硬件中断号。
作为第二方面的一种可能的实现方式，所述将所述硬件中断号与所述结构体进行关联，包括：
将所述结构体的地址赋值给所述硬件中断号对应的指针变量。
作为第二方面的一种可能的实现方式，所述设置为核间中断处理函数后，还包括：
生成核间中断处理模块；
利用载入模块命令，将所述核间中断处理模块载入到所述多核操作系统的内核中。
本申请第三方面提供了一种核间中断执行装置，包括：
获取单元，用于：从接收到的中断信号中获取硬件中断号，所述硬件中断号是预先分配的用于输入输出中断的中断号；
确定单元，用于：确定与所述硬件中断号关联的用于描述中断信息的结构体；
执行单元，用于：执行所述结构体中用于中断处理的成员函数，所述成员函数被预先设置为核间中断处理函数，以将所述预先分配的用于输入输出中断的中断号用于核间中断。
作为第三方面的一种可能的实现方式，所述确定单元用于：
将所述硬件中断号作为中断描述符表的偏移量，根据所述偏移量在所述中断描述符表中确定所述硬件中断号对应的描述符项；
获取所述描述符项对应的用于描述中断信息的结构体。
作为第三方面的一种可能的实现方式，所述执行单元用于：
执行所述描述符项指向的通用中断处理程序；
在所述通用中断处理程序中调用所述结构体中用于中断处理的成员函数。
本申请第四方面提供了一种核间中断处理装置，包括：
第一分配单元，用于：在多核操作系统的中断处理系统中分配用于描述中断信息的结构体；
第二分配单元，用于：在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号；
关联单元，用于：将所述硬件中断号与所述结构体进行关联；
设置单元，用于：将所述结构体中用于中断处理的成员函数设置为核间中断处理函数。
作为第四方面的一种可能的实现方式，所述第二分配单元用于：
检测所述中断域中用于输入输出中断的硬件中断号是否被占用；
在所述硬件中断号没有被占用的情况下，在所述中断域中分配所述硬件中断号。
作为第四方面的一种可能的实现方式，所述关联单元用于：
将所述结构体的地址赋值给所述硬件中断号对应的指针变量。
作为第四方面的一种可能的实现方式，上述装置还包括载入单元，所述载入单元用于：
所述设置为核间中断处理函数后，生成核间中断处理模块；
利用载入模块命令，将所述核间中断处理模块载入到所述多核操作系统的内核中。
本申请第五方面提供了一种计算设备，包括：
通信接口；
至少一个处理器，其与所述通信接口连接；以及
至少一个存储器，其与所述处理器连接并存储有程序指令，所述程序指令当被所述至少一个处理器执行时使得所述至少一个处理器执行上述第一方面任一所述的方法。
本申请第六方面提供了一种计算机可读存储介质，其上存储有程序指令，所述程序指令当被计算机执行时使得所述计算机执行上述第一方面任一所述的方法。
本发明的这些和其它方面在以下(多个)实施例的描述中会更加简明易懂。
附图说明
以下参照附图来进一步说明本发明的各个特征和各个特征之间的联系。附图均为示例性的，一些特征并不以实际比例示出，并且一些附图中可能省略了本申请所涉及领域的惯常的且对于本申请非必要的特征，或是额外示出了对于本申请非必要的特征，附图所示的各个特征的组合并不用以限制本申请。另外，在本说明书全文中，相同的附图标记所指代的内容也是相同的。具体的附图说明如下：
图1为以中断方式实现核间通信的流程示意图；
图2为本申请实施例提供的核间中断执行方法的一实施例的示意图；
图3为本申请实施例提供的核间中断执行方法的一实施例的示意图；
图4为本申请实施例提供的核间中断执行方法的一实施例的示意图；
图5为本申请实施例提供的核间中断执行方法的一实施例的执行流程示意图；
图6为本申请实施例提供的核间中断处理方法的一实施例的示意图；
图7为本申请实施例提供的核间中断执行装置的一实施例的示意图；
图8为本申请实施例提供的核间中断处理装置的一实施例的示意图；
图9为本申请实施例提供的核间中断处理装置的一实施例的示意图；
图10为本申请实施例提供的计算设备的示意图。
具体实施方式
说明书和权利要求书中的词语“第一、第二、第三等”或模块A、模块B、模块 C等类似用语，仅用于区别类似的对象，不代表针对对象的特定排序，可以理解地，在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本申请实施例能够以除了在这里图示或描述的以外的顺序实施。
在以下的描述中，所涉及的表示步骤的标号，如S110、S120……等，并不表示一定会按此步骤执行，在允许的情况下可以互换前后步骤的顺序，或同时执行。
说明书和权利要求书中使用的术语“包括”不应解释为限制于其后列出的内容；它不排除其它的元件或步骤。因此，其应当诠释为指定所提到的所述特征、整体、步骤或部件的存在，但并不排除存在或添加一个或更多其它特征、整体、步骤或部件及其组群。因此，表述“包括装置A和B的设备”不应局限为仅由部件A和B组成的设备。
本说明书中提到的“一个实施例”或“实施例”意味着与该实施例结合描述的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在本说明书各处出现的用语“在一个实施例中”或“在实施例中”并不一定都指同一实施例，但可以指同一实施例。此外，在一个或多个实施例中，能够以任何适当的方式组合各特定特征、结构或特性，如从本公开对本领域的普通技术人员显而易见的那样。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。如有不一致，以本说明书中所说明的含义或者根据本说明书中记载的内容得出的含义为准。另外，本文中所使用的术语只是为了描述本申请实施例的目的，不是旨在限制本申请。为了准确地对本申请中的技术内容进行叙述，以及为了准确地理解本发明，在对具体实施方式进行说明之前先对本说明书中所使用的术语给出如下的解释说明或定义：
1)非对称多处理(Asymmetric Multi-Processing，AMP)架构：目前支持多核处理器平台的实时操作系统体系结构有对称多处理(Symmetric Multi-Processing，SMP)构架和非对称多处理AM构架两种。SMP构架的系统中所有CPU共享系统内存和外设资源，由操作系统负责处理器间协作，并保持数据结构的一致性。而在AMP构架的系统中，用户需要对各个操作系统使用的硬件资源进行划分，CPU间的合作仅限于使用共享存储器的情况。由于CPU间的合作程度不同，AMP则称为松散耦合多CPU系统，SMP系统称为紧耦合多CPU系统。
2)X86平台：x86是英特尔Intel首先开发的一种微处理器体系结构的泛称。基于这种微处理器搭建起来的硬件系统称为X86平台。例如大部分的PC设备都是以X86平台为基础搭建的。
3)中断请求(Interrupt ReQuest，IRQ)：由于在计算机运行中，CPU是持续处于忙碌状态，而当硬件接口设备开始或结束收发信息，需要CPU处理信息运算时，便会透过IRQ对CPU送出中断请求讯号，让CPU储存正在进行的工作，然后暂停手边的工作，先行处理周边硬件提出的需求。这便是中断请求的作用。因为计算机中每个组成组件都会拥有一个独立的IRQ，除了使用外设部件互连标准(Peripheral Component Interconnect，PCI)总线的PCI卡之外，每一组件都会单独占用一个IRQ，且不能重复使用。
4)高级可编程中断控制器(Advanced Programmable Interrupt Controller，APIC)： APIC负责传递中断(Interrupt)至指定的处理器。举例来说，当一台机器上有三个处理器，则它必须相对地要有三个本地APIC。
5)中断描述符表(Interrupt Descriptor Table，IDT)：中断描述符表IDT也称为中断向量表。其中的每个表项叫做一个中断描述符。当中断发生时先通过中断描述符，然后才能进入相应的处理程序。
6)载入模块命令(install module，insmod)：insmod命令用于将指定的模块加载到内核中。Linux系统中有许多功能是通过模块的方式，在需要时才载入内核(kernel)。
下面先对现有的方法进行介绍，然后再对本申请的技术方案进行详细介绍。
现有技术：以中断方式实现核间通信的过程如图1所示，具体如下：
步骤1：核1(core 1)向共享内存写数据。
步骤2：核1(core 1)向核2(core 2)发送核间中断信号。
步骤3：核2(core 2)在中断处理函数里唤醒数据处理进程。数据处理进程从共享内存里读出数据。
现有技术存在着以下的缺陷：目前以中断方式实现核间通信，需要通过修改操作系统内核代码实现对核间中断的处理。在AMP架构上的linux操作系统中，都是修改linux内核代码实现对核间中断的处理。这种方式需要重新编译内核，在第三方不开源内核开发的场景下，无法实现该功能。
基于上述现有技术所存在的技术问题，本申请提供了一种核间中断执行和核间中断处理的方法。本申请实施例将原来分配的用于输入输出中断(IO中断)的硬件中断号，用来处理核间中断，并将该硬件中断号关联的结构体的成员函数设置为核间中断处理函数。基于以上技术手段将中断处理系统中原分配用于IO中断的中断处理资源实际用于核间中断。因此，在不修改内核代码的情况下，即可实现核间中断功能。解决了在第三方不开源内核开发的场景下无法实现核间通信功能的问题。
图2为本申请实施例提供的核间中断执行方法的一实施例的示意图。如图2所示，该核间中断执行方法可以包括：
步骤S210，从接收到的中断信号中获取硬件中断号，所述硬件中断号是预先分配的用于输入输出中断的中断号；
步骤S220，确定与所述硬件中断号关联的用于描述中断信息的结构体；
步骤S230，执行所述结构体中用于中断处理的成员函数，所述成员函数被预先设置为核间中断处理函数，以将所述预先分配的用于输入输出中断的中断号用于核间中断。
在多核操作系统中，本地中断控制器收到中断信号后，将中断信号传递给处理器。CPU暂停正在运行的当前程序并转入执行中断信号对应的处理函数，执行完毕后再返回原被暂停的程序继续运行。
CPU暂停正在运行的当前程序后，将中断信号的硬件中断号作为中断描述符表(IDT表)的偏移量，确定描述符项(IDT项)。IDT表中的IDT项可分为硬件保留、 IO中断、核间中断几个部分。其中，硬件保留部分不使用，IO中断部分提供给中断请求(IRQ)子系统使用，核间中断部分内核内部使用。
IRQ子系统将用于描述中断信息的结构体irq_desc作为IDT项的抽象。也就是说，一个IDT项对应一个irq_desc结构体。可通过IDT项的偏移量，即通过硬件中断号，可找到与IDT项对应的irq_desc。
本申请实施例中，利用IDT表中的IO中断部分实现核间中断的功能。具体地，预先在多核操作系统的IRQ子系统中分配一个用于输入输出中断的硬件中断号，以及在IRQ子系统中分配一个用于描述中断信息的结构体。将上述硬件中断号与上述结构体进行关联。由于上述结构体是原来用于描述IO中断信息的结构体，该结构体中的成员函数可能是一个默认的IO中断处理函数。本申请实施例中，将该结构体中的成员函数设置为核间中断处理函数。基于以上处理步骤可实现将原用于IO中断的硬件中断号，用于处理核间中断的功能。
本申请实施例中，在进行核间通信时，可使用上述处理步骤中分配的硬件中断号。例如，内核1向内核2发送中断信号，请求内核2暂停正在运行的当前程序，去转向执行中断信号对应的处理函数。在步骤S210中，接收到中断信号的内核可从中断信号中获取硬件中断号。该硬件中断号原本是用于IO中断的，在这里将其用于核间中断。在步骤S220中，可将硬件中断号作为中断描述符表的偏移量，根据偏移量确定与硬件中断号关联的结构体。在步骤S230中执行结构体中的成员函数。该成员函数已被预先设置为核间中断处理函数，因此执行该成员函数可以实现核间通信的功能。
本申请实施例将中断处理系统中原分配用于输入输出中断的中断处理资源实际用于核间中断，在不修改内核代码的情况下，即可实现核间中断功能。尤其在第三方不开源内核开发的场景下，增强了核间通信功能的开发便利性。
图3为本申请实施例提供的核间中断执行方法的一实施例的示意图。如图3所示，在一种实施方式中，图2中的步骤S220，确定与所述硬件中断号关联的用于描述中断信息的结构体，具体可包括：
步骤S310，将所述硬件中断号作为中断描述符表的偏移量，根据所述偏移量在所述中断描述符表中确定所述硬件中断号对应的描述符项；
步骤S320，获取所述描述符项对应的用于描述中断信息的结构体。
在IRQ子系统中，可将硬件中断号作为中断描述符表的偏移量。不同的IDT项中在断描述符表中具有不同的偏移量。另外，不同的IDT项对应着不同的中断请求。每个IDT项又对应一个用于描述中断信息的irq_desc结构体。因此，可以先获取硬件中断号对应的IDT项，再获取IDT项对应的irq_desc结构体。
图4为本申请实施例提供的核间中断执行方法的一实施例的示意图。如图4所示，在一种实施方式中，图2中的步骤S230，执行所述结构体中用于中断处理的成员函数，具体可包括：
步骤S410，执行所述描述符项指向的通用中断处理程序；
步骤S420，在所述通用中断处理程序中调用所述结构体中用于中断处理的成员函数。
在一个示例中，IDT表可以用一个数组来表示。该数组中的每一项是一个待执行的函数的地址。对于IO中断而言，数组中的每一项的函数的地址都是通用中断处理程序common_handler的地址。每个中断请求对应一个IDT项，接收到中断请求后，找到对应的IDT项中的函数的地址。因此，所有的IO中断都是从common_handler开始执行。也就是说，执行描述符项指向的通用中断处理程序。
在通用中断处理程序中，再根据硬件中断号，也就是根据偏移量进行中转，去执行硬件中断号对应的具体的中断处理函数。其中，在通用中断处理程序中，可读取寄存器中存储的硬件中断号，以硬件中断号作为索引，可判断对应的IDT项，从而找到IDT项对应的结构体，再调用结构体中用于中断处理的成员函数。
其中，每个IO中断对应一个具体的中断处理函数。每个处理函数的地址存储在对应的结构体irg_desc中。这些结构体构成一个数组irg_desc[IRQ]。也就是说，结构体中用于中断处理的成员函数的地址可以保存在一个数组中。数组中的每个元素是结构体irg_desc，结构体中存储有IDT表中的每个原本用于IO中断的IDT项的成员函数的地址。该数组可以表示为irg_desc[IRQ]；该数组中的成员函数可以表示为irg_desc[IRQ]->handler()。在上述步骤S420中，可根据硬件中断号，在该数组中找到对应的成员函数。
图5为本申请实施例提供的核间中断执行方法的一实施例的执行流程示意图。如图5所示，在一个示例中，X86平台的中断处理流程为：
1)本地APIC收到一个中断信号，中断CPU当前处理程序；
2)CPU根据该中断信号的硬件中断号作为IDT表的偏移量，确定IDT项。从IDT项中给定的函数地址开始执行。
Linux系统根据上述X86平台的中断执行流程。参见图5，IDT表中的IDT项可分为硬件保留、IO中断、核间中断几个部分。其中，硬件保留部分不使用，IO中断部分提供给中断请求(IRQ)子系统使用，核间中断部分内核内部使用。图5中所示的最后两个IDT项为核间中断部分。硬件保留部分不使用，在图5中没有画出。一个IDT项对应一个irq_desc结构体。可通过IDT项的偏移量，即通过硬件中断号，可找到与IDT项对应的irq_desc。
参见图5，本申请实施例中，将原来用于IO中断的结构体中的成员函数irq_desc[IRQ]->handler替换为核间中断处理函数ipi_handler，基于以上技术手段即可达到利用IO中断处理流程来处理核间中断的目的。
图6为本申请实施例提供的核间中断处理方法的一实施例的示意图。如图6所示，该核间中断处理方法可以包括：
步骤S610，在多核操作系统的中断处理系统中分配用于描述中断信息的结构体；
步骤S620，在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号；
步骤S630，将所述硬件中断号与所述结构体进行关联；
步骤S640，将所述结构体中用于中断处理的成员函数设置为核间中断处理函数。
本申请实施例中的多核操作系统可包括linux操作系统。多核操作系统的中断处 理系统可包括linux内核的IRQ子系统。在linux内核IRQ子系统中，默认对于核间中断不开放给外部使用，只用来作为内核自身内部进程同步的功能。但是X86架构上，大部分的中断处理资源都可以分配为不同的用途，因此可以利用这一特性将linux内核中原分配用于IO中断的中断处理资源实际用于核间中断。同时通过模拟IRQ子系统初始化时对中断的初始化流程，向内核注册该中断请求对应的中断处理函数，实现对该中断请求的中断处理。
再参见图5，本申请实施例中，将原来用于IO中断的结构体中的成员函数irq_desc[IRQ]->handler替换为核间中断处理函数ipi_handler，基于以上技术手段可达到利用IO中断处理流程来处理核间中断的目的。具体地，需要利用一个使IRQ子系统能识别的irq_desc结构体。可以在linux内核的IRQ子系统中分配一个irq_desc结构体，然后将该irq_desc结构体和IDT表中的具体表项联系起来。在此基础上，当收到核间中断请求时，按照图5的流程可以正确找到对应的核间中断处理函数ipi_handler。
参见图5和图6，本申请实施例可包括以下步骤：
在步骤S610中，在IRQ子系统中新分配一个irq_desc结构体，并初始化该结构体。在这一步骤中，可以将irg_desc[IRQ]数组中的空的元素赋值。例如可以用预先设置的默认值为数组赋值。
在步骤S620中，在IRQ子系统的中断域(IRQ domain)中新分配一个原用于IO的硬件中断号(硬件irq号)。
其中，Linux使用IRQ domain来描述一个中断控制器(IRQ Controller)所管理的中断源。换句话说，每个中断控制器都有自己的domain。可以将IRQ Domain看作是IRQ Controller的软件抽象。中断控制器不仅指硬件上实际存在的中断控制器，也可以是一个“虚拟”的中断控制器。所谓domain，就是领域、范围的意思。在一个示例中系统中所有的中断控制器可形成树状结构，对于每个中断控制器都可以连接若干个外设的中断请求。中断请求可以称之为中断源(interrupt source)。中断控制器可以对连接其上的中断源，根据其在中断控制器中物理特性进行编号，也就是硬件中断号。这个编号仅仅限制在本中断控制器范围内。
在步骤S630中，将该硬件irq号和irq_desc联系起来。
在步骤S640中，将该irq_desc的handler成员函数重新设置为核间中断处理函数ipi_handler。其中，handler成员函数即为结构体中用于中断处理的成员函数。
利用本申请实施例提供的核间中断处理方法，可将中断处理系统中原分配用于输入输出中断的中断处理资源实际用于核间中断，在不修改内核代码的情况下，即可实现核间中断功能。尤其在第三方不开源内核开发的场景下，增强了核间通信功能的开发便利性。
在一种实施方式中，图6中的步骤S620，所述在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号，具体可包括：
检测所述中断域中用于输入输出中断的硬件中断号是否被占用；
在所述硬件中断号没有被占用的情况下，在所述中断域中分配所述硬件中断号。
在这种实施方式中，可利用中断号检测程序检测中断域中的各个IO中断的硬件中断号有没有被占用。如果该硬件中断号已经被某个设备占用，则不能分配该中断号。如果该硬件中断号没有被占用，则分配该中断号用于核间中断。本申请实施例通过中断号检测，可避免中断号被重复分配，保证系统正常运行，提高系统的可靠性和稳定性。
在一种实施方式中，图6中的步骤S630，所述将所述硬件中断号与所述结构体进行关联，具体可包括：
将所述结构体的地址赋值给所述硬件中断号对应的指针变量。
在这种实施方式中，可以用一个指针数组存储硬件中断号对应的各个结构体的地址。该数组的每个元素都是指针变量。通过硬件中断号可以在数组中定位，找到硬件中断号对应的数组元素。然后将该数组元素赋值成硬件中断号对应的结构体的地址，使得该数组元素指向对应的结构体。
在一种实施方式中，所述设置为核间中断处理函数后，还包括：
生成核间中断处理模块；
利用载入模块命令，将所述核间中断处理模块载入到所述多核操作系统的内核中。
Linux模块是一些可以作为独立程序来编译的函数和数据类型的集合。Linux的内核模块机制允许开发者动态的向内核添加功能。本申请实施例中，可将步骤S610至步骤S640的处理过程编写成模块。利用该模块即可在不修改内核代码的情况下，以模块的方式实现核间中断的功能。在需要实现该功能时，可使用insmod命令将该模块装载入内核即可使用。
本申请实施例中将核间中断处理函数模块化，将原本用于IO中断的结构体中的中断处理函数irq_desc[IRQ]->handler替换为核间中断处理函数ipi_handler，将中断处理系统中原分配用于输入输出中断的中断处理资源实际用于核间中断，在第三方不开源内核开发的场景下，增强了核间通信功能的开发便利性。
如图7所示，本申请还提供了相应的一种核间中断执行装置的实施例，关于该装置的有益效果或解决的技术问题，可以参见与各装置分别对应的方法中的描述，或者参见发明内容中的描述，此处不再一一赘述。
在该核间中断执行装置的实施例中，该装置包括：
获取单元710，用于：从接收到的中断信号中获取硬件中断号，所述硬件中断号是预先分配的用于输入输出中断的中断号；
确定单元720，用于：确定与所述硬件中断号关联的用于描述中断信息的结构体；
执行单元730，用于：执行所述结构体中用于中断处理的成员函数，所述成员函数被预先设置为核间中断处理函数，以将所述预先分配的用于输入输出中断的中断号用于核间中断。
在一种实施方式中，所述确定单元720用于：
将所述硬件中断号作为中断描述符表的偏移量，根据所述偏移量在所述中断描述符表中确定所述硬件中断号对应的描述符项；
获取所述描述符项对应的用于描述中断信息的结构体。
在一种实施方式中，所述执行单元730用于：
执行所述描述符项指向的通用中断处理程序；
在所述通用中断处理程序中调用所述结构体中用于中断处理的成员函数。
如图8所示，本申请还提供了相应的一种核间中断处理装置的实施例，关于该装置的有益效果或解决的技术问题，可以参见与各装置分别对应的方法中的描述，或者参见发明内容中的描述，此处不再一一赘述。
在该核间中断处理装置的实施例中，该装置包括：
第一分配单元810，用于：在多核操作系统的中断处理系统中分配用于描述中断信息的结构体；
第二分配单元820，用于：在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号；
关联单元830，用于：将所述硬件中断号与所述结构体进行关联；
设置单元840，用于：将所述结构体中用于中断处理的成员函数设置为核间中断处理函数。
在一种实施方式中，所述第二分配单元820用于：
检测所述中断域中用于输入输出中断的硬件中断号是否被占用；
在所述硬件中断号没有被占用的情况下，在所述中断域中分配所述硬件中断号。
在一种实施方式中，所述关联单元830用于：
将所述结构体的地址赋值给所述硬件中断号对应的指针变量。
如图9所示，在一种实施方式中，上述装置还包括载入单元850，所述载入单元850用于：
所述设置为核间中断处理函数后，生成核间中断处理模块；
利用载入模块命令，将所述核间中断处理模块载入到所述多核操作系统的内核中。
图10是本申请实施例提供的一种计算设备900的结构性示意性图。该计算设备900包括：处理器910、存储器920、通信接口930。
应理解，图10中所示的计算设备900中的通信接口930可以用于与其他设备之间进行通信。
其中，该处理器910可以与存储器920连接。该存储器920可以用于存储该程序代码和数据。因此，该存储器920可以是处理器910内部的存储单元，也可以是与处理器910独立的外部存储单元，还可以是包括处理器910内部的存储单元和与处理器910独立的外部存储单元的部件。
可选的，计算设备900还可以包括总线。其中，存储器920、通信接口930可以通过总线与处理器910连接。总线可以是外设部件互连标准(Peripheral Component Interconnect，PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，EISA)总线等。所述总线可以分为地址总线、数据总线、控制总线等。
应理解，在本申请实施例中，该处理器910可以采用中央处理单元(central processing unit，CPU)。该处理器还可以是其它通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(Application specific integrated circuit，ASIC)、 现成可编程门矩阵(field programmable gate Array，FPGA)或者其它可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。或者该处理器910采用一个或多个集成电路，用于执行相关程序，以实现本申请实施例所提供的技术方案。
该存储器920可以包括只读存储器和随机存取存储器，并向处理器910提供指令和数据。处理器910的一部分还可以包括非易失性随机存取存储器。例如，处理器910还可以存储设备类型的信息。
在计算设备900运行时，所述处理器910执行所述存储器920中的计算机执行指令执行上述方法的操作步骤。
应理解，根据本申请实施例的计算设备900可以对应于执行根据本申请各实施例的方法中的相应主体，并且计算设备900中的各个模块的上述和其它操作和/或功能分别为了实现本实施例各方法的相应流程，为了简洁，在此不再赘述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等 各种可以存储程序代码的介质。
本申请实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时用于执行一种多样化问题生成方法，该方法包括上述各个实施例所描述的方案中的至少之一。
本申请实施例的计算机存储介质，可以采用一个或多个计算机可读的介质的任意组合。计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质。计算机可读存储介质例如可以是，但不限于，电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本文件中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。
计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。
计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括、但不限于无线、电线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言或其组合来编写用于执行本申请操作的计算机程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、Smalltalk、C++，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算机上执行、部分地在用户计算机上执行、作为一个独立的软件包执行、部分在用户计算机上部分在远程计算机上执行、或者完全在远程计算机或服务器上执行。在涉及远程计算机的情形中，远程计算机可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算机，或者，可以连接到外部计算机(例如利用因特网服务提供商来通过因特网连接)。
注意，上述仅为本申请的较佳实施例及所运用的技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明的构思的情况下，还可以包括更多其他等效实施例，均属于本发明的保护范畴。

Claims (10)

  1. 一种核间中断执行方法，其特征在于，包括：
    从接收到的中断信号中获取硬件中断号，所述硬件中断号是预先分配的用于输入输出中断的中断号；
    确定与所述硬件中断号关联的用于描述中断信息的结构体；
    执行所述结构体中用于中断处理的成员函数，所述成员函数被预先设置为核间中断处理函数，以将所述预先分配的用于输入输出中断的中断号用于核间中断。
  2. 根据权利要求1所述的方法，其特征在于，确定与所述硬件中断号关联的用于描述中断信息的结构体，包括：
    将所述硬件中断号作为中断描述符表的偏移量，根据所述偏移量在所述中断描述符表中确定所述硬件中断号对应的描述符项；
    获取所述描述符项对应的用于描述中断信息的结构体。
  3. 根据权利要求2所述的方法，其特征在于，执行所述结构体中用于中断处理的成员函数，包括：
    执行所述描述符项指向的通用中断处理程序；
    在所述通用中断处理程序中调用所述结构体中用于中断处理的成员函数。
  4. 一种核间中断处理方法，其特征在于，包括：
    在多核操作系统的中断处理系统中分配用于描述中断信息的结构体；
    在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号；
    将所述硬件中断号与所述结构体进行关联；
    将所述结构体中用于中断处理的成员函数设置为核间中断处理函数。
  5. 根据权利要求4所述的方法，其特征在于，
    所述在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号，包括：检测所述中断域中用于输入输出中断的硬件中断号是否被占用；在所述硬件中断号没有被占用的情况下，在所述中断域中分配所述硬件中断号；
    所述将所述硬件中断号与所述结构体进行关联，包括：将所述结构体的地址赋值给所述硬件中断号对应的指针变量。
  6. 根据权利要求5所述的方法，其特征在于，所述设置为核间中断处理函数后，还包括：
    生成核间中断处理模块；
    利用载入模块命令，将所述核间中断处理模块载入到所述多核操作系统的内核中。
  7. 一种核间中断执行装置，其特征在于，包括：
    获取单元，用于：从接收到的中断信号中获取硬件中断号，所述硬件中断号是预先分配的用于输入输出中断的中断号；
    确定单元，用于：确定与所述硬件中断号关联的用于描述中断信息的结构体；
    执行单元，用于：执行所述结构体中用于中断处理的成员函数，所述成员函数被预先设置为核间中断处理函数，以将所述预先分配的用于输入输出中断的中断号用于 核间中断。
  8. 一种核间中断处理装置，其特征在于，包括：
    第一分配单元，用于：在多核操作系统的中断处理系统中分配用于描述中断信息的结构体；
    第二分配单元，用于：在所述中断处理系统的中断域中分配用于输入输出中断的硬件中断号；
    关联单元，用于：将所述硬件中断号与所述结构体进行关联；
    设置单元，用于：将所述结构体中用于中断处理的成员函数设置为核间中断处理函数。
  9. 一种计算设备，其特征在于，包括：
    通信接口；
    至少一个处理器，其与所述通信接口连接；以及
    至少一个存储器，其与所述处理器连接并存储有程序指令，所述程序指令当被所述至少一个处理器执行时使得所述至少一个处理器执行权利要求1-6任一所述的方法。
  10. 一种计算机可读存储介质，其上存储有程序指令，其特征在于，所述程序指令当被计算机执行时使得所述计算机执行权利要求1-6任一所述的方法。
PCT/CN2023/071686 2022-01-20 2023-01-10 核间中断执行方法、处理方法及装置、设备和存储介质 WO2023138449A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101354693A (zh) * 2008-09-11 2009-01-28 重庆邮电大学 一种异构多核处理器的核间通信调度系统及方法
US20110047310A1 (en) * 2008-04-28 2011-02-24 Bonola Thomas J Method and System for Generating and Delivering Inter-Processor Interrupts in a Multi-Core Processor and in Ceterain Shared Memory Multi-Processor Systems
CN113535341A (zh) * 2020-04-14 2021-10-22 大唐移动通信设备有限公司 Linux下CPU核间中断通信的实现方法及装置
CN113821257A (zh) * 2021-09-29 2021-12-21 杭州迪普科技股份有限公司 处理器内核调用栈信息查询方法及装置
CN114416317A (zh) * 2022-01-20 2022-04-29 科东(广州)软件科技有限公司 核间中断执行方法、处理方法及装置、设备和存储介质

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211323B (zh) * 2006-12-28 2011-06-22 联想(北京)有限公司 一种硬件中断的处理方法和处理装置
CN101587448B (zh) * 2009-06-26 2012-03-21 华为技术有限公司 一种中断处理方法和装置
CN103870326B (zh) * 2012-12-11 2018-07-13 厦门雅迅网络股份有限公司 一种将中断处理程序底半部搬移到应用层的方法及应用
CN105404552A (zh) * 2015-12-23 2016-03-16 恒宝股份有限公司 一种非接触卡数据处理方法及装置
CN107025186A (zh) * 2016-01-29 2017-08-08 龙芯中科技术有限公司 中断号分配方法及装置
CN109995828A (zh) * 2017-12-30 2019-07-09 中国移动通信集团河北有限公司 Ipoib性能优化方法、装置、设备及介质
CN113010275B (zh) * 2019-12-20 2024-01-30 大唐移动通信设备有限公司 一种中断处理方法和装置
CN112198820B (zh) * 2020-09-27 2021-11-12 中国第一汽车股份有限公司 一种中断服务实现方法、装置、设备及存储介质

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110047310A1 (en) * 2008-04-28 2011-02-24 Bonola Thomas J Method and System for Generating and Delivering Inter-Processor Interrupts in a Multi-Core Processor and in Ceterain Shared Memory Multi-Processor Systems
CN101354693A (zh) * 2008-09-11 2009-01-28 重庆邮电大学 一种异构多核处理器的核间通信调度系统及方法
CN113535341A (zh) * 2020-04-14 2021-10-22 大唐移动通信设备有限公司 Linux下CPU核间中断通信的实现方法及装置
CN113821257A (zh) * 2021-09-29 2021-12-21 杭州迪普科技股份有限公司 处理器内核调用栈信息查询方法及装置
CN114416317A (zh) * 2022-01-20 2022-04-29 科东(广州)软件科技有限公司 核间中断执行方法、处理方法及装置、设备和存储介质

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