WO2023137666A1 - 数据传输方法和数据传输装置 - Google Patents

数据传输方法和数据传输装置 Download PDF

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Publication number
WO2023137666A1
WO2023137666A1 PCT/CN2022/073010 CN2022073010W WO2023137666A1 WO 2023137666 A1 WO2023137666 A1 WO 2023137666A1 CN 2022073010 W CN2022073010 W CN 2022073010W WO 2023137666 A1 WO2023137666 A1 WO 2023137666A1
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Prior art keywords
field
control word
data
link
bit stream
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PCT/CN2022/073010
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English (en)
French (fr)
Inventor
聂耳
潘伟
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华为技术有限公司
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Priority to PCT/CN2022/073010 priority Critical patent/WO2023137666A1/zh
Publication of WO2023137666A1 publication Critical patent/WO2023137666A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the embodiments of the present application relate to the field of communication networks, and in particular, to a data transmission method and a data transmission device.
  • each communication device usually communicates through a data link, and the physical layer in the signal sending end transmits the bit stream to the physical layer in the signal receiving end through the link, so as to realize the signal exchange between communication devices.
  • the bit stream usually includes various control signals indicating information such as link configuration or link status in addition to encoded data signals.
  • the various control signals include control signals indicating packet frame delimitation, control signals indicating link bandwidth, and the like.
  • the multiple control signals are independent coding segments.
  • the multiple control signals are typically transmitted at specific locations in addition to data signals.
  • the data transmission method and data transmission device provided in the present application can reduce the complexity of control signals transmitted by the physical layer.
  • the present application adopts the following technical solutions.
  • an embodiment of the present application provides a data transmission method, the data transmission method is applied to a sending end, and the data transmission method includes: generating a bit stream, the bit stream includes data and a control word, and the control word includes: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; sending the wired serial link through the bit stream.
  • the sending end may be, for example, the interface controller shown in FIG. 1 , FIG. 4 and FIG. 5 .
  • the first field for indicating the start position information of the control word for example, can be the start field shown in Figure 2;
  • the second field for indicating the end position information of the control word for example, can be the end field shown in Figure 2;
  • the third field for carrying the link information indicating the wired serial link can be, for example, the load field shown in Figure 2.
  • various link information used for link alignment between two communication devices for data transmission is usually a coding segment, and one type of information is a coding segment.
  • the information indicating the power consumption of the link is one coding segment
  • the information indicating the state of each circuit in the link is one coding segment, that is, there are multiple coding segments for implementing link alignment.
  • the control word provided by the embodiment of the present application is set to include the structure of the first field, the second field and the third field, and the link information is carried in the third field, so that multiple link information can be indicated in one control word, the complexity of the control signal transmitted by the physical layer is reduced, and the design of the physical layer is simplified.
  • the second field of the control word is used to indicate the end position information of the control word, that is, the second field of the control word can limit the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thereby providing the flexibility of the control word.
  • the end position information may be the length of the control word or the end position.
  • the end position may be, for example, a preset number of bits from the beginning of the second field.
  • the data is service data or training data.
  • the link information includes at least one of the following: the number of channels for transmitting the first bit stream, the power consumption status of hardware in the link, the working status of circuits in the link, or the codec gain used in the link.
  • the power consumption of each hardware in the link usually includes multiple types, such as low power consumption, medium power consumption and high power consumption.
  • the hardware such as scrambler and data distributor included in the link is in one of standby, sleep or power off
  • the hardware in the link is in a low power consumption state
  • the component hardware included in the link is in one of standby, sleep or power off, and the other part of the hardware is in working state
  • the hardware in the link has a medium power consumption
  • when all the devices in the link are working the hardware in the link is in a high power consumption state.
  • the transmitted data when the transmitted data is training data, it may indicate that the power consumption of each hardware in the link is low power consumption; when the transmitted data is service data, it may indicate that the power consumption of each hardware in the link is medium power consumption or high power consumption.
  • the working state of the circuit in the link may include, for example, a power-on state or a power-off state.
  • the codec circuit when the transmitted data is training data, the codec circuit may be in a power-off state; when the transmitted data is service data, the codec circuit may be in a power-on state. Therefore, the sending end can carry information such as one of various power consumption states, one indicating the working state of the circuit in the link, and the gain of the codec in the third field, and transmit it to the receiving end.
  • the first field and the second field are used to instruct the receiving end to delimit the data frame.
  • control word can be followed by the data content of the data; that is to say, the first field and the second field of the control word can serve as the frame header of the data frame, and after the receiving end recognizes the first field and the second field of the control word, the starting position of the data (that is, the frame delimitation) can be determined to read the data from the bit stream.
  • the first field and the second field of the control word as the frame header of the data frame, there is no need to additionally set the frame header of the data frame, thereby simplifying the design of the bit stream.
  • the bit stream includes multiple
  • the wired serial link includes multiple channels
  • the multiple bit streams correspond to the multiple channels one by one
  • sending the bit stream through the wired serial link specifically includes: sending the corresponding multiple bit streams through the multiple channels.
  • the receiving end can accurately read data from the bit stream transmitted by each channel based on the control word in each channel, improving the accuracy of data reading at the receiving end.
  • control word further includes a fourth field for indicating a channel number.
  • the fourth field may be, for example, the channel identification field shown in FIG. 2 .
  • the receiving end can adjust the order of the data received from each channel based on each channel number, thereby improving the accuracy of the data received by the receiving end.
  • the first field includes multiple sets of identical fields, and each set of fields includes multiple bits; the multiple sets of identical fields are used to compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end.
  • the sending end can encode the above-mentioned first field into continuous "0" and "1" signals, and then based on the local clock cycle, send a bit stream to the receiving end through a wired serial link; when the receiving end receives the bit stream, first recover the clock cycle of the sending end from the first field; then, based on the deviation between the recovered clock cycle and the local cycle, the receiving end adds or deletes at least one set of fields among multiple sets of identical fields.
  • a buffer queue can be set in the receiving end, and the receiving end can write the data carried by the first field into the buffer queue based on the clock cycle recovered from the first field.
  • the receiving end can also read data from the buffer queue based on the local clock cycle, and both are performed simultaneously.
  • the receiving end detects that the rate of data written into the buffer queue is greater than the rate at which data is read from the buffer queue, it indicates that the clock cycle of the sending end is greater than the clock cycle of the receiving end.
  • at least one group of fields in the multiple groups of identical fields included in the first field is deleted to ensure that the clock cycles between the sending end and the receiving end are synchronized; In order to realize the clock cycle synchronization between the sending end and the receiving end.
  • the generating a bit stream includes: adding the control word after the data, so as to generate the bit stream.
  • an embodiment of the present application provides a data transmission method, the data transmission method is applied to a receiving end, and the data transmission method includes: receiving a bit stream, the bit stream includes data and a control word, and the control word includes a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; based on the first field and the second field, read the control word from the bit stream; based on the control word, read the data from the bit stream.
  • the receiving end may be, for example, the network card shown in FIG. 1 , FIG. 4 and FIG. 5 .
  • the first field for indicating the start position information of the control word for example, can be the start field shown in Figure 2;
  • the second field for indicating the end position information of the control word for example, can be the end field shown in Figure 2;
  • the third field for carrying the link information indicating the wired serial link can be, for example, the load field shown in Figure 2.
  • the control word provided in the embodiment of the present application is configured to include a first field, a second field, and a third field, and the link information is carried in the third field, so that multiple link information can be indicated in one control word, which simplifies the design of the physical layer.
  • the second field of the control word is used to indicate the end position information of the control word, that is, the second field of the control word can limit the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thereby providing the flexibility of the control word.
  • the method further includes: adjusting at least one of the following of the wired serial link based on the link information: a power consumption state of hardware in the link, a working state of a circuit in the link, or a codec gain used in the link.
  • the power consumption of each hardware in the link usually includes multiple types, such as low power consumption, medium power consumption and high power consumption.
  • the transmitted data when the transmitted data is training data, it may indicate that the power consumption of each hardware in the link is low power consumption; when the transmitted data is service data, it may indicate that the power consumption of each hardware in the link is medium power consumption or high power consumption.
  • the working state of the circuit in the link may include, for example, a power-on state or a power-off state.
  • the codec circuit when the transmitted data is training data, the codec circuit may be in a power-off state; when the transmitted data is service data, the codec circuit may be in a power-on state.
  • the receiving end Based on one of the multiple power consumption states indicated in the third field, one of the working states of the circuits in the link, and the gain of the codec, the receiving end adjusts the power consumption state of the hardware in the link to the power consumption state indicated in the third field, adjusts the working state of the circuits in the link to the working state indicated in the third field, and adjusts the gain of the codec to the gain indicated in the third field.
  • the reading the data from the bit stream based on the control word includes: determining a code length of the control word based on the first field and the second field; identifying a frame start position of the data from the bit stream based on the code length of the control word, where the frame start position of the data is located after the control word; and reading the data based on the frame start position of the data.
  • control word can be followed by the data content of the data; that is to say, the first field and the second field of the control word can serve as the frame header of the data frame, and when the receiving end recognizes the first field and the second field of the control word, the starting position of the data can be determined to read the data from the bit stream.
  • first field and the second field of the control word as the frame header of the data frame, there is no need to additionally set the frame header of the data frame, thereby simplifying the design of the bit stream.
  • the bit stream includes multiple channels
  • the wired serial link includes multiple channels
  • the multiple bit streams are received from the sending end through the corresponding multiple channels
  • the link information also includes the number of channels for transmitting the bit stream
  • the control word also includes a fourth field for indicating a channel number
  • reading data from the bit stream based on the control word includes: based on the number of channels for transmitting the bit stream and the fourth field, reading the data from the bit stream received by the corresponding channel.
  • the fourth field may be, for example, the channel identification field shown in FIG. 2 .
  • the method further includes: based on the received sequence of the multiple bit streams and the fourth field in each of the multiple control words in the multiple bit streams, eliminating data skew between each of the multiple channels.
  • the first field includes multiple sets of identical fields, and each set of fields includes multiple bits; and the method further includes: performing one of the following operations based on the clock frequency deviation with the transmitting end: deleting at least one of the multiple sets of identical fields, or adding at least one set of the multiple sets of identical fields.
  • the sending end can encode the above-mentioned first field into continuous "0" and "1" signals, and then based on the local clock cycle, send a bit stream to the receiving end through a wired serial link; when the receiving end receives the bit stream, first recover the clock cycle of the sending end from the first field; then, based on the deviation between the recovered clock cycle and the local cycle, the receiving end adds or deletes at least one set of fields among multiple sets of identical fields.
  • a buffer queue can be set in the receiving end, and the receiving end can write the data carried by the first field into the buffer queue based on the clock cycle recovered from the first field.
  • the receiving end can also read data from the buffer queue based on the local clock cycle, and both are performed simultaneously.
  • the receiving end detects that the rate of data written into the buffer queue is greater than the rate at which data is read from the buffer queue, it means that the clock cycle of the sending end is greater than the clock cycle of the receiving end.
  • at least one of the multiple groups of identical fields included in the first field is deleted to ensure that the clock cycles between the sending end and the receiving end are synchronized; , to achieve clock cycle synchronization between the sending end and the receiving end.
  • an embodiment of the present application provides a data transmission device, the data transmission device includes a processor and an interface; the processor is configured to generate a bit stream, the bit stream includes data and a control word, and the control word includes: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; the interface is used to send the bit stream through the wired serial link.
  • the link information includes at least one of the following: the number of channels for transmitting bit streams, the power consumption status of hardware in the link, the working status of circuits in the link, or the gain of a codec used in the link.
  • the first field and the second field are used to instruct the receiving end to delimit the data frame.
  • the bit stream includes multiple channels
  • the wired serial link includes multiple channels
  • the multiple bit streams correspond to the multiple channels one by one
  • the interface is specifically configured to: send the corresponding multiple bit streams through the multiple channels.
  • control word further includes a fourth field for indicating a channel number.
  • the first field includes multiple sets of identical fields, and each set of fields includes multiple bits; the multiple sets of identical fields are used to compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end.
  • an embodiment of the present application provides a data transmission device, the data transmission device includes a processor and an interface; the interface is used to receive a bit stream, the bit stream includes data and a control word, the control word includes a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link; the processor is used to read the control word from the bit stream based on the first field and the second field; read the control word from the bit stream based on the control word data.
  • the processor is further configured to: adjust at least one of the following of the wired serial link based on the link information: a power consumption state of hardware in the link, a working state of a circuit in the link, or a codec gain used in the link.
  • the processor is specifically configured to: determine a code length of the control word based on the first field and the second field; identify a frame start position of the data from the bit stream based on the code length of the control word, where the frame start position of the data is located after the control word; and read the data based on the frame start position of the data.
  • the bit stream includes multiple channels
  • the wired serial link includes multiple channels
  • the multiple bit streams are received from the sending end through the corresponding multiple channels
  • the link information also includes the number of channels for transmitting the bit stream
  • the control word also includes a fourth field for indicating the channel number
  • the processor is specifically configured to: based on the number of channels for transmitting the bit stream and the fourth field, read the data from the bit stream received by the corresponding channel.
  • the processor is further configured to: eliminate data skew between each of the multiple channels based on the received sequence of the multiple bit streams and the fourth field in each of the multiple control words in the multiple bit streams.
  • the first field includes multiple sets of identical fields, and each set of fields includes multiple bits; and the processor is further configured to: based on the clock frequency deviation with the sending end, perform one of the following operations: delete at least one set of the multiple sets of identical fields, or add at least one set of the multiple sets of identical fields.
  • the embodiment of the present application provides a computer-readable storage medium for storing a computer program.
  • the computer program is run by a processor, the data transmission method as described in the first aspect above or the data transmission method as described in the second aspect above is implemented.
  • an embodiment of the present application provides a computer program product.
  • the computer program product runs on a processor, the data transmission method described in the first aspect above or the data transmission method described in the second aspect above is implemented.
  • FIG. 1 is a schematic diagram of a hardware architecture of an electronic device provided by an embodiment of the present application
  • Fig. 2 is a schematic diagram of the frame structure of the control word provided by the embodiment of the present application.
  • FIG. 3A is a schematic diagram of an eBCH codeword set provided by an embodiment of the present application.
  • FIG. 3B is a schematic diagram of the coding structure of the channel identifier provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a hardware architecture of the physical layer provided by the embodiment of the present application.
  • Fig. 5 is a flow chart of the data transmission method provided by the embodiment of the present application.
  • Fig. 6 is another flow chart of the data transmission method provided by the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a data transmission device provided by an embodiment of the present application.
  • Fig. 8 is another schematic structural diagram of the data transmission device provided by the embodiment of the present application.
  • first, or “second” and similar words mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like “a” or “one” do not denote a limitation in number, but indicate that there is at least one. "Coupling” and similar words are not limited to physical or mechanical direct connection, but may include electrical connection, whether direct or indirect, which is equivalent to communication in a broad sense.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • “plurality” means two or more. For example, multiple channels refers to two or more channels.
  • the data transmission system may include a sending end and a receiving end.
  • Both the sending end and the receiving end can be an electronic device, and the electronic device can be, for example, a terminal device, such as a mobile phone, a PC computer, a tablet computer, a notebook computer, or a wearable device (such as a smart watch, an AR device, a VR device, etc.; various types of portable devices); the electronic device can also be a switch device or a router device, etc.
  • the sending end may be a terminal device
  • the receiving end may be a router device
  • the terminal device communicates with the router device through a wired serial link to transmit signals to the router device.
  • the router device may also be called a sending end
  • the terminal device may also be called a receiving end.
  • the sending end and the receiving end may also be modules, chips, chipsets, circuit boards or components equipped with chips or chipsets installed in electronic equipment.
  • the electronic device is, for example, the electronic device described above.
  • the electronic device may be provided with a network card (network card), so that the electronic device may be connected to a network through the network card for communication, and the network may be, for example, Ethernet.
  • the sending end may be an interface controller integrated in the electronic device; the receiving end may be a network card installed in the electronic device. Communication between the interface controller and the network card may be via a wired serial link.
  • the interface controller transmits the bit stream to the network card through the wired serial link, and the network card encapsulates the received bit stream into an Ethernet frame and sends it to the Ethernet.
  • the interface controller is the sending end, and the network card is the receiving end.
  • the sending end is an interface controller and the receiving end is a network card as an example for description, but it is not used to limit the solution.
  • an electronic device 100 includes one or more processors, for example, the one or more processors include an interface controller 10, a central processing unit (CPU, central processing unit) 12, and the like.
  • the one or more processors may be integrated in one or more chips, and the one or more chips may be regarded as a chipset.
  • the interface controller 10 and the CPU 12 may be integrated in a system on chip (SOC, system on chip) as shown in FIG. Among them, the interface controller 10, the CPU 12, the memory 13 and the DMAC 14 carry out signal transmission through the bus.
  • SOC system on chip
  • Software programs or software plug-ins such as operating system software and application software may run in the CPU 12 , and the memory 13 may store software programs or software plug-ins required for the CPU 12 to run.
  • the memory 13 may also store instructions and data required for the CPU 12 to run, and the CPU 12 obtains the instructions and data from the memory 13 through the DMAC 14 .
  • the electronic device 100 further includes a network card 11 .
  • the network card 11 may be provided outside the SOC shown in FIG. 1 .
  • the interface controller 10 includes an interface 101 and a processor 102
  • the network card 11 includes an interface 111 and a processor 112
  • the network card 11 is coupled to the interface 101 in the interface controller 10 through the interface 111 .
  • the interface 101 and the interface 111 may be serdes (serializer/deserializer, serializer and deserializer) interfaces respectively.
  • the interface 101 and the interface 111 may be coupled through various physical media (such as twisted pair or cable).
  • the electronic device 100 is connected to the network through the network card 11, and communicates with other devices (such as server devices or terminal devices) in the network for data exchange.
  • the processor 102 and the processor 112 may respectively include components such as an encoder, a decoder, a control word generator, and a link training state machine.
  • the processor 102 and the processor 112 may optionally include components such as a scrambler and a descrambler.
  • the communication network model of the electronic device 100 may comply with the OSI (open system interconnection reference model) standard.
  • the OSI may specifically include an application layer, a transport layer, a data link layer, and a physical layer, and may also include more layers, which are not specifically limited in this embodiment of the present application.
  • the application layer may include application software running in the CPU 12 . For example, video playback applications, instant messaging applications, and the like.
  • the transport layer is used to describe the transport layer protocol specifications of the system, including data types, definition and arrangement of structures, routing control, bandwidth management, etc.
  • the data link layer is used to encapsulate the data packets provided by the transport layer into data frames and provide transparent transmission.
  • the physical layer is used to define the link state, clock reference, data encoding and circuit of the wired serial link required for data transmission and reception, and to provide a standard interface to the data link layer.
  • the physical layer encodes the data frame to generate a bit stream, and transmits the bit stream through a wired serial link.
  • the interface controller 10 and the network card 11 provided in the embodiment of the present application usually work at the physical layer in the OSI standard.
  • the processor 102 in the interface controller 10 can obtain the original data message (for example, the CPU 12 can trigger the processor 102 to read the data message from the memory 13); the processor 102 processes the obtained data message (for example, encapsulating it into a data frame and performing Hamming encoding), and generates a bit stream that is output to the network card 11 through the interface 101; the interface 111 in the network card 11 receives the bit stream, and the processor 112 in the network card 11 processes the received bit stream Perform further processing (such as decoding to obtain data frames, perform Ethernet frame encapsulation and Manchester encoding on the data frames, etc.), and then transmit to the network. Similarly, after the network card 11 receives the data frame from the network, it processes it (such as performing Manchester decoding, removing the Ethernet frame and Hamming coding, etc.), and then transmits it to the interface controller 10 through the interface 111;
  • the interface controller 10 in order to realize signal transmission with a low bit error rate, in the bit stream transmitted by the interface controller 10 (i.e., the transmitting end) to the network card 11 (i.e., the receiving end), in addition to including the data obtained by encoding the data frame, it also includes a control word, as shown in FIG. 2 , which schematically shows the bit stream transmitted by the interface controller 10 to the network card 11.
  • the control word is used to indicate the link status, clock reference, data frame delimitation and other information of the wired serial link. Therefore, based on the control word, the physical layer of the receiving end determines the frame delimitation of the data, adjusts the clock reference, adjusts the link status, and so on.
  • control word includes a start field for indicating the start position information of the control word, an end field for indicating the end position information of the control word, and a payload field for carrying the indication information.
  • the indication information carried by the payload field is used to indicate link information of the wired serial link.
  • various link information used for link alignment between two communication devices for data transmission is usually a coding segment, and one type of information is a coding segment.
  • the information indicating the power consumption of the link is one coding segment
  • the information indicating the state of each circuit in the link is one coding segment, that is, there are multiple coding segments for implementing link alignment.
  • the control word provided by the embodiment of the present application is configured to include a start field, an end field, and a payload field, and the link information is carried in the payload field, so that multiple link information can be indicated in one control word, which simplifies the design of the physical layer.
  • the end field of the control word is used to indicate the end position information of the control word, that is, the end field of the control word can limit the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thereby providing the flexibility of the control word.
  • the data is located on the left side of the control word.
  • the control word signal is sent first, and then the data signal is sent.
  • the data may be service data, for example.
  • the data may also be located on the right side of the control word.
  • the data signal is sent first, and then the control word signal is sent.
  • the data may be training data, for example.
  • the control word can also be set at any position of the data.
  • the control word includes a start field U_I indicating the start position information of the control word, an end field U_END used to indicate the end position of the control word, and a payload field payload used to indicate link information of the wired serial link.
  • the control word will be described in more detail below in conjunction with the frame structure of the control word shown in FIG. 2 .
  • the initial field U_I includes at least one set of bits U_ID0-U_IDN. That is to say, in the frame structure shown in FIG. 2 , the first N+1 bits are the header of the control word, and the N+1 bits of the header can enable the network card 11 to identify the start field of the control word.
  • the length of the start field U_I can be changed within a preset range.
  • the initial field U_I may include multiple sets of repeated U_ID0-U_IDN, wherein the variable length of the initial field U_I may be, for example, 8 bytes. Assuming that N is 4, and U_ID0-U_IDN are 00101, the start field U_I may be the three sets of repeated code streams of 001010010100101.
  • the interface controller 10 can encode the start field into continuous "0" and "1" signals, and then based on the local clock cycle, send the bit stream to the network card 11 through the wired serial link; when the network card 11 receives the bit stream, first restore the clock cycle of the interface controller 10 from the start field; then, the network card 11 adds or deletes at least one group of fields in multiple sets of identical fields based on the deviation between the recovered clock cycle and the local cycle.
  • a buffer queue may be set in the network card 11, and the network card 11 writes the data carried by the start field into the buffer queue based on the clock cycle recovered from the start field.
  • the network card 11 may also read data from the buffer queue based on the local clock cycle, and both are performed simultaneously.
  • the network card 11 When the network card 11 detects that the rate of data written into the buffer queue is greater than the rate of reading data from the buffer queue, it means that the clock cycle of the interface controller 10 is greater than the clock cycle of the network card 11. At this time, one or more groups of U_ID0 ⁇ U_IDN in the initial field U_I are deleted to ensure that the clock cycles between the interface controller 10 and the network card 11 are synchronized; At this time, one or more sets of U_ID0-U_IDN are added to the initial field U_I to realize clock cycle synchronization between the interface controller 10 and the network card 11.
  • the end field U_END is used to indicate the end position information of the control word.
  • the end position information may be, for example, the length of the control word or the end position.
  • the end position may be, for example, a preset number of bits from the beginning of the end field U_END. Therefore, after the network card 11 recognizes the end field U_END from the control word, it can determine the end of the code stream of the control word by counting back a preset number of bits.
  • control word can be followed by data content; that is to say, the start field and end field of the control word can serve as the frame header of the data frame.
  • the start position of the data can be determined (that is, the frame delimitation), so as to read the data from the bit stream.
  • the start field and the end field of the control word as the frame header of the data frame, there is no need to additionally set the frame header of the data frame, thereby simplifying the design of the bit stream.
  • the payload field payload is used to carry link information.
  • the link information may include, but not limited to, one or more of the following: the clock period for adding the control word to the data, the power consumption status of the hardware in the link, the working status of the circuits in the link, and the output gain of the codec circuit in the link.
  • the power consumption state of the hardware in the link includes, for example, three states of low power consumption, medium power consumption and high power consumption.
  • the hardware in the link When the hardware such as scrambler and data distributor included in the link is in one of standby, dormancy or power off, the hardware in the link is in a low power consumption state; when the component hardware included in the link is in one of standby, dormancy or power off, and the other part of the hardware is in the working state, the hardware in the link is in a medium power consumption state; when all the devices in the link are working, the hardware in the link is in a high power consumption state.
  • the transmitted data is training data, it may indicate that the power consumption of each hardware in the link is low power consumption; when the transmitted data is service data, it may indicate that the power consumption of each hardware in the link is medium power consumption or high power consumption.
  • the working state of the circuit in the link may include, for example, a power-on state or a power-off state.
  • the codec circuit when the transmitted data is training data, the codec circuit may be in a power-off state; when the transmitted data is service data, the codec circuit may be in a power-on state.
  • Gains of the codecs in the link include Gain 1, Gain 2 and Gain 3, for example.
  • the payload field payload may include two parts: a type (type) field and a detail (detail) field.
  • the type field is used to indicate various link information
  • the detail field is used to indicate specific parameters corresponding to each link information.
  • the link information includes the power consumption state of the hardware in the link, the working state of the circuit in the link, or the gain of the codec in the link.
  • the type field is used to indicate that the link information includes the power consumption state of the hardware in the link and the gain of the codec in the link.
  • the detai field further indicates that the power consumption state of the hardware in the link is a medium power consumption state, and the gain of the codec in the link is a gain of 2. Therefore, the network card 11 can determine various link information and parameters corresponding to various link information based on the type field and the detail field, so as to adjust the link.
  • the wired serial link between the interface controller 10 and the network card 11 for transmitting bit streams may include one lane or multiple lanes based on the bandwidth of the wired serial link. That is to say, the interface controller 10 and the network card 11 can transmit bit streams through one lane, or can transmit bit streams through multiple lanes.
  • the bit stream transmitted by each lane includes control words in addition to data.
  • each control word may also include a lane identification field Lane indicating the link number, as shown in FIG. 2 .
  • the network card 11 can implement lane flipping based on the lane identification field Lane, and can also eliminate data skew between data transmitted by each lane. Further, the interface controller 10 can transmit the bit stream to the network card 11 through a fixed number of lanes, and can also transmit the bit stream to the network card 11 through a variable number of lanes. When the interface controller 10 transmits bit streams to the network card 11 through a variable number of lanes, in an optional implementation, the link information carried in the payload field payload may also include link bandwidth (that is, the number of lanes for transmitting bit streams). The network card 11 can receive the bit stream from the corresponding lane based on the link information.
  • control word can indicate more information by setting the start field, end field, payload field and selectively setting the channel identification field, thereby reducing the complexity of the control word transmitted by the physical layer.
  • the control word may be encoded in an error correction coding manner.
  • the interface controller 10 sends codes that can be corrected, and the network card 11 can automatically detect errors and automatically correct errors in code word transmission.
  • error correction coding may include but not limited to: forward error correction coding, Hamming code coding, eBCH (extended Bose Ray-Chaudhuri Hocquenghem) coding, etc.
  • the Hamming code is a linear code.
  • eBCH code For a coded block with a length of m bits, there are n redundant bits, and the rest are payload bits; each redundant bit is obtained by XOR operation of part of the payload bits in a certain way.
  • Hamming coding can correct any single-bit errors.
  • the eBCH code is also a linear code, and the eBCH code can correct multiple bit errors in the coded block. Taking eBCH encoding as an example, the encoding method of the control word is described in detail through specific examples. In this embodiment of the present application, an eBCH coding set may be constructed first.
  • the eBCH code set can include, for example, 32 codes, and the structure of each code can be BCH (16, 5, 1), where 16 (bits) is the code length, 5 (bits) is the payload length, and 1 (bit) is the check code length.
  • the Hamming distance between any two codes in the eBCH code set is 8. That is to say, the number of different bits between any two codes is 8.
  • the set of eBCH codewords is shown in Figure 3A.
  • the eBCH includes 32 codes of CW0-CW31, and the length of each code is 16 bits. The number of different bits between any two codes is eight.
  • Table 1 Based on the eBCH encoding constructed in FIG. 3A , a specific example of the control word described in the embodiment of the present application is shown in Table 1.
  • Control word start field CW21, CW28 4*N ⁇ (4*N+3)
  • Control word end field CW22, CW8 (4*N+4) ⁇ (4*N+11)
  • Channel identification field specifically refer to Figure 3B (4*N+12) ⁇ (4*N+19) payload_type field, refer to Table 2 for details (4*N+20) ⁇ (4*N+27) payload_detail field, refer to Table 3 for details
  • a control word includes 0 to (4*N+27) or (4*N+27) bytes.
  • the number of bytes in the start field of the control word can be variable from 4 to 20.
  • the codes of the control word start field are CW21 and CW28; that is, the lower 16 bits of the control word start field are the code CW28 shown in Table 1, and the upper 16 bits are the code CW21 shown in Table 1.
  • the codes of the control word end field are CW22 and CW8; that is, the lower 16 bits of the control word end field are the code CW22 shown in Table 1, and the upper 16 bits are the code CW8 shown in Table 1.
  • the channel identification field is shown in Figure 3B.
  • the maximum link bandwidth between the interface controller 10 and the network card 11 is 32 lanes, that is, lane0-lane31 shown in FIG. 3B .
  • the identifier of each lane can be represented by four codes, that is, 64 bits.
  • lane2 shown in FIG. 3B as an example, it can be seen from FIG. 3B that lane2 is indicated by four codes of CW3, CW9, CW3 and CW9.
  • the specific bits of CW3 and CW9 refer to Table 1. It can also be seen from FIG.
  • bits [0-15] are CW3
  • bits [16-31] are CW9
  • bits [32-47] are CW3
  • bits [48-63] are CW9.
  • Table 1, Table 2, Table 3 and the tables shown in FIG. 3A and FIG. 3B may be pre-stored in the interface controller 10 and the network card 11 respectively.
  • the link information includes four types of information: forward error correction coder (FEC, forward error correction) gain, link bandwidth, hardware power consumption, and control word adding cycle.
  • FEC forward error correction coder
  • Each type of information is indicated by two codes (ie 32 bits).
  • Table 2 shows that the coding of the FEC gain is CW8 and CW10, that is, the lower 16 bits of the 32 bits indicating the FEC gain are CW10, and the upper 16 bits are CW8.
  • the FEC gain further includes four modes of bypass FEC, FEC gain 1, FEC gain 2 and FEC gain 3 shown in Table 3.
  • the type field in the control word transmitted by the interface controller 10 to the network card 11 includes CW8 and CW10, and the detail field includes CW9 and CW10.
  • the network card 11 After receiving the bit stream, the network card 11 parses out the type field and detail field of the control word. The network card 11 finds out from Table 2 that CW8 and CW10 indicate FEC gains; then, the network card 11 further compares CW3 and CW9 with the codes corresponding to the FEC gains in Table 3, and finds out that the FEC gain is FEC gain 1. Then the network card 11 can adjust the FEC gain to gain 1.
  • Table 2 shows that the codes of the link bandwidth are CW10 and CW22, that is, the lower 16 bits of the 32 bits indicating the link bandwidth are CW10, and the upper 16 bits are CW22.
  • the link bandwidth further includes the seven modes of X0, X1, X2, X4, X8, X16 and X32 shown in Table 3. Assume that in the type field in the control word transmitted by the interface controller 10 to the network card 11, the first 32 bits are CW8 and CW10, and the last 32 bits are CW10 and CW22; in the detail field, the first 32 bits are CW9 and CW10, and the last 32 bits are CW9 and CW21.
  • the network card 11 After receiving the bit stream, the network card 11 parses out that the first 32 bits of the type field of the control word indicate the FEC gain, and the last 32 bits indicate the link bandwidth. Then, the network card 11 compares the first 32 bits in the detail field with the information corresponding to the FEC gain in Table 3, and compares the last 32 bits in the detail field with the information corresponding to the link bandwidth in Table 3, so as to find out that the FEC gain is FEC gain 1 and the link bandwidth is X1. Then the network card 11 can adjust the FEC gain to gain 1 to obtain data from one channel. It should be noted that, the physical layer of the interface controller 10 and the physical layer of the network card 11 may also pre-agree on the channels used under the bandwidth of each link.
  • the service data when one channel is used to transmit service data, the service data will be transmitted through the channel identified as lane0; it can also be pre-agreed that when four channels are used to transmit service data, the service data will be transmitted through the channels identified as lane0-lane3.
  • the type field of the control word indicates link bandwidth information and the detail field is coded CW3 and CW9, it means that the interface controller 10 has finished transmitting service data to the network card 11, and the data to be transmitted in the next cycle is training data.
  • the code used to indicate link bandwidth can also be used to indicate switching between service data and training data.
  • control word transmitted by the interface controller 10 to the network card 11 includes information indicating the power consumption of the hardware and the adding cycle of the control word
  • analysis of the control word by the network card 11 and how to determine the link information to be adjusted are similar to the FEC encoder and link bandwidth, and will not be described again.
  • FIG. 4 is a schematic diagram of the physical layer hardware structure of the interface controller 10 provided by the embodiment of the present application.
  • the hardware structure of the physical layer of the network card 11 may be the same as the hardware structure of the physical layer of the interface controller 10
  • the embodiment of the present application uses the physical layer hardware of the interface controller 10 as an example for description. As shown in FIG.
  • the physical layer of the interface controller 10 includes an encoder 101, a data distributor 102, a control word generator 103, a multiplexer 104, a link training state machine 105, a scrambler 106, a serial deserializer 107, a descrambler 108, a control word decoder 109, a data skew remover 1010 and a decoder 1011. It can be understood that the physical layer of the interface controller 10 may further include more circuits, modules or components, which are not specifically limited in this embodiment of the present application. These components included in the physical layer of the interface controller 10 may be integrated into one or more chips, these components may be implemented by hardware circuits, and some components may also be implemented by software driving hardware.
  • some components may be integrated into a same processor, and the processor executes the functions corresponding to each component or module.
  • the encoder 101 and the data distributor 102 can be integrated into the same processor, and the processor implements the functions of data encoding and distribution.
  • the physical layer of the network card 11 can have the same or similar components as the interface controller 10. The physical layer of the network card 11 is shown in FIG. Taking the bit stream transmission from the physical layer of the interface controller 10 to the physical layer of the network card 11 as an example, the components or functions in the physical layer of the interface controller 10 and the network card 11 will be described below.
  • the encoder 101 is used to encode data frames sent by the data link layer to generate encoded data.
  • the coding can be, for example, forward error coding, error detection and retransmission coding, or hybrid error correction coding.
  • the data distributor 102 is used to divide the coded data into multiple data streams (hereinafter referred to as service data), and distribute them to multiple lanes, and one lane corresponds to one piece of data.
  • the link training state machine 105 is used to generate link information, and provide the generated link information to the control word generator 103, and the control word generator 103 generates the control word based on the link information and the frame structure of the control word as shown in FIG. 2 .
  • the link information may include, for example, a link power consumption state, a link output gain, a link encoding mode, and the like.
  • the link training state machine 105 is also used to control the multiplexer 104 to selectively connect one of the multiple input terminals to an output terminal based on the current state (such as the service data transmission state, the link training state, or the link reset state, etc.) and the clock cycle.
  • FIG. 4 shows that the multiplexer 104 includes three input terminals, one of which is coupled to the data distributor 102 , one of which is used for inputting training data, and the other input is coupled to the control word generator 103 .
  • the multiplexer 104 outputs one of service data, training data or control words to the scrambler 106 based on the control of the link training state machine 105 .
  • the service data in the embodiment of the present application can be, for example, data such as audio data and video data input by the user through the application program, and the data generated after encapsulation and encoding at the application layer, transport layer, data link layer, and physical layer; the training data is used to test and adjust multiple lanes in the link training phase.
  • the scrambler 106 adds a scrambler to the received data stream or control word, and provides the serializer 107.
  • the SerDes 107 converts the received multiple parallel low-speed bit streams into high-speed serial bit streams, and transmits them to the network card 11 through multiple lanes. It should also be noted that the number of lanes is the same as the number of transmitted bit streams, and each bit stream includes data and control words. Based on the control of the link training state machine 105, the control word can be added at any position of the corresponding data. Preferably, the control word can be added before the data.
  • the SerDes 117 receives the serial bit stream signal from the lane, converts the serial bit stream into multiple parallel bit streams and supplies them to the descrambler 118 .
  • the descrambler 118 descrambles the multiple parallel bit streams, and outputs the descrambled bit streams to the control word decoder 119 .
  • the control word decoder 119 Based on the frame structure of the control word shown in FIG. 4 , the control word decoder 119 identifies the control word from each bit stream, and parses the control word to obtain indication information in the payload field, which is used to indicate link information. For example, the indication information indicates that the link enters a medium power consumption state and indicates that the link coding mode is a forward error coding mode.
  • the control word decoder 119 provides the obtained indication information to the link training state machine 115 , and provides the data and the channel identifier corresponding to each piece of data to the data skew remover 1110 .
  • the link training state machine 115 performs corresponding actions based on the indication information. For example, setting the link to a medium power consumption state, providing a coding mode (such as the forward error coding described above) to the decoder 1111 .
  • the data skew remover 1110 performs skew removal processing on each data stream, and provides the data stream after skew removal to the decoder 1111 . Based on the above encoding mode, the decoder 1111 uses a corresponding decoding mode to decode the data stream, and provides the decoded data to the data link layer of the network card 11 .
  • the embodiment of the present application Based on the architecture of the electronic device 100 shown in FIG. 1, the frame structure of the control word shown in FIG. 2, and the hardware architecture of the physical layer of the interface controller 10 (or network card 11) shown in FIG. 4, the embodiment of the present application also provides a data transmission method, which can be applied to the electronic device 100 shown in FIG.
  • the following describes the data transmission method provided by the embodiment of the present application by taking the interface controller 10 as the sending end and the network card 11 as the receiving end as an example.
  • the sending end and the receiving end may be executed by one or more components shown in FIG. 2 .
  • the interface controller 10 may transmit the control word to the network card 11 at any data transmission stage.
  • control word can be added to the training data transmitted in the link training phase, the control word can also be added to the business data transmitted in the service data transmission phase, or the control word can be added to the training data transmitted in the link reset phase.
  • control word can be set before the service data, can also be set at any position of the service data based on the clock cycle, can also be set before the training data, and can also be set after the training data, which is not specifically limited in this embodiment of the present application. Please refer to FIG. 5.
  • FIG. 5 is a flow 500 of the data transmission method provided by the embodiment of the present application.
  • the data transmission method includes:
  • Step 501 the interface controller 10 generates a bit stream, the bit stream includes data and control words, and the control word includes: a start field for indicating the start position information of the control word, an end field for indicating the end position information of the control word, and a load field for carrying link information indicating a wired serial link.
  • the interface controller 10 sends the bit stream through the wired serial link.
  • Step 503 the network card 11 reads the control word from the bit stream based on the start field and the end field; step 504, reads the data from the bit stream based on the control word.
  • the data may be, for example, one of service data or training data.
  • the control word is, for example, the structure shown in FIG. 2 .
  • the link information may include, but not limited to, one or more of the following: the clock cycle for adding the control word to the data, the power consumption status of the hardware in the link, the working status of the circuits in the link, and the output gain of the codec circuit in the link.
  • the start field and end field of the control word may indicate the length of the control word.
  • the control word can be followed by the data content of the data. That is to say, the start field and end field of the control word can serve as the frame header of the data frame.
  • the receiving end recognizes the start field and end field of the control word, it can determine the start position of the data and read the data from the bit stream.
  • the control word provided by the embodiment of the present application is configured to include a start field, an end field, and a payload field, and the link information is carried in the payload field, so that multiple link information can be indicated in one control word, which simplifies the design of the physical layer.
  • the end field of the control word is used to indicate the end position information of the control word, that is, the end field of the control word can limit the length of the control word; furthermore, by flexibly adjusting the end position information of the control word, the number of link information carried in the control word can be flexibly adjusted, thereby providing the flexibility of the control word.
  • the bit stream includes training data and control words, and the bit stream includes service data and control words as examples, and the interface controller 10 transmits data to the network card 11 through four lanes as an example.
  • the data transmission method provided by the embodiment of the present application is described through a more specific scenario. Please continue to refer to FIG. 6.
  • FIG. 6 is a flow 600 of the data transmission method provided by the embodiment of the present application.
  • the data transmission method includes:
  • step 601 the interface controller 10 adds control words C0-C3 to the training data D0-D3 respectively to generate bit streams B0-B3.
  • This step is in the link training phase.
  • the link training phase is used to align the link status of the interface controller 10 with the link status between the network cards 11 .
  • the interface controller 10 may distribute the preset training data D0-D3 to lane0-lane3.
  • the interface controller 10 can also generate control words C0 to C3 based on the current link information (for example, the link enters medium power consumption, all hardware circuits in the physical layer are powered on, the gain of the link encoder in the physical layer is "1", and the link encoding mode is forward error encoding), the clock cycle for adding the control word to the training data, and the frame structure of the control word as shown in FIG. 2 .
  • the lane identification field of the control word C0 is used to indicate lane0
  • the lane identification field of the control word C1 is used to indicate lane1
  • the lane identification field of the control word C2 is used to indicate lane2
  • the lane identification field of the control word C3 is used to indicate lane3.
  • the interface controller 10 adds the control word C0 to the control word C3 to the training data D0 to D3 respectively to generate bit streams B0 to B3.
  • the interface controller 10 transmits the bit streams B0-B3 to the network card 11 through lane0-lane3 respectively.
  • step 603 the network card 11 recognizes the control word C0-C3 from the bit stream B0-B3 based on the start field indicating the start position of the control word C0-C3 and the end field indicating the end position of the control word C0-C3.
  • step 604 the network card 11 adjusts the connection sequence of the links based on the channel identifiers carried in the channel identifier fields in the control word C0 to the control word C3. This step is used to realize the alignment of the link number and the sequence of the data flow.
  • the interface controller 10 transmits the bit stream B0-B1-B2-B3 respectively through lane0-lane1-lane2-lane3; and the data stream received by the network card 11 from lane0-lane1-lane2-lane3 is actually B3-B2-B1-B0, that is, the number of the lane in the interface controller 10 and the number of the lane in the network card 11 are completely reversed.
  • the network card 11 can relabel the lane numbers in the network card 11 based on the channel identification fields in each control word, so as to achieve alignment with the lane numbers in the interface controller 10 .
  • the network card 11 adjusts the link state based on the link information indicated by the payload field in the control word C0-C3.
  • the link information is used to indicate that the link enters medium power consumption, all hardware circuits in the physical layer are powered on, and the gain of the link encoder in the physical layer is "1".
  • the network card 11 adjusts the power consumption state of hardware circuits in the link such as amplifiers and encoders to a medium power consumption state, and adjusts the gain of the link encoder to "1" and so on.
  • the network card 11 aligns the data transmitted by each lane based on the order in which the bit streams B0-B3 are received.
  • step 607 the interface controller 10 adds control words C4 to C7 to the training data D4 to D7 respectively to generate bit streams B4 to B7, wherein the payload fields of the control words C4 to C7 carry indication information indicating the transmission of service data in the next cycle.
  • This step is in the link training phase.
  • the interface controller 10 may also carry the indication information indicating the next period of service data transmission in the payload field of the control word C4 to the control word C7, and the payload field of the control word C4 to the control word C7 may also include the link information as described in step 601.
  • control words C4-C7 also include a start field, an end field, and a channel identification field.
  • the interface controller 10 adds the control word C4 to the control word C7 to the training data D4 to D7 respectively to generate bit streams B4 to B7.
  • Step 608 the interface controller 10 transmits the bit streams B4-B7 to the network card 11 through lane0-lane3 respectively.
  • step 609 the interface controller 10 adds control words C8 to C111 to the service data D8 to D111 respectively to generate bit streams B8 to B111.
  • the interface controller 10 can obtain the data frame from the data link layer. Based on a preset encoding format (for example, a forward error encoding format), the interface controller 10 encodes the data frame to generate service data D8-D11.
  • the interface controller 10 can distribute the service data D8-D11 to lane0-lane3. Then, the interface controller 10 generates control words C8 to C11 based on the current link information, the number of lanes used, the clock cycle for adding the control word to the training data, and the frame structure of the control word shown in FIG. 2 .
  • the interface controller 10 adds the control word C8-C111 to the training data D8-D111 respectively to generate bit streams B8-B111.
  • the control words C8-C111 may be added to preset positions of the service data D8-D111 respectively. The preset position may be, for example, before the service data.
  • the interface controller 10 transmits the bit streams B8-B111 to the network card 11 through lane0-lane3 respectively.
  • the network card 11 identifies the control word C8-C111 from the bit stream B8-B111 based on the start field indicating the start position of the control word C8-C111 and the end field indicating the end position of the control word C8-C111, and reads the service data D8-D111 from the bit stream B8-B111.
  • the network card 11 can delimit the service data frame based on the position of the control word in the bit stream, that is, determine the starting position of the service data.
  • the position of the service data in the bit stream is at a preset position after the control word. For example, the second bit after the end bit of the control word is the start bit of the service data.
  • the network card 11 After the network card 11 reads the end field of the control word, it can determine the end bit of the control word, and then the network card 11 can start to read the service data from the second bit after the end bit of the control word. Step 612 , based on the encoding format adopted by the interface controller 10 , the network card 11 decodes the read service data D8-D111 to obtain decoded data frames.
  • the above-mentioned process 600 of the data transmission method is schematic. It can be understood that the data transmission method provided in the embodiment of the present application may include more or less processes than the process 600 .
  • the network card 11 may also transmit to the interface controller 10 information indicating that the link setting is completed.
  • the network card 11 may also send a bit stream to the interface controller 10, the bit stream includes training data and a control word added to the training data, and the control word is used to indicate the link status of the physical layer of the network card 11.
  • the interface controller includes corresponding hardware and/or software modules for performing various functions.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions in combination with the embodiments for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.
  • FIG. 7 shows a possible schematic diagram of a data transmission device 700 .
  • the data transmission device 700 may include: a processing unit 701 and a sending unit 702 , which may further expand the aforementioned device.
  • the processing unit 701 is configured to generate a bit stream, the bit stream includes data and a control word, and the control word includes: a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a third field for carrying link information indicating a wired serial link.
  • the sending unit 702 is configured to send the bit stream through the wired serial link.
  • the link information includes at least one of the following: the number of channels for transmitting bit streams, the power consumption status of hardware in the link, the working status of circuits in the link, or the gain of a codec used in the link.
  • the first field and the second field are used to instruct the receiving end to delimit the data frame.
  • the bit stream includes multiple channels
  • the wired serial link includes multiple channels
  • the multiple bit streams correspond to the multiple channels one by one
  • the sending unit 702 is specifically configured to: send the corresponding multiple bit streams through the multiple channels.
  • control word further includes a fourth field for indicating a channel number.
  • the first field includes multiple sets of identical fields, and each set of fields includes multiple bits; the multiple sets of identical fields are used to compensate for the difference between the clock cycle of the sending end and the clock cycle of the receiving end.
  • the data transmission device 700 provided in this embodiment is used in the data transmission method executed by the interface controller 10, and can achieve the same effect as the above-mentioned implementation method or device.
  • the above modules corresponding to FIG. 7 may be implemented by software, hardware or a combination of the two.
  • each module can be implemented in the form of software, corresponding to the processor 102 and the interface 101 corresponding to the module in FIG. 1 , and used to drive the corresponding components to work.
  • each module may include corresponding components and corresponding driver software, that is, implemented in combination of software or hardware. Therefore, the data transmission device 700 can be considered to logically include the interface controller 10 shown in FIG. 1 and FIG. 4 , and each module includes at least a driver software program for a corresponding function, which is not expanded in this embodiment.
  • FIG. 8 shows a possible schematic diagram of a data transmission device 800 .
  • the data transmission device 800 may include: a receiving unit 801 and a processing unit 802 , which may further expand the aforementioned device.
  • the receiving unit 801 is configured to receive a bit stream, the bit stream includes data and a control word, and the control word includes a first field for indicating the start position information of the control word, a second field for indicating the end position information of the control word, and a load field for carrying link information indicating a wired serial link.
  • the processing unit 802 is configured to read the control word from the bit stream based on the first field and the second field; and read the data from the bit stream based on the control word.
  • the processing unit 802 is further configured to: adjust at least one of the following of the wired serial link based on the link information: a power consumption state of hardware in the link, a working state of a circuit in the link, or a codec gain used in the link.
  • the processing unit 802 is specifically configured to: determine a code length of the control word based on the first field and the second field; identify a frame start position of the data from the bit stream based on the code length of the control word, where the frame start position of the data is located after the control word; and read the data based on the frame start position of the data.
  • the bit stream includes multiple channels
  • the wired serial link includes multiple channels
  • the multiple bit streams are received from the sending end through the corresponding multiple channels
  • the link information also includes the number of channels for transmitting the bit stream
  • the control word also includes a channel identification field for indicating the channel number
  • the processing unit 802 is specifically configured to: based on the number of channels for transmitting the bit stream and the channel identification field, read the data from the bit stream received by the corresponding channel.
  • the processing unit 802 is further configured to: eliminate data skew between each of the multiple channels based on the received sequence of the multiple bit streams and the channel identification field in each of the multiple control words in the multiple bit streams.
  • the first field includes multiple sets of identical fields, and each set of fields includes multiple bits; and the processing unit 802 is further configured to: based on the clock frequency deviation with the sending end, perform one of the following operations: delete at least one set of the multiple sets of identical fields, or add at least one set of the multiple sets of identical fields.
  • the data transmission device 800 can use the data transmission method executed by the network card 11 to achieve the same effect as the above implementation method or device.
  • the above modules corresponding to FIG. 8 may be implemented by software, hardware or a combination of the two.
  • each module can be implemented in the form of software, corresponding to the interface 111 and processor 112 corresponding to the module in FIG. 1 , and used to drive the corresponding components to work.
  • each module may include corresponding components and corresponding driver software, that is, implemented in combination of software or hardware. Therefore, the data transmission device 500 can be considered to logically include the network card 11 shown in FIG. 1 and FIG. 4 , and each module includes at least a driver software program for a corresponding function, which is not expanded in this embodiment.
  • the disclosed system and device can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art or a part of the technical solution.
  • the computer software product is stored in a storage medium and includes several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the application.
  • the aforementioned storage medium or memory includes various media capable of storing program codes such as U disk, mobile hard disk, ROM, RAM, magnetic disk or optical disk.

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Abstract

本申请实施例提供了一种数据传输方法和数据传输装置，该数据传输方法包括：生成比特流，所述比特流包括数据和控制字，所述控制字包括：用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段以及用于承载指示有线串行链路的链路信息的第三字段；通过所述有线串行链路发送所述比特流，该数据传输方法可以降低物理层所传输的控制信号的复杂度。

Description

数据传输方法和数据传输装置 技术领域
本申请实施例涉及通信网络领域，尤其涉及一种数据传输方法和数据传输装置。
背景技术
通信网络技术中，各通信装置之间通常通过数据链路通信，信号发送端中的物理层将比特流通过链路传输至信号接收端中的物理层，从而实现通信设备之间的信号交流。为了使得信号接收端能够从比特流中准确解码出数据，比特流中除了包括已编码的数据信号之外，通常还会包括指示链路配置或者链路状态等信息的多种控制信号。例如，多种控制信号包括指示数据包帧定界的控制信号、指示链路带宽的控制信号等。该多种控制信号分别为独立的编码段。此外，该多个控制信号通常添加数据信号的特定位置处传输。
然而，随着物理层工作速率的持续演进以及对链路等更加精确的控制，这就需要设置更多个控制信号以满足要求，导致控制信号的数量庞大，进而导致通信装置中物理层的设计极其复杂，提高了物理层成本。由此，如何降低物理层所传输的控制信号的复杂度成为需要解决的问题。
发明内容
本申请提供的数据传输方法和数据传输装置，可以降低物理层所传输的控制信号的复杂度。为达到上述目的，本申请采用如下技术方案。
第一方面，本申请实施例提供一种数据传输方法，该数据传输方法应用于发送端，该数据传输方法包括：生成比特流，所述比特流包括数据和控制字，所述控制字包括：用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段以及用于承载指示有线串行链路的链路信息的第三字段；通过所述比特流发送所述有线串行链路。
该实现方式中，发送端例如可以为图1、图4和图5中所示的接口控制器。用于指示所述控制字起始位置信息的第一字段，例如可以为图2中所示的起始字段；用于指示所述控制字结束位置信息的第二字段，例如可以为图2中所示的结束字段；用于承载指示有线串行链路的链路信息的第三字段例如可以为图2中所示的载荷字段。
传统有线串行链路中，用于传输数据的两通信装置之间、实现链路对齐的各种链路信息通常为编码段，一种信息为一个编码段。例如，指示链路功耗的信息为一个编码段、指示链路中各电路的状态的信息为一个编码段，也即实现链路对齐的编码段包括多个。然而，随着物理层工作速率的持续演进以及对链路等更加精确的控制，这就需要设置更多的链路信息以满足要求，导致链路信息的数量庞大，也即编码段的数量庞大，进而导致通信装置中物理层的设计极其复杂，提高了物理层设计成本。本申请实施例提供的控制字，通过设置成包括第一字段、第二字段以及第三字段的结构，将链路信息承载于第三字段中，从而 可以实现在一个控制字中指示出多种链路信息，降低物理层所传输的控制信号的复杂度，简化了物理层的设计。另外，由于控制字的第二字段用于指示控制字的结束位置信息，也即控制字的第二字段可以限定出控制字的长度；进而，通过灵活调整控制字的结束位置信息，即可灵活调整控制字中所承载的链路信息的数目，从而提供了控制字的灵活性。
可选的，结束位置信息可以为控制字的长度或者结束位置。该结束位置例如可以为：从第二字段开始起的预设数目个比特位。
可选的，所述数据为业务数据或者训练数据。
在一种可能的实现方式中，所述链路信息包括以下至少一项：传输第一比特流的通道数目、链路中的硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
为了降低物理层链路中硬件的功耗，链路中各硬件的功耗通常包括多种，例如低功耗、中等功耗和高功耗。例如，链路中所包括的诸如扰码器、数据分配器等硬件均处于待机、休眠或下电中的一项时，链路中硬件为低功耗状态；链路中所包括的部件硬件处于待机、休眠或下电中的一项、另外一部分硬件处于工作状态时，链路中的硬件为中等功耗；链路中所有的器件均工作时，链路中的硬件为高功耗。例如，当所传输的数据为训练数据时，可以指示链路中各硬件的功耗为低功耗；当所传输的数据为业务数据时，可以指示链路中各硬件的功耗为中等功耗或高功耗。链路中电路的工作状态例如可以包括上电状态或下电状态。例如，当所传输的数据为训练数据时，可以使得编解码电路的状态为下电状态；当所传输的数据为业务数据时，可以使得编解码电路的状态为上电状态。从而，发送端可以将多种功耗状态中的一种、将指示链路中电路的工作状态的一种以及编解码器的增益等信息承载于第三字段中，传输至接收端。
在一种可能的实现方式中，所述第一字段和所述第二字段，用于指示接收端对所述数据帧定界。
该可能的实现方式中，控制字之后可以为数据的数据内容；也即是说，控制字的第一字段和第二字段可以充当数据帧的帧头，当接收端识别出控制字的第一字段和第二字段后，即可判定出数据的起始位置(也即帧定界)，以从比特流中读取出数据。本申请实施例通过将控制字的第一字段和第二字段充当数据帧的帧头，可以不需要额外设置数据帧的帧头，从而可以简化比特流的设计。
在一种可能的实现方式中，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流与所述多条通道一一对应；所述通过所述有线串行链路发送所述比特流，具体包括：通过所述多条通道发送对应的所述多条比特流。
当有线串行链路包括多条通道时，通过在每条通道中分别设置一个控制字，可以使得接收端基于每一条通道中的控制字，从每一条通道传输的比特流中准确读取出数据，提高接收端数据读取的准确性。
在一种可能的实现方式中，所述控制字还包括用于指示通道编号的第四字段。
第四字段例如可以为图2所示的通道标识字段。
该实现方式中，通过设置控制字中通过设置指示通道编号的第四字段，可以使得接收端基于每一个通道编号，调整从每一个通道接收到的数据的顺序，从而提高接收端所接收到的数据的准确性。
在一种可能的实现方式中，所述第一字段包括多组相同的字段，每一组字段包括多个 比特位；所述多组相同的字段用于补偿所述发送端的时钟周期、与接收端时钟周期之间的差异。
该实现方式中，发送端可以将上述第一字段编码成连续的“0”“1”信号，然后基于本地时钟周期，通过有线串行链路向接收端发送比特流；当接收端接收到比特流后，首先从第一字段中恢复出发送端的时钟周期；然后，接收端基于所恢复出的时钟周期与本地周期之间的偏差，添加或删除多组相同的字段中的至少一组字段。
例如，接收端中可以设置有缓冲队列，接收端基于从第一字段中恢复出的时钟周期，向缓冲队列中写入第一字段承载的数据，此外，接收端还可以基于本地时钟周期从缓冲队列中读取数据，二者同时进行。当接收端检测出写入缓冲队列的数据的速率，大于从缓冲队列读取数据的速率时，则说明发送端的时钟周期大于接收端的时钟周期，此时删除第一字段所包括的多组相同的字段中的至少一组字段，以保证发送端与接收端之间的时钟周期同步；当接收端检测出写入缓冲队列的数据的速率，小于从缓冲队列读取数据的速率时，则说明发送端的时钟周期小于接收端的时钟周期，此时在第一字段中添加所述多组相同的字段中的至少一组，以实现发送端与接收端之间的时钟周期同步。
传统技术中，由于未设置具有结构化的控制字，通常在传输的比特流中设置专用于补偿发送端时钟周期与接收端时钟周期差异的序列，该序列不携带任何有用数据。本申请实施例通过在控制字的第一字段设置多组相同的字段，可以使得该控制字实现更多的功能，也即不需要比特流中额外设置专用于补偿发送端时钟周期与接收端时钟周期差异的序列；与现有技术相比，可以简化物理层的设计。
在一种可能的实现方式中，当所述数据为训练数据时，所述生成比特流包括：在所述数据之后添加所述控制字，以生成所述比特流。
第二方面，本申请实施例提供一种数据传输方法，该数据传输方法应用于接收端，该数据传输方法包括：接收比特流，所述比特流包括数据以及控制字，所述控制字包括用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段、以及用于承载指示有线串行链路的链路信息的第三字段；基于所述第一字段和所述第二字段，从所述比特流中读取所述控制字；基于所述控制字，从所述比特流中读取所述数据。
该实现方式中，接收端例如可以为图1、图4和图5中所示的网卡。用于指示所述控制字起始位置信息的第一字段，例如可以为图2中所示的起始字段；用于指示所述控制字结束位置信息的第二字段，例如可以为图2中所示的结束字段；用于承载指示有线串行链路的链路信息的第三字段例如可以为图2中所示的载荷字段。
本申请实施例提供的控制字，通过设置成包括第一字段、第二字段以及第三字段的结构，将链路信息承载于第三字段中，从而可以实现在一个控制字中指示出多种链路信息，简化了物理层的设计。另外，由于控制字的第二字段用于指示控制字的结束位置信息，也即控制字的第二字段可以限定出控制字的长度；进而，通过灵活调整控制字的结束位置信息，即可灵活调整控制字中所承载的链路信息的数目，从而提供了控制字的灵活性。
在一种可能的实现方式中，所述方法还包括：基于所述链路信息，调整所述有线串行链路的以下至少一项：链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
为了降低物理层链路中硬件的功耗，链路中各硬件的功耗通常包括多种，例如低功耗、 中等功耗和高功耗。例如，当所传输的数据为训练数据时，可以指示链路中各硬件的功耗为低功耗；当所传输的数据为业务数据时，可以指示链路中各硬件的功耗为中等功耗或高功耗。链路中电路的工作状态例如可以包括上电状态或下电状态。例如，当所传输的数据为训练数据时，可以使得编解码电路的状态为下电状态；当所传输的数据为业务数据时，可以使得编解码电路的状态为上电状态。接收端基于第三字段中所指示的多种功耗状态中的一种、链路中电路的工作状态的一种以及编解码器的增益，将链路中的硬件的功耗状态调整为第三字段中所指示的功耗状态、将链路中电路的工作状态调整为第三字段所指示的工作状态、将编解码器的增益调整为与第三字段中所指示的增益。
在一种可能的实现方式中，所述基于所述控制字，从所述比特流中读取所述数据，包括：基于所述第一字段和所述第二字段，确定所述控制字的编码长度；基于所述控制字的编码长度，从所述比特流中识别出所述数据的帧起始位置，其中，所述数据的帧起始位置位于所述控制字之后；基于所述数据的帧起始位置，读取所述数据。
该可能的实现方式中，控制字之后可以为数据的数据内容；也即是说，控制字的第一字段和第二字段可以充当数据帧的帧头，当接收端识别出控制字的第一字段和第二字段后，即可判定出数据的起始位置，以从比特流中读取出数据。本申请实施例通过将控制字的第一字段和第二字段充当数据帧的帧头，可以不需要额外设置数据帧的帧头，从而可以简化比特流的设计。
在一种可能的实现方式中，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流通过相对应的所述多条通道从所述发送端接收；所述链路信息还包括传输所述比特流的通道数目；所述控制字还包括用于指示通道编号的第四字段；所述基于所述控制字，从所述比特流中读取数据，包括：基于传输所述比特流的通道数目以及所述第四字段，从相应通道所接收的比特流中读取所述数据。
第四字段例如可以为图2所示的通道标识字段。
在一种可能的实现方式中，所述方法还包括：基于所接收到的所述多条比特流的先后顺序、以及所述多条比特流中的多个控制字的每一个控制字中的第四字段，消除所述多条通道中每一条通道之间的数据偏斜。
在一种可能的实现方式中，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；以及所述方法还包括：基于与所述发送端之间的时钟频率偏差，执行以下一项操作：删除所述多组相同的字段中的至少一组，或者增加所述多组相同的字段中的至少一组。
该实现方式中，发送端可以将上述第一字段编码成连续的“0”“1”信号，然后基于本地时钟周期，通过有线串行链路向接收端发送比特流；当接收端接收到比特流后，首先从第一字段中恢复出发送端的时钟周期；然后，接收端基于所恢复出的时钟周期与本地周期之间的偏差，添加或删除多组相同的字段中的至少一组字段。
例如，接收端中可以设置有缓冲队列，接收端基于从第一字段中恢复出的时钟周期，向缓冲队列中写入第一字段承载的数据，此外，接收端还可以基于本地时钟周期从缓冲队列中读取数据，二者同时进行。当接收端检测出写入缓冲队列的数据的速率，大于从缓冲队列读取数据的速率时，则说明发送端的时钟周期大于接收端的时钟周期，此时删除第一字段所包括的多组相同的字段中的至少一组字段，以保证发送端与接收端之间的时钟周期同步；当接收端检测出写入缓冲队列的数据的速率，小于从缓冲队列读取数据的速率时， 则说明发送端的时钟周期小于接收端的时钟周期，此时在第一字段中添加所述多组相同的字段中的至少一组，以实现发送端与接收端之间的时钟周期同步。
传统技术中，由于未设置具有结构化的控制字，通常在传输的比特流中设置专用于补偿发送端时钟周期与接收端时钟周期差异的序列，该序列不携带任何有用数据。本申请实施例通过在控制字的第一字段设置多组相同的字段，可以使得该控制字实现更多的功能，也即不需要比特流中额外设置专用于补偿发送端时钟周期与接收端时钟周期差异的序列；与现有技术相比，可以简化物理层的设计。
第三方面，本申请实施例提供一种数据传输装置，该数据传输装置包括所述数据传输装置包括处理器和接口；所述处理器用于生成比特流，所述比特流包括数据和控制字，所述控制字包括：用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段以及用于承载指示有线串行链路的链路信息的第三字段；所述接口，通过所述有线串行链路发送所述比特流。
在一种可能的实现方式中，所述链路信息包括以下至少一项：传输比特流的通道数目、链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
在一种可能的实现方式中，所述第一字段和所述第二字段，用于指示所述接收端对所述数据帧定界。
在一种可能的实现方式中，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流与所述多条通道一一对应；所述接口具体用于：通过所述多条通道发送对应的所述多条比特流。
在一种可能的实现方式中，所述控制字还包括用于指示通道编号的第四字段。
在一种可能的实现方式中，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；所述多组相同的字段用于补偿所述发送端的时钟周期、与接收端时钟周期之间的差异。
第四方面，本申请实施例提供一种数据传输装置，该数据传输装置包括所述数据传输装置包括处理器和接口；所述接口用于接收比特流，所述比特流包括数据以及控制字，所述控制字包括用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段、以及用于承载指示有线串行链路的链路信息的第三字段；所述处理器，用于基于所述第一字段和所述第二字段，从所述比特流中读取所述控制字；基于所述控制字，从所述比特流中读取所述数据。
在一种可能的实现方式中，所述处理器还用于：基于所述链路信息，调整所述有线串行链路的以下至少一项：链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
在一种可能的实现方式中，所述处理器具体用于：基于所述第一字段和所述第二字段，确定所述控制字的编码长度；基于所述控制字的编码长度，从所述比特流中识别出所述数据的帧起始位置，其中，所述数据的帧起始位置位于所述控制字之后；基于所述数据的帧起始位置，读取所述数据。
在一种可能的实现方式中，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流通过相对应的所述多条通道从所述发送端接收；所述链路信息还包括传输所述比特流的通道数目；所述控制字还包括用于指示通道编号的第四字段；所述处理器具 体用于：基于传输所述比特流的通道数目以及所述第四字段，从相应通道所接收的比特流中读取所述数据。
在一种可能的实现方式中，所述处理器还用于：基于所接收到的所述多条比特流的先后顺序、以及所述多条比特流中的多个控制字的每一个控制字中的第四字段，消除所述多条通道中每一条通道之间的数据偏斜。
在一种可能的实现方式中，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；以及所述处理器还用于：基于与所述发送端之间的时钟频率偏差，执行以下一项操作：删除所述多组相同的字段中的至少一组，或者增加所述多组相同的字段中的至少一组。
第五方面，本申请实施例提供一种计算机可读存储介质，用于存储计算机程序，所述计算机程序被处理器运行时，实现如上述第一方面所述的数据传输方法或如上述第二方面所述的数据传输方法。
第六方面，本申请实施例提供一种计算机程序产品，当所述计算机程序产品在处理器上运行时，实现如上述第一方面所述的数据传输方法或如上述第二方面所述的数据传输方法。
应当理解的是，本申请的第二方面～第六方面与本申请的第一方面的技术方案一致，各方面及对应的可行实施方式所取得的有益效果相似，不再赘述。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的电子设备的一个硬件架构示意图；
图2是本申请实施例提供的控制字的帧结构的一个示意图；
图3A是本申请实施例提供的eBCH码字集合的一个示意图；
图3B是本申请实施例提供的通道标识的编码结构的一个示意图；
图4是本申请实施例提供的物理层的一个硬件架构示意图；
图5是本申请实施例提供的数据传输方法的一个流程图；
图6是本申请实施例提供的数据传输方法的又一个流程图；
图7是本申请实施例提供的数据传输装置的一个结构示意图；
图8是本申请实施例提供的数据传输装置的又一个结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、或"第二"以及类似的词语并不表示任何顺序、数量或者重要性， 而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。"耦合"等类似的词语并非限定于物理的或者机械的直接连接，而是可以包括电性的连接，不管是直接的还是间接的，等同于广义上的联通。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个通道是指两个或两个以上的通道。
本申请实施例提供的数据传输系统，可以包括发送端和接收端。发送端和接收端均可以是一个电子设备，该电子设备例如可以是一个终端设备，如手机、PC端电脑、平板电脑、笔记本电脑、或可穿戴设备(如智能手表、AR设备、VR设备)等各种类型的便携式设备)；该电子设备也可以为交换机设备或者路由器设备等。一种应用场景中，发送端可以是终端设备，接收端可以是路由器设备，终端设备通过有线串行链路与路由器设备通信，以向路由器设备传输信号。在该应用场景下，当路由器设备向终端设备传输信号时，路由器设备也可以称为发送端，终端设备也可以称为接收端。
此外，发送端和接收端也可以是设置于电子设备内的模组、芯片、芯片组、搭载有芯片或芯片组的电路板或部件。该电子设备例如为如上所述的电子设备。该电子设备中可以设置有网卡(network card)，从而该电子设备可以通过网卡接入网络中以进行通信，该网络例如可以为以太网。一种应用场景中，发送端可以是集成于电子设备内的接口控制器；接收端可以是设置于电子设备内的网卡。接口控制器与网卡之间可以通过有线串行链路通信。接口控制器通过有线串行链路向网卡传输比特流，网卡将所接收到的比特流进行以太网帧封装，发送至以太网中。在该应用场景下，当网卡从以太网接收到比特流后，需要将所接收到的比特流传输至接口控制器，此时接口控制器为发送端，网卡为接收端。本申请实施例以发送端为接口控制器、接收端为网卡为例进行描述，但不用于对方案的限定。
请参考图1，图1是本申请实施例提供的电子设备100的一个结构示意图。在图1中，电子设备100包括一个或多个处理器，该一个或多个处理器例如包括接口控制器10、中央处理器(CPU，central processing unit)12等。可选的，该一个或多个处理器可以集成在一个或多个芯片内，所述一个或多个芯片可以被视为是一个芯片组。一种可选的实现方式中，接口控制器10和CPU12可以集成于如图1所示的系统级芯片(SOC，system on chip)中，该SOC中还可以集成有诸如存储器13、直接内存访问控制器(DMAC，direct memory access controler)14等装置或部件。其中，接口控制器10、CPU12、存储器13和DMAC14之间通过总线进行信号传输。CPU12中可以运行有诸如操作系统软件和应用软件等软件程序或软件插件，存储器13中可以存储有CPU12运行所需要的软件程序或软件插件。此外存储器13中还可以存储有CPU12运行所需要的指令和数据，CPU12通过DMAC14从存储器13中获得该指令和数据。
如图1所示，电子设备100中还包括网卡11。网卡11可以设置于图1所示的SOC之外。接口控制器10包括接口101和处理器102，网卡11包括接口111和处理器112，网卡11通过接口111与接口控制器10中的接口101耦合。一种可选的实现方式中，接口101和接口111可以分别为serdes(串行器/解串行器，serializer and deserializer)接口。 接口101和接口111之间可以通过各种物理媒介(例如双绞线或电缆等)耦合。从而，电子设备100通过网卡11接入到网络中，与网络中的其他设备(例如服务器设备或者终端设备等)通信，以进行数据交换。一种可能的实现方式中，处理器102和处理器112，可以分别包括编码器、解码器、控制字生成器和链路训练状态机等部件，另外，处理器102和处理器112还可以选择性的包括扰码器、解扰码器等部件。其中，接口控制器10和网卡11更为详细的结构参考图4的相关描述。
本申请实施例中，电子设备100的通信网络模型可以遵从OSI(开放系统互联基本参考模型，open system interconnection reference model)标准。OSI具体可以包括应用层(application layer)、传输层(transportation layer)、数据链路层(data link layer)和物理层(physical layer)，另外还可以包括更多的层，本申请实施例对此不做具体限定。应用层可以包括CPU12中运行的应用软件。例如视频播放类应用、即时通信类应用等。传输层用于描述系统的传输层协议规范，包括数据类型、结构的定义及排布，路由控制，带宽管理等。数据链路层用于对传输层提供的数据报文封装成数据帧以及提供透明传输。物理层用于定义数据传送与接收所需要的有线串行链路的链路状态、时钟基准、数据编码和电路等，以及向数据链路层提供标准接口。物理层将数据帧进行编码生成比特流，将比特流通过有线串行链路传输。需要说明的是，本申请实施例提供的接口控制器10和网卡11，通常工作在OSI标准中的物理层。
电子设备100运行过程中，接口控制器10中的处理器102可以获得原始的数据报文(例如，CPU12可以触发处理器102从存储器13读取数据报文)；处理器102对所获得的数据报文进行处理(例如，封装成数据帧以及进行汉明编码)，生成比特流通过接口101输出至网卡11；网卡11中的接口111接收比特流，网卡11中的处理器112对所接收到的比特流进行进一步处理(例如解码获得数据帧、对数据帧进行以太网帧封装以及曼彻斯特编码等)，然后传输至网络中。同样，网卡11可以从网络接收到数据帧后，进行处理(例如进行曼彻斯特解码、去除以太网帧以及汉明编码等)，然后通过接口111传输至接口控制器10；接口控制器10对所获得的数据帧进行进一步处理(例如进行解码和解封装)后，生成数据报文存储至存储器13中或者直接提供至CPU12。
本申请实施例中，为了实现低误码率的信号传输，接口控制器10(也即发送端)向网卡11(也即接收端)输的比特流中，除了包括对数据帧编码得到的数据之外，还包括控制字，如图2所示，图2示意性的示出了接口控制器10向网卡11传输的比特流。该控制字用于指示有线串行链路的链路状态、时钟基准、数据帧定界等信息。从而接收端的物理层基于控制字，确定出数据的帧定界、调整时钟基准、调整链路状态等。其中，控制字包括用于指示控制字起始位置信息的起始字段、用于指示控制字结束位置信息的结束字段以及用于承载指示信息的载荷字段。该载荷字段所承载的指示信息用于指示有线串行链路的链路信息。
传统有线串行链路中，用于传输数据的两通信装置之间、实现链路对齐的各种链路信息通常为编码段，一种信息为一个编码段。例如，指示链路功耗的信息为一个编码段、指示链路中各电路的状态的信息为一个编码段，也即实现链路对齐的编码段包括多个。然而，随着物理层工作速率的持续演进以及对链路等更加精确的控制，这就需要设置更多的链路信息以满足要求，导致链路信息的数量庞大，也即编码段的数量庞大，进而导致通信装置 中物理层的设计极其复杂，提高了物理层设计成本。本申请实施例提供的控制字，通过设置成包括起始字段、结束字段以及载荷字段的结构，将链路信息承载于载荷字段中，从而可以实现在一个控制字中指示出多种链路信息，简化了物理层的设计。另外，由于控制字的结束字段用于指示控制字的结束位置信息，也即控制字的结束字段可以限定出控制字的长度；进而，通过灵活调整控制字的结束位置信息，即可灵活调整控制字中所承载的链路信息的数目，从而提供了控制字的灵活性。
需要说明的是，如图2所示的比特流中，数据位于控制字的左边，比特流发送过程中，先发送控制字的信号、再发送数据信号。图2所示的实现方式中，数据例如可以为业务数据。可选的，数据也可以位于控制字的右边，比特流发送过程中，先发送数据信号、再发送控制字信号，该实现方式中，数据例如可以为训练数据。此外，由于数据和控制字在物理层中被编码为“0”、“1”信号，控制字也可以设置于数据的任意位置处。
请继续参考图2，图2中进一步示意性的示出了控制字的帧结构。在图2中，控制字包括指示控制字起始位置信息的起始字段U_I、用于指示控制字结束位置的结束字段U_END以及用于指示有线串行链路的链路信息的载荷字段payload。下面结合图2所示的控制字的帧结构，对控制字进行更为详细的描述。
起始字段U_I中，包括至少一组U_ID0～U_IDN该多个比特位。也即是说，图2所示的帧结构中，前N+1位为控制字的头部，该N+1位头部可以使得网卡11识别出控制字的起始字段。为了保证控制字具有一定的容错能力，同时为了补偿发送端的时钟周期、与接收端时钟周期之间的差异，本申请实施例一种可选的实现方式中，起始字段U_I的长度可以在预设范围内变化。例如，起始字段U_I可以包括多组重复的U_ID0～U_IDN，其中起始字段U_I的可变长度例如可以为8字节。假设N为4，U_ID0～U_IDN为00101，则起始字段U_I可以为001010010100101该三组重复的码流。
接口控制器10可以将起始字段编码成连续的“0”“1”信号，然后基于本地时钟周期，通过有线串行链路向网卡11发送比特流；当网卡11接收到比特流后，首先从起始字段中恢复出接口控制器10的时钟周期；然后，网卡11基于所恢复出的时钟周期与本地周期之间的偏差，添加或删除多组相同的字段中的至少一组字段。具体的，网卡11中可以设置有缓冲队列，网卡11基于从起始字段中恢复出的时钟周期，向缓冲队列中写入起始字段承载的数据，此外，网卡11还可以基于本地时钟周期从缓冲队列中读取数据，二者同时进行。当网卡11检测出写入缓冲队列的数据的速率，大于从缓冲队列读取数据的速率时，则说明接口控制器10的时钟周期大于网卡11的时钟周期，此时删除起始字段U_I中的一组或多组U_ID0～U_IDN，以保证接口控制器10与网卡11之间的时钟周期同步；当网卡11检测出写入缓冲队列的数据的速率，小于从缓冲队列读取数据的速率时，则说明接口控制器10的时钟周期小于网卡11的时钟周期，此时在起始字段U_I中添加一组或多组U_ID0～U_IDN，以实现接口控制器10与网卡11之间的时钟周期同步。
结束字段U_END，用于指示控制字结束位置信息。该结束位置信息例如可以为控制字的长度或者结束位置。该结束位置例如可以为：从结束字段U_END开始起的预设数目个比特位。从而，网卡11从控制字中识别出结束字段U_END后，再向后数预设数目个比特位，可以确定出控制字码流结束。
该可能的实现方式中，控制字之后可以为数据内容；也即是说，控制字的起始字段和 结束字段可以充当数据帧的帧头，当接收端识别出控制字的起始字段和结束字段后，即可判定出数据的起始位置(也即帧定界)，以从比特流中读取出数据。本申请实施例通过将控制字的起始字段和结束字段充当数据帧的帧头，可以不需要额外设置数据帧的帧头，从而可以简化比特流的设计。
载荷字段payload用于承载链路信息。该链路信息可以包括但不限于以下一项或多项：数据中添加控制字的时钟周期、链路中硬件的功耗状态、链路中电路的工作状态和链路中编解码电路的输出增益。举例来说，链路中硬件的功耗状态例如包括低功耗、中等功耗和高功耗三种状态。链路中所包括的诸如扰码器、数据分配器等硬件均处于待机、休眠或下电中的一项时，链路中硬件为低功耗状态；链路中所包括的部件硬件处于待机、休眠或下电中的一项、另外一部分硬件处于工作状态时，链路中的硬件为中等功耗；链路中所有的器件均工作时，链路中的硬件为高功耗。例如，当所传输的数据为训练数据时，可以指示链路中各硬件的功耗为低功耗；当所传输的数据为业务数据时，可以指示链路中各硬件的功耗为中等功耗或高功耗。链路中电路的工作状态例如可以包括上电状态或下电状态。例如，当所传输的数据为训练数据时，可以使得编解码电路的状态为下电状态；当所传输的数据为业务数据时，可以使得编解码电路的状态为上电状态。链路中编解码器的增益例如包括增益1、增益2和增益3。
在一种可选的实现方式中，载荷字段payload可以包括类型(type)字段和细节(detail)字段该两部分。其中，type字段用于指示各种链路信息，detail字段用于指示每一种链路信息对应的具体参数。举例来说，链路信息包括链路中的硬件的功耗状态、链路中电路的工作状态或链路中编解码器的增益该三种信息，type字段用于指示链路信息包括链路中硬件的功耗状态以及链路中编解码器的增益；detai字段进一步指示链路中硬件的功耗状态为中等功耗状态、链路中编解码器的增益为增益2。从而，网卡11可以基于type字段和detail字段确定出各链路信息、以及与各种链路信息对应的参数，以调节链路。
本申请实施例中，接口控制器10与网卡11之间用于传输比特流的有线串行链路中，基于有线串行链路的带宽，可以包括一路通道(lane)，也可以包括多路lane。也即是说，接口控制器10与网卡11之间可以通过一路lane进行比特流的传输，也可以通过多路lane进行比特流的传输。当接口控制器10通过多路lane向网卡11传输比特流时，在一种可选的实现方式中，每一条lane所传输的比特流中除了包括数据之外，还包括控制字。每一个控制字中除了包括如上所述的各字段之外，还可以包括指示链路编号的通道标识字段Lane，如图2所示。网卡11可以基于通道标识字段Lane，实现lane翻转，还可以消除各路lane所传输的数据之间的数据偏斜。进一步的，接口控制器10可以通过固定数目的lane向网卡11传输比特流，还可以通过可变数目的lane向网卡11传输比特流。当接口控制器10通过可变数目的lane向网卡11传输比特流时，在一种可选的实现方式中，载荷字段payload所承载的链路信息中，还可以包括链路带宽(也即传输比特流的lane数目)。网卡11可以基于该链路信息从相应lane接收比特流。
综上可以看出，控制字通过设置起始字段、结束字段、载荷字段以及选择性的设置通道标识字段，使得控制字可以指示出较多的信息，从而降低物理层所传输的控制字的复杂度。
基于如上所述的控制字的帧结构，在一种可能的实现方式中，本申请实施例中，可以 采用纠错编码方式对控制字进行编码。接口控制器10发送能够被纠错的码，网卡11能够自动地发现错误，而且能够自动地纠正码字传输中的错误。纠错编码例如可以包括但不限于：前向纠错编码、汉明码编码、eBCH(extended Bose Ray-Chaudhuri Hocquenghem)编码等。其中，汉明码编码是一种线性码，对于一个长度为m比特的编码块，有n个冗余比特，其余的为载荷比特；每个冗余比特都是部分载荷比特按照一定方式进行异或运算得到的。汉明码编码可以纠正任意单比特错误。eBCH编码同样也是一种线性码，eBCH编码可以纠正编码块中的多个比特错误。下面以eBCH编码为例，通过具体的例子对控制字的编码方法进行详细描述。本申实施例中可以首先构建eBCH编码集合。eBCH编码集合例如可以包括32个编码，每一个编码的结构可以为BCH(16，5，1)，其中16(比特)为编码长度、5(比特)为净荷长度、1(比特)为校验码长度。eBCH编码集合中任意两个编码之间的汉明距离为8。也即是说，任意两个编码之间不同比特的数目为8。eBCH码字集合如图3A所示。
从图3A中可以看出，eBCH包括CW0～CW31该32个编码，每一个编码的长度为16比特。任意两个编码之间不同比特的数目为8。基于图3A所构建的eBCH编码，本申请实施例中所述的控制字的一个具体实例如表一所示。
表一 控制字实例
符号编号 描述
0～(4*N-1)，N的范围为[1～5] 控制字起始字段，CW21,CW28
4*N～(4*N+3) 控制字结束字段，CW22,CW8
(4*N+4)～(4*N+11) 通道标识字段，具体参考图3B
(4*N+12)～(4*N+19) payload_type字段，具体参考表二
(4*N+20)～(4*N+27) payload_detail字段，具体参考表三
从表一所示的控制字实例中可以看出，一个控制字包括0～(4*N+27)该(4*N+27)个字节。控制字起始字段的字节数目可以在4～20内可变。控制字起始字段的编码为CW21,CW28；也即控制字起始字段的低16位为表一所示的编码CW28，高16位为表一所示的编码CW21。控制字结束字段的编码为CW22,CW8；也即控制字结束字段的低16位为表一所示的编码CW22，高16位为表一所示的编码CW8。
通道标识字段如图3B所示。假设接口控制器10与网卡11之间最大的链路带宽为32路lane，也即图3B中所示的lane0～lane31。则每路lane的标识可以由四个编码也即64个比特位表示。以图3B中所示的lane2为例，从图3B中可以看出，lane2由CW3、CW9、CW3和CW9该四个编码指示。其中，CW3和CW9的具体比特位参考表一。从图3B中还可以看出，该64个比特位中，比特位[0～15]为CW3，比特位[16～31]为CW9，比特位[32～47]为CW3，比特位[48～63]为CW9。其余各路lane的详细编码参考图3A和图3B，不再赘述。
需要说明的是，表一、表二、表三以及图3A和图3B所示的表格，可以分别预先存储在接口控制器10和网卡11中。
表二 载荷类型(payload_type)
链路信息 比特位[31-16] 比特位[15-0]
FEC增益 CW8 CW10
链路带宽 CW10 CW22
硬件的功耗 CW8 CW13
控制字添加周期 CW10 CW15
表三 载荷细节(payload_detail)
链路信息 链路细节信息 比特位[31-16] 比特位[15-0]
FEC增益 旁路FEC CW3 CW9
  FEC增益1 CW9 CW10
  FEC增益2 CW9 CW21
  FEC增益3 CW10 CW22
链路带宽 X0(业务数据结束) CW3 CW9
  X1(1条通道) CW8 CW10
  X2(2条通道) CW9 CW21
  X4(4条通道) CW11 CW22
  X8(8条通道) CW21 CW23
  X16(16条通道) CW22 CW28
  X32(32条通道) CW28 CW8
硬件的功耗 Lp0 CW3 CW9
  Lp1 CW8 CW10
  Lp1.1 CW9 CW21
  Lp1.2 CW10 CW22
  Lp2 CW21 CW23
  进入电气空闲 CW22 CW28
控制字添加周期 周期0 CW3 CW9
  周期1 CW8 CW10
  周期2 CW9 CW21
从表二中可以看出，链路信息包括前向纠错编码器(FEC，forward error correction)增益、链路带宽、硬件的功耗、控制字添加周期该四种类型的信息。每一种类型的信息均由两个编码(也即32个比特位)指示。表二中示出了FEC增益的编码为CW8和CW10，也即指示FEC增益的32个比特位中低16位为CW10、高16位为CW8。FEC增益又进一步包括表三中所示的旁路FEC、FEC增益1、FEC增益2和FEC增益3四种模式。假设接口控制器10向网卡11传输的控制字中的type字段包括CW8和CW10，detail字段包括CW9和CW10。网卡11接收到比特流后，解析出控制字的type字段和detail字段。网卡11从表二中查询出CW8和CW10指示FEC增益；然后，网卡11进一步将CW3和CW9与表三中FEC增益对应的各编码比较，查询出FEC增益为FEC增益1。则网卡11可以 将FEC增益调整为增益1。
表二中示出了链路带宽的编码为CW10和CW22，也即指示链路带宽的32个比特位中低16位为CW10、高16位为CW22。链路带宽又进一步包括表三中所示的X0、X1、X2、X4、X8、X16和X32该七中模式。假设接口控制器10向网卡11传输的控制字中的type字段中，前32位为CW8和CW10，后32位为CW10和CW22；detail字段中，前32位为CW9和CW10，后32位为CW9和CW21。网卡11接收到比特流后，解析出控制字的type字段的前32位指示FEC增益，后32位指示链路带宽。然后，网卡11将detail字段中的前32位与表三中FEC增益对应的信息进行比较，将detail字段中的后32位与表三中链路带宽对应的信息进行比较，从而查询出FEC增益为FEC增益1、链路带宽为X1。则网卡11可以将FEC增益调整为增益1，从一条通道获得数据。需要说明的是，接口控制器10的物理层和网卡11的物理层之间还可以预先约定好各链路带宽下所采用的通道。例如，可以预先约定当采用一条通道传输业务数据时、通过通道标识为lane0的通道传输业务数据；还可以预先约定采用四条通道传输业务数据时、通过通道标识为lane0～lane3的通道传输业务数据。还需要说明的是，当控制字的type字段指示出链路带宽信息、且detail字段为编码CW3和CW9时，说明接口控制器10向网卡11传输业务数据结束，下个周期传输的数据为训练数据。也即是说，当控制字中指示链路带宽的信息为X0时，指示业务数据传输结束，下个周期传输的数据为训练数据；当控制字中指示链路带宽的信息为X0之外的任意一个时，说明接口控制器10向网卡11传输的数据为业务数据。由此，用于指示链路带宽的编码还可以用于指示业务数据和训练数据之间的切换。
当接口控制器10向网卡11传输的控制字中包括指示硬件的功耗和控制字的添加周期的信息时，网卡11对控制字的解析以及如何确定出所要调整的链路信息同FEC编码器和链路带宽相类似，不再赘述。
基于图1所示的电子设备100的结构以及图2所示的控制字的帧结构，请继续参考图4，图4是本申请实施例提供的接口控制器10的物理层硬件结构示意图。需要说明的是，网卡11的物理层的硬件结构可以与接口控制器10的物理层硬件结构相同，本申请实施例以接口控制器10的物理层硬件为例进行描述。如图4所示，接口控制器10的物理层包括编码器101、数据分配器102、控制字生成器103、多路选择器104、链路训练状态机105、扰码器106、串行解串行器107、解扰码器108、控制字解码器109、数据偏斜消除器1010以及解码器1011。可以理解的是，接口控制器10的物理层还可以包括更多的电路、模块或部件，本申请实施例不做具体限定。接口控制器10的物理层所包括的这些部件，可以集成与一个或多个芯片中，这些部件可以由硬件电路实现，部分部件也可以由软件驱动硬件实现。一种可能的实现方式中，部分部件的可以集成于同一个处理器中，由该处理器执行各部件或模块对应的功能。例如，编码器101和数据分配器102可以集成于同一个处理器中，由该处理器实现数据的编码与分配的功能。另外，网卡11的物理层可以具有与接口控制器10相同或相似的部件，图4中示出了网卡11的物理层包括编码器111、数据分配器112、控制字生成器113、多路选择器114、链路训练状态机115、扰码器116、串行解串行器117、解扰码器118、控制字解码器119、数据偏斜消除器1110以及解码器1111。下面以接口控制器10的物理层向网卡11的物理层传输比特流为例，对接口控制器10和网卡11的物理层中的各部件或功能进行描述。
在接口控制器10的物理层，编码器101用于对数据链路层发送的数据帧进行编码，生成编码后的数据。该编码例如可以为前向差错编码、检错重发编码或者混合纠错编码等。数据分配器102用于将编码后的数据分成多条数据流(下文中称为业务数据)，分配到多路lane中，一路lane对应一条数据。链路训练状态机105用于生成链路信息，将所生成的链路信息提供至控制字生成器103，控制字生成器103基于链路信息以及如图2所示的控制字的帧结构生成控制字。该链路信息例如可以包括链路功耗状态、链路输出增益和链路编码模式等。此外，链路训练状态机105还用于基于当前的状态(例如业务数据传输状态、链路训练状态或者链路重置状态等)以及时钟周期，控制多路选择器104选择性的将多个输入端中的其中一个输入端与输出端形成通路。图4示出了多路选择器104包括三个输入端，其中一个输入端与数据分配器102耦合、其中一个输入端用于输入训练数据、另外一个输入端与控制字生成器103耦合。也即是说，多路选择器104基于链路训练状态机105的控制，将业务数据、训练数据或者控制字中的一个输出至扰码器106。需要说明的是，本申请实施例中的业务数据，例如可以是用户通过应用程序输入的音频数据和视频数据等数据，经过应用层、传输层、数据链路层以及物理层进行封装和编码后所生成的数据；训练数据用于在链路训练阶段对多路lane进行测试和调整。扰码器106对所接收到的数据流或者控制字增加扰码，提供串行解串行器107。串行解串行器107将所接收到的多路并行低速比特流转换成高速串行的比特流，通过多路lane传输至网卡11。还需要说明的是，lane的数目与所传输的比特流的数目相同，每一条比特流中均包括数据以及控制字。基于链路训练状态机105的控制，控制字可以添加相应数据的任意位置处。优选的，控制字可以在数据之前添加。
在网卡11的物理层，串行解串行器117从lane接收到串行的比特流信号，将串行的比特流转换成多路并行的比特流提供至解扰码器118。解扰码器118对多路并行的比特流解扰码，将解扰码后的比特流输出至控制字解码器119。基于图4所示的控制字的帧结构，控制字解码器119从每一路比特流中识别出控制字，以及对控制字进行解析，得到payload字段中的指示信息，该指示信息用于指示链路信息。例如，指示信息指示链路进入中等功耗状态以及指示链路编码模式为前向差错编码模式。控制字解码器119将所得到的指示信息提供至链路训练状态机115、将数据以及每一条数据对应的通道标识提供至数据偏斜消除器1110。链路训练状态机115基于指示信息，执行相应动作。例如，将链路设置成中等功耗状态、将编码模式(例如上述前向差错编码)提供至解码器1111。数据偏斜消除器1110对各条数据流之间进行消除偏斜的处理，将偏斜消除后的数据流提供至解码器1111。解码器1111基于上述编码模式，采用相应的解码模式对数据流解码，将解码后的数据提供至网卡11的数据链路层。
基于图1所示的电子设备100的架构、图2所示的控制字的帧结构以及图4所示的接口控制器10(或者网卡11)的物理层的硬件架构，本申请实施例还提供一种数据传输方法，该数据传输方法可以应用于图1所示的电子设备100中。下面以接口控制器10为发送端、网卡11为接收端为例，对本申请实施例提供的数据传输方法进行描述。本申请实施例提供的数据传输方法，其发送端和接收端可以由图2所示的一个或多个部件执行。需要说明的是，本申请实施例中，接口控制器10可以在任意数据传输阶段向网卡11传输控制字。例如，在链路训练阶段所传输的训练数据中添加控制字，也可以在业务数据传输阶 段所传输的业务数据中添加控制字，也可以是在链路重置阶段传输的训练数据中添加控制字。还需要说明的是，控制字可以设置于业务数据之前，还可以基于时钟周期设置于业务数据的任意位置处，还可以设置于训练数据之前，还可以设置于训练数据之后，本申请实施例对此不做具体限定。请参考图5，图5是本申请实施例提供的数据传输方法的一个流程500，该数据传输方法包括：
步骤501，接口控制器10生成比特流，该比特流包括数据和控制字，该控制字包括：用于指示控制字起始位置信息的起始字段、用于指示控制字结束位置信息的结束字段以及用于承载指示有线串行链路的链路信息的载荷字段。步骤502，接口控制器10通过有线串行链路发送比特流。
步骤503，网卡11基于起始字段和结束字段，从比特流中读取控制字；步骤504，基于控制字，从比特流中读取所述数据。
该实现方式中，数据例如可以为业务数据或者训练数据中的一种。控制字例如为图2所示的结构。链路信息可以包括但不限于以下一项或多项：数据中添加控制字的时钟周期、链路中硬件的功耗状态、链路中电路的工作状态和链路中编解码电路的输出增益。
该实现方式中，控制字的起始字段和结束字段可以指示出控制字的长度。例如，网卡11读取到起始字段后，识别出比特流中包括控制字；读取到结束字段后，识别出从该字段开始预设数目个比特位为控制字的结束位置。另外，控制字之后可以为数据的数据内容。也即是说，控制字的起始字段和结束字段可以充当数据帧的帧头，当接收端识别出控制字的起始字段和结束字段后，即可判定出数据的起始位置，以从比特流中读取出数据。
本申请实施例提供的控制字，通过设置成包括起始字段、结束字段以及载荷字段的结构，将链路信息承载于载荷字段中，从而可以实现在一个控制字中指示出多种链路信息，简化了物理层的设计。另外，由于控制字的结束字段用于指示控制字的结束位置信息，也即控制字的结束字段可以限定出控制字的长度；进而，通过灵活调整控制字的结束位置信息，即可灵活调整控制字中所承载的链路信息的数目，从而提供了控制字的灵活性。
下面以比特流包括训练数据和控制字、以及比特流包括业务数据和控制字为例，以接口控制器10通过四路lane向网卡11传输数据为例，结合图6，通过更为具体的场景，对本申请实施例提供的数据传输方法进行描述。请继续参考图6，图6是本申请实施例提供的数据传输方法的一个流程600，该数据传输方法包括：
步骤601，接口控制器10在训练数据D0～D3中分别添加控制字C0～控制字C3，生成比特流B0～B3。该步骤位于链路训练阶段。链路训练阶段用于将接口控制器10的链路状态与网卡11之间的链路状态对齐。在该步骤中，接口控制器10可以将预先设置的训练数据D0～D3分配至lane0～lane3。接口控制器10还可以基于当前的链路信息(例如链路进入中等功耗、物理层的各硬件电路均为上电状态、物理层中链路编码器的增益为“1”、链路编码模式为前向差错编码)、在训练数据中添加控制字的时钟周期、以及如图2所示的控制字的帧结构，生成控制字C0～控制字C3。其中，控制字C0的通道标识字段用于指示lane0、控制字C1的通道标识字段用于指示lane1、控制字C2的通道标识字段用于指示lane2、控制字C3的通道标识字段用于指示lane3。除此之外，控制字C0～控制字C3中的起始字段、结束字段以及载荷字段均所承载的数据均可以相同。然后，接口控制器10将控制字C0～控制字C3分别添加至训练数据D0～D3中，生成比特流B0～B3。步骤602，接口控制器10 将比特流B0～B3分别通过lane0～lane3同时传输至网卡11。
步骤603，网卡11基于指示控制字C0～控制字C3起始位置的起始字段、以及指示控制字C0～控制字C3结束位置的结束字段，分别从比特流B0～B3中识别出控制字C0～控制字C3。步骤604，网卡11基于控制字C0～控制字C3中的通道标识字段所承载的通道标识，调整链路对接顺序。该步骤用于实现链路编号与数据流先后顺序的对齐。举例来说，接口控制器10通过lane0-lane1-lane2-lane3分别传输比特流B0-B1-B2-B3；而网卡11从lane0-lane1-lane2-lane3接收到的数据流实际为B3-B2-B1-B0，也即接口控制器10中的lane的编号与网卡11中的lane的编号完全是反相的。网卡11基于各控制字中的通道标识字段，可以对网卡11中的lane的编号重新标注，以实现与接口控制器10中的lane编号之间的对齐。步骤605，网卡11基于控制字C0～控制字C3中的载荷字段所指示的链路信息，调整链路状态。例如，链路信息用于指示链路进入中等功耗、物理层的各硬件电路均为上电状态、物理层中链路编码器的增益为“1”。网卡11基于该链路信息，将链路中诸如放大器、编码器等硬件电路的功耗状态调整为中等功耗状态、将链路编码器的增益调整为“1”等。步骤606，网卡11基于比特流B0～B3所接收的先后顺序，将各路lane所传输的数据对齐。
步骤607，接口控制器10在训练数据D4～D7中分别添加控制字C4～控制字C7，生成比特流B4～B7，其中控制字C4～控制字C7的载荷字段承载指示下一周期传输业务数据的指示信息。该步骤位于链路训练阶段。接口控制器10在步骤601中将链路信息承载于载荷字段提供至网卡11后，还可以将指示下一周期传输业务数据的指示信息承载于控制字C4～控制字C7的载荷字段，控制字C4～控制字C7的载荷字段还可以包括如步骤601中所述的链路信息。除此之外，控制字C4～控制字C7还包括起始字段、结束字段以及通道标识字段。接口控制器10将控制字C4～控制字C7分别添加至训练数据D4～D7中，生成比特流B4～B7。步骤608，接口控制器10将比特流B4～B7分别通过lane0～lane3同时传输至网卡11。
步骤609，接口控制器10在业务数据D8～D111中分别添加控制字C8～控制字C111，生成比特流B8～B111。在该步骤中，接口控制器10可以从数据链路层获得数据帧。基于预先设置的编码格式(例如前向差错编码格式)，接口控制器10对数据帧进行编码，生成业务数据D8～D11。接着，接口控制器10可以将业务数据D8～D11分配至lane0～lane3。然后，接口控制器10基于当前的链路信息、所采用的lane的数目、在训练数据中添加控制字的时钟周期、以及如图2所示的控制字的帧结构，生成控制字C8～控制字C11。其中，所采用的lane的数目承载于控制字C8～控制字C11的载荷字段。最后，接口控制器10将控制字C8～控制字C111分别添加至训练数据D8～D111中，生成比特流B8～B111。一种可选的实现方式中，可以将控制字C8～控制字C111分别添加至业务数据D8～D111的预设位置处。该预设位置例如可以为业务数据之前。步骤610，接口控制器10将比特流B8～B111分别通过lane0～lane3同时传输至网卡11。
步骤611，网卡11基于指示控制字C8～控制字C111起始位置的起始字段、以及指示控制字C8～控制字C111结束位置的结束字段，分别从比特流B8～B111中识别出控制字C8～控制字C111，以及从比特流B8～B111中读取出业务数据D8～D111。该步骤中，网卡11基于控制字在比特流中的位置，可以对业务数据帧定界，也即确定出业务数据的起始位 置。一种可选的实现方式中，业务数据在比特流中的位置位于控制字之后预设位置处。例如，控制字的结束位之后的第二位为业务数据的起始位置位。网卡11读取出控制字的结束字段后，即可确定出控制字的结束位，进而网卡11可以从控制字的结束位之后的第二位开始读取业务数据。步骤612，网卡11基于接口控制器10所采用的编码格式，对所读取的业务数据D8～D111解码，得到解码后的数据帧。
需要说明的是，如上所述的数据传输方法的流程600为示意性的。可以理解的是，本申请实施例提供的数据传输方法可以包括比流程600更多或更少的流程。例如，在步骤604之前、步骤603之后，网卡11还可以向接口控制器10传输指示链路设置完毕的信息。再例如，在步骤604之前、步骤603之后，网卡11还可以向接口控制器10发送比特流，该比特流中包括训练数据以及添加至训练数据中的控制字，该控制字用于指示网卡11的物理层的链路状态。
可以理解的是，接口控制器为了实现上述功能，其包含了执行各个功能相应的硬件和/或软件模块。结合本文中所公开的实施例描述的各示例的步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以结合实施例对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本实施例可以根据上述方法示例对图1所示的接口控制器10中所包括的各部件进行功能模块的划分，例如，可以对应各个功能划分各个不同部件，也可以将两个或两个以上的功能的部件集成在一个处理器模块中。上述集成的处理器模块可以采用硬件的形式实现。需要说明的是，本实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。在采用集成模块的情况下，图7示出了数据传输装置700的一种可能的示意图。如图7所示，该数据传输装置700可以包括：处理单元701和发送单元702，可以对之前提到的装置进行进一步扩展。该处理单元701用于生成比特流，所述比特流包括数据和控制字，所述控制字包括：用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段以及用于承载指示有线串行链路的链路信息的第三字段。该发送单元702用于通过所述有线串行链路发送所述比特流。
在一种可能的实现方式中，所述链路信息包括以下至少一项：传输比特流的通道数目、链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
在一种可能的实现方式中，所述第一字段和所述第二字段，用于指示所述接收端对所述数据帧定界。
在一种可能的实现方式中，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流与所述多条通道一一对应；所述发送单元702具体用于：通过所述多条通道发送对应的所述多条比特流。
在一种可能的实现方式中，所述控制字还包括用于指示通道编号的第四字段。
在一种可能的实现方式中，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；所述多组相同的字段用于补偿所述发送端的时钟周期、与接收端时钟周期之间的差异。
本实施例提供的数据传输装置700，用于接口控制器10所执行的数据传输方法，可以 达到与上述实现方法或装置相同的效果。具体地，以上图7对应的各个模块可以软件、硬件或二者结合实现。例如，每个模块可以以软件形式实现，对应于图1中与该模块对应的处理器102和接口101，用于驱动该相应部件工作。或者，每个模块可包括对应的部件和相应的驱动软件两部分，即以软件或硬件结合实现。因此，数据传输装置700可以认为在逻辑上包含了图1、图4所示的接口控制器10，每个模块中均至少包含了对应功能的驱动软件程序，本实施例对此不做展开。
本实施例可以根据上述方法示例对图1所示的网卡11中所包括的各部件进行功能模块的划分，例如，可以对应各个功能划分各个不同部件，也可以将两个或两个以上的功能的部件集成在一个处理器模块中。上述集成的处理器模块可以采用硬件的形式实现。需要说明的是，本实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。在采用集成模块的情况下，图8示出了数据传输装置800的一种可能的示意图。如图8所示，该数据传输装置800可以包括：接收单元801和处理单元802，可以对之前提到的装置进行进一步扩展。该接收单元801用于接收比特流，所述比特流包括数据以及控制字，所述控制字包括用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段、以及用于承载指示有线串行链路的链路信息的载荷字段。该处理单元802用于基于所述第一字段和所述第二字段，从所述比特流中读取所述控制字；基于所述控制字，从所述比特流中读取所述数据。
在一种可能的实现方式中，所述处理单元802还用于：基于所述链路信息，调整所述有线串行链路的以下至少一项：链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
在一种可能的实现方式中，所述处理单元802具体用于：基于所述第一字段和所述第二字段，确定所述控制字的编码长度；基于所述控制字的编码长度，从所述比特流中识别出所述数据的帧起始位置，其中，所述数据的帧起始位置位于所述控制字之后；基于所述数据的帧起始位置，读取所述数据。
在一种可能的实现方式中，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流通过相对应的所述多条通道从所述发送端接收；所述链路信息还包括传输所述比特流的通道数目；所述控制字还包括用于指示通道编号的通道标识字段；所述处理单元802具体用于：基于传输所述比特流的通道数目以及所述通道标识字段，从相应通道所接收的比特流中读取所述数据。
在一种可能的实现方式中，所述处理单元802还用于：基于所接收到的所述多条比特流的先后顺序、以及所述多条比特流中的多个控制字的每一个控制字中的通道标识字段，消除所述多条通道中每一条通道之间的数据偏斜。
在一种可能的实现方式中，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；以及所述处理单元802还用于：基于与所述发送端之间的时钟频率偏差，执行以下一项操作：删除所述多组相同的字段中的至少一组，或者增加所述多组相同的字段中的至少一组。
本实施例提供的数据传输装置800，用网卡11所执行的数据传输方法，可以达到与上述实现方法或装置相同的效果。具体地，以上图8对应的各个模块可以软件、硬件或二者结合实现。例如，每个模块可以以软件形式实现，对应于图1中与该模块对应的接口111 和处理器112，用于驱动该相应部件工作。或者，每个模块可包括对应的部件和相应的驱动软件两部分，即以软件或硬件结合实现。因此，数据传输装置500可以认为在逻辑上包含了图1、图4所示的网卡11，每个模块中均至少包含了对应功能的驱动软件程序，本实施例对此不做展开。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统和装置，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质或者存储器包括：U盘、移动硬盘、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (27)

  1. 一种有线串行链路的数据传输方法，应用于发送端，其特征在于，包括：
    生成比特流，所述比特流包括数据和控制字，所述控制字包括：用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段以及用于承载指示有线串行链路的链路信息的第三字段；
    通过所述有线串行链路发送所述比特流。
  2. 根据权利要求1所述的数据传输方法，其特征在于，所述链路信息包括以下至少一项：传输比特流的通道数目、链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
  3. 根据权利要求1或2所述的数据传输方法，其特征在于，所述第一字段和所述第二字段，用于指示接收端对所述数据帧定界。
  4. 根据权利要求1-3任一项所述的数据传输方法，其特征在于，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流与所述多条通道一一对应；所述通过所述有线串行链路发送所述比特流，具体包括：
    通过所述多条通道发送对应的所述多条比特流。
  5. 根据权利要求4所述的数据传输方法，其特征在于，所述控制字还包括用于指示通道编号的第四字段。
  6. 根据权利要求1-5任一项所述的数据传输方法，其特征在于，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；
    所述多组相同的字段用于补偿所述发送端的时钟周期、与接收端时钟周期之间的差异。
  7. 根据权利要求1-6任一项所述的数据传输方法，其特征在于，所述数据为业务数据或训练数据；
    当所述数据为训练数据时，所述生成比特流包括：
    在所述数据之后添加所述控制字，以生成所述比特流。
  8. 一种有线串行链路的数据传输方法，应用于接收端，其特征在于，包括：
    接收比特流，所述比特流包括数据以及控制字，所述控制字包括用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段、以及用于承载指示有线串行链路的链路信息的第三字段；
    基于所述第一字段和所述第二字段，从所述比特流中读取所述控制字；
    基于所述控制字，从所述比特流中读取所述数据。
  9. 根据权利要求8所述的数据传输方法，其特征在于，所述方法还包括：
    基于所述链路信息，调整所述有线串行链路的以下至少一项：链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
  10. 根据权利要求8或9所述的数据传输方法，其特征在于，所述基于所述控制字，从所述比特流中读取所述数据，包括：
    基于所述第一字段和所述第二字段，确定所述控制字的编码长度；
    基于所述控制字的编码长度，从所述比特流中识别出所述数据的帧起始位置；
    基于所述数据的帧起始位置，读取所述数据。
  11. 根据权利要求8-10任一项所述的数据传输方法，其特征在于，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流通过相对应的所述多条通道从发送端接收；所述链路信息还包括传输所述多条比特流的通道数目；所述控制字还包括用于指示通道编号的第四字段；
    所述基于所述控制字，从所述比特流中读取所述数据，包括：
    基于传输所述多条比特流的通道数目以及所述第四字段，从相应通道所接收的比特流中读取所述数据。
  12. 根据权利要求11所述的数据传输方法，其特征在于，所述方法还包括：
    基于所接收到的所述多条比特流的先后顺序、以及所述多条比特流中的多个控制字的每一个控制字中的第四字段，消除所述多条通道中每一条通道之间的数据偏斜。
  13. 根据权利要求8-12任一项所述的数据传输方法，其特征在于，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；以及
    所述方法还包括：
    基于与发送端之间的时钟频率偏差，执行以下一项操作：删除所述多组相同的字段中的至少一组，或者增加所述多组相同的字段中的至少一组。
  14. 一种数据传输装置，其特征在于，所述数据传输装置包括处理器和接口；
    所述处理器用于生成比特流，所述比特流包括数据和控制字，所述控制字包括：用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段以及用于承载指示有线串行链路的链路信息的第三字段；
    所述接口，通过所述有线串行链路发送所述比特流。
  15. 根据权利要求14所述的数据传输装置，其特征在于，所述链路信息包括以下至少一项：传输比特流的通道数目、链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
  16. 根据权利要求14或15所述的数据传输装置，其特征在于，所述第一字段和所述第二字段，用于指示接收端对所述数据帧定界。
  17. 根据权利要求14-16任一项所述的数据传输装置，其特征在于，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流与所述多条通道一一对应；所述接口具体用于：
    通过所述多条通道发送对应的所述多条比特流。
  18. 根据权利要求17所述的数据传输装置，其特征在于，所述控制字还包括用于指示通道编号的第四字段。
  19. 根据权利要求14-18任一项所述的数据传输装置，其特征在于，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；
    所述多组相同的字段用于补偿所述发送端的时钟周期、与接收端时钟周期之间的差异。
  20. 一种数据传输装置，其特征在于，所述数据传输装置包括处理器和接口；
    所述接口用于接收比特流，所述比特流包括数据以及控制字，所述控制字包括用于指示所述控制字起始位置信息的第一字段、用于指示所述控制字结束位置信息的第二字段、以及用于承载指示有线串行链路的链路信息的载荷字段；
    所述处理器，用于基于所述第一字段和所述第二字段，从所述比特流中读取所述控制 字；基于所述控制字，从所述比特流中读取所述数据。
  21. 根据权利要求20所述的数据传输装置，其特征在于，所述处理器还用于：
    基于所述链路信息，调整所述有线串行链路的以下至少一项：链路中硬件的功耗状态、链路中电路的工作状态或链路中所使用的编解码器增益。
  22. 根据权利要求20或21所述的数据传输装置，其特征在于，所述处理器具体用于：
    基于所述第一字段和所述第二字段，确定所述控制字的编码长度；
    基于所述控制字的编码长度，从所述比特流中识别出所述数据的帧起始位置；
    基于所述数据的帧起始位置，读取所述数据。
  23. 根据权利要求20-22任一项所述的数据传输装置，其特征在于，所述比特流包括多条，所述有线串行链路包括多条通道，所述多条比特流通过相对应的所述多条通道从所述发送端接收；所述链路信息还包括传输所述多条比特流的通道数目；所述控制字还包括用于指示通道编号的第四字段；所述处理器具体用于：
    基于传输所述多条比特流的通道数目以及所述第四字段，从相应通道所接收的比特流中读取所述数据。
  24. 根据权利要求23所述的数据传输装置，其特征在于，所述处理器还用于：
    基于所接收到的所述多条比特流的先后顺序、以及所述多条比特流中的多个控制字的每一个控制字中的第四字段，消除所述多条通道中每一条通道之间的数据偏斜。
  25. 根据权利要求20-24任一项所述的数据传输装置，其特征在于，所述第一字段包括多组相同的字段，每一组字段包括多个比特位；以及所述处理器还用于：
    基于与发送端之间的时钟频率偏差，执行以下一项操作：删除所述多组相同的字段中的至少一组，或者增加所述多组相同的字段中的至少一组。
  26. 一种计算机可读存储介质，其特征在于，用于存储计算机程序，所述计算机程序被处理器运行时，实现如上述权利要求1-7中任一项所述的方法或如上述权利要求8-13中任一项所述的方法。
  27. 一种计算机程序产品，其特征在于，当所述计算机程序产品在处理器上运行时，实现如上述权利要求1-7中任一项所述的方法或如上述权利要求8-13中任一项所述的方法。
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US7072406B1 (en) * 1999-09-06 2006-07-04 Nokia Mobile Phones Ltd. Serial interface and method for transferring digital data over a serial interface
US20160261375A1 (en) * 2015-03-04 2016-09-08 Qualcomm Incorporated Packet format and coding method for serial data transmission
WO2016144953A1 (en) * 2015-03-10 2016-09-15 Intel Corporation Monitoring errors during idle time in ethernet pcs
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Publication number Priority date Publication date Assignee Title
US7072406B1 (en) * 1999-09-06 2006-07-04 Nokia Mobile Phones Ltd. Serial interface and method for transferring digital data over a serial interface
US20160261375A1 (en) * 2015-03-04 2016-09-08 Qualcomm Incorporated Packet format and coding method for serial data transmission
WO2016144953A1 (en) * 2015-03-10 2016-09-15 Intel Corporation Monitoring errors during idle time in ethernet pcs
CN109391298A (zh) * 2017-08-03 2019-02-26 上海朗帛通信技术有限公司 一种用于无线通信的用户设备、基站中的方法和装置

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