WO2023137582A1

WO2023137582A1 - Ferroelectric memory and vertical transistor

Info

Publication number: WO2023137582A1
Application number: PCT/CN2022/072483
Authority: WO
Inventors: 林琪; 范人士; 刘晓真; 赵思宇; 丁士成; 方亦陈; 卜思童
Original assignee: 华为技术有限公司
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2023-07-27
Also published as: CN116803232A

Abstract

The present application provides a ferroelectric memory, comprising: a substrate; word lines, a source line, a bit line and a control line; and a first ferroelectric capacitor, a first transistor and a second transistor which are stacked in the vertical direction; the first ferroelectric capacitor comprises a first electrode and a second electrode; the second electrode is exposed at the lower end and/or the upper end of the first ferroelectric capacitor; the first transistor has a first electrode connected to the source line, a second electrode connected to the bit line, and a gate in contact with the second electrode of the first ferroelectric capacitor; a channel layer of the first transistor is arranged in the vertical direction, and the gate of the first transistor forms the upper end and/or the lower end of the first transistor; the second transistor has a gate connected to the control line, a second electrode connected to the bit line, and a first electrode in contact with the second electrode of the first ferroelectric capacitor or the gate of the first transistor; a channel layer of the second transistor is arranged in the vertical direction, and the first electrode of the second transistor forms the upper end or the lower end of the second transistor. The ferroelectric memory has high storage density.

Description

Ferroelectric memory and vertical structure transistor

technical field

The present application relates to the technical field of semiconductors, in particular to a ferroelectric memory and a vertical structure transistor.

Background technique

With the development of information technology, there is a demand for low-latency and large-capacity storage. Among them, low latency helps to improve data processing speed. Large capacity helps to increase storage density and save memory manufacturing costs.

Currently, mainstream memories include static random-access memory (SRAM), dynamic random-access memory (DRAM), flash memory (flash), and hard disk (hard disk). These memories either have small capacity or high latency, and it is difficult to meet the requirements of low latency and large capacity at the same time.

Ferroelectric memory is a new type of memory, which has the characteristics of fast read and write speed and non-volatility. A memory cell in a conventional ferroelectric memory adopts the structure shown in FIG. 1A and FIG. 1B , or adopts the structure shown in FIG. 2 . Wherein, the ferroelectric capacitor is integrated at the source of the transistor (as shown in FIG. 1A and FIG. 1B ) or integrated at the gate of the transistor (as shown in FIG. 2 ). In these two structures, the transistor is a traditional planar transistor, and its source, drain, and gate are arranged horizontally, all of which occupy the integrated area of the substrate surface, resulting in a large substrate area occupied by a single ferroelectric memory cell. As shown in FIG. 3 , the integrated area of a single ferroelectric memory cell using the structure shown in FIG. 1B or the structure shown in FIG. 2 is at least 8F ² , where F is the minimum feature size. In this way, fewer storage units can be integrated on the substrate, and the storage density of the ferroelectric memory is lower.

In addition, if the ferroelectric memory cells shown in FIG. 1B or FIG. 2 are stacked in a direction perpendicular to the substrate. Then each layer needs a large number of photomasks, which will lead to a sharp increase in the cost of the ferroelectric memory.

Contents of the invention

The embodiment of the present application provides a ferroelectric memory and a vertical structure transistor, specifically higher storage density.

A first aspect provides a ferroelectric memory, comprising: a substrate; a word line WL, a source line SL, a bit line and a control line CL; a first ferroelectric capacitor, a first transistor, and a second transistor stacked vertically; wherein the first ferroelectric capacitor includes a first electrode and a second electrode; wherein the first electrode is connected to the word line WL, and the second electrode is exposed at the lower end and/or upper end of the first ferroelectric capacitor; The layers are arranged in the vertical direction, and the gate of the first transistor forms the upper end and/or lower end of the first transistor; the gate of the second transistor is connected to the control line CL, the second pole is connected to the bit line, and the first pole is in contact with the second electrode or the gate of the first transistor; wherein, the channel layer of the second transistor is arranged in the vertical direction, and the first pole of the second transistor forms the upper or lower end of the second transistor; wherein, the vertical direction is perpendicular to the surface of the substrate, and the upper end is an end away from the substrate, and the lower end is an end close to the substrate;

Wherein, the first pole of the transistor may be the source of the transistor, and the second pole of the transistor may be the drain of the transistor. Alternatively, the first pole of the transistor can be the drain of the transistor, and the second pole of the transistor can be the source of the transistor. The transistors here include a first transistor and a second transistor.

In the ferroelectric memory provided in this application, the second electrode of the ferroelectric capacitor needs to be connected to the gate of the first transistor, and also needs to be connected to the first electrode of the second transistor. The second electrode is exposed at the upper end and/or lower end of the ferroelectric capacitor, the channel layers of the first transistor and the second transistor are vertically arranged (that is, both the first transistor and the second transistor adopt a vertical structure), the gate of the first transistor is set to form the upper end and/or lower end of the first transistor, and the first pole of the second transistor forms the upper end or lower end of the second transistor, while ensuring that the second electrode of the ferroelectric capacitor is connected to the gate of the first transistor and also connected to the first pole of the second transistor, the vertical stacking of the ferroelectric capacitor, the first transistor, and the second transistor can be realized.

Specifically, when the second electrode is exposed at the lower end of the ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first pole of the second transistor forms the upper end of the second transistor, the ferroelectric capacitor can be positioned above the first transistor to realize the contact between the second electrode and the upper end (ie, the gate) of the first transistor (that is, the second electrode and the gate of the first transistor are connected by mutual contact), and the second transistor is located below the first transistor, so that the upper end (ie, the first pole) of the second transistor can contact the lower end (ie, the gate) of the first transistor, so that the first pole of the second transistor can pass through the first transistor. The gate of the transistor is connected to the second electrode.

When the second electrode is exposed at the upper end and the lower end of the ferroelectric capacitor, the gate of the first transistor forms the lower end of the first transistor, and the first pole of the second transistor forms the upper end of the second transistor, the first transistor is positioned above the ferroelectric capacitor to realize the contact between the lower end (i.e. the gate) of the first transistor and the second electrode exposed at the upper end of the ferroelectric capacitor (i.e. the second electrode and the gate of the first transistor are connected by mutual contact), and the second transistor is located below the ferroelectric capacitor to realize the contact between the upper end (i.e. the first pole) of the second transistor and the second electrode exposed at the lower end of the ferroelectric capacitor ( That is, the second electrode and the first electrode of the second transistor are connected by contacting each other).

When the second electrode is exposed on the upper end of the ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first pole of the second transistor forms the lower end of the second transistor, the first transistor is positioned above the ferroelectric capacitor to realize the contact between the lower end (ie, gate) of the first transistor and the second electrode exposed at the upper end of the ferroelectric capacitor (ie, the second electrode and the gate of the first transistor are connected by mutual contact), and the second transistor is located above the first transistor, so that the lower end of the second transistor (ie, the first pole) can contact the upper end (ie, the gate) of the first transistor, so that the second transistor is connected. The first electrode may be connected to the second electrode through the gate of the first transistor.

Thus, the stacking of the ferroelectric capacitor, the first transistor, and the second transistor in the vertical direction can be realized, and the first transistor and the second transistor themselves have a vertical structure, and the parts of the transistor can be stacked in the vertical direction, thereby reducing the substrate integration area occupied by the parts of the transistor, so that more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is improved.

In addition, both the first transistor and the second transistor are manufactured by the back-end process, and have low dependence on the substrate, which can reduce the requirement of the ferroelectric memory on the substrate.

In a possible implementation manner, the second electrode is exposed at the lower end of the first ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor; wherein, the first ferroelectric capacitor is located above the first transistor, the second transistor is located below the first transistor, the upper side is away from the substrate, and the lower side is close to the substrate.

In this embodiment, the second electrode is exposed at the lower end of the ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor. Thus, the ferroelectric capacitor can be arranged above the first transistor so that the second electrode contacts the gate of the first transistor to realize the connection between the second electrode and the first transistor; the second transistor can be arranged below the first transistor so that the first pole of the second transistor contacts the gate of the first transistor, and then the first pole of the second transistor can be connected to the second electrode through the gate of the first transistor. Thus, the stacking of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction is realized.

Moreover, in this embodiment, the ferroelectric capacitor is located above the second transistor and the first transistor, so that the ferroelectric capacitor can be fabricated after the second transistor and the first transistor are fabricated, thereby avoiding the degradation of ferroelectric properties caused by the high temperature stage in the transistor fabrication process.

Further, in this embodiment, the first transistor and the second transistor are closer to the substrate, so that the leads of the bit line, the lead of the control line, and the lead of the source line can be directly pulled down to connect with the corresponding drive circuit on the substrate, and all can be set as shorter lines, shortening the path, and reducing the read and write operation delay of the ferroelectric capacitor.

In a possible implementation manner, the first transistor includes: a first channel layer arranged in a vertical direction; a first gate oxide layer surrounded by the first channel layer; a first gate penetrating through the first gate oxide layer and protruding from an upper end and a lower end of the first gate oxide layer; a first electrode and a second electrode surrounding the first channel layer, wherein there is a gap between the first electrode and the second electrode.

This embodiment provides a first transistor. The channel layer of the first transistor is arranged in the vertical direction, so that the two-dimensional electron gas that conducts the source and drain can move in the vertical direction, which can reduce the dependence of the first transistor on the substrate, thereby reducing the requirement of the ferroelectric memory on the substrate.

In addition, the gate of the first transistor can pass through the gate oxide layer and protrude from the upper and lower ends of the gate oxide layer to form the upper and lower ends of the first transistor, so that the gate of the first transistor can be in contact with the second electrode of the ferroelectric capacitor, and the bottom can be in contact with the first electrode of the second transistor, so that the vertical stacking of the first transistor, the ferroelectric capacitor, and the second transistor can be realized, so that more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory can be improved.

In a possible implementation manner, the second transistor includes: a second channel layer arranged in a vertical direction; a second gate oxide layer surrounded by the second channel layer; a second gate, a part of the second gate is surrounded by the second gate oxide layer, and another part protrudes from the lower end of the second gate oxide layer; a first electrode located at the upper end of the second channel layer, and the first electrode is insulated from the second gate;

This embodiment provides a second transistor, the channel layer of the second transistor is arranged along the vertical direction, so that the two-dimensional electron gas that conducts the source and the drain can move in the vertical direction, which can reduce the dependence of the second transistor on the substrate, thereby reducing the requirement of the ferroelectric memory on the substrate.

Moreover, the first pole of the second transistor is located at the upper end of the channel layer, and can be in contact with the gate of the first transistor above the second transistor, and then can be connected to the second electrode through the gate of the first transistor, so as to realize the stacking of the second transistor, the ferroelectric capacitor and the first transistor in the vertical direction, so that more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory can be improved.

In a possible implementation manner, the second transistor includes: a third channel layer arranged vertically; a first electrode located at the upper end of the third channel layer; a second electrode located at the lower end of the third channel layer; a third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer, there is a gap between the third gate and the first electrode, and there is a gap between the third gate and the second electrode.

In a possible implementation manner, the second electrode is exposed at the upper end and the lower end of the first ferroelectric capacitor, the gate of the first transistor forms the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor; wherein, the first transistor is located above the first ferroelectric capacitor, and the second transistor is located below the first ferroelectric capacitor, the upper side is away from the substrate, and the lower side is close to the substrate.

In this embodiment, the second electrode is exposed at the upper end and the lower end of the ferroelectric capacitor, the gate of the first transistor forms the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor. Thus, the first transistor can be arranged above the ferroelectric capacitor, so that the gate of the first transistor can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the gate of the first transistor and the second electrode; the second transistor can be arranged below the ferroelectric capacitor, so that the first pole of the second transistor can be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor to realize the connection between the first electrode of the second transistor and the second electrode. Thus, the stacking of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction is realized.

Moreover, the first transistor is arranged above the ferroelectric capacitor, and the first transistor can be prepared after the ferroelectric capacitor is prepared, so that the first transistor does not need to withstand the high temperature stage of the ferroelectric capacitor manufacturing process, and avoids performance degradation of the first transistor caused by high temperature.

Further, in this embodiment, the second transistor is closer to the substrate, so that the leads of the bit line and the control line can be directly pulled down and connected to the corresponding drive circuit on the substrate, and can be set as shorter lines, which shortens the path and reduces the read and write operation delay of the ferroelectric capacitor.

In a possible implementation manner, both the first transistor and the second transistor adopt the first structure; the first structure includes: a second channel layer arranged in a vertical direction; a second gate oxide layer surrounded by the second channel layer; a second gate, a part of the second gate is surrounded by the second gate oxide layer, and another part protrudes from the lower end of the second gate oxide layer; a first electrode located at the upper end of the second channel layer, and the first electrode is insulated from the second gate;

In this implementation manner, the first transistor and the second transistor can adopt the same structure, which can reduce the difficulty of the ferroelectric memory manufacturing process as a whole.

Moreover, in this embodiment, the channel layers of the first transistor and the second transistor are arranged along the vertical direction, so that the two-dimensional electron gas that turns on the source and the drain can move in the vertical direction, which can reduce the dependence of the first transistor and the second transistor on the substrate, thereby reducing the requirement of the ferroelectric memory on the substrate.

Further, the gate of the first transistor forms the lower end of the first transistor, so that the gate of the first transistor can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the gate of the first transistor and the second electrode. The first pole of the second transistor forms the upper end of the second transistor, so that the first pole of the second transistor can be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor to realize the connection between the first pole and the second electrode of the second transistor. Therefore, the stacking of the first transistor, the ferroelectric capacitor and the second transistor in the vertical direction is realized, so that more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is increased.

In a possible implementation manner, the first transistor includes: a second channel layer arranged vertically; a second gate oxide layer surrounded by the second channel layer; a second gate, a part of the second gate is surrounded by the second gate oxide layer, and another part protrudes from the lower end of the second gate oxide layer; a first electrode located at the upper end of the second channel layer, and the first electrode is insulated from the second gate; a second electrode surrounding the second channel layer with a gap between the first electrode; ; the second pole located at the lower end of the third channel layer; the third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer, there is a space between the third gate and the first pole, and there is a space between the third gate and the second pole.

In this embodiment, the channel layers of the first transistor and the second transistor are arranged along the vertical direction, so that the two-dimensional electron gas that conducts the source and drain can move in the vertical direction, which can reduce the dependence of the first transistor and the second transistor on the substrate, thereby reducing the requirement of the ferroelectric memory on the substrate.

In addition, the gate of the first transistor forms the lower end of the first transistor, so that the gate of the first transistor can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the gate of the first transistor and the second electrode. The first pole of the second transistor forms the upper end of the second transistor, so that the first pole of the second transistor can be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor to realize the connection between the first pole and the second electrode of the second transistor. Therefore, the stacking of the first transistor, the ferroelectric capacitor and the second transistor in the vertical direction is realized, so that more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is increased.

In a possible implementation manner, the second electrode is exposed at the upper end of the first ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first electrode of the second transistor forms the lower end of the second transistor; wherein, the first transistor is located above the first ferroelectric capacitor, the second transistor is located above the first transistor, and the upper end is a side away from the substrate.

In this embodiment, the second electrode is exposed at the upper end of the ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first electrode of the second transistor forms the lower end of the second transistor. Thus, the first transistor can be arranged above the ferroelectric capacitor, so that the gate of the first transistor can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the first transistor gate and the second electrode; the second transistor can be arranged above the first transistor, so that the first pole of the second transistor can be in contact with the gate of the first transistor, so that the first pole of the second transistor is connected to the second electrode through the gate of the first transistor. Thus, the stacking of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction is realized.

Moreover, in this embodiment, the second electrode is only exposed at the upper end of the ferroelectric capacitor, and does not need to be exposed at the lower end of the ferroelectric capacitor, so that when preparing the ferroelectric capacitor, the lower end of the second electrode can be opened, avoiding the etching process of the lower end opening, damage to the sidewall ferroelectric layer, and further avoiding the deterioration of the ferroelectric performance caused by the damage.

In a possible implementation manner, the first transistor includes: a first channel layer arranged vertically; a first gate oxide layer surrounded by the first channel layer; a first gate penetrating through the first gate oxide layer and protruding from the upper end and lower end of the first gate oxide layer; a first electrode and a second electrode surrounding the first channel layer, and there is a gap between the first electrode and the second electrode; the second transistor includes: a third channel layer arranged vertically; The third gate, wherein there is a third gate oxide layer between the third gate and the third channel layer, there is an interval between the third gate and the first electrode, and there is an interval between the third gate and the second electrode.

And, the gate of the first transistor forms the lower end of the first transistor, so that the gate of the first transistor can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the gate of the first transistor and the second electrode; the first pole of the second transistor forms the lower end of the second transistor, and the gate of the first transistor also forms the upper end of the first transistor, so that the gate of the first transistor can be in contact with the first pole of the second transistor, so that the first pole of the second transistor can be connected to the second electrode through the gate of the first transistor. Therefore, the stacking of the first transistor, the ferroelectric capacitor and the second transistor in the vertical direction is realized, so that more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is increased.

In a possible implementation manner, the ferroelectric memory includes a plurality of word lines; the first ferroelectric capacitor includes a plurality of ferroelectric capacitors stacked in a vertical direction, wherein the first electrodes of different ferroelectric capacitors in the plurality of ferroelectric capacitors are connected to different word lines in the plurality of word lines, and the plurality of ferroelectric capacitors share the second electrode.

In this embodiment, multiple ferroelectric capacitors can be stacked in the vertical direction, so that multiple ferroelectric capacitors can be arranged on the same substrate integration area, further reducing the integration area occupied by a single ferroelectric capacitor, thereby further improving the storage density of the ferroelectric memory.

Moreover, in this embodiment, multiple ferroelectric capacitors share the second electrode, and the second electrode is exposed from the upper end and/or lower end of the ferroelectric capacitors, so that multiple ferroelectric capacitors can be vertically stacked with the first transistor and the second transistor. For specific stacking methods, refer to the introduction above, and will not repeat them here.

In addition, the first electrodes of different ferroelectric capacitors are connected to different word lines, so that different ferroelectric capacitors can be distinguished and operated through the word lines, so that each ferroelectric capacitor can be operated independently to store corresponding data.

In a possible implementation manner, the multiple ferroelectric capacitors include: a cylindrical electrode extending in a vertical direction, and the cylindrical electrode is used as a second electrode; a ferroelectric layer surrounding the cylindrical electrode; a plurality of electrode layers surrounding the ferroelectric layer, wherein two adjacent electrode layers are separated by an insulating material, and different electrode layers in the multiple electrode layers are used as first electrodes of different ferroelectric capacitors in the multiple ferroelectric capacitors. In this embodiment, the columnar electrodes extending in the vertical direction can be used as the second electrodes of multiple ferroelectric capacitors, so that the second electrodes can be exposed at the upper end and/or lower end of the ferroelectric capacitors, so that multiple ferroelectric capacitors can be vertically stacked with the first transistor and the second transistor.

Moreover, in this embodiment, the word lines connected to the first electrode of the ferroelectric capacitor can be drawn out from around the ferroelectric capacitor and connected to corresponding driving circuits respectively, which improves the driving capability of the first electrode and reduces the driving time delay.

In a second aspect, a transistor is provided, including: a channel layer arranged in a vertical direction; a gate oxide layer surrounded by the channel layer; a gate, a part of the gate is surrounded by the gate oxide layer, and another part protrudes from the lower end of the gate oxide layer; a first electrode located at the upper end of the channel layer, and the first electrode is insulated from the gate; a second electrode surrounds the channel layer and is spaced from the first electrode; Wherein, the first pole can be used as the source of the transistor, and the second pole can be used as the drain of the transistor; or, the first pole can be used as the drain of the transistor, and the second pole can be used as the source of the transistor.

The transistor provided by the second aspect can be applied to a memory, and can be used as a control element in the memory. For example, it can be applied to ferroelectric memory, DRAM memory, phase change memory, resistive change memory, and magnetic memory. Since the transistor has a vertical structure and occupies less substrate for integration, the storage density of the memory can be increased by using the transistor as a control element of the memory.

In addition, the channel layer of the transistor provided by the second aspect is arranged along the vertical direction, so that the two-dimensional electron gas that conducts the source and the drain can move in the vertical direction, which can reduce the dependence of the transistor on the substrate, thereby reducing the requirements of the memory on the substrate.

Taking the application in ferroelectric memory as an example, the first pole of the transistor forms the upper end of the transistor, and the gate forms the lower end of the transistor, so that the transistor and the ferroelectric capacitor can be stacked in the vertical direction, reducing the substrate integration area occupied by the transistor and the ferroelectric capacitor as a whole, and improving the storage density of the memory. details as follows.

The transistor provided in the second aspect is used as the second transistor, which can be combined with the gate to form the first transistor at the upper end and the lower end, and a ferroelectric capacitor with the second electrode exposed at the lower end to form a vertical stack with the ferroelectric capacitor on the top, the first transistor in the middle, and the second transistor on the bottom. Specifically, the first pole of the second transistor forms the upper end of the second transistor, so that the first pole of the second transistor is upward and can be in contact with the gate forming the lower end of the first transistor, and the gate forming the upper end of the first transistor is upward and can be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, thereby realizing the connection between the gate of the first transistor and the second electrode, and also making the first pole of the second transistor connected to the second electrode through the gate of the first transistor. Thus, the stacking of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction is realized.

One of the transistors provided in the two second aspects is used as the first transistor, and the other second transistor can be combined with the ferroelectric capacitor whose second electrode is exposed at the upper end and the lower end to form a vertical stack with the first transistor on top, the ferroelectric capacitor in the middle, and the second transistor on the bottom. Specifically, the first pole of the second transistor forms the upper end of the second transistor, so that the first pole of the second transistor is upward and can contact the second electrode exposed at the lower end of the ferroelectric capacitor to realize the connection between the first pole of the second transistor and the second electrode; the gate of the first transistor forms the lower end of the first transistor, so that the gate of the first transistor is downward and can contact the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the gate of the first transistor and the second electrode. Thus, the stacking of the first transistor, the ferroelectric capacitor and the second transistor in the vertical direction is realized.

The transistor provided in the second aspect is used as the first transistor, which can be combined with the ferroelectric capacitor whose second electrode is exposed at the upper end and the lower end, and the second transistor whose first electrode forms the upper end, to form a vertical stack with the first transistor on top, the ferroelectric capacitor in the middle, and the second transistor on the bottom. Specifically, the gate of the first transistor forms the lower end of the first transistor, so that the gate of the first transistor is downward and can contact the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the gate of the first transistor and the second electrode; the selected first electrode of the second transistor forms the upper end of the second transistor, so that the first electrode of the second transistor is upward and can contact the second electrode exposed at the lower end of the ferroelectric capacitor to realize the connection between the first electrode of the second transistor and the second electrode. Thus, the stacking of the first transistor, the ferroelectric capacitor and the second transistor in the vertical direction is realized.

In a possible implementation manner, the channel layer is made of N-type lightly doped semiconductor material, and the first electrode includes a metal electrode and N-type heavily doped region, wherein the N-type heavily doped region is made of N-type heavily doped semiconductor material, and the N-type heavily doped region is in contact with the channel layer.

In this implementation, the channel layer is made of N-type lightly doped semiconductor material, and the metal electrode can be connected to the channel layer through the N-type heavily doped region, thereby reducing the ohmic contact resistance between the metal electrode and the channel layer and improving the electrical performance of the transistor.

In a third aspect, a transistor is provided, comprising: a channel layer arranged in a vertical direction; a gate oxide layer surrounded by the channel layer; a gate penetrating through the gate oxide layer and protruding from the upper end and the lower end of the gate oxide layer; a first pole and a second pole surrounding the channel layer, and there is a gap between the first pole and the second pole; wherein, the vertical direction is perpendicular to the surface of the transistor substrate, the upper end is an end away from the substrate, and the lower end is an end close to the substrate. Wherein, the first pole can be used as the source of the transistor, and the second pole can be used as the drain of the transistor; or, the first pole can be used as the drain of the transistor, and the second pole can be used as the source of the transistor.

The transistor provided by the third aspect can be applied to a memory, and can be used as a control element in the memory. For example, it can be applied to ferroelectric memory, DRAM memory, phase change memory, resistive change memory, and magnetic memory. Since the transistor has a vertical structure and occupies less substrate for integration, the storage density of the memory can be increased by using the transistor as a control element of the memory.

In addition, the channel layer of the transistor provided in the third aspect is arranged in the vertical direction, so that the two-dimensional electron gas that conducts the first electrode and the second electrode can move in the vertical direction, which can reduce the dependence of the transistor on the substrate, thereby reducing the requirements of the memory on the substrate.

Taking the application in ferroelectric memory as an example, the gate of the transistor forms the upper end and lower end of the transistor, which can make the transistor and ferroelectric capacitor stack in the vertical direction, reduce the overall substrate integration area occupied by the transistor and ferroelectric capacitor, and increase the storage density of the memory. details as follows.

The transistor provided in the third aspect as the first transistor can be combined with a ferroelectric capacitor whose second electrode is exposed at the lower end and a second transistor whose first electrode forms the upper end to form a vertical stack with the ferroelectric capacitor on top, the first transistor in the middle, and the second transistor on the bottom. Specifically, the gate forming the upper end of the first transistor is upward, and can be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, thereby realizing the connection between the gate of the first transistor and the second electrode; the gate forming the lower end of the first transistor is downward, and can be in contact with the first electrode forming the upper end of the second transistor, so that the first electrode of the second transistor is connected to the second electrode through the gate of the first transistor. Thus, the stacking of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction is realized.

The transistor provided in the third aspect is used as the first transistor, which can be combined with a ferroelectric capacitor whose second electrode is exposed at the upper end, and a second transistor whose first electrode forms the lower end to form a vertical stack with the second transistor on top, the first transistor in the middle, and the ferroelectric capacitor on the bottom. Specifically, the gate forming the lower end of the first transistor is downward, and can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor, thereby realizing the connection between the gate of the first transistor and the second electrode; the gate forming the upper end of the first transistor can be downward, and can be in contact with the first electrode forming the lower end of the second transistor, so that the first electrode of the second transistor is connected to the second electrode through the gate of the first transistor. Thus, the stacking of the second transistor, the first transistor and the ferroelectric capacitor in the vertical direction is realized.

In a fourth aspect, a transistor is provided, comprising: a channel layer arranged along a vertical direction; wherein, the inside of the channel layer is filled with an insulator, and the vertical direction is perpendicular to the surface of the substrate where the transistor is located; a third electrode located at the upper end of the channel layer; a fourth electrode located at the lower end of the channel layer; Wherein, the third pole is used as the first pole of the transistor, and the fourth pole is used as the second pole of the transistor; or, the third pole is used as the second pole of the transistor, and the fourth pole is used as the first pole of the transistor; wherein, the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is an end far away from the substrate, and the lower end is an end close to the substrate.

The channel layer of the transistor provided in the fourth aspect is filled with an insulator, and this structure can improve the reliability of the fabrication process of the transistor, so that the same batch of transistors produced have good consistency.

The transistor provided in the fourth aspect can be applied to a memory, and can be used as a control element in the memory. For example, it can be applied to ferroelectric memory, DRAM memory, phase change memory, resistive change memory, and magnetic memory. Since the transistor has a vertical structure and occupies less substrate for integration, the storage density of the memory can be increased by using the transistor as a control element of the memory.

In addition, the channel layer of the transistor provided in the fourth aspect is arranged in the vertical direction, so that the two-dimensional electron gas that conducts the source and the drain can move in the vertical direction, which can reduce the dependence of the transistor on the substrate, thereby reducing the requirements of the memory on the substrate.

Taking the application in ferroelectric memory as an example, the first pole of the transistor forms the upper end of the transistor, and the second pole forms the lower end of the transistor; or, the first pole of the transistor forms the lower end of the transistor, and the second pole forms the upper end of the transistor. Thus, the transistors and the ferroelectric capacitors can be stacked in the vertical direction, reducing the overall substrate integration area occupied by the transistors and the ferroelectric capacitors, and increasing the storage density of the memory. details as follows.

When the first pole of the transistor provided in the fourth aspect forms the upper end of the transistor, the transistor provided in the fourth aspect can be used as a second transistor, and the gate forms the first transistor at the upper end and the lower end, and the ferroelectric capacitor with the second electrode exposed at the lower end, forming a vertical stack with the ferroelectric capacitor on the top, the first transistor in the middle, and the second transistor on the bottom. Specifically, the first pole of the second transistor forms the upper end of the second transistor, so that the first pole of the second transistor is upward and can be in contact with the gate forming the lower end of the first transistor; and the gate forming the upper end of the first transistor is upward and can be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, thereby realizing the connection between the gate of the first transistor and the second electrode, and also making the first pole of the second transistor connected to the second electrode through the gate of the first transistor. Thus, the stacking of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction is realized.

When the first pole of the transistor provided in the fourth aspect forms the upper end of the transistor, the fourth aspect provides that it can be used as the second transistor, and the gate forms the first transistor at the lower end, and the ferroelectric capacitor with the second electrode exposed at the upper end and the lower end, forming a vertical stack in which the first transistor is on the top, the ferroelectric capacitor is in the middle, and the second transistor is on the bottom. Specifically, the first pole of the second transistor forms the upper end of the second transistor, so that the first pole of the second transistor is upward and can contact the second electrode exposed at the lower end of the ferroelectric capacitor to realize the connection between the first pole of the second transistor and the second electrode; the gate of the selected first transistor forms the lower end of the first transistor, so that the gate of the first transistor is downward and can contact the second electrode exposed at the upper end of the ferroelectric capacitor to realize the connection between the gate of the first transistor and the second electrode. Thus, the stacking of the first transistor, the ferroelectric capacitor and the second transistor in the vertical direction is realized.

When the first pole of the transistor provided in the fourth aspect forms the lower end of the transistor, the transistor provided in the fourth aspect can be used as a second transistor, and the gate can be combined to form the first transistor at the upper end and the lower end, and the ferroelectric capacitor with the second electrode exposed at the upper end, forming a vertical stack with the second transistor on top, the first transistor in the middle, and the ferroelectric capacitor on the bottom. Specifically, the gate forming the lower end of the first transistor is downward, and can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor, thereby realizing the connection between the gate of the first transistor and the second electrode; the gate forming the upper end of the first transistor can be downward, and can be in contact with the first electrode forming the lower end of the second transistor, so that the first electrode of the second transistor is connected to the second electrode through the gate of the first transistor. Thus, the stacking of the second transistor, the first transistor and the ferroelectric capacitor in the vertical direction is realized.

In a possible implementation manner, the channel layer is made of N-type lightly doped semiconductor material, and the third pole and/or the fourth pole includes a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of N-type heavily doped semiconductor material, and the N-type heavily doped region is in contact with the channel layer.

In the ferroelectric memory provided by the present application, the first transistor and the second transistor have a vertical structure, and the electrodes are distributed along the direction perpendicular to the substrate, and the structure of the first transistor, the second transistor, and the ferroelectric capacitor can make these three stacked in the direction perpendicular to the substrate, reducing the integrated area occupied by the memory module, so that more memory modules can be integrated on the substrate, thereby increasing the storage density of the ferroelectric memory.

Description of drawings

1A is a schematic structural diagram of a ferroelectric memory cell;

Fig. 1B is a schematic structural diagram of a ferroelectric memory cell;

Fig. 2 is a schematic structural diagram of a ferroelectric memory cell;

FIG. 3 is a schematic diagram of a ferroelectric memory cell occupying a substrate integration area;

FIG. 4A is a schematic structural diagram of a transistor provided in an embodiment of the present application;

FIG. 4B is a schematic diagram of a transistor preparation scheme provided in the embodiment of the present application;

FIG. 5A is a schematic structural diagram of a transistor provided in an embodiment of the present application;

FIG. 5B is a schematic diagram of a transistor preparation scheme provided in the embodiment of the present application;

FIG. 6A is a schematic structural diagram of a transistor provided in an embodiment of the present application;

FIG. 6B is a schematic diagram of a transistor preparation scheme provided in the embodiment of the present application;

FIG. 7A is a schematic structural diagram of a ferroelectric capacitor provided in an embodiment of the present application;

FIG. 7B is a schematic diagram of an arrangement of multiple ferroelectric capacitors provided by the embodiment of the present application;

8 is a schematic diagram of the circuit connection of the ferroelectric capacitor, the precharge transistor and the sensing transistor;

FIG. 9A is a schematic structural diagram of a memory module using a 2TnC structure provided by an embodiment of the present application;

FIG. 9B is a schematic structural diagram of a memory module adopting a 2TnC structure provided by the embodiment of the present application;

FIG. 9C is a schematic structural diagram of a memory module adopting a 2TnC structure provided by an embodiment of the present application;

FIG. 9D is a schematic structural diagram of a memory module adopting a 2TnC structure provided by an embodiment of the present application;

FIG. 9E is a schematic structural diagram of a memory module adopting a 2TnC structure provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of a three-dimensional stack of storage modules provided by an embodiment of the present application;

FIG. 11 is a schematic diagram of circuit connections between different memory modules provided in the embodiment of the present application;

FIG. 12 is an operation truth table provided by the embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. Apparently, the described embodiments are only some of the embodiments of this application, not all of them.

A ferroelectric memory, also known as a ferroelectric random access memory (FeRAM), may include one or more memory cells. Wherein, each storage unit is mainly composed of a capacitor (capacitor, C) and a transistor (transistor, T). Wherein, a ferroelectric crystal is deposited between the two electrode plates of the capacitor, so that the storage unit can utilize the ferroelectric effect of the ferroelectric crystal to realize data storage. The iron atom in the crystal center of a ferroelectric crystal has two stable or polarized states. These two polarization states can be set as polarization state D1 and polarization state D2 respectively. The ferroelectric effect means that when a certain electric field is applied to the ferroelectric crystal, the central atoms of the crystal move under the action of the electric field and reach a stable state (or polarization state D1); when the electric field is removed from the crystal, the central atoms will remain in their original position. This is because there is a high energy level between the two states of the crystal, and the central atom cannot cross the high energy level to reach another stable position (or polarization state D2) without obtaining external energy. Therefore, ferroelectric memory can retain data in the event of power failure, has non-volatility, and can be used as a non-volatile memory.

In the following description, the above capacitor may be referred to as a ferroelectric capacitor, and the above storage unit may be referred to as a ferroelectric storage unit.

Stacking can also be understood as permutation or distribution. The three-dimensional direction may also be referred to as a vertical direction. Wherein, the vertical direction or the three-dimensional direction refers to the direction perpendicular to the surface of the substrate.

An embodiment of the present application provides a three-dimensional ferroelectric memory, including a plurality of memory modules, wherein a single memory module is a 2TnC structure composed of n ferroelectric capacitors (nC, n being an integer greater than or equal to 1) and two vertical structure transistors (2T) stacked in the vertical direction. This structure increases the storage density of the ferroelectric memory. Specifically, compared with the horizontal structure transistor, the channel layer of the vertical structure transistor is vertical, and the three electrodes of the gate, electrode F1 and electrode F2 do not all need to occupy the integrated area of the substrate surface, so that more memory modules with a 2TnC structure can be integrated on the substrate, and each memory module with a 2TnC structure has n ferroelectric capacitors, thereby increasing the storage density. Wherein, the greater the n values, the greater the storage density of the ferroelectric memory. In one example, the integrated area occupied by each ferroelectric capacitor in n ferroelectric capacitors can be reduced to 4F ² /n, thereby greatly improving the storage density of the ferroelectric memory.

Wherein, in the embodiment of the present application, the electrode F1 of the transistor may refer to the source of the transistor, and the electrode F2 of the transistor may also refer to the drain of the transistor. Alternatively, the electrode F1 of the transistor may refer to the drain of the transistor, and the electrode F2 may also refer to the source of the transistor. That is to say, the electrode F1 can be either a source or a drain; the electrode F1 can be either a source or a drain. Wherein, when the electrode F1 is a source, the electrode F2 is a drain; when the electrode F1 is a drain, the electrode F2 is a source.

Wherein, the two vertical structure transistors of the memory module are jointly used as a gating device, and n ferroelectric capacitors in the memory module can be selected, and then, through one terminal electrode of the ferroelectric capacitor, a certain ferroelectric capacitor is selected from the n ferroelectric capacitors, and then the selected ferroelectric capacitor can be read and written.

For convenience of description, one of the two vertical structure transistors in the storage module may be called a sense transistor, and the other transistor may be called a precharge transistor, wherein the precharge transistor and the sense transistor are combined with one end electrode of a ferroelectric capacitor, and one ferroelectric capacitor can be selected from the n ferroelectric capacitors of the memory module, and the selected ferroelectric capacitor can be read and written. Wherein, the n ferroelectric capacitors may be selected by using the pre-charge transistor first, and then one ferroelectric capacitor is selected from the selected n ferroelectric capacitors by using one terminal electrode of the ferroelectric capacitor. Wherein, the use of the pre-charge transistor to select the n ferroelectric capacitors may be referred to as address selection, that is, the pre-charge transistor has an address selection function. Wherein, the sensing transistor can sense the signal generated by the read operation, and then read the information stored in the ferroelectric capacitor. The details will be described below in conjunction with the operation truth table for the storage module, and will not be repeated here.

Next, the vertical structure transistor provided in the embodiment of the present application, the circuit connection manner of the memory module, and the structure of the memory module will be introduced in sequence. Wherein, in the following description, top, tip, upper end, above, upper surface, etc. refer to a side away from the substrate in the vertical direction. The bottom, bottom end, lower end, underside, lower surface, etc. refer to a side close to the substrate in the vertical direction.

In some embodiments, a vertical structure transistor as shown in FIG. 4A is provided. Wherein, the electrode F1 and the gate of the vertical structure transistor are drawn out from the vertical direction. Wherein, the electrode F1 is specifically drawn out from the top, and the gate is specifically drawn out from the bottom. For convenience of description, the vertical structure may be referred to as a transistor T1. Wherein, in the embodiment of the present application, "drawing out" can be understood as revealing or exposing. Wherein, leading out from the vertical direction refers to protruding or exposing from the upper end and/or the lower end in the vertical direction. To emerge from the top means to expose or show through at the top. Bottom-derived means exposed or exposed at the bottom.

The electrode F1 drawn from the top of the transistor T1 can be understood as: the electrode F1 forms the upper end or the top of the transistor T1, and the gate drawn from the bottom of the transistor T1 can be understood as: the gate forms the upper end or the top of the transistor T1. In other words, the upper end or the top of the transistor T1 is the electrode F1, and the lower end or the bottom is the gate.

The preparation of the transistor T1 adopts the back-end preparation process, and the preparation of the transistor in the back-end process no longer depends on the bulk silicon substrate, and the transistor components can be stacked in the three-dimensional direction. In contrast to the latter, the planar transistors prepared by the front end of line (FEOL) process rely heavily on bulk silicon substrates.

Referring to FIG. 4A, in order to meet the requirements of back end of line (BEOL) integration and get rid of the dependence on the bulk silicon substrate, the channel layer of the transistor T1 is arranged in the vertical direction, so that the two-dimensional electron gas (two-dimensional electron gas, 2DEG) that conducts the electrode F1 and the electrode F2 moves in the vertical direction. The channel layer has a cylindrical shape, for example, a cylindrical shape, a square cylindrical shape, or the like.

In one example, the material of the channel layer may be N-type lightly doped semiconductor. Wherein, the N-type doped semiconductor refers to doping the semiconductor with N-type impurities to provide free electrons for the semiconductor. Wherein, the N-type impurity may also be referred to as a donor impurity, which is an impurity that can provide free electrons for the semiconductor material. In one example, the N-type impurity may be P element, or As element, or Sb element. In one example, the semiconductor used may specifically be polysilicon. Among them, lightly doped, that is, lightly doped, means that the semiconductor is doped with less impurities. Corresponding to light doping is heavy doping, heavy doping, that is, heavy doping, refers to the doping of more impurities into the semiconductor. That is to say, it can be divided into light doping and heavy doping according to the amount of doped impurities. In this example, N-type lightly doped semiconductor is relative to N-type heavily doped semiconductor which will be described below. That is to say, compared with the N-type heavily doped semiconductor described below, the N-type lightly doped semiconductor is doped with less N-type impurities. Correspondingly, compared with the N-type lightly doped semiconductor, the N-type heavily doped semiconductor described below is doped with more N-type impurities.

In one example, the material of the channel layer may be an oxide film with high electron mobility. For example, the oxide film may be any one of In-Ga-Zn-O (indium gallium zinc oxide, IGZO), In-Sn-O (indium tin oxide, ITO), In-Al-Zn-O (IAZO), In-Ga-Sn-O (IGTO), and ZnO.

A cylindrical gate oxide layer S1 is disposed inside the cylindrical channel layer. That is, the gate oxide layer S1 is surrounded by the channel layer. The shape of the gate oxide layer S1 corresponds to the channel layer, so that the gate oxide layer can be adhered to the channel layer. The gate oxide layer is made of gate oxide, which is an insulating material. Exemplarily, the gate oxide may be any one of silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide.

A part of the gate of the transistor T1 is located in the cylindrical gate oxide layer S1 , or in other words, this part is surrounded by the gate oxide layer S1 . Another part of the gate of the transistor T1 protrudes from the bottom of the cylindrical gate oxide layer S1. In one example, the gate can be a metal electrode, such as a tungsten electrode.

An electrode F1 is disposed on the top of the channel layer, wherein the electrode F1 is insulated from the gate. Exemplarily, as shown in FIG. 4A , the electrode F1 and the gate may be separated by a gate oxide layer S2 . Exemplarily, as shown in FIG. 4A, the electrode F1 may be composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer that are successively connected in the vertical direction, wherein the N-type heavily doped semiconductor is in contact with the channel layer, thereby reducing the ohmic contact resistance between the electrode F1 and the channel layer.

Wherein, in the embodiment of the present application, "contact" can be understood as "touching", which usually refers to two objects in the form of blocks or sheets touching each other, or that one of the two objects is located on the surface of the other. In addition, in this embodiment of the present application, "connection" may refer to direct contact between two objects. "Connection" can also mean that two objects are connected by a third object, that is, one side or one end of the third object touches one of the two objects, and the other side or end of the third object touches the other of the two objects.

Wherein, as mentioned above, compared with the N-type lightly doped semiconductor mentioned above, the N-type heavily doped semiconductor is doped with more N-type impurities.

Silicide refers to the binary compound formed by metal (such as lithium, calcium, magnesium, iron, chromium, etc.) or non-metal (such as boron, etc.) and silicon, which has good high temperature oxidation resistance and electrical conductivity. Exemplarily, the silicide may be TiSi or WSi.

Exemplarily, the metal electrode may be a tungsten electrode.

Continuing to refer to FIG. 4A , the electrode F2 of the transistor T1 is disposed on the outer sidewall of the channel layer, or in other words, the electrode F2 surrounds the channel layer. And there is a preset distance between the electrode F2 and the electrode F1. Exemplarily, the electrode F1 may be composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer which are successively connected in the vertical direction. Wherein, the N-type heavily doped semiconductor layer is located on a side close to the electrode F1. Wherein, the metal electrode layer, the silicide layer, and the N-type heavily doped semiconductor layer can refer to the introduction of the electrode F1 above, and will not be repeated here.

In the transistor T1, the part of the channel layer between the electrode F1 and the electrode F2 can be connected to the electrode F1 and the electrode F2 under the action of the gate. For example, a positive voltage is applied to the gate to generate an electric field. Under the action of the electric field, the channel layer accumulates electrons, and the gate oxide layer can block the flow of electrons to the gate, thereby forming a two-dimensional electron gas in the channel layer that can conduct electrode F1 and electrode F2.

The structure of the transistor T1 is introduced above with reference to FIG. 4A . Next, in conjunction with 4B, the fabrication process of the transistor T1 is introduced.

As shown in FIG. 4B , the fabrication process of the transistor T1 may include step 401, in which a metal electrode 41, an insulating layer 42, a metal electrode 43, a silicide 44, an N-type heavily doped semiconductor 45, an insulating layer 46, and an N-type heavily doped semiconductor 47 are sequentially deposited on the substrate along the vertical direction. Wherein, the base can be a substrate (such as a silicon substrate), or a dielectric layer deposited on the substrate, or a base formed of a plurality of transistors distributed laterally as described below, or a base formed of ferroelectric capacitors in a three-dimensional stack structure described below. The details will be shown in the figures described below, and will not be repeated here.

Wherein, a plurality of metal electrodes 41 may be deposited on the substrate, and the plurality of metal electrodes are discontinuously distributed in the lateral direction. Wherein, the lateral direction refers to a direction parallel to the upper surface of the substrate. The insulating layer 42 is distributed between different metal electrodes 41 and above the metal electrodes 41 . Then, metal electrodes 43 , silicide 44 , N-type heavily doped semiconductor 45 , insulating layer 46 , and N-type heavily doped semiconductor 47 are sequentially deposited on the insulating layer 42 to obtain a multilayer structure.

In one illustrative example, the metal may be deposited by sputtering. In one example, the insulating layer, silicide, and N-type heavily doped semiconductor can be deposited by chemical vapor deposition (chemical vapor deposition, CVD).

Next, in step 402, the multilayer structure prepared in step 401 is etched. Specifically, etching is performed on the region corresponding to the metal electrode 41 , and the insulating layer 42 is etched. Wherein, the insulating layer 42 is not completely cut through, so that a part of the insulating layer remains above the metal electrode 41 . Exemplarily, etching may be performed by photolithography.

Next, in step 403, the channel layer 48 and the gate oxide layer 49 are sequentially filled in the etched area and the bottom is opened, and then the metal electrode 510 is deposited and ground. Specifically, firstly, the channel layer 48 is filled along the sidewall of the etched region to form a cylindrical channel layer. Wherein, the channel layer 48 can be an N-type lightly doped semiconductor, or an oxide film with high electron mobility, and details can be referred to above. Then, a gate oxide layer 49 is filled along the sidewall of the channel layer to form a cylindrical gate oxide layer. Among them, the metal electrode 43, the silicide 44, and the N-type heavily doped semiconductor 45 can form the electrode F2. Then the insulating layer 42 at the bottom of the cylindrical gate oxide layer is etched away to expose the metal electrode 41 . Then, a metal electrode 410 is deposited on the exposed metal electrode 41 , and the upper end of the metal electrode 410 is lower than the upper end of the cylindrical gate oxide layer 47 . The upper surface of the metal electrode 410 may be ground flat. The metal electrode 410 and the metal electrode 41 form a gate electrode.

Afterwards, in step 404 , the gate oxide 411 is filled, and the silicide 412 and the metal electrode 413 are sequentially deposited. Specifically, the gate oxide 411 may be filled above the metal electrode 410 , and the upper surface of the filled gate oxide 4110 is level with the upper end of the cylindrical gate oxide layer 49 . Then, a silicide 412 and a metal electrode 413 may be deposited on the entire region including the N-type heavily doped semiconductor 47 , the upper end of the channel layer 48 , the upper end of the gate oxide layer 49 , and the upper end of the gate oxide 411 to form the electrode F1 .

Thus, the transistor T1 can be fabricated through the process shown in FIG. 4B . Moreover, as shown in FIG. 4B , multiple transistors T1 distributed in the lateral direction can be fabricated simultaneously.

Wherein, the process operations such as deposition, etching, and filling in the process shown in FIG. 4B can refer to the introduction of the prior art, and will not be repeated here.

In some embodiments, a vertical structure transistor as shown in FIG. 5A is provided. Wherein, the gate of the transistor is drawn out in the vertical direction. Specifically, the grid is drawn through in the vertical direction. For convenience of description, the vertical structure may be referred to as a transistor T2. Wherein, the gate of the transistor T2 is drawn through in the vertical direction, which can be understood as: one end of the gate of the transistor T2 forms the upper end or the top of the transistor T2, and the other end forms the lower end or the bottom of the transistor T2.

Referring to FIG. 5A , in order to meet the requirements of later integration and get rid of the dependence on the bulk silicon substrate, the channel layer of the transistor T2 is arranged in the vertical direction, so that the two-dimensional electron gas that conducts the electrode F1 and the electrode F2 moves in the vertical direction. The channel layer has a cylindrical shape, for example, a cylindrical shape, a square cylindrical shape, or the like. In one example, the material of the channel layer may be N-type lightly doped semiconductor. In one example, the material of the channel layer may be an oxide film with high electron mobility. For the material of the channel layer, reference may be made to the introduction of the transistor T1 above, which will not be repeated here.

A channel layer surrounds the gate oxide layer. Specifically, a cylindrical gate oxide layer is provided inside the cylindrical channel layer. The shape of the gate oxide layer corresponds to the channel layer so that the gate oxide layer can be attached to the channel layer. The gate oxide layer is made of gate oxide, which is an insulating material. Exemplarily, the gate oxide may be any one of silicon oxide, silicon nitride, and silicon oxynitride.

The gate of the transistor T2 penetrates through the cylindrical gate oxide layer and protrudes from the upper end and the lower end of the gate oxide layer. In one example, the gate can be a metal electrode, such as a tungsten electrode.

The electrode F1 and the electrode F2 of the transistor T2 are disposed at different positions on the outer sidewall of the channel layer, or both the electrode F1 and the electrode F2 surround the channel layer. Wherein, on the outer sidewall of the channel layer, the electrodes F1 and F2 are arranged vertically, and there is a preset distance between the electrodes F1 and F2. The electrode F1 may be located above the electrode F2, or may be located below the electrode F2. Exemplarily, both the electrode F1 and the electrode F2 may be composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer that are successively connected in the vertical direction. Wherein, the N-type heavily doped semiconductor layer of the electrode F1 is located on the side close to the electrode F2, and the N-type heavily doped semiconductor layer of the electrode F2 is located on the side close to the electrode F1.

The metal electrode layer, the silicide layer, and the N-type heavily doped semiconductor layer can be specifically implemented with reference to the introduction of the transistor T1 above.

In the transistor T2, the part of the channel layer between the electrode F1 and the electrode F2 can conduct the electrode F1 and the electrode F2 under the action of the gate.

The structure of the transistor T2 is introduced above with reference to FIG. 5A . Next, in conjunction with 5B, the fabrication process of the transistor T2 is introduced.

As shown in FIG. 5B , the fabrication process of the transistor T2 may include step 501. Along the vertical direction, sequentially deposit a metal electrode 51, an insulating layer 52, a metal electrode 53, a silicide 54, an N-type heavily doped semiconductor 55, an insulating layer 56, an N-type heavily doped semiconductor 57, an insulating layer 58, a metal electrode 59, and an insulating layer 510. Wherein, the base may be a substrate, or a base formed of multiple transistors distributed laterally (for example, multiple transistors shown in FIG. 4B ), or a base formed of ferroelectric capacitors in a three-dimensional stack structure described below.

Wherein, a plurality of metal electrodes 51 may be deposited on the substrate, and the plurality of metal electrodes 51 are discontinuously distributed in the lateral direction. Wherein, the lateral direction refers to a direction parallel to the upper surface of the substrate. The insulating layer 52 is distributed between different metal electrodes 51 and above the metal electrodes 51 . Then, metal electrode 53, silicide 54, N-type heavily doped semiconductor 55, insulating layer 56, N-type heavily doped semiconductor 57, insulating layer 58, metal electrode 59, and insulating layer 510 are sequentially deposited on insulating layer 52 to obtain a multilayer structure.

Next, in step 502, the multilayer structure prepared in step 501 is etched. Specifically, etching is performed on the region corresponding to the metal electrode 41 , and the insulating layer 52 is etched. Wherein, the insulating layer 52 is not completely cut through, so that a part of the insulating layer remains above the metal electrode 51 .

Next, in step 503, the channel layer 511, the gate oxide layer 512 are sequentially filled, and the bottom opening is opened, and then the metal electrode 513 is deposited. Specifically, firstly, the channel layer 511 is filled along the sidewall of the etched region to form a cylindrical channel layer. Then, a gate oxide layer 512 is filled along the sidewall of the channel layer to form a cylindrical gate oxide layer. Then the insulating layer 52 at the bottom of the cylindrical gate oxide layer is etched away to expose the metal electrode 51 . Then, a metal electrode 513 is deposited on the exposed metal electrode 51 , and the upper end of the metal electrode 513 is lower than the upper end of the cylindrical gate oxide layer 512 . The upper surface of the metal electrode 513 may be ground flat.

Afterwards, in step 504 , an insulating layer 514 is deposited on the entire area including the insulating layer 510 , the upper end of the channel layer 511 , the upper end of the gate oxide layer 512 , and the upper end of the metal electrode 513 . Next, the area of the insulating layer 514 corresponding to the metal electrode 513 is etched, and etched to the metal electrode 513 to expose the metal electrode 513 . Metal electrode 515 may then be deposited on metal electrode 513 . The metal electrode 515 , the metal electrode 513 and the metal electrode 51 constitute the vertically drawn gate of the transistor T2 , wherein the metal electrode 513 forms the upper end of the transistor T2 , and the metal electrode B2 forms the lower end of the transistor T2 .

Thus, the transistor T2 can be fabricated through the process shown in FIG. 5B. Moreover, as shown in FIG. 5B , multiple transistors T2 distributed in the lateral direction can be fabricated simultaneously.

In some embodiments, a vertical structure transistor as shown in FIG. 6A is provided. Wherein, the electrodes F1 and F2 of the vertical structure transistor are drawn out in the vertical direction. Wherein, the electrode F1 and the electrode F2 are led out from the top and the bottom of the transistor respectively, that is, the electrode F1 and the electrode F2 respectively form the upper end and the lower end of the transistor. Specifically, when the electrode F1 is drawn from the top of the transistor, the electrode F2 is drawn from the bottom of the transistor; when the electrode F1 is drawn from the bottom of the transistor, the top is drawn from the top of the transistor. That is, when the electrode F1 is the upper end of the transistor, the electrode F2 is the lower end of the transistor; when the electrode F1 is the lower end of the transistor, the electrode F2 is the upper end of the transistor.

For convenience of description, the vertical structure may be referred to as a transistor T3. Wherein, the transistor T3 may also be referred to as a gate-all-around (GAA) transistor.

Referring to FIG. 6A , the channel layer of the transistor T3 is U-shaped, which may be referred to as a U-shaped channel layer. Wherein, the opening of the U-shaped channel layer faces upward. In one example, the material of the channel layer may be N-type lightly doped semiconductor. In one example, the material of the channel layer may be an oxide film with high electron mobility. For the material of the channel layer, reference may be made to the introduction of the transistor T1 above, which will not be repeated here.

The inside of the U-shaped channel layer is filled with an insulator. The outer sidewall of the U-shaped channel layer is provided with a gate oxide layer. In other words, the gate oxide surrounds the channel layer.

The gate oxide is surrounded by the gate. In one example, the gate can be a metal electrode. As shown in FIG. 6A , in the lateral direction, one side of the gate oxide layer is attached to the outer sidewall of the U-shaped channel layer, and the other side is provided with a metal electrode. This metal electrode serves as the gate of transistor T3.

The upper end of the U-shaped channel layer is provided with an electrode A1, and the lower end is provided with an electrode A2. There is a gap between the electrode A1 and the grid, and there is also a gap between the electrode A2 and the grid. Wherein, the electrode A1 can be used as the electrode F1 of the transistor T3, and can also be used as the electrode F2 of the transistor T3. Correspondingly, the electrode A2 can be used as the electrode F2 of the transistor T3, and can also be used as the electrode F1 of the transistor T3. Specifically, when the electrode A1 is used as the electrode F1 of the transistor T3, the electrode A2 is used as the electrode F2 of the transistor T3; when the electrode A1 is used as the electrode F2 of the transistor T3, the electrode A2 is used as the electrode F1 of the transistor T3.

As shown in FIG. 6A , the electrode A1 and the electrode A2 are composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer, which may be successively connected in the vertical direction. Wherein, the N-type heavily doped semiconductor layer of the electrode A1 is in contact with the upper end of the U-shaped channel layer, and the N-type heavily doped semiconductor layer of the electrode A2 is in contact with the bottom of the U-shaped channel layer.

Under the action of the gate, the U-shaped channel layer generates a two-dimensional electron gas, so that the electrode F1 and the electrode F2 can be connected.

The structure of the transistor T3 is introduced above with reference to FIG. 6A . Next, in conjunction with 6B, the fabrication process of the transistor T3 is introduced.

As shown in FIG. 6B, the fabrication process of the transistor T3 may include step 601, depositing a metal electrode 61, a silicide 62, an N-type heavily doped semiconductor 63, an insulating layer 64, a metal electrode 65, and an insulating layer 66 in sequence on the substrate along the vertical direction. Wherein, the base may be a substrate, or may be a base formed by ferroelectric capacitors in the three-dimensional stacked structure described below.

Wherein, a plurality of metal electrodes 61 may be deposited on the substrate, and the plurality of metal electrodes 61 are discontinuously distributed in the lateral direction. A silicide 62 is deposited on each metal electrode 61, and an N-type heavily doped semiconductor 63 is deposited on the silicide 62 to form an electrode A2. An insulating layer 64 is deposited between and over electrodes A2. Then, a metal electrode 65 and an insulating layer 66 are sequentially deposited on the insulating layer 64 to obtain a multilayer structure.

Next, in step 602, the multilayer structure prepared in step 601 is etched. Specifically, etching is performed on the region corresponding to the N-type heavily doped semiconductor 63 , and the N-type heavily doped semiconductor 63 is etched.

Next, in step 603 , the gate oxide 67 is sequentially filled and opened, and the channel layer 68 and the insulator 69 are filled. Specifically, the gate oxide 67 is firstly filled along the sidewall of the etched region to form a gate oxide layer. The deposited gate oxide of the N-type heavily doped semiconductor 63 is removed, that is, an opening is made to expose the N-type heavily doped semiconductor 63 . Then, a channel layer 68 is filled on the N-type heavily doped semiconductor 63 and the sidewall of the gate oxide layer to form a U-type channel layer. The insulator 69 is refilled into the U-shaped channel layer. Finally, the upper end of the gate oxide layer, the upper end of the U-shaped channel layer, and the upper end of the insulator 69 may be ground flat.

Afterwards, in step 604, on the entire area including the upper end of the gate oxide layer, the upper end of the U-shaped channel layer and the upper end of the insulator 69, sequentially deposit N-type heavily doped semiconductor 610, silicide 611 and metal electrode 612 to form electrode A1.

Thus, the transistor T3 can be fabricated through the process shown in FIG. 6B. Moreover, as shown in FIG. 6B , multiple transistors T3 distributed in the lateral direction can be fabricated simultaneously.

As shown in FIG. 7A , the embodiment of the present application provides a ferroelectric capacitor in which electrodes are drawn out from a vertical direction. Wherein, the ferroelectric capacitor includes an electrode B1, an electrode B2 opposite to the electrode B1, and a ferroelectric layer deposited between the electrode B1 and the electrode B2. In other words, the ferroelectric layer surrounds the electrode B2, and the electrode B1 surrounds the ferroelectric layer. Wherein, the ferroelectric layer may specifically be a ferroelectric crystal. The electrode B2 may be a floating gate (FG). Exemplarily, the electrodes B1 and B2 may be metal electrodes, such as tungsten electrodes.

Wherein, the electrode B2 is drawn out from the vertical direction, that is, the electrode B2 is exposed at the upper end of the ferroelectric capacitor, or is exposed at the lower end of the ferroelectric capacitor, or is exposed at both the upper end and the lower end of the ferroelectric capacitor.

Through the electrodes B1 and B2, an electric field can be applied to the ferroelectric layer to change the position of the central atom of the crystal in the ferroelectric layer, so that the ferroelectric layer can record information, that is, to write information into the ferroelectric layer. Through the electrodes B1 and B2, another electric field can be applied to the ferroelectric layer to sense whether the position of the crystal center atom in the ferroelectric layer has changed, so as to read the information recorded in the ferroelectric layer.

In some embodiments, as shown in FIG. 7B , n ferroelectric capacitors may be stacked or arranged vertically, where n is an integer greater than or equal to 1. Wherein, n electrode layers surround the ferroelectric layer, and two adjacent electrode layers among the n electrode layers are separated by an insulating material. The n electrode layers correspond to the n ferroelectric capacitors one by one, and are used as the electrode B1. A ferroelectric layer surrounds the cylindrical electrodes. The columnar electrode is used as the electrode B2 of the n ferroelectric capacitors.

Specifically, a ferroelectric layer extending in the vertical direction may be provided, and the ferroelectric layer has a cylindrical shape. There are n electrode layers arranged on the outer wall of the cylindrical ferroelectric layer, the n electrode layers are arranged in sequence along the vertical direction, and there is an insulating layer between the upper and lower adjacent electrode layers, that is, the upper and lower adjacent electrode layers are separated or insulated by insulating materials. The n electrode layers correspond to the n ferroelectric capacitors one by one, and are respectively used as electrodes B1 of the corresponding ferroelectric capacitors.

A columnar electrode extending vertically is provided inside the cylindrical ferroelectric layer. The columnar electrode can be used as the electrode B2 of the n ferroelectric capacitors. That is to say, the plurality of ferroelectric capacitors share the electrode B2.

Ferroelectric capacitors can be fabricated as follows.

First, insulating layers and electrode layers are alternately deposited on the substrate along the vertical direction, wherein n insulating layers and n electrode layers are co-deposited to obtain a multilayer structure. Wherein, n is an integer greater than or equal to 1. The electrode layer may be a metal electrode layer. The base may be a substrate, or a plurality of transistors T1 as shown in FIG. 4B , or a plurality of transistors T2 as shown in FIG. 5B , or a plurality of transistors T3 as shown in FIG. 6B .

Then, the multi-layer structure is etched, and etched to the substrate.

Then, the sidewall of the etched region is filled with a ferroelectric layer to form a cylindrical ferroelectric layer extending in the vertical direction. Then the columnar electrodes are filled in the cylindrical ferroelectric layer. The columnar electrode may be a columnar metal electrode.

Thus, n ferroelectric capacitors arranged in the vertical direction can be prepared.

The above examples describe transistors and ferroelectric capacitors that can be provided in embodiments of the present application. Next, a memory module with a 2TnC structure that can be formed using the above-mentioned transistors and ferroelectric capacitors is introduced.

The circuit connection mode of the memory module with 2TnC structure is shown in FIG. 8 . Wherein, as mentioned above, 2T in the 2TnC structure is a sensing transistor and a precharge transistor, nC is n ferroelectric capacitors, and n is an integer greater than or equal to 1. Both the gate of the sensing transistor and the electrode F1 of the precharge crystal transistor are connected to the electrodes B2 of the n ferroelectric capacitors, and the n ferroelectric capacitors share the electrode B2. Therefore, the sensing transistor is a transistor whose gate is drawn out from the vertical direction, such as the transistor T1 and the transistor T2 mentioned above. The pre-charging transistor of the storage module is selected from the transistor drawn from the electrode F1 in the vertical direction, for example, the above-mentioned transistor T1 and transistor T3. Combined with the ferroelectric capacitance drawn from the vertical direction of electrode B2. The three-dimensional stacking of the sensing transistor, the precharge transistor and the ferroelectric capacitor can be realized, so that more memory modules can be integrated on the substrate, and the storage density and capacity of the ferroelectric memory are improved.

8, the electrode F1 of the sensing transistor is connected to the source line (source line, SL), the electrode F2 of the sensing transistor is connected to the bit line (bit line, BL), the electrode F1 of the pre-charging transistor is connected to the control line (control line, CL), and the electrode F2 of the pre-charging transistor is connected to the bit line. The electrodes B1 of the n ferroelectric capacitors are connected to a word line (word line, WL).

The bit lines, the control lines and the word lines can respectively provide corresponding voltages to operate the corresponding ferroelectric capacitors. The details will be introduced below in conjunction with the operation truth table, and will not be repeated here.

Wherein, when n is greater than 1, the electrodes B1 of different capacitors in the n ferroelectric capacitors are connected to different word lines, for example, the electrode B1 of the first ferroelectric capacitor in the n ferroelectric capacitors is connected to the word line WL ₁ , ..., and the electrode B1 of the nth ferroelectric capacitor is connected to the word line WL _n . In this way, corresponding to any ferroelectric capacitor among the n ferroelectric capacitors, the voltage of the word line corresponding to the ferroelectric capacitor can be controlled, and the voltage of the source line, bit line, control line, and electrode B2 can be controlled by operating the sensing transistor and the precharge transistor, so as to perform read and write operations on the ferroelectric capacitor. The details will be introduced below in conjunction with the operation truth table, and will not be repeated here.

Next, taking the memory module M1 as an example, the structure of the memory module with the 2TnC structure is introduced. Wherein, in the memory module M1, the electrode B2 may be exposed at the upper end and/or lower end of the ferroelectric capacitor, the gate of the sensing transistor may form the upper end and/or lower end of the sensing transistor, and the electrode F1 of the pre-charging transistor may form the upper end and/or lower end of the pre-charging transistor. Combined with the circuit connection method of 2TnC, that is, the gate of the sensing transistor is connected to the electrode B2, and the electrode F1 of the pre-charging transistor is connected to the electrode B2, the ferroelectric capacitor B2, the gate of the sensing transistor and the electrode F1 of the pre-charging transistor can be used to realize the stacking of the ferroelectric capacitor, the sensing transistor and the pre-charging transistor in the vertical direction. Next, the situation will be introduced.

In Embodiment 1, the electrode B2 may be exposed at the lower end of the ferroelectric capacitor, the gate of the sensing transistor may form the upper end and the lower end of the sensing transistor, and the electrode F1 of the pre-charging transistor may form the upper end of the pre-charging transistor. In this way, the electrode B2 exposed at the lower end of the ferroelectric capacitor can be in contact with the upper end of the sensing transistor, and the lower end of the sensing transistor can be in contact with the upper end of the pre-charging transistor, so that the ferroelectric capacitor can be arranged above the sensing transistor, and the pre-charging transistor can be arranged below the sensing transistor, so as to realize the vertical stacking of the ferroelectric capacitor, the sensing transistor, and the pre-charging transistor. In addition, the gate of the sensing transistor also runs through the sensing transistor, so that the electrode F1 of the precharge transistor can be connected to the electrode B2 of the ferroelectric capacitor through the gate of the sensing transistor.

Wherein, in the embodiment of the present application, the lower part refers to the side close to the substrate, and the upper part refers to the side away from the substrate.

In the first example of Embodiment 1, the sensing transistor may be the transistor T2, and the pre-charging transistor may be the transistor T1.

The specific structure can be shown in FIG. 9A , in the vertical direction, n ferroelectric capacitors, sensing transistors and pre-charging transistors are sequentially connected. Wherein, the n ferroelectric capacitors are located above the sensing transistor, and the precharge transistor is located below the sensing transistor. The gate of the sensing transistor penetrates through the sensing transistor, whereby the upper end of the sensing transistor gate contacts the lower end of the electrode B2 shared by the n ferroelectric capacitors above, so as to realize the connection between the electrode B2 and the sensing transistor gate. The lower end of the gate of the sensing transistor is in contact with the electrode F1 drawn from the top of the pre-charging transistor, so that the electrode F1 of the pre-charging transistor can be connected to the electrode B2 through the gate of the sensing transistor. Exemplarily, as shown in FIG. 9A , the lower end of the gate of the sensing transistor and the electrode F1 of the pre-charging transistor share a metal electrode, so as to save manufacturing cost and simplify the manufacturing process of the memory module.

For example, the n ferroelectric capacitors in the memory module M1 can be specifically set to be four ferroelectric capacitors, then the electrode B1 of the first ferroelectric capacitor is connected to the word line WL1, the electrode B1 of the second ferroelectric capacitor is connected to the word line WL2, the electrode B1 of the third ferroelectric capacitor is connected to the word line WL3, and the electrode B1 of the fourth ferroelectric capacitor is connected to the word line WL4.

In addition, as shown in FIG. 9A , the electrode F1 of the sensing transistor in the memory module M1 can be connected to the source line SL1 , and the electrode F2 can be connected to the bit line BL1 . The gate of the pre-charge transistor in the memory module M1 can be connected to the control line CL1, and the electrode F2 can be connected to the bit line BL1.

When preparing the memory module M1 shown in FIG. 9A, a pre-charge transistor (i.e. transistor T1 can be prepared on the substrate, the preparation process can refer to the introduction of the embodiment shown in FIG. 4B above), and then a sensing transistor can be prepared on the prepared pre-charge transistor (i.e. transistor T2, the preparation process can refer to the introduction of the embodiment shown in FIG. 5B above), and then n ferroelectric capacitors can be prepared on the prepared pre-charge transistor.

In the embodiment shown in FIG. 9A , the ferroelectric capacitor is manufactured after the transistor, which avoids the degradation of ferroelectric performance caused by the high temperature stage in the transistor manufacturing process. Moreover, the transistor is closer to the substrate, so that the lead wires of the bit line, the control line, and the source line can be directly pulled down to connect with the corresponding drive circuit on the substrate, and all can be set as shorter lines, shortening the path, and reducing the read and write operation delay of the memory module M1. Moreover, the word lines connected to the electrodes B1 of different ferroelectric capacitors among the n ferroelectric capacitors can be led out from the surroundings of the memory module M1 and connected to corresponding driving circuits respectively, which improves the driving capability of the electrode B1 and reduces the driving time delay.

In the second example of Embodiment 1, the sensing transistor may be the transistor T2, and the pre-charging transistor may be the transistor T3. Wherein, in this example, the electrode A1 of the transistor T3 is used as the electrode F1, and the electrode A2 is used as the electrode F2.

The specific structure can be shown in Figure 9A. In the vertical direction, n ferroelectric capacitors, sensing transistors and pre-charging transistors are sequentially connected. Wherein, the n ferroelectric capacitors are located above the sensing transistor, and the precharge transistor is located below the sensing transistor. The gate of the sensing transistor penetrates through the sensing transistor, thus, the upper end of the gate of the sensing transistor is in contact with the electrode B2 shared by the upper n ferroelectric capacitors, so as to realize the connection between the electrode B2 and the gate of the sensing transistor. The lower end of the gate of the sensing transistor is in contact with the electrode F1 drawn from the top of the pre-charging transistor, so that the electrode F1 of the pre-charging transistor (that is, the electrode A1 of the transistor T3 is used as electrode F1) can be connected to the electrode B2 through the gate of the sensing transistor. Exemplarily, as shown in FIG. 9B , the lower end of the gate of the sensing transistor and the electrode F1 of the precharge transistor share a metal electrode, so as to save manufacturing cost and simplify the manufacturing process of the memory module.

For the n ferroelectric capacitors in the memory module M1 shown in FIG. 9B , reference can be made to the introduction above, and details will not be repeated here.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor in the memory module M1 shown in FIG. 9B , as well as the gate of the pre-charging transistor and the electrode F2 can be referred to above, and will not be repeated here.

When preparing the memory module M1 shown in FIG. 9B , a pre-charge transistor (ie, transistor T3 , the preparation process can refer to the above description of the embodiment shown in FIG. 6B ) can be prepared on the substrate. Then, a sensing transistor (that is, transistor T2 , the manufacturing process may refer to the above introduction to the embodiment shown in FIG. 5B ) is fabricated on the prepared pre-charged transistor. Then, n ferroelectric capacitors are prepared on the prepared precharge transistor.

The storage module M1 shown in FIG. 9B also has the advantages of the storage module M1 shown in FIG. 9A . For details, reference may be made to the introduction above, and details will not be repeated here.

Embodiment 2, the electrode B2 can be exposed at the upper end and the lower end of the ferroelectric capacitor, the gate of the sensing transistor can form the lower end of the sensing transistor, and the electrode F1 of the pre-charging transistor can form the upper end of the pre-charging transistor. In this way, the electrode B2 exposed at the upper end of the ferroelectric capacitor can be in contact with the upper end of the sensing transistor, and the electrode B2 exposed at the lower end of the ferroelectric capacitor is in contact with the upper end of the pre-charging transistor, so that the sensing transistor can be arranged above the ferroelectric capacitor, and the pre-charging transistor can be arranged below the sensing transistor, so as to realize the vertical stacking of the ferroelectric capacitor, the sensing transistor and the pre-charging transistor.

In the first example of Embodiment 2, the sensing transistor can be the transistor T1, and the pre-charge transistor can also be the transistor T1. The specific structure is shown in FIG. 9C , in the vertical direction, the sensing transistor, n ferroelectric capacitors and the pre-charging transistor are sequentially connected. Wherein, the sensing transistor is located above the n ferroelectric capacitors, thus, the gates of the sensing transistors drawn from the bottom can be in contact with the tops of the electrodes B2 of the n ferroelectric capacitors to realize the connection between the electrode B2 and the gates of the sensing transistors. The pre-charge transistor is located below the n ferroelectric capacitors, thus, the electrode F1 led out from the top of the pre-charge transistor can contact the bottom of the electrode B2 of the n ferroelectric capacitors to realize the connection between the electrode B2 and the electrode F1 of the pre-charge transistor.

For the n ferroelectric capacitors in the memory module M1 shown in FIG. 9C , reference can be made to the introduction above, and details will not be repeated here.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor in the memory module M1 shown in FIG. 9C , as well as the gate of the pre-charging transistor and the electrode F2 can be referred to above, and will not be repeated here.

When preparing the memory module M1 shown in FIG. 9C , a pre-charge transistor (ie, transistor T1 , the preparation process can refer to the above description of the embodiment shown in FIG. 4B ) can be prepared on the substrate. Then, n ferroelectric capacitors are prepared on the prepared precharge transistor. Then, a sensing transistor (that is, transistor T1 , the fabrication process may refer to the above introduction to the embodiment shown in FIG. 4B ) is fabricated on the n ferroelectric capacitors.

In the embodiment shown in FIG. 9C , the structures of the sensing transistor and the pre-charging transistor are the same, which reduces the difficulty of the manufacturing process of the memory model as a whole. Moreover, the sensing transistor does not need to withstand the high temperature stage of the ferroelectric capacitor manufacturing process, which avoids performance degradation of the sensing transistor caused by high temperature.

In the second example of Embodiment 2, the sensing transistor may be the transistor T1, and the pre-charging transistor may be the transistor T3. Wherein, in this example, the electrode A1 of the transistor T3 is used as the electrode F1, and the electrode A2 is used as the electrode F2.

The specific structure is shown in FIG. 9D , in the vertical direction, the sensing transistor, n ferroelectric capacitors and the pre-charging transistor are sequentially connected. Wherein, the sensing transistor is located above the n ferroelectric capacitors, thus, the gates of the sensing transistors drawn from the bottom can be in contact with the tops of the electrodes B2 of the n ferroelectric capacitors to realize the connection between the electrode B2 and the gates of the sensing transistors. The pre-charge transistor is located below the n ferroelectric capacitors, thus, the electrode F1 drawn from the top of the pre-charge transistor (that is, the electrode A1 of the transistor T3 is used as the electrode F1) can be in contact with the bottom end of the electrode B2 of the n ferroelectric capacitors to realize the connection between the electrode B2 and the electrode F1 of the pre-charge transistor.

For the n ferroelectric capacitors in the memory module M1 shown in FIG. 9D , reference can be made to the introduction above, and details will not be repeated here.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor in the memory module M1 shown in FIG. 9D , as well as the gate of the pre-charging transistor and the electrode F2 can be referred to above, and will not be repeated here.

When preparing the memory module M1 shown in FIG. 9D , a pre-charge transistor (ie, transistor T3 , the preparation process may refer to the above introduction to the embodiment shown in FIG. 6B ) may be prepared on the substrate. Then, n ferroelectric capacitors are prepared on the prepared precharge transistor. Then, a sensing transistor (that is, transistor T1 , the fabrication process may refer to the above introduction to the embodiment shown in FIG. 4B ) is fabricated on the n ferroelectric capacitors.

In the embodiment shown in FIG. 9D , the sensing transistor does not need to withstand the high temperature stage of the ferroelectric capacitor manufacturing process, which avoids performance degradation of the sensing transistor caused by high temperature.

In Embodiment 3, the electrode B2 may be exposed at the upper end of the ferroelectric capacitor, the gate of the sensing transistor may form the upper end and the lower end of the sensing transistor, and the electrode F1 of the pre-charging transistor may form the lower end of the pre-charging transistor. In this way, the electrode B2 exposed at the upper end of the ferroelectric capacitor can be in contact with the lower end of the sensing transistor, and the upper end of the sensing transistor is in contact with the lower end of the pre-charge transistor. Therefore, the sensing transistor can be arranged above the ferroelectric capacitor, and the precharge transistor can be arranged above the sensing transistor, so as to realize the stacking of the ferroelectric capacitor, the sensing transistor and the precharge transistor in the vertical direction. In addition, the gate of the sensing transistor also runs through the sensing transistor, so that the electrode F1 of the precharge transistor can be connected to the electrode B2 of the ferroelectric capacitor through the gate of the sensing transistor.

In the first example of Embodiment 3, the sensing transistor may be the transistor T2, and the pre-charging transistor may be the transistor T3. Wherein, in this example, the electrode A2 of the transistor T3 is used as the electrode F1, and the electrode A1 is used as the electrode F2. The specific structure is shown in FIG. 9E , in the vertical direction, the precharge transistor, the sensing transistor and n ferroelectric capacitors are connected in sequence. Wherein, the sensing transistor is located above the n ferroelectric capacitors, and the gate of the sensing transistor runs through the sensing transistor. Thus, the lower end of the gate of the sensing transistor can be in contact with the upper ends of the electrodes B2 of the n ferroelectric capacitors to realize the connection between the electrode B2 and the gate of the sensing transistor. The pre-charging transistor is located above the sensing transistor, so that the electrode F1 drawn from the top of the pre-charging transistor (that is, the electrode A2 of the transistor T3 is used as the electrode F1) can be in contact with the upper end of the gate of the sensing transistor, so that the electrode F1 of the pre-charging transistor can be connected to the electrode B2 through the gate of the sensing transistor. Exemplarily, as shown in FIG. 9E , the upper end of the gate of the sensing transistor and the electrode F1 of the precharge transistor share one metal electrode, so as to save manufacturing cost and simplify the manufacturing process of the memory module.

For the n ferroelectric capacitors in the memory module M1 shown in FIG. 9E , reference can be made to the introduction above, and details will not be repeated here.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor in the memory module M1 shown in FIG. 9E , as well as the gate of the pre-charging transistor and the electrode F2 can be referred to above, and will not be repeated here.

When preparing the memory module M1 shown in FIG. 9E, n ferroelectric capacitors may be prepared on the substrate first. Then, a sensing transistor (that is, transistor T2 , the fabrication process may refer to the above introduction to the embodiment shown in FIG. 5B ) is fabricated on the n ferroelectric capacitors. Then, a precharge transistor (that is, transistor T3 , the preparation process may refer to the above introduction to the embodiment shown in FIG. 6B ) is prepared on the prepared sensing transistor.

In the embodiment shown in FIG. 9E , when preparing n ferroelectric capacitors, the bottom of the columnar electrode does not need to be opened, which can avoid the etching process of the bottom opening of the columnar electrode, damage to the sidewall ferroelectric layer, and further avoid the degradation of ferroelectric properties caused by the damage.

The memory module provided by the embodiment of the present application can stack transistors and at least one ferroelectric capacitor in the vertical direction, and the transistors have a vertical structure, so that the integration area of the substrate can be saved, and the storage density and capacity of the ferroelectric memory can be improved.

Multiple memory modules with a 2TnC structure can be integrated on one substrate. In some embodiments, taking the memory module shown in FIG. 9A as an example, referring to FIG. 10 , multiple memory modules may be integrated on the substrate. Memory modules integrated on the same substrate may be referred to as a memory module array.

The ferroelectric capacitors in the memory module array can be divided into multiple ferroelectric capacitor sets according to whether the word lines are the same. In other words, the ferroelectric capacitors of the same word line in the memory module array can be divided into the same ferroelectric capacitor set. Wherein, each set of ferroelectric capacitors includes at least one ferroelectric capacitor. Wherein, the ferroelectric capacitors in each ferroelectric capacitor set are connected to the same word line, which is different from the word lines connected to the ferroelectric capacitors in other sets (the ferroelectric capacitor is connected to the word line through its electrode B1). For example, the electrode B1 of the ferroelectric capacitor in one ferroelectric capacitor set is connected to the word line WL1, the electrode B1 of the ferroelectric capacitor in another ferroelectric capacitor set is connected to the word line WL2, the electrode B1 of the ferroelectric capacitor in another ferroelectric capacitor set is connected to the word line WL3, and the electrode B1 of the ferroelectric capacitor in another ferroelectric capacitor set is connected to the word line WL4. Word line WL1 , word line WL2 , word line WL3 and word line WL4 are all different word lines.

In addition, it should be noted that in this embodiment of the application, "shared" means "same", and "A1 and A1 share B" means "B of A1 is the same as B of A2".

Exemplarily, different word lines correspond to different metal plates, and different metal plates are connected to different word line driving circuits. The word line can be connected to the corresponding metal plate, and then connected to the corresponding word line driving circuit through the metal plate. Therefore, the corresponding word line can be controlled by the word line driving circuit. In one example, the metal plate may be disposed above the corresponding word line, whereby the word line may be connected upwardly to the corresponding metal plate.

Exemplarily, before preparing the pre-charged transistor, a plurality of metal plates E1 may be deposited on the substrate. The plurality of metal plates E1 are all parallel to the upper surface of the substrate, and the plurality of metal plates E1 are parallel to each other and insulated from each other. The plurality of metal plates E1 are respectively used as different bit lines. For example, the bit line BL1 , the bit line BL2 , and the bit line BL3 shown in FIG. 10 . Wherein, the electrode F2 of the pre-charging transistor and the electrode F2 of the sensing transistor can be connected to the corresponding metal plate E1 through wires. Wherein, the metal plate E1 can be connected to the BL driving circuit on the circuit board through wires. Wherein, the circuit board is a circuit board for carrying a substrate.

An insulating layer is deposited on the plurality of metal plates E1, and the plurality of metal plates E2 is deposited on the insulating layer. The upper surfaces of the plurality of metal plates E2 are evenly parallel to the substrate, and the plurality of metal plates E2 are parallel to each other and insulated from each other. Exemplarily, the metal plate E1 and the metal plate E2 are perpendicular to each other. The plurality of metal plates E2 are respectively used as different control lines. For example, the bit line CL1 , the bit line CL2 , and the bit line CL3 shown in FIG. 10 . Wherein, the metal plate E2 can be connected to the CL driving circuit on the circuit board through wires.

Afterwards, a metal electrode used as the gate of the pre-charge transistor can be deposited on the metal plate E2, thereby preparing a memory module according to the embodiment of FIG. 4B. No more details here.

Continuing to refer to FIG. 10 , the electrodes B2 of ferroelectric capacitors with the same word line are different. Moreover, the control line and the bit line corresponding to the same ferroelectric capacitance of the word line are not the same at the same time. That is, some ferroelectric capacitors with the same word line have the same control line, but these ferroelectric capacitors with the same control line have different bit lines. For example, as shown in FIG. 10 , among the ferroelectric capacitors sharing the word line WL1 , three ferroelectric capacitors share the control line CL1 , and the three ferroelectric capacitors are respectively connected to the bit lines BL1 , BL2 , and BL3 . For another example, among the ferroelectric capacitors sharing the word line WL1 , there are three ferroelectric capacitors sharing the control line CL2 , and the three ferroelectric capacitors are respectively connected to the bit lines BL1 , BL2 , and BL3 . For another example, among the ferroelectric capacitors sharing the word line WL1 , there are three ferroelectric capacitors sharing the control line CL3 , and the three ferroelectric capacitors are respectively connected to the bit lines BL1 , BL2 , and BL3 . For another example, among the ferroelectric capacitors sharing the word line WL1 , there are three ferroelectric capacitors sharing the control line CL4 , and the three ferroelectric capacitors are respectively connected to the bit lines BL1 , BL2 , and BL3 .

In addition, as shown in FIG. 10 , the bit lines of ferroelectric capacitors having the same control lines are the same. For example, the ferroelectric capacitors sharing the bit line BL1 also share the source line SL1, the ferroelectric capacitors sharing the bit line BL2 also share the source line SL2, and the ferroelectric capacitors sharing the source line BL3 also share the source line SL3.

From the above description, it can be seen that in the memory array, different ferroelectric capacitor electrodes B1, B2, control lines, and bit lines are not the same at the same time. Therefore, when performing read and write operations, different ferroelectric capacitors can be distinguished or selected through the electrodes B1 , electrode B2 , control lines, and bit lines, and the selected ferroelectric capacitors can be operated.

Next, the working principle of the ferroelectric capacitor is illustrated by combining the schematic diagram of the circuit connection mode of the storage array and the operation truth table.

FIG. 11 shows a partial circuit connection of the memory array. Among them, sharing the same word line (word line WL1 or word line WL2 or word line WL3 or word line WL4), corresponding to the control line CL1 and control line CL2, and corresponding to the bit lines BL1 and BL2 through different pre-charge transistors. Sharing the same word line corresponds to source line SL1 and source line SL2 through different pre-charge transistors. The electrodes B2 sharing the same word line are different.

Hereinafter, the ferroelectric capacitor C1 , the ferroelectric capacitor C2 , the ferroelectric capacitor C3 and the ferroelectric capacitor C4 sharing the word line WL1 are taken as an example.

The ferroelectric capacitor C1 corresponds to the control line CL1 , the bit line BL2 and the source line SL2 .

The ferroelectric capacitor C2 corresponds to the control line CL1 , the bit line BL1 and the source line SL1 .

The ferroelectric capacitor C3 corresponds to the control line CL2 , the bit line BL1 and the source line SL1 .

The ferroelectric capacitor C4 corresponds to the control line CL2, the bit line BL2, and the source line SL2.

Next, with reference to FIG. 12 , taking the operation of the ferroelectric capacitor C1 as an example, the working principle of the ferroelectric capacitor is introduced. Wherein, the electrode F1 may specifically be a source, and the electrode F2 may specifically be a drain.

Figure 12 shows a possible truth table for the operation. By operating the truth table, binary data can be stored in the ferroelectric capacitor. details as follows.

The operation of writing 0 or writing 1 can be performed on the ferroelectric capacitor C1, that is, writing 0 or writing 1 into the ferroelectric capacitor C1. It can be set to write 0 to the ferroelectric capacitor C1. The voltage Vw can be applied to the word line WL1; the voltage Vdd can be applied to the control line CL1; the voltage V0 can be applied to the bit line BL2 first, and then the voltage Vw can be applied; the voltage V0 can be applied to the source line BL2 first, and then the voltage Vw can be applied; Thus, the crystal center atoms in the ferroelectric layer of the ferroelectric capacitor C1 can be in a polarization state, which represents zero.

Among them, the voltage Vdd may be referred to as the highest voltage. In one example, the voltage Vdd is 2.5V. The voltage Vw may be referred to as a write voltage. In one example, the voltage Vw is 2V. The voltage V0 is zero voltage, that is, the voltage V0 is 0V.

Wherein, as described above, when the ferroelectric capacitor C1 is written to 0, the electrode B2 is operated with the voltage V0 first and then the voltage Vw. In order to avoid this operation, it will affect other ferroelectric capacitors that share the electrode B2 with the ferroelectric capacitor C1. A voltage Vw/2 can be applied to the word line of the other ferroelectric capacitors that share the electrode B2 with the ferroelectric capacitor C1 (that is, the unsel WL corresponding to C1 in FIG. 12 ). Wherein, the voltage Vw/2 may be called a half-selected voltage, and its voltage is half of the voltage Vw. Wherein, "unsel" in Fig. 12 means unselected.

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1 . During the write 0 operation to the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 and the voltage applied to the control line CL1 on the ferroelectric capacitor C2, the voltage Vw/2 can be applied to the bit line BL1 (that is, the bit line corresponding to the ferroelectric capacitor C2), the voltage Vw/2 can be applied to the source line SL1 (that is, the source line corresponding to the ferroelectric capacitor C2), and the electrode B2 of the ferroelectric capacitor C2 (that is, the unsel electrode B2 corresponding to the ferroelectric capacitor C2 in FIG. 12 ) ) to apply a voltage Vw/2.

The ferroelectric capacitor C3 and the ferroelectric capacitor C1 share the word line WL1. During the operation of writing 0 to the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, a voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 can be applied to the bit line BL1 (ie, the bit line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 can be applied to the source line SL1 (ie, the source line corresponding to the ferroelectric capacitor C3), and a voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C3 (ie, in FIG. 12 ). The unsel electrode B2 corresponding to C3 applies a voltage Vw/2.

The ferroelectric capacitor C4 and the ferroelectric capacitor C1 share the word line WL1 , the bit line BL2 and the source line SL2 . During the operation of writing 0 to the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1, the voltage applied to the bit line BL2 and the voltage applied to the source line SL2 from affecting the ferroelectric capacitor C4, a voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C4), and a voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C2 (ie, the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in FIG. 12 ).

The above example introduces the specific operation mode of the ferroelectric capacitor C1 and the operation mode of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 when the operation of writing 0 is performed on the ferroelectric capacitor C1.

Next, an example will be introduced to describe the specific operation mode of the ferroelectric capacitor C1 and the operation mode of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 when the operation of writing 1 is performed on the ferroelectric capacitor C1.

Continuing to refer to FIG. 12 , the operation of writing 1 to the ferroelectric capacitor C1 can be performed. The voltage V0 can be applied to the word line WL1; the voltage Vdd can be applied to the control line CL1; the voltage V0 can be applied to the bit line BL2 first, and then the voltage Vw can be applied; the voltage V0 can be applied to the source line BL2 first, and then the voltage Vw can be applied; As a result, the crystal center atoms in the ferroelectric layer of the ferroelectric capacitor C1 can be in another polarization state, which represents 1.

Wherein, when performing a write 1 operation on the ferroelectric capacitor C1, the electrode B2 is first operated on the voltage V0 and then on the voltage Vw. In order to avoid the impact of this operation on other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1, a voltage Vw/2 can be applied to the word line of the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1 (that is, the unsel WL corresponding to C1 in FIG. 12 ).

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1 . During the write 1 operation on the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1 and the voltage applied to the control line CL1 from affecting the ferroelectric capacitor C2, a voltage Vw/2 can be applied to the bit line BL1 (that is, the bit line corresponding to the ferroelectric capacitor C2), a voltage Vw/2 can be applied to the source line SL1 (that is, the source line corresponding to the ferroelectric capacitor C2), and the electrode B2 of the ferroelectric capacitor C2 (that is, the unsel electrode B2 corresponding to the ferroelectric capacitor C2 in FIG. 12 ) can be applied. ) to apply a voltage Vw/2.

The ferroelectric capacitor C3 and the ferroelectric capacitor C1 share the word line WL1. During the write 1 operation to the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1 from affecting the ferroelectric capacitor C3, the voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C3), the voltage Vw/2 can be applied to the bit line BL1 (ie, the bit line corresponding to the ferroelectric capacitor C3), the voltage Vw/2 can be applied to the source line SL1 (ie, the source line corresponding to the ferroelectric capacitor C3), and the voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C3 (ie, in FIG. 12 ). The unsel electrode B2 corresponding to C3 applies a voltage Vw/2.

The ferroelectric capacitor C4 and the ferroelectric capacitor C1 share the word line WL1 , the bit line BL2 and the source line SL2 . During the write 1 operation on the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1, the voltage applied to the bit line BL2 and the voltage applied to the source line SL2 from affecting the ferroelectric capacitor C4, a voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C4), and a voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C2 (ie, the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in FIG. 12 ).

The above example introduces the specific operation mode of ferroelectric capacitor C1 when writing 1 to ferroelectric capacitor C1, and the operation mode of ferroelectric capacitors that may be affected by ferroelectric capacitor C1.

After a write operation is performed on the ferroelectric capacitor, a standby precharge operation is usually performed on the ferroelectric capacitor, so that the ferroelectric capacitor is in a standby state. Wherein, the standby state is a state of waiting for operation, and in the standby state, the influence of the operating voltage of other ferroelectric capacitors is also prevented. Therefore, a standby prediction operation is performed to apply a specific voltage to the ferroelectric capacitor to prevent the influence of the operating voltage of other ferroelectric capacitors.

Next, the example introduces the standby pre-charging operation on the ferroelectric capacitor C1, and the operation of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 during the standby pre-charging operation on the ferroelectric capacitor C1.

Continuing to refer to FIG. 12 , a standby precharge operation can be performed on the ferroelectric capacitor C1 . The voltage Vw/2 can be applied to the word line WL1; the voltage Vdd can be applied to the control line CL1; the voltage Vw/2 can be applied to the bit line BL2; the voltage Vw/2 can be applied to the source line BL2; and the voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C1. Thus, the standby precharging operation for the ferroelectric capacitor C1 is completed.

Wherein, when performing standby precharging operation on ferroelectric capacitor C1, voltage Vw/2 is applied to electrode B2. In order to avoid the impact of this operation on other ferroelectric capacitors sharing electrode B2 with ferroelectric capacitor C1, voltage Vw/2 can be applied to word lines of other ferroelectric capacitors sharing electrode B2 with ferroelectric capacitor C1 (ie unsel WL corresponding to C1 in FIG. 12 ).

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1 . During the standby precharge operation on the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1 and the voltage applied to the control line CL1 from affecting the ferroelectric capacitor C2, a voltage Vw/2 can be applied to the bit line BL1 (that is, the bit line corresponding to the ferroelectric capacitor C2), a voltage Vw/2 can be applied to the source line SL1 (that is, the source line corresponding to the ferroelectric capacitor C2), and a voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C2 (that is, the unsel electrode corresponding to the ferroelectric capacitor C2 in FIG. 12 ). B2) The voltage Vw/2 is applied.

The ferroelectric capacitor C3 and the ferroelectric capacitor C1 share the word line WL1. During the standby precharging operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, a voltage V0 can be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 can be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 can be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C3), and a voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C3 (i.e., FIG. 1 The unsel electrode B2 corresponding to C3 in 2) applies a voltage Vw/2.

The ferroelectric capacitor C4 and the ferroelectric capacitor C1 share the word line WL1 , the bit line BL2 and the source line SL2 . During the standby precharging operation on the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1, the voltage applied to the bit line BL2 and the voltage applied to the source line SL2 from affecting the ferroelectric capacitor C4, a voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C4), and a voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C2 (ie, the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in FIG. 12 ).

The above example introduces the specific operation mode of the ferroelectric capacitor C1 and the operation mode of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 when the write 1 operation is performed on the ferroelectric capacitor C1.

Before the read operation of the ferroelectric capacitor, the ferroelectric capacitor is usually read and precharged, so that the voltage of the electrode B2 of the ferroelectric capacitor is pulled up to Vw, and the voltage of WL1 (i.e., electrode B1) is Vw/2, so that in the subsequent read operation, the voltage of WL1 is pulled down to V0, so that the voltage difference between the two ends of the ferroelectric capacitor can reach Vw, so that the polarization state of the iron atom in the crystal center can be changed to realize the reading of the signal. Wherein, the process of signal reading will be introduced below, and will not be repeated here.

Next, the example introduces the read precharge operation on the ferroelectric capacitor C1, and the operation on the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 during the standby precharge operation on the ferroelectric capacitor C1.

Continuing to refer to FIG. 12 , the read precharge operation can be performed on the ferroelectric capacitor C1 . The voltage Vw/2 can be applied to the word line WL1; the voltage Vdd can be applied to the control line CL1; the voltage Vw can be applied to the bit line BL2; the voltage Vw can be applied to the source line BL2; and the voltage Vw can be applied to the electrode B2 of the ferroelectric capacitor C1. Thus, the read precharge operation on the ferroelectric capacitor C1 is completed.

Wherein, when the ferroelectric capacitor C1 is read and precharged, the voltage Vw is applied to the electrode B2. In order to avoid the impact of this operation on other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1, the voltage Vw/2 can be applied to the word line of the other ferroelectric capacitors that share the electrode B2 with the ferroelectric capacitor C1 (that is, unsel WL corresponding to C1 in FIG. 12 ).

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1 . During the read precharge operation on the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1 and the voltage applied to the control line CL1 from affecting the ferroelectric capacitor C2, a voltage Vw/2 can be applied to the bit line BL1 (ie, the bit line corresponding to the ferroelectric capacitor C2), a voltage Vw/2 can be applied to the source line SL1 (ie, the source line corresponding to the ferroelectric capacitor C2), and the electrode B2 of the ferroelectric capacitor C2 (ie, the unsel electrode B corresponding to the ferroelectric capacitor C2 in FIG. 12 ) can be applied. 2) Apply voltage Vw/2.

The ferroelectric capacitor C3 and the ferroelectric capacitor C1 share the word line WL1. During the read precharge operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, the voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C3), the voltage Vw/2 can be applied to the bit line BL1 (ie, the bit line corresponding to the ferroelectric capacitor C3), the voltage Vw/2 can be applied to the source line SL1 (ie, the source line corresponding to the ferroelectric capacitor C3), and the voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C3 (ie, FIG. 12 ). The unsel electrode B2 corresponding to C3 in the center applies a voltage Vw/2.

The ferroelectric capacitor C4 and the ferroelectric capacitor C1 share the word line WL1 , the bit line BL2 and the source line SL2 . During the read precharge operation on the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1, the voltage applied to the bit line BL2 and the voltage applied to the source line SL2 from affecting the ferroelectric capacitor C4, the voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C4), and the voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C2 (ie, the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in FIG. 12 ).

The above example introduces the specific operation mode of the ferroelectric capacitor C1 and the operation mode of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 when the read precharge operation is performed on the ferroelectric capacitor C1.

Next, the example introduces the specific operation mode of the read operation on the ferroelectric capacitor C1 (that is, the operation of reading 0/1 or the operation of reading the signal), and the operation mode of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1.

When performing a read operation on the ferroelectric capacitor C1, a known voltage may be applied to the ferroelectric capacitor C1. The known voltage can promote the iron atom in the center of the crystal to reach a polarization state. For example, when the known voltage is set to promote the iron atom in the center of the crystal to reach the polarization state D1, and the iron atom in the center of the crystal is in the polarization state D1, the bit value recorded by the ferroelectric capacitor is 1. Wherein, if the polarization state of the iron atom in the crystal center of the ferroelectric electric field C1 is also the polarization state D1. Then, after the voltage is applied to the ferroelectric capacitor C1, the bit value recorded by the ferroelectric capacitor C1 can be judged by detecting whether the polarization state of the iron atoms in the center of the crystal changes. Wherein, when the polarization state of the iron atom in the center of the crystal changes, the potential of the electrode B2 will change. Sensing transistors can sense potential changes and convert the potential changes into currents. This current can be detected by a sense amplifier (SA). Therefore, when the current is not detected by the sense amplifier, it can be known that the polarization state of the iron atom in the center of the crystal has not changed. When the sense amplifier detects this current, it can be known that the polarization state of the iron atom in the center of the crystal has changed. Thus, the bit value recorded by the ferroelectric capacitor C1 is determined.

Continuing to refer to Fig. 12, the known voltage applied by the read operation can be set as the voltage to promote the iron atom in the center of the crystal to reach the polarization state D1, and when the iron atom in the center of the crystal is in the polarization state D1, the ferroelectric capacitor C1 records 1. The specific operation method of the read operation is to apply the voltage V0 to the word line WL1; apply the voltage V0 to the control line CL1; apply the voltage Vw to the bit line BL2; apply the voltage Vw/2 to the source line BL2; first apply the voltage Vpre to the electrode B2 of the ferroelectric capacitor C1, and then apply the voltage Vw. If the sense amplifier does not detect the corresponding spike, then it can be obtained that the bit value recorded by the ferroelectric capacitor C1 is 1. If the sense amplifier detects the corresponding spike, then the bit value recorded by the ferroelectric capacitor C1 can be obtained as 0.

Wherein, the voltage Vpre may also be referred to as a precharge voltage. In one example, the voltage Vpre is 1.6V.

Wherein, when the ferroelectric capacitor C1 is read, the voltage Vw is applied to the electrode B2. In order to avoid this operation from affecting other ferroelectric capacitors that share the electrode B2 with the ferroelectric capacitor C1, a voltage Vw/2 can be applied to the word line of the other ferroelectric capacitors that share the electrode B2 with the ferroelectric capacitor C1 (that is, the unsel WL corresponding to C1 in FIG. 12 ).

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1 . During the read operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 and the voltage applied to the control line CL1 on the ferroelectric capacitor C2, a voltage Vw/2 can be applied to the bit line BL1 (ie, the bit line corresponding to the ferroelectric capacitor C2), a voltage Vw/2 can be applied to the source line SL1 (ie, the source line corresponding to the ferroelectric capacitor C2), and the electrode B2 of the ferroelectric capacitor C2 (ie, the unsel electrode B2 corresponding to the ferroelectric capacitor C2 in FIG. 12 ) A voltage Vw/2 is applied.

The ferroelectric capacitor C3 and the ferroelectric capacitor C1 share the word line WL1. During the read operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, a voltage V0 can be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 can be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 can be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C3), and a voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C3 (i.e. C in FIG. 12 ). 3 corresponding to the unsel electrode B2) to apply a voltage Vw/2.

The ferroelectric capacitor C4 and the ferroelectric capacitor C1 share the word line WL1 , the bit line BL2 and the source line SL2 . During the read operation on the ferroelectric capacitor C1, in order to avoid the voltage applied to the word line WL1, the voltage applied to the bit line BL2 and the voltage applied to the source line SL2 from affecting the ferroelectric capacitor C4, the voltage V0 can be applied to the control line CL2 (ie, the control line corresponding to the ferroelectric capacitor C4), and the voltage Vw/2 can be applied to the electrode B2 of the ferroelectric capacitor C2 (ie, the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in FIG. 12 ).

As mentioned above, the read operation may cause the polarization state of the iron atom in the crystal center of the ferroelectric capacitor C1 to change. For example, when the voltage applied by the read operation is the voltage applied by the write 1 operation, and the bit value recorded by the ferroelectric capacitor C1 is 0, the read operation causes the polarization state of the iron atom in the crystal center of the ferroelectric capacitor C1 to change. That is to say, the read operation causes the information recorded by the ferroelectric capacitor C1 to change. Therefore, after the read operation, a write-back operation is required. Wherein, the voltage of the write-back operation is another known voltage. Wherein, when the known voltage of the read operation is the voltage of the write 1 operation, then the voltage of the write back operation is the voltage of the write 0 operation. When the known voltage of the read operation is the voltage of the write 0 operation, then the voltage of the write back operation is the voltage of the write 1 operation.

Continuing to refer to FIG. 12 , the known voltage of the write-back operation can be set as the voltage of the write-0 operation, that is, the write-back operation is an operation of writing back 0. Wherein, the operation of writing back 0 is the operation of writing 0. For details, reference may be made to the introduction of the operation of writing 0 above, and details will not be repeated here.

After the operation of writing back 0 is completed, the standby precharge operation can be performed on the ferroelectric capacitor C1. For details, please refer to the introduction of standby precharge operation above, and will not repeat them here.

In some embodiments, a standby operation can also be performed on the ferroelectric capacitor C1. Wherein, the standby operation is an operation that puts the ferroelectric capacitor C1 in a standby state. The ferroelectric capacitor C1 being in the standby state refers to not performing read and write operations, standby precharge operations, and read precharge operations on the ferroelectric capacitors. Wherein, when the ferroelectric capacitor C1 is in the standby state, other ferroelectric capacitors sharing the word line WL1 with the ferroelectric capacitor C1 are also in the standby state.

Next, with reference to FIG. 12 , the voltage applied for the standby operation will be described.

Taking the ferroelectric capacitor C1 as an example, a voltage Vw/2 can be applied to the word line (ie WL1), bit line (BL2), source line (ie SL2), and electrode B2 of the ferroelectric capacitor C1, and a voltage V0 can be applied to the control line (ie CL1) of the ferroelectric capacitor C1 to perform standby operation.

Wherein, during the standby operation of the ferroelectric capacitor C1, the voltage Vw/2 can be applied to the word line of other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1 (that is, the unsel WL corresponding to C1 in FIG. 12 ).

During the standby operation on the ferroelectric capacitor C1 , the operations on the ferroelectric capacitor C2 , the ferroelectric capacitor C3 , and the ferroelectric capacitor C4 are the same as those on the ferroelectric capacitor C1 , and will not be repeated here.

The ferroelectric capacitor C1 is taken as an example above to describe the operation of a ferroelectric capacitor in the memory module array. Operations of other ferroelectric capacitors in the memory module array can be implemented with reference to the ferroelectric capacitor C1 , which will not be repeated here.

The vertical structure transistor and at least the ferroelectric capacitor provided by the embodiment of the present application can be stacked in the vertical direction, thereby saving the integration area of the substrate and increasing the storage density and capacity of the ferroelectric memory.

The application of the vertical structure transistor provided by the embodiment of the present application in the preparation of the ferroelectric memory is introduced above. It does not limit the application of vertical structure crystals in other types of memory.

In some embodiments, the transistor T1 , the transistor T2 or the transistor T3 can be used as a transistor in a DRAM memory, so as to realize three-dimensional stacking of storage components in the DRAM memory and increase the storage density of the DRAM memory.

In some embodiments, the transistor T1, the transistor T2, or the transistor T3 can be used as a transistor in a phase change memory (phase change memory, PCM) memory, and the storage density of the phase change memory is increased by three-dimensional stacking of storage components of the phase change memory.

In some embodiments, the transistor T1, the transistor T2 or the transistor T3 can be used as a transistor in a resistive variable memory (ReRAM) memory, so as to realize three-dimensional stacking of the storage components of the resistive variable memory, and increase the storage density of the storage components of the resistive variable memory.

In some embodiments, the transistor T1, the transistor T2, or the transistor T3 can be used as a transistor in a magnetic random access memory (MRAM) memory, so as to realize three-dimensional stacking of the storage components of the magnetic memory and increase the storage density of the storage components of the magnetic memory.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

It can be understood that, in the description of the embodiments of the present application, words such as "exemplary", "for example" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application shall not be construed as being more preferred or more advantageous than other embodiments or designs. Rather, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific manner.

In the description of the embodiments of the present application, the term "and/or" is only a relationship describing the relationship between related objects, which means that there may be three kinds of relationships, for example, A and/or B can mean: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "plurality" means two or more. For example, multiple systems refer to two or more systems, and multiple terminals refer to two or more terminals.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically stated otherwise.

It can be understood that the above embodiments are only used to illustrate the technical solutions of the present application and limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the various embodiments of the application.

The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention, and all should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A kind of ferroelectric memory, is characterized in that, comprises:

Substrate;

word line WL, source line SL, bit line BL and control line CL;

A first ferroelectric capacitor, a first transistor, and a second transistor stacked in a vertical direction; wherein,

The first ferroelectric capacitor includes a first electrode and a second electrode; wherein the first electrode is connected to the word line, and the second electrode is exposed at a lower end and/or an upper end of the first ferroelectric capacitor;

The first pole of the first transistor is connected to the source line, the second pole is connected to the bit line, and the gate is in contact with the second electrode; wherein, the channel layer of the first transistor is arranged in a vertical direction, and the gate of the first transistor forms an upper end and/or a lower end of the first transistor;

The gate of the second transistor is connected to the control line, the second pole is connected to the bit line, and the first pole is in contact with the second electrode or the gate of the first transistor; wherein, the channel layer of the second transistor is arranged along the vertical direction, and the first pole of the second transistor forms an upper end or a lower end of the second transistor;

Wherein, the vertical direction is perpendicular to the surface of the substrate, the upper end is an end away from the substrate, and the lower end is an end close to the substrate; both the first transistor and the second transistor are manufactured by post-processing techniques.
The ferroelectric memory according to claim 1, wherein the second electrode is exposed at the lower end of the first ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor; wherein, the first ferroelectric capacitor is located above the first transistor, and the second transistor is located below the first transistor, the upper portion is a side away from the substrate, and the lower portion is a side close to the substrate.
The ferroelectric memory according to claim 2, wherein the first transistor comprises:

a first channel layer arranged along the vertical direction;

a first gate oxide layer surrounded by the first channel layer;

a first gate that penetrates through the first gate oxide layer and protrudes from the upper end and the lower end of the first gate oxide layer;

surrounding the first pole and the second pole of the first channel layer.
The ferroelectric memory according to claim 3, wherein the second transistor comprises:

a second channel layer arranged along the vertical direction;

a second gate oxide layer surrounded by the second channel layer;

a second gate, a part of the second gate is surrounded by the second gate oxide layer, and another part protrudes from the lower end of the second gate oxide layer;

a first electrode located at the upper end of the second channel layer and insulated from the second gate;

Surrounding the second pole of the second channel layer.
The ferroelectric memory according to claim 3, wherein the second transistor comprises:

a third channel layer arranged along the vertical direction;

a first pole located at the upper end of the third channel layer;

a second pole located at the lower end of the third channel layer;

A third gate surrounding the third channel layer, wherein there is a third gate oxide layer between the third gate and the third channel layer.
The ferroelectric memory according to claim 1, wherein the second electrode is exposed at the upper end and the lower end of the first ferroelectric capacitor, the gate of the first transistor forms the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor; wherein the first transistor is located above the first ferroelectric capacitor, and the second transistor is located below the first ferroelectric capacitor, the upper portion is a side away from the substrate, and the lower portion is a side close to the substrate.
The ferroelectric memory according to claim 6, wherein both the first transistor and the second transistor adopt a first structure;

The first structure includes:

a second channel layer arranged along the vertical direction;

a second gate oxide layer surrounded by the second channel layer;

a second gate, a part of the second gate is surrounded by the second gate oxide layer, and another part protrudes from the lower end of the second gate oxide layer;

a first electrode located at the upper end of the second channel layer and insulated from the second gate;

Surrounding the second pole of the second channel layer.
The ferroelectric memory according to claim 6, characterized in that,

The first transistor includes:

a second channel layer arranged along the vertical direction;

a second gate oxide layer surrounded by the second channel layer;

a second gate, a part of the second gate is surrounded by the second gate oxide layer, and another part protrudes from the lower end of the second gate oxide layer;

a first electrode located at the upper end of the second channel layer and insulated from the second gate;

a second pole surrounding the second channel layer;

The second transistor includes:

a third channel layer arranged along the vertical direction;

a first pole located at the upper end of the third channel layer;

a second pole located at the lower end of the third channel layer;

A third gate surrounding the third channel layer, wherein there is a third gate oxide layer between the third gate and the third channel layer.
The ferroelectric memory according to claim 1, wherein the second electrode is exposed at the upper end of the first ferroelectric capacitor, the gate of the first transistor forms the upper end and the lower end of the first transistor, and the first electrode of the second transistor forms the lower end of the second transistor; wherein the first transistor is located above the first ferroelectric capacitor, the second transistor is located above the first transistor, and the upper portion is a side away from the substrate.
The ferroelectric memory according to claim 9, characterized in that,

The first transistor includes:

a first channel layer arranged along the vertical direction;

a first gate oxide layer surrounded by the first channel layer;

a first gate that penetrates through the first gate oxide layer and protrudes from the upper end and the lower end of the first gate oxide layer;

surrounding the first pole and the second pole of the first channel layer;

The second transistor includes:

a third channel layer arranged along the vertical direction;

a second pole located at the upper end of the third channel layer;

a first pole located at the lower end of the third channel layer;

A third gate surrounding the third channel layer, wherein there is a third gate oxide layer between the third gate and the third channel layer.
The ferroelectric memory according to any one of claims 1-10, wherein the ferroelectric memory comprises a plurality of word lines; the first ferroelectric capacitor comprises a plurality of ferroelectric capacitors stacked along the vertical direction, wherein the first electrodes of different ferroelectric capacitors in the plurality of ferroelectric capacitors are connected to different word lines in the plurality of word lines, and the plurality of ferroelectric capacitors share the second electrode.
The ferroelectric memory according to claim 11, wherein the plurality of ferroelectric capacitors comprise:

a cylindrical electrode extending in the vertical direction, the cylindrical electrode serving as the second electrode;

a ferroelectric layer surrounding the cylindrical electrode;

A plurality of electrode layers surrounding the ferroelectric layer, wherein two adjacent electrode layers are separated by an insulating material, and different electrode layers in the plurality of electrode layers are used as first electrodes of different ferroelectric capacitors in the plurality of ferroelectric capacitors.
A transistor, characterized in that it comprises:

a channel layer arranged in a vertical direction;

a gate oxide layer surrounded by the channel layer;

a gate, a part of the gate is surrounded by the gate oxide layer, and another part protrudes from the lower end of the gate oxide layer;

a first pole located at the upper end of the channel layer, the first pole is insulated from the gate;

a second pole surrounding the channel layer and having a gap between the first pole and the first pole;

Wherein, the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is an end far away from the substrate, and the lower end is an end close to the substrate.
The transistor according to claim 13, wherein the channel layer is made of N-type lightly doped semiconductor material, the first electrode includes a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of N-type heavily doped semiconductor material, and the N-type heavily doped region is in contact with the channel layer.
A transistor, characterized in that it comprises:

a channel layer arranged vertically;

a gate oxide layer surrounded by the channel layer;

a gate penetrating through the gate oxide layer and protruding from the upper end and the lower end of the gate oxide layer;

Surrounding the first pole and the second pole of the channel layer, there is a space between the first pole and the second pole;

Wherein, the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is an end far away from the substrate, and the lower end is an end close to the substrate.
The transistor according to claim 15, wherein the channel layer is made of N-type lightly doped semiconductor material, and the first electrode includes a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of N-type heavily doped semiconductor material, and the N-type heavily doped region is in contact with the channel layer.
A transistor, characterized in that it comprises:

A channel layer arranged along a vertical direction; wherein, the inside of the channel layer is filled with an insulator, and the vertical direction is perpendicular to the surface of the substrate where the transistor is located;

a third pole located at the upper end of the channel layer;

a fourth pole located at the lower end of the channel layer;

A gate surrounding the channel layer, wherein there is a gate oxide layer between the gate and the channel layer, there is a space between the gate and the third electrode, and there is a space between the gate and the fourth electrode; wherein the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is an end away from the substrate, and the lower end is an end close to the substrate;

The third pole is used as the first pole of the transistor, and the fourth pole is used as the second pole of the transistor; or, the third pole is used as the second pole of the transistor, and the fourth pole is used as the first pole of the transistor; or.
The transistor according to claim 17, wherein the channel layer is made of N-type lightly doped semiconductor material, the third pole and/or the fourth pole includes a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of N-type heavily doped semiconductor material, and the N-type heavily doped region is in contact with the channel layer.