CN116803232A

CN116803232A - Ferroelectric memory and vertical structure transistor

Info

Publication number: CN116803232A
Application number: CN202280003570.9A
Authority: CN
Inventors: 林琪; 范人士; 刘晓真; 赵思宇; 丁士成; 方亦陈; 卜思童
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-01-18
Filing date: 2022-01-18
Publication date: 2023-09-22
Also published as: WO2023137582A1

Abstract

The present application provides a ferroelectric memory comprising: a substrate; word lines, source lines, bit lines, and control lines; a first ferroelectric capacitor, a first transistor, and a second transistor stacked in a vertical direction; the first ferroelectric capacitor comprises a first electrode and a second electrode; the second electrode is exposed at the lower end and/or the upper end of the first ferroelectric capacitor; a first electrode of the first transistor is connected with the source line, a second electrode is connected with the bit line, and a grid electrode is contacted with the second electrode; the channel layer of the first transistor is arranged along the vertical direction, and the grid electrode of the first transistor forms the upper end and/or the lower end of the first transistor; the grid electrode of the second transistor is connected with the control line, the second electrode is connected with the bit line, and the first electrode is contacted with the second electrode or the grid electrode of the first transistor; the channel layer of the second transistor is disposed in a vertical direction, and the first electrode of the second transistor forms an upper end or a lower end of the second transistor. The ferroelectric memory has a high memory density.

Description

Ferroelectric memory and vertical structure transistor

Technical Field

The application relates to the technical field of semiconductors, in particular to a ferroelectric memory and a transistor with a vertical structure.

Background

The development of information technology has put demands on low-latency and high-capacity memories. Wherein low latency contributes to an increase in data processing speed. The large capacity contributes to an increase in storage density and a saving in memory manufacturing cost.

Currently, the mainstream memories include static random-access memory (SRAM), dynamic random-access memory (dynamic random access memory, DRAM), flash memory (flash), hard disk (hard disk), and the like. These memories have small or high delay, and it is difficult to satisfy both low delay and large capacity.

The ferroelectric memory is a novel memory and has the characteristics of high read-write speed, non-volatility and the like. The memory cell in the conventional ferroelectric memory adopts the structure shown in fig. 1A and 1B or the structure shown in fig. 2. Wherein the ferroelectric capacitor is integrated at the source of the transistor (as shown in fig. 1A and 1B) or at the gate of the transistor (as shown in fig. 2). In both structures, the transistor is a conventional planar transistor with its source, drain and gate arranged horizontally, all occupying the integrated area of the substrate surface, resulting in a single ferroelectric memory cell occupying the substrate The area is large. As shown in fig. 3, the integrated area of a single ferroelectric memory cell employing the structure shown in fig. 1B or the structure shown in fig. 2 is at least 8F ² Wherein F is the minimum feature size. In this way, fewer memory cells can be integrated on the substrate and the memory density of ferroelectric memory is lower.

In addition, if the ferroelectric memory cell shown in fig. 1B or fig. 2 is stacked in a direction perpendicular to the substrate. A large number of masks are required per layer, which leads to a dramatic increase in the cost of ferroelectric memories.

Disclosure of Invention

The embodiment of the application provides a ferroelectric memory and a transistor with a vertical structure, in particular to a memory with higher density.

In a first aspect, there is provided a ferroelectric memory comprising: a substrate; word line WL, source line SL, bit line and control line CL; a first ferroelectric capacitor, a first transistor, and a second transistor stacked in a vertical direction; wherein the first ferroelectric capacitor comprises a first electrode and a second electrode; wherein the first electrode is connected with the word line WL, and the second electrode is exposed at the lower end and/or the upper end of the first ferroelectric capacitor; a first electrode of the first transistor is connected with the source line, a second electrode is connected with the bit line, and a grid electrode is contacted with the second electrode; the channel layer of the first transistor is arranged along the vertical direction, and the grid electrode of the first transistor forms the upper end and/or the lower end of the first transistor; the grid electrode of the second transistor is connected with the control line CL, the second electrode is connected with the bit line, and the first electrode is contacted with the second electrode or the grid electrode of the first transistor; wherein the channel layer of the second transistor is arranged along the vertical direction, and the first electrode of the second transistor forms the upper end or the lower end of the second transistor; wherein the vertical direction is perpendicular to the surface of the substrate, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate; the first transistor and the second transistor are manufactured by adopting a back-end process.

The first pole of the transistor may be a source of the transistor, and the second pole of the transistor may be a drain of the transistor. Alternatively, the first pole of the transistor may be the drain of the transistor and the second pole of the transistor may be the source of the transistor. The transistors herein include a first transistor and a second transistor.

In the ferroelectric memory provided by the application, the second electrode of the ferroelectric capacitor is required to be connected with the gate of the first transistor and also is required to be connected with the first electrode of the second transistor. The second electrode is exposed at the upper end and/or the lower end of the ferroelectric capacitor, channel layers of the first transistor and the second transistor are vertically arranged (namely, the first transistor and the second transistor are in vertical structures), the grid electrode of the first transistor is arranged to form the upper end and/or the lower end of the first transistor, the first pole of the second transistor is arranged to form the upper end or the lower end of the second transistor, the second electrode of the ferroelectric capacitor is connected with the grid electrode of the first transistor, and the ferroelectric capacitor, the first transistor and the second transistor are stacked in the vertical direction while being connected with the first pole of the second transistor.

Specifically, when the second electrode is exposed at the lower end of the ferroelectric capacitor, the gate electrode of the first transistor forms the upper and lower ends of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor, the ferroelectric capacitor may be located above the first transistor, the second electrode may be in contact with the upper end (i.e., gate electrode) of the first transistor (i.e., the second electrode and the gate electrode of the first transistor may be connected by being in contact with each other), and the second transistor may be located below the first transistor, such that the upper end (i.e., first electrode) of the second transistor may be in contact with the lower end (i.e., gate electrode) of the first transistor, and thus the first electrode of the second transistor may be connected to the second electrode through the gate electrode of the first transistor.

When the second electrode is exposed at the upper end and the lower end of the ferroelectric capacitor, the gate electrode of the first transistor forms the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor, the first transistor is located above the ferroelectric capacitor, so that the lower end of the first transistor (i.e., the gate electrode) is contacted with the second electrode exposed at the upper end of the ferroelectric capacitor (i.e., the second electrode and the gate electrode of the first transistor are contacted with each other to realize connection), and the second transistor is located below the ferroelectric capacitor to realize the contact between the upper end of the second transistor (i.e., the first electrode) and the second electrode exposed at the lower end of the ferroelectric capacitor (i.e., the second electrode and the first electrode of the second transistor are contacted with each other to realize connection).

When the second electrode is exposed at the upper end of the ferroelectric capacitor, the gate electrode of the first transistor forms the upper end and the lower end of the first transistor, and the first electrode of the second transistor forms the lower end of the second transistor, the first transistor is positioned above the ferroelectric capacitor, contact between the lower end (i.e., gate electrode) of the first transistor and the second electrode exposed at the upper end of the ferroelectric capacitor is achieved (i.e., the second electrode and the gate electrode of the first transistor are connected by being in contact with each other), and the second transistor is positioned above the first transistor, so that the lower end (i.e., the first electrode) of the second transistor can contact the upper end (i.e., gate electrode) of the first transistor, and thus the first electrode of the second transistor can be connected to the second electrode through the gate electrode of the first transistor.

Therefore, the ferroelectric capacitor, the first transistor and the second transistor can be stacked in the vertical direction, the first transistor and the second transistor are of vertical structures, and the components of the transistors can be stacked in the vertical direction, so that the substrate integration area occupied by the components of the transistors is reduced, more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is improved.

And the first transistor and the second transistor are manufactured by adopting a back-end process, so that the dependence on the substrate is low, and the requirement of the ferroelectric memory on the substrate can be reduced.

In one possible embodiment, the second electrode is exposed at a lower end of the first ferroelectric capacitor, the gate of the first transistor forms an upper end and a lower end of the first transistor, and the first pole of the second transistor forms an upper end of the second transistor; the first ferroelectric capacitor is positioned above the first transistor, the second transistor is positioned below the first transistor, the upper part is a side far away from the substrate, and the lower part is a side close to the substrate.

In this embodiment, the second electrode is exposed at the lower end of the ferroelectric capacitor, the gate electrode of the first transistor forms the upper and lower ends of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor. Thus, the ferroelectric capacitor can be arranged above the first transistor, so that the second electrode is in contact with the gate electrode of the first transistor, and the connection between the second electrode and the first transistor is realized; the second transistor may be disposed under the first transistor such that the first electrode of the second transistor contacts the gate electrode of the first transistor, and thus the first electrode of the second transistor may be connected to the second electrode through the gate electrode of the first transistor. Thereby realizing a stack of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction.

In addition, in the embodiment, the ferroelectric capacitor is positioned above the second transistor and the first transistor, so that the ferroelectric capacitor can be prepared after the second transistor and the first transistor are prepared, and the ferroelectric property degradation caused by a high temperature stage in the transistor preparation process is avoided.

Further, in this embodiment, the first transistor and the second transistor are closer to the substrate, and thus, the leads of the bit line, the control line, and the source line can be directly pulled down to be connected to the corresponding driving circuits on the substrate, and can be set to be shorter lines, so that the path is shortened, and the time delay of the read-write operation of the ferroelectric capacitor can be reduced.

In one possible implementation, the first transistor includes: a first channel layer disposed in a vertical direction; a first gate oxide layer surrounded by the first channel layer; a first gate penetrating the first gate oxide layer and protruding from upper and lower ends of the first gate oxide layer; a first pole and a second pole surrounding the first channel layer, wherein a space exists between the first pole and the second pole.

This embodiment provides a first transistor. The channel layer of the first transistor is arranged in the vertical direction, so that two-dimensional electron gas for conducting the source electrode and the drain electrode can move in the vertical direction, dependence of the first transistor on the substrate can be reduced, and further requirements of the ferroelectric memory on the substrate are reduced.

And the grid electrode of the first transistor can penetrate through the grid oxide layer and protrude from the upper end and the lower end of the grid oxide layer to form the upper end and the lower end of the first transistor, so that the grid electrode of the first transistor can be in contact with the second electrode of the ferroelectric capacitor, and the grid electrode of the first transistor can be in contact with the first electrode of the second transistor, the stacking of the first transistor, the ferroelectric capacitor and the second transistor in the vertical direction is realized, more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is improved.

In one possible implementation, the second transistor includes: a second channel layer disposed in a vertical direction; a second gate oxide layer surrounded by the second channel layer; a second gate electrode, a part of which is surrounded by the second gate oxide layer and another part of which protrudes from the lower end of the second gate oxide layer; a first electrode positioned at the upper end of the second channel layer, and insulated between the first electrode and the second grid electrode; a second pole surrounding the second channel layer and spaced from the first pole.

The embodiment provides the second transistor, and the channel layer of the second transistor is arranged along the vertical direction, so that the two-dimensional electron gas for conducting the source electrode and the drain electrode can move along the vertical direction, the dependence of the second transistor on the substrate can be reduced, and the requirement of the ferroelectric memory on the substrate is further reduced.

And the first electrode of the second transistor is positioned at the upper end of the channel layer and can be contacted with the grid electrode of the first transistor above the second transistor, so that the second transistor, the ferroelectric capacitor and the first transistor can be stacked in the vertical direction by connecting the grid electrode of the first transistor to the second electrode, more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is improved.

In one possible implementation, the second transistor includes: a third channel layer disposed in a vertical direction; a first electrode located at an upper end of the third channel layer; a second channel layer located at a lower end of the first channel layer; and a third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer, a space is provided between the third gate and the first pole, and a space is provided between the third gate and the second pole.

In one possible embodiment, the second electrode is exposed at an upper end and a lower end of the first ferroelectric capacitor, the gate of the first transistor forms a lower end of the first transistor, and the first electrode of the second transistor forms an upper end of the second transistor; the first transistor is located above the first ferroelectric capacitor, the second transistor is located below the first ferroelectric capacitor, the upper side is a side far away from the substrate, and the lower side is a side close to the substrate.

In this embodiment, the second electrode is exposed at the upper and lower ends of the ferroelectric capacitor, the gate of the first transistor forms the lower end of the first transistor, and the first electrode of the second transistor forms the upper end of the second transistor. Therefore, the first transistor can be arranged above the ferroelectric capacitor, so that the grid electrode of the first transistor can be contacted with the second electrode exposed at the upper end of the ferroelectric capacitor, and the connection between the grid electrode of the first transistor and the second electrode is realized; the second transistor may be disposed under the ferroelectric capacitor such that the first electrode of the second transistor may be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, to thereby realize connection of the first electrode and the second electrode of the second transistor. Thereby realizing a stack of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction.

And the first transistor is arranged above the ferroelectric capacitor, and can be prepared after the ferroelectric capacitor is prepared, so that the first transistor does not need to bear the high temperature stage of the ferroelectric capacitor preparation process, and the performance degradation of the first transistor caused by high temperature is avoided.

Further, in this embodiment, the second transistor is closer to the substrate, and thus, both the lead of the bit line and the lead of the control line can be directly pulled down to be connected with the corresponding driving circuit on the substrate, and can be set to be a shorter line, so that the path is shortened, and the time delay of the read-write operation of the ferroelectric capacitor can be reduced.

In one possible implementation, the first transistor and the second transistor each employ a first structure; the first structure includes: a second channel layer disposed in a vertical direction; a second gate oxide layer surrounded by the second channel layer; a second gate electrode, a part of which is surrounded by the second gate oxide layer and another part of which protrudes from the lower end of the second gate oxide layer; a first electrode positioned at the upper end of the second channel layer, and insulated between the first electrode and the second grid electrode; a second pole surrounding the second channel layer and spaced from the first pole.

In this embodiment mode, the first transistor and the second transistor may have the same structure, and the difficulty of the ferroelectric memory manufacturing process may be reduced as a whole.

In addition, in the embodiment, the channel layers of the first transistor and the second transistor are arranged along the vertical direction, so that two-dimensional electron gas for conducting the source electrode and the drain electrode can move along the vertical direction, dependence of the first transistor and the second transistor on the substrate can be reduced, and further requirements of the ferroelectric memory on the substrate are reduced.

Further, the gate of the first transistor forms the lower end of the first transistor, so that the gate of the first transistor can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor, and connection between the gate of the first transistor and the second electrode is achieved. The first electrode of the second transistor forms an upper end of the second transistor such that the first electrode of the second transistor may be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, enabling connection of the first electrode and the second electrode of the second transistor. Therefore, the first transistor, the ferroelectric capacitor and the second transistor are stacked in the vertical direction, more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is improved.

In one possible implementation, the first transistor includes: a second channel layer disposed in a vertical direction; a second gate oxide layer surrounded by the second channel layer; a second gate electrode, a part of which is surrounded by the second gate oxide layer and another part of which protrudes from the lower end of the second gate oxide layer; a first electrode positioned at the upper end of the second channel layer, and insulated between the first electrode and the second grid electrode; a second pole surrounding the second channel layer and spaced apart from the first pole; the second transistor includes a third channel layer disposed in a vertical direction; a first electrode located at an upper end of the third channel layer; a second pole located at the lower end of the third channel layer; and a third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer, a space is provided between the third gate and the first pole, and a space is provided between the third gate and the second pole.

In the embodiment, the channel layers of the first transistor and the second transistor are arranged along the vertical direction, so that two-dimensional electron gas for conducting the source electrode and the drain electrode can move along the vertical direction, dependence of the first transistor and the second transistor on the substrate can be reduced, and further requirements of the ferroelectric memory on the substrate are reduced.

And the grid electrode of the first transistor forms the lower end of the first transistor, so that the grid electrode of the first transistor can be contacted with the second electrode exposed at the upper end of the ferroelectric capacitor, and the connection between the grid electrode of the first transistor and the second electrode is realized. The first electrode of the second transistor forms an upper end of the second transistor such that the first electrode of the second transistor may be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, enabling connection of the first electrode and the second electrode of the second transistor. Therefore, the first transistor, the ferroelectric capacitor and the second transistor are stacked in the vertical direction, more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is improved.

In one possible embodiment, the second electrode is exposed at an upper end of the first ferroelectric capacitor, the gate of the first transistor forms an upper end and a lower end of the first transistor, and the first pole of the second transistor forms a lower end of the second transistor; the first transistor is located above the first ferroelectric capacitor, and the second transistor is located above the first transistor, and the upper side is far away from the substrate.

In this embodiment, the second electrode is exposed at the upper end of the ferroelectric capacitor, the gate electrode of the first transistor forms the upper and lower ends of the first transistor, and the first electrode of the second transistor forms the lower end of the second transistor. Therefore, the first transistor can be arranged above the ferroelectric capacitor, so that the grid electrode of the first transistor can be contacted with the second electrode exposed at the upper end of the ferroelectric capacitor, and the connection between the grid electrode of the first transistor and the second electrode is realized; the second transistor may be disposed above the first transistor such that a first pole of the second transistor may be in contact with a gate of the first transistor, thereby causing the first pole of the second transistor to be connected to the second electrode through the gate of the first transistor. Thereby realizing a stack of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction.

In addition, in the embodiment, the second electrode is only exposed at the upper end of the ferroelectric capacitor, and is not required to be exposed at the lower end of the ferroelectric capacitor, so that the second electrode can be opened at the lower end of the second electrode when the ferroelectric capacitor is manufactured, the etching process of the lower end opening is avoided, the damage to the ferroelectric layer of the side wall is avoided, and further the ferroelectric property degradation caused by the damage is avoided.

In one possible implementation, the first transistor includes: a first channel layer disposed in a vertical direction; a first gate oxide layer surrounded by the first channel layer; a first gate penetrating the first gate oxide layer and protruding from upper and lower ends of the first gate oxide layer; a first pole and a second pole surrounding the first channel layer, a space being present between the first pole and the second pole; the second transistor includes: a third channel layer disposed in a vertical direction; a second pole located at the upper end of the third channel layer; a first electrode located at a lower end of the third channel layer; and a third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer, a space is provided between the third gate and the first pole, and a space is provided between the third gate and the second pole.

The grid electrode of the first transistor forms the lower end of the first transistor, so that the lower part of the grid electrode of the first transistor can be in contact with the second electrode exposed at the upper end of the ferroelectric capacitor, and the connection between the grid electrode of the first transistor and the second electrode is realized; the first electrode of the second transistor forms a lower end of the second transistor, and the gate of the first transistor also forms an upper end of the first transistor such that the gate of the first transistor may be in contact with the first electrode of the second transistor such that the first electrode of the second transistor may be connected to the second electrode through the gate of the first transistor. Therefore, the first transistor, the ferroelectric capacitor and the second transistor are stacked in the vertical direction, more ferroelectric capacitors and corresponding transistors can be integrated on the substrate, and the storage density of the ferroelectric memory is improved.

In one possible implementation, a ferroelectric memory includes a plurality of word lines; the first ferroelectric capacitor includes a plurality of ferroelectric capacitors stacked in a vertical direction, wherein first electrodes of different ones of the plurality of ferroelectric capacitors are connected to different ones of the plurality of word lines, and the plurality of ferroelectric capacitors share a second electrode.

In this embodiment, a plurality of ferroelectric capacitors can be stacked in the vertical direction, so that a plurality of ferroelectric capacitors can be disposed on the same substrate integration area, further reducing the integration area occupied by a single ferroelectric capacitor, and further improving the storage density of the ferroelectric memory.

Also, in this embodiment mode, the plurality of ferroelectric capacitors share the second electrode, and the second electrode is exposed from the upper end and/or the lower end of the ferroelectric capacitor, so that the plurality of ferroelectric capacitors can be stacked in the vertical direction with the first transistor, the second transistor. The specific stacking manner may be referred to above, and will not be described in detail herein.

In addition, the first electrodes of the different ferroelectric capacitors are connected to different word lines, so that the different ferroelectric capacitors can be distinguished and operated by the word lines, so that each ferroelectric capacitor can be independently operated for storing corresponding data.

In one possible implementation, the plurality of ferroelectric capacitors includes: a columnar electrode extending in the vertical direction, the columnar electrode serving as a second electrode; a ferroelectric layer surrounding the columnar electrode; a plurality of electrode layers surrounding the ferroelectric layer, wherein adjacent two electrode layers are separated by an insulating material, different ones of the plurality of electrode layers serving as first electrodes of different ones of the plurality of ferroelectric capacitors. In this embodiment, a columnar electrode extending in the vertical direction may be used as the second electrode of the plurality of ferroelectric capacitors, so that the second electrode may be exposed at the upper and/or lower ends of the ferroelectric capacitors to realize that the plurality of ferroelectric capacitors may be stacked in the vertical direction with the first and second transistors.

In addition, in the embodiment, the word lines connected with the first electrode of the ferroelectric capacitor can be led out from the periphery of the ferroelectric capacitor and respectively connected to the corresponding driving circuits, so that the driving capability of the first electrode is improved, and the driving time delay is reduced.

In a second aspect, there is provided a transistor comprising: a channel layer arranged in a vertical direction; a gate oxide layer surrounded by the channel layer; a gate electrode, a part of which is surrounded by the gate oxide layer and another part of which protrudes from the lower end of the gate oxide layer; a first electrode positioned at the upper end of the channel layer, and insulated between the first electrode and the grid electrode; a second pole surrounding the channel layer and spaced from the first pole; the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate. Wherein the first pole can be used as the source of the transistor and the second pole can be used as the drain of the transistor; alternatively, the first pole may be used as the drain of the transistor and the second pole may be used as the source of the transistor.

The transistor provided in the second aspect can be applied to a memory and can be used as a control element in the memory. For example, the method can be applied to ferroelectric memories, DRAM memories, phase change memories, resistive random access memories and magnetic memories. Because the transistor is of a vertical structure and occupies less substrate integration, the memory density of the memory can be improved by adopting the transistor as a control element of the memory.

And the channel layer of the transistor provided in the second aspect is arranged along the vertical direction, so that the two-dimensional electron gas for conducting the source electrode and the drain electrode can move in the vertical direction, the dependence of the transistor on the substrate can be reduced, and the requirement of the memory on the substrate is further reduced.

Taking the application in the ferroelectric memory as an example, the first pole of the transistor forms the upper end of the transistor, and the grid electrode forms the lower end of the transistor, so that the transistor and the ferroelectric capacitor are stacked in the vertical direction, the substrate integration area occupied by the transistor and the ferroelectric capacitor is reduced, and the memory density of the memory is improved. Specifically, the following is described.

The transistor provided in the second aspect is used as a second transistor, and the first transistor of the upper end and the lower end and the ferroelectric capacitor with the second electrode exposed at the lower end can be formed by combining the grid electrodes, so that a vertical stack of the ferroelectric capacitor is formed, wherein the first transistor is arranged in the middle, and the second transistor is arranged below. Specifically, the first electrode of the second transistor forms the upper end of the second transistor such that the first electrode of the second transistor is upward, and may be in contact with the gate electrode forming the lower end of the first transistor, and the gate electrode forming the upper end of the first transistor is upward, and may be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, thereby achieving connection of the gate electrode and the second electrode of the first transistor, and also such that the first electrode of the second transistor is connected to the second electrode through the gate electrode of the first transistor. Thereby realizing a stack of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction.

One of the transistors provided in the second aspect is used as a first transistor, and the other second transistor can be combined with the ferroelectric capacitor with the second electrode exposed at the upper end and the lower end to form a vertical stack of the first transistor with the upper ferroelectric capacitor in the middle and the second transistor in the lower. Specifically, the first electrode of the second transistor forms the upper end of the second transistor, so that the first electrode of the second transistor faces upwards and can contact the second electrode exposed at the lower end of the ferroelectric capacitor, and the connection between the first electrode and the second electrode of the second transistor is realized; the grid electrode of the first transistor forms the lower end of the first transistor, so that the grid electrode of the first transistor is downward, and the second electrode exposed at the upper end of the ferroelectric capacitor can be contacted, and the connection between the grid electrode of the first transistor and the second electrode is realized. Thereby realizing a stack of the first transistor, the ferroelectric capacitor and the second transistor in a vertical direction.

The transistor provided in the second aspect is used as a first transistor, and the first electrode and the second electrode are combined to form a ferroelectric capacitor exposed at the upper end and the lower end, and the first electrode forms a second transistor at the upper end, so that the first transistor is vertically stacked with the ferroelectric capacitor in the middle and the second transistor in the lower. Specifically, the grid electrode of the first transistor forms the lower end of the first transistor, so that the grid electrode of the first transistor is downward and can be contacted with the second electrode exposed at the upper end of the ferroelectric capacitor, and the connection between the grid electrode of the first transistor and the second electrode is realized; the first electrode of the second transistor is selected to form the upper end of the second transistor, so that the first electrode of the second transistor is upward, and the second electrode exposed at the lower end of the ferroelectric capacitor can be contacted, thereby realizing the connection between the first electrode of the second transistor and the second electrode. Thereby realizing a stack of the first transistor, the ferroelectric capacitor and the second transistor in a vertical direction.

In one possible embodiment, the channel layer is made of an N-type lightly doped semiconductor material, and the first electrode includes a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of an N-type heavily doped semiconductor material, and the N-type heavily doped region is in contact with the channel layer.

In the implementation mode, the channel layer is made of an N-type lightly doped semiconductor material, and the metal electrode can be connected with the channel layer through the N-type heavily doped region, so that ohmic contact resistance between the metal electrode and the channel layer can be reduced, and the electrical performance of the transistor is improved.

In a third aspect, there is provided a transistor comprising: a channel layer disposed in a vertical direction; a gate oxide layer surrounded by the channel layer; a gate penetrating the gate oxide layer and protruding from upper and lower ends of the gate oxide layer; a first pole and a second pole surrounding the channel layer, a space being present between the first pole and the second pole; the vertical direction is perpendicular to the surface of the transistor substrate, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate. Wherein the first pole can be used as the source of the transistor and the second pole can be used as the drain of the transistor; alternatively, the first pole may be used as the drain of the transistor and the second pole may be used as the source of the transistor.

The transistor provided in the third aspect can be applied to a memory and can be used as a control element in the memory. For example, the method can be applied to ferroelectric memories, DRAM memories, phase change memories, resistive random access memories and magnetic memories. Because the transistor is of a vertical structure and occupies less substrate integration, the memory density of the memory can be improved by adopting the transistor as a control element of the memory.

And the channel layer of the transistor provided by the third aspect is arranged along the vertical direction, so that the two-dimensional electron gas for conducting the first pole and the second pole can move in the vertical direction, the dependence of the transistor on the substrate can be reduced, and the requirement of the memory on the substrate is further reduced.

Taking the application in ferroelectric memory as an example, the gate of the transistor forms the upper end and the lower end of the transistor, so that the transistor and the ferroelectric capacitor are stacked in the vertical direction, the substrate integration area occupied by the transistor and the ferroelectric capacitor is reduced, and the storage density of the memory is improved. Specifically, the following is described.

The transistor provided in the third aspect is used as a first transistor, and the ferroelectric capacitor with the second electrode exposed at the lower end and the second transistor with the first electrode formed at the upper end can be combined to form a vertical stack of the ferroelectric capacitor in the upper, the first transistor in the middle and the second transistor in the lower. Specifically, a gate electrode forming an upper end of the first transistor is upward and can be in contact with a second electrode exposed at a lower end of the ferroelectric capacitor, so that connection of the gate electrode and the second electrode of the first transistor is realized; the gate electrode forming the lower end of the first transistor is downward and may be in contact with the first electrode forming the upper end of the second transistor such that the first electrode of the second transistor is connected to the second electrode through the gate electrode of the first transistor. Thereby realizing a stack of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction.

The transistor provided in the third aspect is used as a first transistor, and the ferroelectric capacitor with the second electrode exposed at the upper end and the second transistor with the first electrode formed at the lower end can be combined to form a vertical stack of the second transistor with the upper end, the first transistor in the middle and the ferroelectric capacitor in the lower end. Specifically, a gate electrode forming the lower end of the first transistor is downward and can be in contact with a second electrode exposed at the upper end of the ferroelectric capacitor, so that the connection between the gate electrode of the first transistor and the second electrode is realized; the gate electrode forming the upper end of the first transistor may be downward and may be in contact with the first electrode forming the lower end of the second transistor such that the first electrode of the second transistor is connected to the second electrode through the gate electrode of the first transistor. Thereby realizing a stack of the second transistor, the first transistor and the ferroelectric capacitor in the vertical direction.

In a fourth aspect, there is provided a transistor comprising: a channel layer disposed in a vertical direction; the channel layer is internally filled with an insulator, and the vertical direction is perpendicular to the surface of the substrate where the transistor is located; a third electrode positioned at the upper end of the channel layer; a fourth electrode located at the lower end of the channel layer; and a gate surrounding the channel layer, wherein a gate oxide layer is arranged between the gate and the channel layer, a space is arranged between the gate and the third electrode, and a space is arranged between the gate and the fourth electrode. Wherein the third pole is used as a first pole of the transistor and the fourth pole is used as a second pole of the transistor; alternatively, the third pole serves as the second pole of the transistor and the fourth pole serves as the first pole of the transistor; the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate.

The insulator is filled in the channel layer of the transistor provided in the fourth aspect, and the structure can improve the reliability of the manufacturing process of the transistor, so that the manufactured transistors in the same batch have good consistency.

The transistor provided in the fourth aspect can be applied to a memory and can be used as a control element in the memory. For example, the method can be applied to ferroelectric memories, DRAM memories, phase change memories, resistive random access memories and magnetic memories. Because the transistor is of a vertical structure and occupies less substrate integration, the memory density of the memory can be improved by adopting the transistor as a control element of the memory.

And the channel layer of the transistor provided in the fourth aspect is arranged along the vertical direction, so that the two-dimensional electron gas for conducting the source electrode and the drain electrode can move in the vertical direction, the dependence of the transistor on the substrate can be reduced, and the requirement of the memory on the substrate is further reduced.

Taking the application in ferroelectric memories as an example, the first pole of the transistor forms the upper end of the transistor and the second pole can form the lower end of the transistor; alternatively, the first pole of the transistor may form the lower end of the transistor and the second pole may form the upper end of the transistor. Therefore, the transistor and the ferroelectric capacitor can be stacked in the vertical direction, the substrate integration area occupied by the transistor and the ferroelectric capacitor is reduced, and the storage density of the memory is improved. Specifically, the following is described.

When the first electrode of the transistor provided in the fourth aspect forms the upper end of the transistor, the transistor provided in the fourth aspect can be used as the second transistor, and the ferroelectric capacitor with the first transistor of the upper end and the lower end and the second electrode exposed at the lower end is formed by combining the gates, so that the vertical stack of the ferroelectric capacitor is formed with the upper, the first transistor in the middle and the second transistor in the lower. Specifically, the first pole of the second transistor forms the upper end of the second transistor so that the first pole of the second transistor is upward and can be in contact with the gate forming the lower end of the first transistor; and, the gate electrode forming the upper end of the first transistor is upward and can be in contact with the second electrode exposed at the lower end of the ferroelectric capacitor, thereby realizing the connection of the gate electrode and the second electrode of the first transistor, and also enabling the first electrode of the second transistor to be connected to the second electrode through the gate electrode of the first transistor. Thereby realizing a stack of the ferroelectric capacitor, the first transistor and the second transistor in the vertical direction.

When the first electrode of the transistor provided in the fourth aspect forms the upper end of the transistor, the first transistor provided in the fourth aspect can be used as the second transistor, and the ferroelectric capacitor exposed at the upper end and the lower end is formed by combining the first transistor and the second electrode of the lower end, so that the vertical stack of the first transistor is formed with the upper ferroelectric capacitor in the middle and the second transistor in the lower. Specifically, the first electrode of the second transistor forms the upper end of the second transistor, so that the first electrode of the second transistor faces upwards and can contact the second electrode exposed at the lower end of the ferroelectric capacitor, and the connection between the first electrode and the second electrode of the second transistor is realized; the gate of the selected first transistor forms the lower end of the first transistor, so that the gate of the first transistor is downward, and the second electrode exposed at the upper end of the ferroelectric capacitor can be contacted, thereby realizing the connection between the gate of the first transistor and the second electrode. Thereby realizing a stack of the first transistor, the ferroelectric capacitor and the second transistor in a vertical direction.

When the first electrode of the transistor provided in the fourth aspect forms the lower end of the transistor, the transistor provided in the fourth aspect can be used as a second transistor, and the first transistor of the upper end and the lower end and the ferroelectric capacitor with the second electrode exposed at the upper end can be formed by combining the gates, so that the vertical stack of the second transistor is formed with the first transistor in the middle and the ferroelectric capacitor in the lower. Specifically, a gate electrode forming the lower end of the first transistor is downward and can be in contact with a second electrode exposed at the upper end of the ferroelectric capacitor, so that the connection between the gate electrode of the first transistor and the second electrode is realized; the gate electrode forming the upper end of the first transistor may be downward and may be in contact with the first electrode forming the lower end of the second transistor such that the first electrode of the second transistor is connected to the second electrode through the gate electrode of the first transistor. Thereby realizing a stack of the second transistor, the first transistor and the ferroelectric capacitor in the vertical direction.

In one possible embodiment, the channel layer is made of an N-type lightly doped semiconductor material, and the third electrode and/or the fourth electrode comprise a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of an N-type heavily doped semiconductor material, and the N-type heavily doped region is in contact with the channel layer.

In the ferroelectric memory provided by the application, the first transistor and the second transistor are of vertical structures, the electrodes are distributed along the direction vertical to the substrate, and the structures of the first transistor, the second transistor and the ferroelectric capacitor can enable the three to be stacked along the direction vertical to the substrate, so that the integration area occupied by the memory module is reduced, more memory modules can be integrated on the substrate, and the memory density of the ferroelectric memory is improved.

Drawings

FIG. 1A is a schematic diagram of a ferroelectric memory cell;

FIG. 1B is a schematic diagram of a ferroelectric memory cell;

FIG. 2 is a schematic diagram of a ferroelectric memory cell structure;

FIG. 3 is a schematic diagram of ferroelectric memory cells occupying the integrated area of a substrate;

fig. 4A is a schematic structural diagram of a transistor according to an embodiment of the present application;

fig. 4B is a schematic diagram of a transistor manufacturing scheme according to an embodiment of the present application;

fig. 5A is a schematic structural diagram of a transistor according to an embodiment of the present application;

FIG. 5B is a schematic diagram of a transistor manufacturing scheme according to an embodiment of the present application;

fig. 6A is a schematic structural diagram of a transistor according to an embodiment of the present application;

FIG. 6B is a schematic diagram of a transistor manufacturing scheme according to an embodiment of the present application;

fig. 7A is a schematic structural diagram of a ferroelectric capacitor according to an embodiment of the present application;

FIG. 7B is a schematic diagram of an arrangement of ferroelectric capacitors according to an embodiment of the present application;

FIG. 8 is a schematic diagram of the circuit connections of the ferroelectric capacitor, the pre-charge transistor and the sense transistor;

FIG. 9A is a schematic diagram of a memory module with a 2TnC structure according to an embodiment of the present application;

FIG. 9B is a schematic diagram of a memory module with a 2TnC structure according to an embodiment of the present application;

FIG. 9C is a schematic diagram of a memory module with a 2TnC structure according to an embodiment of the present application;

FIG. 9D is a schematic diagram of a memory module with a 2TnC structure according to an embodiment of the present application;

FIG. 9E is a schematic diagram of a memory module with a 2TnC structure according to an embodiment of the present application;

FIG. 10 is a schematic diagram of three-dimensional stacking of memory modules according to an embodiment of the present application;

FIG. 11 is a schematic diagram illustrating circuit connection between different memory modules according to an embodiment of the present application;

fig. 12 is a truth table of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application.

Ferroelectric memory, also known as ferroelectric random access memory (ferroelectric random access memory, feRAM), may comprise one or more memory cells. Each memory cell is mainly composed of a capacitor (C) and a transistor (T). The ferroelectric crystal is deposited between the two electrode plates of the capacitor, so that the memory unit can realize data storage by utilizing the ferroelectric effect of the ferroelectric crystal. The iron atoms in the crystal center of the ferroelectric crystal have two stable states or polarization states. The two polarization states may be set to be polarization state D1 and polarization state D2, respectively. Ferroelectric effect means that when a certain electric field is applied to a ferroelectric crystal, the central atoms of the crystal move under the action of the electric field and reach a stable state (or polarization state D1); when the electric field is removed from the crystal, the central atom remains in place. This is due to the fact that the crystal is at a high energy level between the two states, and the central atom cannot reach another stable position (or polarization state D2) beyond the high energy level without external energy being available. Accordingly, the ferroelectric memory can hold data in the event of power failure, has a nonvolatile property, and can be used as a nonvolatile memory.

In the following description, the above-described capacitance may be referred to as ferroelectric capacitance, and the above-described memory cell may be referred to as ferroelectric memory cell.

A stack may also be understood as an arrangement or distribution. The three-dimensional direction may also be referred to as a vertical direction. Wherein the vertical direction or three-dimensional direction refers to a direction perpendicular to the surface of the substrate.

The embodiment of the application provides a three-dimensional ferroelectric memory, which comprises a plurality of memory modules, wherein a single memory module is a 2TnC structure consisting of n ferroelectric capacitors (nC, n is an integer greater than or equal to 1) stacked in the vertical direction and two transistors (2T) with vertical structures. This structure improves the memory density of the ferroelectric memory. Specifically, compared with a transistor with a horizontal structure, the channel layer of the transistor with the vertical structure is vertical, and the three electrodes of the gate electrode, the electrode F1 and the electrode F2 do not need to occupy the integrated area of the surface of the substrate, so that more memory modules with 2TnC structures can be integrated on the substrate, and each memory module with 2TnC structures has n ferroelectric capacitors, so that the memory density is improved. Wherein the larger the n number is, the larger the storage density of the ferroelectric memory is. In one example, the integration area occupied by each of the n ferroelectric capacitors may be reduced to 4F ² And/n, thereby greatly improving the storage density of the ferroelectric memory.

In the embodiment of the present application, the electrode F1 of the transistor may refer to a source of the transistor, and the electrode F2 of the transistor may refer to a drain of the transistor. Alternatively, the electrode F1 of the transistor may refer to the drain of the transistor, and the electrode F2 may refer to the source of the transistor. That is, the electrode F1 may be either a source or a drain; the electrode F1 may be a source or a drain. Wherein, when the electrode F1 is a source electrode, the electrode F2 is a drain electrode; when electrode F1 is the drain, electrode F2 is the source.

The two transistors with vertical structures of the memory module are jointly used as gating devices, n ferroelectric capacitors in the memory module can be selected, one ferroelectric capacitor is selected from the n ferroelectric capacitors through one end electrode of the ferroelectric capacitor, and then reading and writing operations can be performed on the selected ferroelectric capacitors.

For convenience of description, one of the two vertical structure transistors in the memory module may be referred to as a sense transistor, and the other transistor may be referred to as a precharge transistor, wherein the precharge transistor and the sense transistor are combined with one end electrode of the ferroelectric capacitor, and one ferroelectric capacitor may be selected from n ferroelectric capacitors of the memory module, and read/write operations may be performed on the selected ferroelectric capacitor. The n ferroelectric capacitors may be selected by the precharge transistor, and then one ferroelectric capacitor may be selected from the selected n ferroelectric capacitors by using one end electrode of the ferroelectric capacitor. The precharge transistor is used for selecting the n ferroelectric capacitors and can be called as address selection, i.e. the precharge transistor has an address selection function. The sensing transistor can sense signals generated by the reading operation, and further read information stored in the ferroelectric capacitor. The operation truth table for the memory module will be specifically described below, and will not be described herein.

Next, a vertical structure transistor, a circuit connection manner of a memory module, and a structure of the memory module provided in the embodiment of the present application will be described in order. Wherein, in the following description, top, upper end, upper side, upper surface, etc., refer to a side away from the substrate in a vertical direction. Bottom, bottom end, lower end, under, lower surface, etc. refer to a side in the vertical direction that is closer to the substrate.

In some embodiments, a vertical structure transistor is provided as shown in fig. 4A. Wherein the electrode F1 and the gate of the vertical structure transistor are led out from the vertical direction. Wherein the electrode F1 is specifically led out from the top, and the grid is specifically led out from the bottom. For convenience of description, this vertical structure may be referred to as a transistor T1. In the embodiments of the present application, "led out" may be understood as being transparent or exposed. Wherein, the vertical direction is led out or exposed from the upper end and/or the lower end in the vertical direction. By top out is meant exposed or penetrated at the top. By bottom out is meant exposed or penetrated at the bottom.

The electrode F1 is drawn from the top of the transistor T1 can be understood as: electrode F1 forms the upper or top of transistor T1, and the gate leading from the bottom of transistor T1 can be understood as: the gate forms the upper or top of transistor T1. In other words, the upper end or top of the transistor T1 is the electrode F1, and the lower end or bottom is the gate.

The transistor T1 is prepared by adopting a later preparation process, the transistor prepared by the later process is no longer dependent on a bulk silicon substrate, and transistor components can be stacked in a three-dimensional direction. Planar transistors fabricated using the front-end-of-line (front end of line, FEOL) process, as opposed to the back-end-of-line, rely heavily on bulk silicon substrates.

Referring to fig. 4A, in order to meet the requirement of back end of line (BEOL) integration, the channel layer of the transistor T1 is disposed in a vertical direction, so that two-dimensional electron gas (2 DEG) that turns on the electrode F1 and the electrode F2 moves in the vertical direction, independent of the bulk silicon substrate. The channel layer may be cylindrical, square, or the like.

In one example, the material of the channel layer may be an N-type lightly doped semiconductor. The N-type doped semiconductor is to dope N-type impurities in the semiconductor to provide free electrons for the semiconductor. The N-type impurity may also be referred to as a donor impurity, which is an impurity that can provide a semiconductor material with free electrons. In one example, the N-type impurity may be a P element, or an As element, or an Sb element. In one example, the semiconductor employed may be polysilicon in particular. Wherein lightly doped, i.e., lightly doped, means that the semiconductor is doped with fewer impurities. The heavy doping corresponds to the light doping, and the heavy doping means that the impurity doped into the semiconductor is more. That is, it can be classified into light doping and heavy doping according to the amount of the doped impurities. In this example, the N-type lightly doped semiconductor is relative to an N-type heavily doped semiconductor which will be described later. That is, the N-type lightly doped semiconductor has less N-type impurity doped therein relative to the N-type heavily doped semiconductor described below. Accordingly, the N-type heavily doped semiconductor described below is more doped with N-type impurities than the N-type lightly doped semiconductor.

In one example, the material of the channel layer may be an oxide thin film having high electron mobility. For example, the oxide film may be any of In-Ga-Zn-O (indium zinc oxide (indium gallium zinc oxide, IGZO)), in-Sn-O (indium tin oxide (ITO)), in-Al-Zn-O (IAZO), in-Ga-Sn-O (IGTO), and ZnO.

A cylindrical gate oxide layer S1 is provided inside the cylindrical channel layer. That is, the gate oxide layer S1 is surrounded by the channel layer. The shape of the gate oxide layer S1 corresponds to the channel layer so that the gate oxide layer can be attached to the channel layer. The gate oxide layer is composed of a gate oxide, which is an insulating material. The gate oxide may be any of silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide, for example.

A portion of the gate of the transistor T1 is located in the cylindrical gate oxide layer S1, or the portion is surrounded by the gate oxide layer S1. Another portion of the gate of the transistor T1 protrudes from the bottom of the cylindrical gate oxide layer S1. In one example, the gate electrode may be a metal electrode, such as a tungsten electrode.

An electrode F1 is provided on top of the channel layer, wherein the electrode F1 is insulated from the gate electrode. Illustratively, as shown in fig. 4A, the electrode F1 and the gate electrode may be separated by a gate oxide layer S2. As illustrated in fig. 4A, the electrode F1 may be composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer sequentially connected in a vertical direction, wherein the N-type heavily doped semiconductor layer is in contact with the channel layer, whereby ohmic contact resistance between the electrode F1 and the channel layer may be reduced.

In this embodiment of the present application, "contact" is understood to mean "top-up", which generally refers to the two objects that are in a block or sheet shape that are brought together, or one of the two objects is located on the surface of the other object. In addition, in embodiments of the present application, "connected" may refer to the direct contact of two objects. "connected" may also mean that two objects are connected by a third object, i.e., one side or end of the third object contacts one of the two objects and the other side or end of the third object contacts the other of the two objects.

Wherein, as described above, the N-type heavily doped semiconductor is doped with more N-type impurities than the N-type lightly doped semiconductor described above.

Silicide refers to binary compounds formed by metals (such as lithium, calcium, magnesium, iron, chromium and the like) or non-metals (such as boron and the like) and silicon, and has good high-temperature oxidation resistance and electric conduction. The silicide may be TiSi or WSi, for example.

The metal electrode may be a tungsten electrode, for example.

With continued reference to fig. 4A, electrode F2 of transistor T1 is disposed on the outer sidewall of the channel layer, or electrode F2 surrounds the channel layer. And a predetermined distance is provided between the electrode F2 and the electrode F1. The electrode F1 may be composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer, which are sequentially connected in the vertical direction, for example. Wherein the N-type heavily doped semiconductor layer is located at a side close to the electrode F1. The metal electrode layer, the silicide layer, and the N-type heavily doped semiconductor layer may refer to the description of the electrode F1 above, and will not be repeated here.

In the transistor T1, the portion of the channel layer between the electrode F1 and the electrode F2 may turn on the electrode F1 and the electrode F2 by the gate electrode. For example, a positive voltage is applied to the gate electrode, an electric field is generated, electrons are collected by the channel layer under the action of the electric field, and the gate oxide layer can block the electrons from flowing to the gate electrode, thereby forming a two-dimensional electron gas in the channel layer, which can turn on the electrode F1 and the electrode F2.

The structure of the transistor T1 is described above in connection with fig. 4A. Next, a process for manufacturing the transistor T1 is described in conjunction with 4B.

As shown in fig. 4B, the fabrication process of the transistor T1 may include a step 401 of sequentially depositing a metal electrode 41, an insulating layer 42, a metal electrode 43, a silicide 44, an N-type heavily doped semiconductor 45, an insulating layer 46, and an N-type heavily doped semiconductor 47 on a substrate along a vertical direction. The base may be a substrate (for example, a silicon substrate), a dielectric layer deposited on the substrate, a base formed by a plurality of transistors distributed laterally as described below, or a base formed by a ferroelectric capacitor in a three-dimensional stacked structure as described below. The drawings described below are specifically shown and will not be described in detail herein.

Wherein a plurality of metal electrodes 41 may be deposited on the substrate, the plurality of metal electrodes being discontinuously distributed in the lateral direction. Wherein the lateral direction refers to a direction parallel to the upper surface of the substrate. The insulating layer 42 is distributed between the different metal electrodes 41 and above the metal electrodes 41. Then, a metal electrode 43, silicide 44, N-type heavily doped semiconductor 45, insulating layer 46, N-type heavily doped semiconductor 47 are sequentially deposited on the insulating layer 42, resulting in a multilayer structure.

In one illustrative example, the metal may be deposited by sputtering. In one example, chemical vapor deposition (chemical vapor deposition, CVD) may be used to deposit insulating layers, silicides, N-type heavily doped semiconductors.

Next, in step 402, the multilayer structure prepared in step 401 is etched. Specifically, etching is performed in a region corresponding to the metal electrode 41, and etching is performed to the insulating layer 42. Wherein the insulating layer 42 is not completely etched through, so that a portion of the insulating layer remains over the metal electrode 41. For example, etching may be performed by photolithography.

Next, in step 403, the channel layer 48 and the gate oxide layer 49 are sequentially filled in the etched region and opened at the bottom, and then the metal electrode 510 is deposited and planarized. Specifically, the channel layer 48 is filled along the side walls of the etched region to form a cylindrical channel layer. The channel layer 48 may be an N-type lightly doped semiconductor, or an oxide film with high electron mobility, as described above. Then, the gate oxide layer 49 is filled along the sidewall of the channel layer to form a cylindrical gate oxide layer. The metal electrode 43, silicide 44, and N-type heavily doped semiconductor 45 may form an electrode F2. The insulating layer 42 at the bottom of the cylindrical gate oxide layer is etched away to expose the metal electrode 41. Then, a metal electrode 410 is deposited on the exposed metal electrode 41, and the upper end of the metal electrode 410 is made lower than the upper end of the cylindrical gate oxide layer 47. The upper surface of the metal electrode 410 may be ground flat. The metal electrode 410 and the metal electrode 41 form a gate electrode.

Thereafter, in step 404, the gate oxide 411 is filled and silicide 412 and metal electrode 413 are deposited sequentially. Specifically, the gate oxide 411 may be filled over the metal electrode 410, and the upper surface of the filled gate oxide 4110 may be made flush with the upper end of the cylindrical gate oxide layer 49. Then, silicide 412 and metal electrode 413 may be deposited on the entire region including N-type heavily doped semiconductor 47, the upper end of channel layer 48, the upper end of gate oxide 49, and the upper end of gate oxide 411 to form electrode F1.

Thus, the transistor T1 can be manufactured by the process shown in fig. 4B. Also, as shown in fig. 4B, a plurality of transistors T1 distributed in the lateral direction can be simultaneously prepared.

The process operations of deposition, etching, filling, etc. in the process shown in fig. 4B may refer to the description of the prior art, and will not be described herein in detail.

In some embodiments, a vertical structure transistor is provided as shown in fig. 5A. Wherein the gate of the transistor is led out in the vertical direction. Specifically, the gate is led out in a vertical direction. For convenience of description, this vertical structure may be referred to as a transistor T2. The gate of the transistor T2 is led out in the vertical direction by the following way: one end of the gate of the transistor T2 forms the upper or top of the transistor T2 and the other end forms the lower or bottom of the transistor T2.

Referring to fig. 5A, in order to meet the requirement of the subsequent integration, the channel layer of the transistor T2 is disposed in the vertical direction, so that the two-dimensional electron gas that turns on the electrode F1 and the electrode F2 moves in the vertical direction, independent of the bulk silicon substrate. The channel layer may be cylindrical, square, or the like. In one example, the material of the channel layer may be an N-type lightly doped semiconductor. In one example, the material of the channel layer may be an oxide thin film having high electron mobility. The material of the channel layer may be specifically referred to the description of the transistor T1 above, and will not be repeated here.

The channel layer surrounds the gate oxide layer. Specifically, a cylindrical gate oxide layer is provided inside the cylindrical channel layer. The shape of the gate oxide layer corresponds to the channel layer so that the gate oxide layer can be attached to the channel layer. The gate oxide layer is composed of a gate oxide, which is an insulating material. The gate oxide may be any of silicon oxide, silicon nitride, and silicon oxynitride, for example.

The gate of the transistor T2 penetrates the cylindrical gate oxide layer and protrudes from the upper and lower ends of the gate oxide layer. In one example, the gate electrode may be a metal electrode, such as a tungsten electrode.

The electrode F1 and the electrode F2 of the transistor T2 are disposed at different positions on the outer side wall of the channel layer, or the electrode F1 and the electrode F2 each surround the channel layer. Wherein, on the outer sidewall of the channel layer, the electrode F1 and the electrode F2 are arranged in the vertical direction with a preset distance between the electrode F1 and the electrode F2. The electrode F1 may be located above the electrode F2 or below the electrode F2. For example, the electrode F1 and the electrode F2 may each be composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer connected in sequence in the vertical direction. The N-type heavily doped semiconductor layer of the electrode F1 is located at a side close to the electrode F2, and the N-type heavily doped semiconductor layer of the electrode F2 is located at a side close to the electrode F1.

The metal electrode layer, the silicide layer, and the N-type heavily doped semiconductor layer may be specifically implemented with reference to the description of the transistor T1 above.

In the transistor T2, the portion of the channel layer between the electrode F1 and the electrode F2 may turn on the electrode F1 and the electrode F2 by the gate electrode.

The structure of the transistor T2 is described above in connection with fig. 5A. Next, a process for manufacturing the transistor T2 is described in conjunction with fig. 5B.

As shown in fig. 5B, the process for preparing the transistor T2 may include a step 501 of sequentially depositing a metal electrode 51, an insulating layer 52, a metal electrode 53, a silicide 54, an N-type heavily doped semiconductor 55, an insulating layer 56, an N-type heavily doped semiconductor 57, an insulating layer 58, a metal electrode 59, and an insulating layer 510 on a substrate along a vertical direction. The substrate may be a substrate, a substrate formed by a plurality of transistors (for example, a plurality of transistors shown in fig. 4B) distributed in a lateral direction, or a substrate formed by a ferroelectric capacitor in a three-dimensional stacked structure described below.

Wherein a plurality of metal electrodes 51 may be deposited on the substrate, the plurality of metal electrodes 51 being discontinuously distributed in the lateral direction. Wherein the lateral direction refers to a direction parallel to the upper surface of the substrate. The insulating layer 52 is distributed between the different metal electrodes 51 and over the metal electrodes 51. Then, a metal electrode 53, a silicide 54, an N-type heavily doped semiconductor 55, an insulating layer 56, an N-type heavily doped semiconductor 57, an insulating layer 58, a metal electrode 59, and an insulating layer 510 are sequentially deposited on the insulating layer 52, resulting in a multilayer structure.

Next, in step 502, the multilayer structure prepared in step 501 is etched. Specifically, etching is performed in a region corresponding to the metal electrode 41, and etching is performed to the insulating layer 52. Wherein the insulating layer 52 is not completely etched through, so that a portion of the insulating layer remains over the metal electrode 51.

Next, in step 503, the channel layer 511, the gate oxide layer 512, and the bottom opening are sequentially filled, and then the metal electrode 513 is deposited. Specifically, the channel layer 511 is filled along the sidewall of the etched region to form a cylindrical channel layer. Then, the gate oxide layer 512 is filled along the sidewall of the channel layer to form a cylindrical gate oxide layer. The insulating layer 52 at the bottom of the cylindrical gate oxide layer is etched away to expose the metal electrode 51. Then, a metal electrode 513 is deposited on the exposed metal electrode 51, and the upper end of the metal electrode 513 is made lower than the upper end of the cylindrical gate oxide layer 512. The upper surface of the metal electrode 513 may be polished flat.

Thereafter, in step 504, an insulating layer 514 is deposited over the entire region including the insulating layer 510, the upper end of the channel layer 511, the upper end of the gate oxide layer 512, and the upper end of the metal electrode 513. Next, the insulating layer 514 is etched to the metal electrode 513 in a region corresponding to the metal electrode 513 to expose the metal electrode 513. Then, a metal electrode 515 may be deposited on the metal electrode 513. The metal electrode 515, the metal electrode 513, and the metal electrode 51 constitute a gate through which the transistor T2 is drawn in the vertical direction, wherein the metal electrode 513 forms an upper end of the transistor T2 and the metal electrode B2 forms a lower end of the transistor T2.

Thus, the transistor T2 can be manufactured by the process shown in fig. 5B. Also, as shown in fig. 5B, a plurality of transistors T2 distributed in the lateral direction can be simultaneously prepared.

In some embodiments, a vertical structure transistor is provided as shown in fig. 6A. Wherein the electrode F1 and the electrode F2 of the vertical structure transistor are led out in the vertical direction. Wherein the electrode F1 and the electrode F2 are led out from the top and the bottom of the transistor, respectively, i.e. the electrode F1 and the electrode F2 form the upper and the lower end of the transistor, respectively. Specifically, when the electrode F1 is drawn out from the top of the transistor, the electrode F2 is drawn out from the bottom of the transistor; when electrode F1 is drawn from the bottom of the transistor, the top is drawn from the top of the transistor. That is, when the electrode F1 is the upper end of the transistor, the electrode F2 is the lower end of the transistor; when the electrode F1 is the lower end of the transistor, the electrode F2 is the upper end of the transistor.

For convenience of description, this vertical structure may be referred to as a transistor T3. The transistor T3 may also be referred to as a gate-all-around (GAA) transistor.

Referring to fig. 6A, the channel layer of the transistor T3 has a U shape, and may be referred to as a U-shaped channel layer. Wherein the opening of the U-shaped channel layer faces upwards. In one example, the material of the channel layer may be an N-type lightly doped semiconductor. In one example, the material of the channel layer may be an oxide thin film having high electron mobility. The material of the channel layer may be specifically referred to the description of the transistor T1 above, and will not be repeated here.

The inside of the U-shaped channel layer is filled with an insulator. The outer side wall of the U-shaped channel layer is provided with a gate oxide layer. In other words, the gate oxide layer surrounds the channel layer.

The gate oxide layer is surrounded by the gate electrode. In one example, the gate may be a metal electrode. As shown in fig. 6A, in the lateral direction, one side of the gate oxide layer is attached to the outer side wall of the U-shaped channel layer, and the other side is provided with a metal electrode. The metal electrode serves as the gate of transistor T3.

The upper end of the U-shaped channel layer is provided with an electrode A1, and the lower end is provided with an electrode A2. There is a space between electrode A1 and the gate, and there is a space between electrode A2 and the gate. The electrode A1 may be the electrode F1 of the transistor T3 or the electrode F2 of the transistor T3. Accordingly, the electrode A2 may be used as the electrode F2 of the transistor T3 or as the electrode F1 of the transistor T3. Specifically, when the electrode A1 is used as the electrode F1 of the transistor T3, the electrode A2 is used as the electrode F2 of the transistor T3; when the electrode A1 is used as the electrode F2 of the transistor T3, the electrode A2 is used as the electrode F1 of the transistor T3.

As shown in fig. 6A, the electrode A1 and the electrode A2 are composed of a metal electrode layer, a silicide layer, and an N-type heavily doped semiconductor layer, which may be sequentially connected in the vertical direction. The N-type heavily doped semiconductor layer of the electrode A1 is contacted with the upper end of the U-shaped channel layer, and the N-type heavily doped semiconductor layer of the electrode A2 is contacted with the bottom of the U-shaped channel layer.

The U-shaped channel layer generates two-dimensional electron gas under the action of the grid electrode, so that the electrode F1 and the electrode F2 can be conducted.

The structure of the transistor T3 is described above in connection with fig. 6A. Next, a process for manufacturing the transistor T3 is described in conjunction with fig. 6B.

As shown in fig. 6B, the process for preparing the transistor T3 may include a step 601 of sequentially depositing a metal electrode 61, a silicide 62, an N-type heavily doped semiconductor 63, an insulating layer 64, a metal electrode 65, and an insulating layer 66 on a substrate along a vertical direction. The substrate may be a substrate, or may be a substrate formed by ferroelectric capacitors in a three-dimensional stacked structure as described below.

Wherein a plurality of metal electrodes 61 may be deposited on the substrate, the plurality of metal electrodes 61 being discontinuously distributed in the lateral direction. Silicide 62 is deposited on each metal electrode 61, and N-type heavily doped semiconductor 63 is deposited on silicide 62 to form electrode A2. An insulating layer 64 is deposited between and over the electrodes A2. Then, a metal electrode 65 and an insulating layer 66 are sequentially deposited on the insulating layer 64, resulting in a multilayer structure.

Next, in step 602, the multilayer structure prepared in step 601 is etched. Specifically, etching is performed in a region corresponding to the N-type heavily doped semiconductor 63, and etching is performed to the N-type heavily doped semiconductor 63.

Next, in step 603, the gate oxide 67 is filled and opened in sequence, filling the channel layer 68 and the insulator 69. Specifically, the gate oxide 67 is first filled along the sidewalls of the etched region to form a gate oxide layer. The gate oxide of the deposited N-type heavily doped semiconductor 63 is removed, i.e., opened, to expose the N-type heavily doped semiconductor 63. Then, a channel layer 68 is filled on the N-type heavily doped semiconductor 63 and the sidewalls of the gate oxide layer to form a U-type channel layer. The U-shaped channel layer is refilled with insulator 69. Finally, the upper end of the gate oxide layer, the upper end of the U-shaped channel layer, and the upper end of the insulator 69 may be planarized.

Thereafter, in step 604, an N-type heavily doped semiconductor 610, a silicide 611, and a metal electrode 612 are sequentially deposited on the entire region including the upper end of the gate oxide layer, the upper end of the U-shaped channel layer, and the upper end of the insulator 69 to form an electrode A1.

Thus, the transistor T3 can be manufactured by the process shown in fig. 6B. Also, as shown in fig. 6B, a plurality of transistors T3 distributed in the lateral direction can be simultaneously prepared.

As shown in fig. 7A, an embodiment of the present application provides a ferroelectric capacitor in which an electrode is drawn from a vertical direction. Wherein the ferroelectric capacitor comprises an electrode B1, an electrode B2 opposite to the electrode B1, and a ferroelectric layer deposited between the electrode B1 and the electrode B2. In other words, the ferroelectric layer surrounds the electrode B2, and the electrode B1 surrounds the ferroelectric layer. Wherein the ferroelectric layer may in particular be a ferroelectric crystal. The electrode B2 may be a Floating Gate (FG). By way of example, electrodes B1 and B2 may be metal electrodes, such as tungsten electrodes.

Wherein the electrode B2 is drawn out from the vertical direction, i.e., the electrode B2 is exposed at the upper end of the ferroelectric capacitor, or at the lower end of the ferroelectric capacitor, or at both the upper and lower ends of the ferroelectric capacitor.

An electric field can be applied to the ferroelectric layer through the electrode B1 and the electrode B2 to change the position of the crystal center atom in the ferroelectric layer so that the ferroelectric layer records information, i.e., information is written into the ferroelectric layer, and another electric field can be applied to the ferroelectric layer through the electrode B1 and the electrode B2 to sense whether the position of the crystal center atom in the ferroelectric layer is changed or not so as to read the information recorded in the ferroelectric layer.

In some embodiments, as shown in fig. 7B, n ferroelectric capacitors may be stacked or arranged in a vertical direction, where n is an integer greater than or equal to 1. Wherein n electrode layers surround the ferroelectric layer, adjacent two electrode layers of the n electrode layers being separated by an insulating material. n electrode layers are used as the electrode B1 in one-to-one correspondence with n ferroelectric capacitors. The ferroelectric layer surrounds the columnar electrodes. The columnar electrode serves as electrode B2 of the n ferroelectric capacitors.

Specifically, a ferroelectric layer extending in the vertical direction may be provided, the ferroelectric layer having a cylindrical shape. The outer side wall of the cylindrical ferroelectric layer is provided with n electrode layers which are sequentially arranged along the vertical direction, and an insulating layer is arranged between two upper and lower adjacent electrode layers, namely the two upper and lower adjacent electrode layers are separated or insulated by an insulating material. The n electrode layers and the n ferroelectric capacitors are in one-to-one correspondence and serve as electrodes B1 of the corresponding ferroelectric capacitors, respectively.

The inner side of the cylindrical ferroelectric layer is provided with a columnar electrode extending in the vertical direction. The columnar electrode may be used as the electrode B2 of the n ferroelectric capacitors. That is, the plurality of ferroelectric capacitors share the electrode B2.

Ferroelectric capacitors can be prepared as follows.

First, on a substrate, insulating layers and electrode layers are alternately deposited along a vertical direction, wherein n insulating layers and n electrode layers are co-deposited to obtain a multilayer structure. Wherein n is an integer greater than or equal to 1. The electrode layer may be a metal electrode layer. The base may be a substrate, a plurality of transistors T1 shown in fig. 4B, a plurality of transistors T2 shown in fig. 5B, or a plurality of transistors T3 shown in fig. 6B.

Then, the multi-layer structure is etched and etched to the substrate.

Then, the ferroelectric layer is filled in the side wall of the etched region to generate a cylindrical ferroelectric layer extending in the vertical direction. And filling the cylindrical ferroelectric layer with a cylindrical electrode. The columnar electrode may be a columnar metal electrode.

Thus, n ferroelectric capacitors arranged in the vertical direction can be prepared.

The above examples describe transistors and ferroelectric capacitors that may be provided by embodiments of the present application. Next, a memory module having a 2TnC structure that can be formed using the above transistor and ferroelectric capacitor will be described.

The circuit connection mode of the memory module with the 2TnC structure is shown in fig. 8. Wherein, as described above, 2T in the 2TnC structure is a sense transistor and a precharge transistor, nC is n ferroelectric capacitors, and n is an integer greater than or equal to 1. The gate of the sense transistor and the electrode F1 of the precharge transistor are both connected to the electrode B2 of the n ferroelectric capacitors, and the electrode B2 is shared by the n ferroelectric capacitors. Thus, the sensing transistor is selected from transistors with gates led out from the vertical direction, such as the transistors T1 and T2 described above. The precharge transistors of the memory module are transistors, such as the transistors T1 and T3 described above, which are led out from the vertical direction by the electrode F1. Ferroelectric capacitors led out from the vertical direction by the bonding electrode B2. The three-dimensional stacked induction transistor, the pre-charge transistor and the ferroelectric capacitor can be realized, so that more memory modules can be integrated on the substrate, and the memory density and the capacity of the ferroelectric memory are improved.

With continued reference to fig. 8, an electrode F1 of the sense transistor is connected to a Source Line (SL), an electrode F2 of the sense transistor is connected to a Bit Line (BL), an electrode F1 of the precharge transistor is connected to a Control Line (CL), and an electrode F2 of the precharge transistor is connected to the bit line. The electrodes B1 of the n ferroelectric capacitors are connected to Word Lines (WL).

The bit line, the control line, and the word line may each provide a corresponding voltage to operate the corresponding ferroelectric capacitor. The operation truth table will be specifically described below, and will not be described in detail here.

Wherein when n is greater than 1, the electrode B1 of a different one of the n ferroelectric capacitors is connected to a different word line, e.g., the electrode B1 of a first one of the n ferroelectric capacitors is connected to the word line WL ₁ …, electrode B1 of the nth ferroelectric capacitor is connected to word line WL _n . Thus, for any one ferroelectric capacitor of n ferroelectric capacitors, the voltage of the word line corresponding to the ferroelectric capacitor can be controlled, and the voltages of the source line, the bit line, the control line and the electrode B2 are controlled by operating the sensing transistor and the pre-charging transistor, so that the ferroelectric capacitor is subjected to read-write operation. The operation truth table will be specifically described below, and will not be described in detail here.

Next, taking the memory module M1 as an example, the structure of the memory module having the 2TnC structure will be described. In the memory module M1, the electrode B2 may be exposed at an upper end and/or a lower end of the ferroelectric capacitor, the gate electrode of the sensing transistor may form the upper end and/or the lower end of the sensing transistor, and the electrode F1 of the precharge transistor may form the upper end and/or the lower end of the precharge transistor. In combination with the circuit connection mode of 2TnC, namely the gate electrode connection electrode B2 of the induction transistor and the electrode F1 connection electrode B2 of the pre-charge transistor, the stacking of the ferroelectric capacitor B2, the gate electrode of the induction transistor and the electrode F1 of the pre-charge transistor in the vertical direction can be realized. Next, the case will be described.

In embodiment 1, the electrode B2 may be exposed at the lower end of the ferroelectric capacitor, the gate electrode of the sensing transistor may form the upper and lower ends of the sensing transistor, and the electrode F1 of the precharge transistor may form the upper end of the precharge transistor. In this way, the electrode B2 exposed at the lower end of the ferroelectric capacitor may be in contact with the upper end of the sense transistor, and the lower end of the sense transistor may be in contact with the upper end of the precharge transistor, so that the ferroelectric capacitor may be disposed above the sense transistor, and the precharge transistor may be disposed below the sense transistor, thereby realizing stacking of the ferroelectric capacitor, the sense transistor, and the precharge transistor in the vertical direction. In addition, the gate of the sense transistor also extends through the sense transistor, so that the electrode F1 of the precharge transistor can be connected to the electrode B2 of the ferroelectric capacitor through the gate of the sense transistor.

In the embodiment of the application, the lower part refers to the side close to the substrate, and the upper part refers to the side far away from the substrate.

In the first example in embodiment 1, the sense transistor may employ the transistor T2, and the precharge transistor may employ the transistor T1.

The specific structure may be as shown in fig. 9A, where n ferroelectric capacitors, a sense transistor and a precharge transistor are sequentially connected in the vertical direction. Wherein, n ferroelectric capacitors are positioned above the induction transistor, and the pre-charge transistor is positioned below the induction transistor. The gate of the sense transistor penetrates the sense transistor, and thus, the upper end of the gate of the sense transistor is in contact with the lower end of the electrode B2 shared by the n ferroelectric capacitors above, so that the connection between the electrode B2 and the gate of the sense transistor is realized. The lower end of the gate of the sense transistor is in contact with the electrode F1 drawn from the top of the precharge transistor so that the electrode F1 of the precharge transistor can be connected to the electrode B2 through the gate of the sense transistor. For example, as shown in fig. 9A, the lower end of the gate electrode of the sensing transistor and the electrode F1 of the precharge transistor share one metal electrode to save manufacturing costs and simplify manufacturing processes of the memory module.

For example, n ferroelectric capacitors in the memory module M1 may be set to be specifically 4 ferroelectric capacitors, where the electrode B1 of the first ferroelectric capacitor is connected to the word line WL1, the electrode B1 of the second ferroelectric capacitor is connected to the word line WL2, the electrode B1 of the third ferroelectric capacitor is connected to the word line WL3, and the electrode B1 of the fourth ferroelectric capacitor is connected to the word line WL4.

In addition, as shown in fig. 9A, an electrode F1 of the sense transistor in the memory module M1 may be connected to the source line SL1, and an electrode F2 may be connected to the bit line BL1. The gate of the precharge transistor in the memory module M1 may be connected to the control line CL1, and the electrode F2 may be connected to the bit line BL1.

In preparing the memory module M1 shown in fig. 9A, a pre-charge transistor (i.e., transistor T1, the preparation process may be described above with respect to the embodiment shown in fig. 4B) may be prepared on a substrate, then a sense transistor (i.e., transistor T2, the preparation process may be described above with respect to the embodiment shown in fig. 5B) may be prepared on the prepared pre-charge transistor, and then n ferroelectric capacitors may be prepared on the prepared pre-charge transistor.

In the embodiment shown in fig. 9A, the ferroelectric capacitor is fabricated after the transistor, avoiding the ferroelectric property degradation caused by the high temperature stage in the transistor fabrication process. And the transistor is closer to the substrate, therefore, the leads of the bit line, the control line and the source line can be directly pulled down to be connected with the corresponding driving circuits on the substrate, and can be set into shorter lines, so that the path is shortened, and the read-write operation time delay of the memory module M1 can be reduced. Moreover, word lines connected with the electrodes B1 of different ferroelectric capacitors in the n ferroelectric capacitors can be led out from the periphery of the memory module M1 and respectively connected to corresponding driving circuits, so that the driving capability of the electrodes B1 is improved, and the driving time delay is reduced.

In the second example of embodiment 1, the sense transistor may employ a transistor T2, and the precharge transistor may employ a transistor T3. In this example, the electrode A1 of the transistor T3 is used as the electrode F1, and the electrode A2 is used as the electrode F2.

The specific structure can be shown in fig. 9A. In the vertical direction, n ferroelectric capacitors, a sensing transistor and a pre-charge transistor are connected in sequence. Wherein, n ferroelectric capacitors are positioned above the induction transistor, and the pre-charge transistor is positioned below the induction transistor. The gate of the sense transistor penetrates the sense transistor, and therefore the upper end of the gate of the sense transistor is in contact with an electrode B2 shared by n ferroelectric capacitors above, so that connection between the electrode B2 and the gate of the sense transistor is achieved. The lower end of the gate of the sense transistor is in contact with the electrode F1 drawn from the top of the pre-charge transistor so that the electrode F1 of the pre-charge transistor (i.e., the electrode A1 of the transistor T3 serves as the electrode F1) can be connected to the electrode B2 through the gate of the sense transistor. For example, as shown in fig. 9B, the lower end of the gate electrode of the sensing transistor and the electrode F1 of the precharge transistor share one metal electrode to save manufacturing costs and simplify manufacturing processes of the memory module.

The n ferroelectric capacitors in the memory module M1 shown in fig. 9B can be described above, and will not be described herein.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor and the gate electrode F2 of the pre-charge transistor in the memory module M1 shown in fig. 9B can be described with reference to the above, and will not be described herein.

In preparing the memory module M1 shown in fig. 9B, a pre-charge transistor (i.e., transistor T3) may be prepared on the substrate (the preparation process may be referred to above for the embodiment shown in fig. 6B). Then, an induction transistor (i.e., transistor T2, a process for manufacturing which is referred to in the description of the embodiment shown in fig. 5B above) is fabricated on the fabricated precharge transistor. And then n ferroelectric capacitors are prepared in the prepared pre-charge transistor.

The memory module M1 shown in fig. 9B also has the advantages of the memory module M1 shown in fig. 9A, and the description thereof is specifically referred to above, and will not be repeated here.

In embodiment 2, the electrode B2 may be exposed at the upper and lower ends of the ferroelectric capacitor, the gate electrode of the sensing transistor may form the lower end of the sensing transistor, and the electrode F1 of the precharge transistor may form the upper end of the precharge transistor. In this way, the electrode B2 exposed at the upper end of the ferroelectric capacitor can be in contact with the upper end of the induction transistor, and the electrode B2 exposed at the lower end of the ferroelectric capacitor is in contact with the upper end of the pre-charge transistor, so that the induction transistor can be arranged above the ferroelectric capacitor, and the pre-charge transistor is arranged below the induction transistor, thereby realizing the stacking of the ferroelectric capacitor, the induction transistor and the pre-charge transistor in the vertical direction.

In the first example of embodiment 2, the sense transistor may employ the transistor T1, and the precharge transistor may employ the transistor T1. The specific structure is shown in fig. 9C, in which the induction transistor, the n ferroelectric capacitors and the precharge transistor are connected in sequence in the vertical direction. The induction transistor is positioned above the n ferroelectric capacitors, so that a grid electrode led out from the bottom of the induction transistor can be contacted with the top ends of the electrodes B2 of the n ferroelectric capacitors, and the connection between the electrodes B2 and the grid electrode of the induction transistor is realized. The pre-charge transistor is positioned below the n ferroelectric capacitors, so that an electrode F1 led out from the top of the pre-charge transistor can be contacted with the bottom ends of the electrodes B2 of the n ferroelectric capacitors, and the connection between the electrodes B2 and the pre-charge transistor electrode F1 is realized.

The n ferroelectric capacitors in the memory module M1 shown in fig. 9C can be described above, and will not be described herein.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor and the gate electrode F2 of the pre-charge transistor in the memory module M1 shown in fig. 9C can be described with reference to the above, and will not be described herein.

In preparing the memory module M1 shown in fig. 9C, a pre-charge transistor (i.e., transistor T1) may be prepared on the substrate (the preparation process may be referred to above for the embodiment shown in fig. 4B). Then, n ferroelectric capacitors are prepared on the prepared precharge transistor. The sense transistor is then fabricated on n ferroelectric capacitors (i.e., transistor T1, the fabrication process is described above with reference to the embodiment of fig. 4B).

In the embodiment shown in fig. 9C, the sense transistor and the precharge transistor have the same structure, and the difficulty of the memory cell manufacturing process is reduced as a whole. In addition, the induction transistor does not need to bear the high temperature stage of the ferroelectric capacitor preparation process, and the performance degradation of the induction transistor caused by high temperature is avoided.

In a second example of embodiment 2, the sense transistor may employ transistor T1 and the precharge transistor may employ transistor T3. In this example, the electrode A1 of the transistor T3 is used as the electrode F1, and the electrode A2 is used as the electrode F2.

The specific structure is shown in fig. 9D, in which the sense transistor, the n ferroelectric capacitors, and the precharge transistor are sequentially connected in the vertical direction. The induction transistor is positioned above the n ferroelectric capacitors, so that a grid electrode led out from the bottom of the induction transistor can be contacted with the top ends of the electrodes B2 of the n ferroelectric capacitors, and the connection between the electrodes B2 and the grid electrode of the induction transistor is realized. The precharge transistor is located below the n ferroelectric capacitors, whereby the electrode F1 of the precharge transistor (i.e., the electrode A1 of the transistor T3 serves as the electrode F1) led from the top can be contacted with the bottom ends of the electrodes B2 of the n ferroelectric capacitors, enabling connection of the electrodes B2 and the electrodes F1 of the precharge transistor.

The n ferroelectric capacitors in the memory module M1 shown in fig. 9D can be described above, and will not be described herein.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor and the gate electrode F2 of the pre-charge transistor in the memory module M1 shown in fig. 9D can be described with reference to the above, and will not be described herein.

In preparing the memory module M1 shown in fig. 9D, a pre-charge transistor (i.e., transistor T3) may be prepared on the substrate (the preparation process may be referred to above for the embodiment shown in fig. 6B). Then, n ferroelectric capacitors are prepared on the prepared precharge transistor. The sense transistor is then fabricated on n ferroelectric capacitors (i.e., transistor T1, the fabrication process is described above with reference to the embodiment of fig. 4B).

In the embodiment shown in fig. 9D, the sense transistor does not undergo the high temperature phase of the ferroelectric capacitor fabrication process, avoiding degradation of the sense transistor performance due to high temperature.

In embodiment 3, the electrode B2 may be exposed at the upper end of the ferroelectric capacitor, the gate electrode of the sensing transistor may form the upper and lower ends of the sensing transistor, and the electrode F1 of the precharge transistor may form the lower end of the precharge transistor. In this way, the electrode B2 of the ferroelectric capacitor exposed at the upper end may be in contact with the lower end of the sense transistor, and the upper end of the sense transistor is in contact with the lower end of the precharge transistor. Therefore, the induction transistor can be arranged above the ferroelectric capacitor, the pre-charge transistor is arranged above the induction transistor, and the ferroelectric capacitor, the induction transistor and the pre-charge transistor are stacked in the vertical direction. In addition, the gate of the sense transistor also extends through the sense transistor, so that the electrode F1 of the precharge transistor can be connected to the electrode B2 of the ferroelectric capacitor through the gate of the sense transistor.

In the first example of embodiment 3, the sense transistor may employ a transistor T2 and the precharge transistor may employ a transistor T3. In this example, the electrode A2 of the transistor T3 is used as the electrode F1, and the electrode A1 is used as the electrode F2. The specific structure is shown in fig. 9E, in which the precharge transistor, the sense transistor and the n ferroelectric capacitors are sequentially connected in the vertical direction. The sensing transistor is positioned above the n ferroelectric capacitors, and the grid electrode of the sensing transistor penetrates through the sensing transistor. Therefore, the lower end of the grid electrode of the induction transistor can be contacted with the upper ends of the electrodes B2 of the n ferroelectric capacitors, and the connection between the electrodes B2 and the grid electrode of the induction transistor is realized. The precharge transistor is located above the sense transistor, whereby the electrode F1 of the precharge transistor drawn from the top (i.e., the electrode A2 of the transistor T3 serves as the electrode F1) may be in contact with the upper end of the gate of the sense transistor, so that the electrode F1 of the precharge transistor may be connected to the electrode B2 through the gate of the sense transistor. Illustratively, as shown in fig. 9E, the upper end of the gate electrode of the sensing transistor and the electrode F1 of the precharge transistor share one metal electrode, so as to save manufacturing costs and simplify manufacturing processes of the memory module.

The n ferroelectric capacitors in the memory module M1 shown in fig. 9E can be described above, and will not be described herein.

The circuit connection of the electrode F1 and the electrode F2 of the sensing transistor and the gate electrode F2 of the pre-charge transistor in the memory module M1 shown in fig. 9E can be described with reference to the above, and will not be described herein.

In preparing the memory module M1 shown in fig. 9E, n ferroelectric capacitors may be first prepared on a substrate. Then, the sense transistor is fabricated on n ferroelectric capacitors (i.e., transistor T2, the fabrication process is described above with reference to the embodiment shown in fig. 5B). A pre-charge transistor (i.e., transistor T3) is then fabricated on the fabricated sense transistor (the fabrication process is described above with reference to the embodiment of fig. 6B).

In the embodiment shown in fig. 9E, when n ferroelectric capacitors are fabricated, the bottom of the columnar electrode is not opened, so that the bottom opening etching process of the columnar electrode can be avoided, the ferroelectric layer of the sidewall is damaged, and further, the ferroelectric performance degradation caused by the damage is avoided.

The memory module provided by the embodiment of the application can stack the transistor and at least one ferroelectric capacitor in the vertical direction, and the transistor is of a vertical structure, so that the integrated area of a substrate can be saved, and the memory density and capacity of the ferroelectric memory are improved.

A plurality of memory modules having a 2TnC structure may be integrated on one substrate. In some embodiments, referring to fig. 10, using the memory module shown in fig. 9A as an example, a plurality of memory modules may be integrated on a substrate. Memory modules integrated onto the same substrate may be referred to as an array of memory modules.

The ferroelectric capacitors in the memory module array may be divided into a plurality of ferroelectric capacitor sets according to whether the word lines are identical. In other words, the same ferroelectric capacitances of word lines in the memory module array can be divided into the same ferroelectric capacitance set. Wherein each ferroelectric capacitor set comprises at least one ferroelectric capacitor. Wherein the ferroelectric capacitors in each set of ferroelectric capacitors are connected to the same word line and are different from the word lines connected to the ferroelectric capacitors in the other sets (the ferroelectric capacitors are connected to the word line specifically through their electrodes B1). For example, electrode B1 of a ferroelectric capacitor in one set of ferroelectric capacitors is connected to word line WL1, electrode B1 of a ferroelectric capacitor in the other set of ferroelectric capacitors is connected to word line WL2, electrode B1 of a ferroelectric capacitor in the other set of ferroelectric capacitors is connected to word line WL3, and electrode B1 of a ferroelectric capacitor in the other set of ferroelectric capacitors is connected to word line WL4. Word line WL1, word line WL2, word line WL3, and word line WL4 are all different word lines.

In addition, in the embodiment of the present application, "shared" means "same", "A1 and A1 share B" means "B of A1 and B of A2 are the same".

Illustratively, different word lines correspond to different metal plates, which are connected to different word line driving circuits. The word lines may be connected to the corresponding metal plates, and thus connected to the corresponding word line driving circuits through the metal plates. Thus, the corresponding word line can be controlled by the word line driving circuit. In one example, the metal plates may be disposed above the corresponding word lines, whereby the word lines may be connected upward to the corresponding metal plates.

For example, before the preparation of the pre-charge transistor, a plurality of metal plates E1 may now be deposited on the substrate, the plurality of metal plates E1 being parallel to the upper surface of the substrate, and the plurality of metal plates E1 being parallel to each other and insulated from each other. The plurality of metal plates E1 are used as different bit lines, respectively. Such as bit lines BL1, BL2, and BL3 shown in fig. 10. Wherein the electrode F2 of the pre-charge transistor and the electrode F2 of the sense transistor may be connected to the corresponding metal plate E1 by wires. Wherein the metal plate E1 may be connected to a BL driving circuit on the circuit board through a wire. The circuit board is used for bearing a substrate.

An insulating layer is deposited on the plurality of metal plates E1, and the plurality of metal plates E2 are deposited on top of the insulating layer. The plurality of metal plates E2 are uniformly arranged on the upper surface of the substrate in parallel, and the plurality of metal plates E2 are mutually parallel and mutually insulated. Illustratively, the metal plates E1 and E2 are perpendicular to each other. The plurality of metal plates E2 serve as different control lines, respectively. Such as bit lines CL1, CL2, and CL3 shown in fig. 10. Wherein the metal plate E2 may be connected to a CL driving circuit on the circuit board through a wire.

Thereafter, a metal electrode serving as a gate electrode of the precharge transistor may be deposited on the metal plate E2, thereby preparing a memory module according to the embodiment of fig. 4B. And will not be described in detail herein.

With continued reference to fig. 10, the electrodes B2 of the ferroelectric capacitors of the same word line are different. Moreover, the control lines and the bit lines corresponding to the same ferroelectric capacitors of the word lines are not identical at the same time. That is, control lines of some of the plurality of ferroelectric capacitors having the same word line are the same, but bit lines of the ferroelectric capacitors having the same control lines are different. For example, as shown in fig. 10, among the ferroelectric capacitors sharing the word line WL1, there are 3 ferroelectric capacitors sharing the control line CL1, and the 3 ferroelectric capacitors are connected to the bit lines BL1, BL2, BL3, respectively. For another example, among the ferroelectric capacitors sharing the word line WL1, 3 ferroelectric capacitors sharing the control line CL2 are connected to the bit lines BL1, BL2, BL3, respectively. For another example, among the ferroelectric capacitors sharing the word line WL1, 3 ferroelectric capacitors sharing the control line CL3 are connected to the bit lines BL1, BL2, BL3, respectively. For another example, among the ferroelectric capacitors sharing the word line WL1, 3 ferroelectric capacitors sharing the control line CL4 are connected to the bit lines BL1, BL2, BL3, respectively.

In addition, as shown in fig. 10, the bit lines of the ferroelectric capacitors having the same control lines are the same. For example, the ferroelectric capacitor sharing the bit line BL1 also shares the source line SL1, the ferroelectric capacitor sharing the bit line BL2 also shares the source line SL2, and the ferroelectric capacitor sharing the source line BL3 also shares the source line SL3.

From the above description, it can be seen that in the memory array, the different ferroelectric capacitor electrodes B1, B2, control lines, bit lines are not identical at the same time. Therefore, when performing read-write operation, different ferroelectric capacitances or selected ferroelectric capacitances can be distinguished by the electrode B1, the electrode B2, the control line and the bit line, and the selected ferroelectric capacitances are operated.

Next, the working principle of the ferroelectric capacitor is illustrated by combining a schematic diagram of the circuit connection mode of the memory array and an operation truth table.

Fig. 11 shows a partial circuit connection of a memory array. In which the same word line (word line WL1 or word line WL2 or word line WL3 or word line WL 4) is shared, and the control line CL1 and the control line CL2, and the bit lines BL1 and BL2 are respectively connected by different precharge transistors. Sharing the same word line corresponds to source line SL1 and source line SL2 through different pre-charge transistors. The electrodes B2 sharing the same word line are different.

Hereinafter, ferroelectric capacitor C1, ferroelectric capacitor C2, ferroelectric capacitor C3, and ferroelectric capacitor C4 sharing word line WL1 are exemplified.

Ferroelectric capacitor C1 corresponds to control line CL1, bit line BL2, and source line SL2.

The ferroelectric capacitor C2 corresponds to the control line CL1, the bit line BL1, and the source line SL1.

Ferroelectric capacitor C3 corresponds to control line CL2, bit line BL1, and source line SL1.

Ferroelectric capacitor C4 corresponds to control line CL2, bit line BL2, and source line SL2.

Next, with reference to fig. 12, the operation principle of the ferroelectric capacitor will be described by taking the operation of the ferroelectric capacitor C1 as an example. The electrode F1 may be a source electrode, and the electrode F2 may be a drain electrode.

Fig. 12 shows one possible operating truth table. Binary data can be stored in the ferroelectric capacitor by this operation truth table. Specifically, the following is described.

A write 0 operation or a write 1 operation may be performed on the ferroelectric capacitor C1, i.e., 0 is written to the ferroelectric capacitor C1 or 1 is written to the ferroelectric capacitor C1. It may be set to perform a write 0 operation on the ferroelectric capacitor C1. A voltage Vw may be applied to the word line WL 1; applying a voltage Vdd to the control line CL 1; the voltage V0 is applied to the bit line BL2, and then the voltage Vw is applied; the voltage V0 is applied to the source line BL2, and then the voltage Vw is applied; the voltage V0 is applied to the electrode B2 of the ferroelectric capacitor C1, and then the voltage Vw is applied. Thereby, the crystal center atoms in the ferroelectric layer of the ferroelectric capacitor C1 can be brought into a polarization state representing 0.

Where the voltage Vdd may be referred to as the highest voltage. In one example, the voltage Vdd is 2.5V. The voltage Vw may be referred to as a write voltage. In one example, the voltage Vw is 2V. The voltage V0 is zero voltage, i.e., the voltage V0 is 0V.

In the case of performing the write 0 operation on the ferroelectric capacitor C1 as described above, the electrode B2 is subjected to the operation of the voltage V0 and then the voltage Vw, and in order to avoid this operation, the voltage Vw/2 may be applied to the word line (i.e., unsel WL corresponding to C1 in fig. 12) of the other ferroelectric capacitor sharing the electrode B2 with the ferroelectric capacitor C1, which affects the other ferroelectric capacitor sharing the electrode B2 with the ferroelectric capacitor C1. The voltage Vw/2 may be referred to as a half-select voltage, which is half the voltage Vw. Wherein "unsel" in fig. 12 indicates unselected.

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1. During the write 0 operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 and the voltage applied to the control line CL1 on the ferroelectric capacitor C2, the voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C2), the voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C2), and the voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C2 in fig. 12).

Ferroelectric capacitor C3 and ferroelectric capacitor C1 share word line WL1. During the write 0 operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, a voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C3), and a voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C3 (i.e., the unsel electrode B2 corresponding to the C3 in fig. 12).

Ferroelectric capacitor C4 and ferroelectric capacitor C1 share word line WL1, bit line BL2 and source line SL2. During the write 0 operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1, the voltage applied to the bit line BL2, and the voltage applied to the source line SL2 on the ferroelectric capacitor C4, the voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C4), and the voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in fig. 12).

The above examples describe the specific manner of operation of the ferroelectric capacitor C1 and the manner of operation of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 when the write 0 operation is performed on the ferroelectric capacitor C1.

Next, an example is described in which, when the write 1 operation is performed on the ferroelectric capacitor C1, a specific operation manner is performed on the ferroelectric capacitor C1, and an operation manner of the ferroelectric capacitor which may be affected by the ferroelectric capacitor C1.

With continued reference to fig. 12, a write 1 operation may be performed on ferroelectric capacitor C1. A voltage V0 may be applied to the word line WL 1; applying a voltage Vdd to the control line CL 1; the voltage V0 is applied to the bit line BL2, and then the voltage Vw is applied; the voltage V0 is applied to the source line BL2, and then the voltage Vw is applied; the voltage V0 is applied to the electrode B2 of the ferroelectric capacitor C1, and then the voltage Vw is applied. Thereby, the crystal center atoms in the ferroelectric layer of the ferroelectric capacitor C1 can be brought to another polarization state, which represents 1.

In the write 1 operation on the ferroelectric capacitor C1, the electrode B2 is operated with the voltage V0 and then with the voltage Vw, and in order to avoid the influence of the operation on the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1, the voltage Vw/2 may be applied to the word line (i.e., unsel WL corresponding to C1 in fig. 12) of the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1.

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1. During the write 1 operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 and the voltage applied to the control line CL1 on the ferroelectric capacitor C2, the voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C2), the voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C2), and the voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C2 in fig. 12).

Ferroelectric capacitor C3 and ferroelectric capacitor C1 share word line WL1. During the write 1 operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, a voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C3), and a voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C3 (i.e., the unsel electrode B2 corresponding to the C3 in fig. 12).

Ferroelectric capacitor C4 and ferroelectric capacitor C1 share word line WL1, bit line BL2 and source line SL2. During the write 1 operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the bit line BL2 and the voltage applied to the source line SL2 on the ferroelectric capacitor C4, a voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C4) and a voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in fig. 12).

The above examples describe the specific manner of operation of the ferroelectric capacitor C1 and the manner of operation of the ferroelectric capacitor C1 that may be affected by the ferroelectric capacitor C1 when the write 1 operation is performed on the ferroelectric capacitor C1.

After the writing operation is performed on the ferroelectric capacitor, the ferroelectric capacitor is usually subjected to a standby pre-charge operation, so that the ferroelectric capacitor is in a standby state. The standby state is a state of waiting for operation, and in the standby state, the influence of the operating voltage of other ferroelectric capacitors is also prevented, so that the standby prediction operation is performed, and a specific voltage is applied to the ferroelectric capacitors to prevent the influence of the operating voltage of other ferroelectric capacitors.

Next, examples are presented of the standby precharge operation on the ferroelectric capacitor C1, and the operation of the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 during the standby precharge operation on the ferroelectric capacitor C1.

With continued reference to fig. 12, a standby precharge operation may be performed on the ferroelectric capacitor C1. The voltage Vw/2 may be applied to the word line WL 1; applying a voltage Vdd to the control line CL 1; applying a voltage Vw/2 to the bit line BL 2; applying a voltage Vw/2 to the source line BL 2; a voltage Vw/2 is applied to electrode B2 of ferroelectric capacitor C1. Thereby, the standby precharge operation on the ferroelectric capacitor C1 is completed.

When the ferroelectric capacitor C1 is subjected to the standby precharge operation, the voltage Vw/2 is applied to the electrode B2, and in order to avoid the influence of the operation on the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1, the voltage Vw/2 may be applied to the word line (i.e., unsel WL corresponding to C1 in fig. 12) of the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1.

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1. During the standby precharge operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 and the voltage applied to the control line CL1 on the ferroelectric capacitor C2, the voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C2), the voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C2), and the voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C2 in fig. 12).

Ferroelectric capacitor C3 and ferroelectric capacitor C1 share word line WL1. During the standby precharge operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, the voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C3), the voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C3), the voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C3), and the voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C3 (i.e., the unsel electrode B2 corresponding to the C3 in fig. 12).

Ferroelectric capacitor C4 and ferroelectric capacitor C1 share word line WL1, bit line BL2 and source line SL2. During the standby precharge operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the bit line BL2 and the voltage applied to the source line SL2 on the ferroelectric capacitor C4, the voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C4) and the voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in fig. 12).

Before the reading operation of the ferroelectric capacitor, the reading pre-charge operation is usually performed on the ferroelectric capacitor, so that the voltage of the electrode B2 of the ferroelectric capacitor is raised to Vw, the voltage of the WL1 (i.e. the electrode B1) is set to Vw/2, and therefore, in the subsequent reading operation, the voltage of the WL1 is lowered to V0, so that the voltage difference between two ends of the ferroelectric capacitor can reach Vw, and the polarization state of the iron atom in the center of the crystal can be changed, and the reading of signals is realized. The process of signal reading will be described below, and will not be described herein.

Next, examples are presented of a read precharge operation on the ferroelectric capacitor C1, and an operation on the ferroelectric capacitor that may be affected by the ferroelectric capacitor C1 during a standby precharge operation on the ferroelectric capacitor C1.

With continued reference to fig. 12, a read precharge operation may be performed on ferroelectric capacitor C1. The voltage Vw/2 may be applied to the word line WL 1; applying a voltage Vdd to the control line CL 1; applying a voltage Vw to the bit line BL 2; applying a voltage Vw to the source line BL 2; a voltage Vw is applied to the electrode B2 of the ferroelectric capacitor C1. Thereby, the read precharge operation on the ferroelectric capacitor C1 is completed.

In the case of performing the read precharge operation on the ferroelectric capacitor C1, the voltage Vw is applied to the electrode B2, and in order to avoid the influence of the operation on the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1, the voltage Vw/2 may be applied to the word line (i.e., unsel WL corresponding to C1 in fig. 12) of the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1.

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1. During the read precharge operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 and the voltage applied to the control line CL1 on the ferroelectric capacitor C2, the voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C2), the voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C2), and the voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C2 in fig. 12).

Ferroelectric capacitor C3 and ferroelectric capacitor C1 share word line WL1. During the read precharge operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, a voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C3), and a voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C3 (i.e., the unsel electrode B2 corresponding to the C3 in fig. 12).

Ferroelectric capacitor C4 and ferroelectric capacitor C1 share word line WL1, bit line BL2 and source line SL2. During the read precharge operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the bit line BL2 and the voltage applied to the source line SL2 on the ferroelectric capacitor C4, a voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C4) and a voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C2 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C4 in fig. 12).

The above examples describe the specific manner of operation of the ferroelectric capacitor C1 and the manner of operation of the ferroelectric capacitor C1 that may be affected by the ferroelectric capacitor C1 when the read precharge operation is performed on the ferroelectric capacitor C1.

Next, a specific operation manner of the read operation (i.e., the operation of reading 0/1 or the operation of reading the signal) on the ferroelectric capacitor C1, and an operation manner of the ferroelectric capacitor that may be affected on the ferroelectric capacitor C1 will be described as an example.

In performing a read operation on the ferroelectric capacitor C1, a known voltage may be applied to the ferroelectric capacitor C1. The known voltage may cause the crystal center iron atom to reach a polarization state, e.g., setting the known voltage causes the crystal center iron atom to reach polarization state D1, and the ferroelectric capacitor records a bit value of 1 when the crystal center iron atom is in polarization state D1. If the polarization state of the iron atom at the center of the crystal of the ferroelectric field C1 is also the polarization state D1. Then after the voltage is applied to the ferroelectric capacitor C1, the bit value recorded by the ferroelectric capacitor C1 can be determined by detecting whether the polarization state of the iron atom in the center of the crystal is changed. Wherein the potential of the electrode B2 changes when the polarization state of the iron atom in the center of the crystal changes. The sense transistor can sense a potential change and the potential change is converted into a current. This current can be detected by a Sense Amplifier (SA). Thus, when the sense amplifier does not detect the current, it can be known that the polarization state of the iron atom in the center of the crystal is not changed. When the sense amplifier detects this current, it can be known that the polarization state of the iron atoms in the center of the crystal has changed. Thereby, the bit value recorded by the ferroelectric capacitor C1 is determined.

With continued reference to fig. 12, the known voltage applied by the read operation may be set to a voltage that causes the central iron atom of the crystal to reach polarization state D1, and ferroelectric capacitor C1 records a 1 when the central iron atom of the crystal is in polarization state D1. The specific operation mode of the read operation is that a voltage V0 is applied to the word line WL 1; applying a voltage V0 to the control line CL 1; applying a voltage Vw to the bit line BL 2; applying a voltage Vw/2 to the source line BL 2; the voltage Vpre is applied to the electrode B2 of the ferroelectric capacitor C1, and then the voltage Vw is applied. If the sense amplifier does not detect a corresponding spike, a bit value of 1 recorded by ferroelectric capacitor C1 may be obtained. If the sense amplifier detects a corresponding spike, it can be obtained that the ferroelectric capacitor C1 records a bit value of 0.

The voltage Vpre may also be referred to as a precharge voltage. In one example, the voltage Vpre is 1.6V.

In the case of performing a read operation on the ferroelectric capacitor C1, the voltage Vw is applied to the electrode B2, and in order to avoid the effect of the read operation on the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1, the voltage Vw/2 may be applied to the word line (i.e., unsel WL corresponding to C1 in fig. 12) of the other ferroelectric capacitors sharing the electrode B2 with the ferroelectric capacitor C1.

The ferroelectric capacitor C2 and the ferroelectric capacitor C1 share the word line WL1 and the control line CL1. During a read operation on ferroelectric capacitor C1, in order to avoid the effect of the voltage applied to word line WL1 and the voltage applied to control line CL1 on ferroelectric capacitor C2, voltage Vw/2 may be applied to bit line BL1 (i.e., the bit line corresponding to ferroelectric capacitor C2), voltage Vw/2 may be applied to source line SL1 (i.e., the source line corresponding to ferroelectric capacitor C2), and voltage Vw/2 may be applied to electrode B2 of ferroelectric capacitor C2 (i.e., unsel electrode B2 corresponding to ferroelectric capacitor C2 in fig. 12).

Ferroelectric capacitor C3 and ferroelectric capacitor C1 share word line WL1. During the read operation on the ferroelectric capacitor C1, in order to avoid the influence of the voltage applied to the word line WL1 on the ferroelectric capacitor C3, a voltage V0 may be applied to the control line CL2 (i.e., the control line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the bit line BL1 (i.e., the bit line corresponding to the ferroelectric capacitor C3), a voltage Vw/2 may be applied to the source line SL1 (i.e., the source line corresponding to the ferroelectric capacitor C3), and a voltage Vw/2 may be applied to the electrode B2 of the ferroelectric capacitor C3 (i.e., the unsel electrode B2 corresponding to the ferroelectric capacitor C3 in fig. 12).

Ferroelectric capacitor C4 and ferroelectric capacitor C1 share word line WL1, bit line BL2 and source line SL2. During a read operation on ferroelectric capacitor C1, in order to avoid the effect of the voltage applied to word line WL1 on bit line BL2 and the voltage applied to source line SL2 on ferroelectric capacitor C4, voltage V0 may be applied to control line CL2 (i.e., the control line corresponding to ferroelectric capacitor C4) and voltage Vw/2 may be applied to electrode B2 of ferroelectric capacitor C2 (i.e., unsel electrode B2 corresponding to ferroelectric capacitor C4 in fig. 12).

As described above, the read operation may cause the polarization state of the crystal center iron atom of the ferroelectric capacitor C1 to change. For example, when the voltage applied by the read operation is the voltage applied by the write 1 operation and the bit value recorded by the ferroelectric capacitor C1 is 0, the read operation causes the polarization state of the crystal center iron atom of the ferroelectric capacitor C1 to change. That is, the read operation causes the information recorded by the ferroelectric capacitor C1 to be changed. Therefore, after the read operation, a write-back operation is required. Wherein the voltage of the write-back operation is another known voltage. When the known voltage of the read operation is the voltage of the write 1 operation, then the voltage of the write back operation is the voltage of the write 0 operation. When the known voltage for the read operation is the voltage for the write 0 operation, then the voltage for the write back operation is the voltage for the write 1 operation.

With continued reference to fig. 12, the known voltage for the write back operation may be set to the voltage for the write 0 operation, i.e., the write back operation is the write back 0 operation. The operation of writing back 0, i.e. writing 0 operation, may refer to the description of writing 0 operation, and will not be repeated here.

After the operation of writing back 0 is completed, the ferroelectric capacitor C1 may be subjected to a standby precharge operation again. Reference may be made specifically to the description of the standby precharge operation above, and no further description is given here.

In some embodiments, the ferroelectric capacitor C1 may also be standby-operated. The standby operation is an operation of placing the ferroelectric capacitor C1 in a standby state. The ferroelectric capacitor C1 is in the standby state, which means that the read-write operation and the standby precharge operation and the read precharge operation are not performed on the ferroelectric capacitor. When the ferroelectric capacitor C1 is in the standby state, other ferroelectric capacitors sharing the word line WL1 with the ferroelectric capacitor C1 are also in the standby state.

Next, the voltage applied by the standby operation will be described with reference to fig. 12.

Taking the ferroelectric capacitor C1 as an example, the voltage Vw/2 may be applied to the word line (WL 1), the bit line (BL 2), the source line (SL 2), and the electrode B2 of the ferroelectric capacitor C1, and the voltage V0 may be applied to the control line (CL 1) of the ferroelectric capacitor C1 to perform the standby operation.

During the standby operation on the ferroelectric capacitor C1, the voltage Vw/2 may be applied to the word line of the other ferroelectric capacitor sharing the electrode B2 with the ferroelectric capacitor C1 (i.e., the unsel WL corresponding to C1 in fig. 12).

During standby operation of the ferroelectric capacitor C1, operations of the ferroelectric capacitor C2, the ferroelectric capacitor C3, and the ferroelectric capacitor C4 are the same as operations applied to the ferroelectric capacitor C1, and will not be described in detail.

The above description has been made with respect to the operation of a ferroelectric capacitor in a memory module array, taking the ferroelectric capacitor C1 as an example. The operation of the other ferroelectric capacitors in the memory module array may be implemented with reference to the ferroelectric capacitor C1, which is not described herein in detail.

The transistor with the vertical structure and at least the ferroelectric capacitor provided by the embodiment of the application can be stacked in the vertical direction, so that the integrated area of a substrate can be saved, and the storage density and capacity of the ferroelectric memory are improved.

The application of the vertical structure transistor provided by the embodiment of the application in preparing the ferroelectric memory is introduced. And are not limited to vertical structure crystals for other types of memory applications.

In some embodiments, transistor T1, transistor T2, or transistor T3 may be used as a transistor in a DRAM memory to enable three-dimensional stacking of memory components in the DRAM memory to increase the memory density of the DRAM memory.

In some embodiments, transistor T1, transistor T2, or transistor T3 may be used as a transistor in a phase change memory (phase change memory, PCM) memory to increase the storage density of the phase change memory in a three-dimensional stack of the memory components of the phase change memory.

In some embodiments, the transistor T1, the transistor T2, or the transistor T3 may be used as a transistor in a resistance random access memory (ReRAM) memory to realize three-dimensional stacking of memory components of the resistance random access memory, and to increase the memory density of the memory components of the resistance random access memory.

In some embodiments, transistor T1, transistor T2, or transistor T3 may be used as a transistor in a magnetic memory (magnetic random access memory, MRAM) memory to enable three-dimensional stacking of the memory components of the magnetic memory, increasing the memory density of the memory components of the magnetic memory.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

It is understood that in the description of embodiments of the application, words such as "exemplary," "such as" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, the term "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a alone, B alone, and both A and B. In addition, unless otherwise indicated, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of terminals means two or more terminals.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

It should be understood that the above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A ferroelectric memory, comprising:

a substrate;

word line WL, source line SL, bit line BL and control line CL;

a first ferroelectric capacitor, a first transistor, and a second transistor stacked in a vertical direction; wherein,

the first ferroelectric capacitor comprises a first electrode and a second electrode; wherein the first electrode is connected with the word line, and the second electrode is exposed at the lower end and/or the upper end of the first ferroelectric capacitor;

a first electrode of the first transistor is connected with the source line, a second electrode is connected with the bit line, and a grid electrode is contacted with the second electrode; the channel layer of the first transistor is arranged along the vertical direction, and the grid electrode of the first transistor forms the upper end and/or the lower end of the first transistor;

the grid electrode of the second transistor is connected with the control line, the second electrode is connected with the bit line, and the first electrode is contacted with the second electrode or the grid electrode of the first transistor; wherein the channel layer of the second transistor is arranged along the vertical direction, and the first electrode of the second transistor forms the upper end or the lower end of the second transistor;

Wherein the vertical direction is perpendicular to the surface of the substrate, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate; the first transistor and the second transistor are manufactured by adopting a back-end process.
The ferroelectric memory according to claim 1, wherein the second electrode is exposed at a lower end of the first ferroelectric capacitor, wherein a gate of the first transistor forms an upper end and a lower end of the first transistor, and wherein a first pole of the second transistor forms an upper end of the second transistor; the first ferroelectric capacitor is located above the first transistor, the second transistor is located below the first transistor, the upper side is far away from the substrate, and the lower side is close to the substrate.
The ferroelectric memory of claim 2, wherein the first transistor comprises:

a first channel layer disposed along the vertical direction;

a first gate oxide layer surrounded by the first channel layer;

a first gate penetrating the first gate oxide and protruding from upper and lower ends of the first gate oxide;

A first pole and a second pole surrounding the first channel layer.
The ferroelectric memory of claim 3, wherein the second transistor comprises:

a second channel layer disposed along the vertical direction;

a second gate oxide layer surrounded by the second channel layer;

a second gate electrode, a part of which is surrounded by the second gate oxide layer and another part of which protrudes from the lower end of the second gate oxide layer;

a first electrode located at an upper end of the second channel layer and insulated from the second gate electrode;

a second pole surrounding the second channel layer.
The ferroelectric memory of claim 3, wherein the second transistor comprises:

a third channel layer disposed along the vertical direction;

a first electrode located at an upper end of the third channel layer;

a second pole located at the lower end of the third channel layer;

and a third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer.
The ferroelectric memory according to claim 1, wherein the second electrode is exposed at an upper end and a lower end of the first ferroelectric capacitor, wherein a gate of the first transistor forms a lower end of the first transistor, and wherein a first pole of the second transistor forms an upper end of the second transistor; the first transistor is located above the first ferroelectric capacitor, the second transistor is located below the first ferroelectric capacitor, the upper side is far away from the substrate, and the lower side is close to the substrate.
The ferroelectric memory of claim 6, wherein said first transistor and said second transistor each adopt a first structure;

the first structure includes:

a second channel layer disposed along the vertical direction;

a second gate oxide layer surrounded by the second channel layer;

a second gate electrode, a part of which is surrounded by the second gate oxide layer and another part of which protrudes from the lower end of the second gate oxide layer;

a first electrode located at an upper end of the second channel layer and insulated from the second gate electrode;

a second pole surrounding the second channel layer.
The ferroelectric memory according to claim 6, wherein,

the first transistor includes:

a second channel layer disposed along the vertical direction;

a second gate oxide layer surrounded by the second channel layer;

a second gate electrode, a part of which is surrounded by the second gate oxide layer and another part of which protrudes from the lower end of the second gate oxide layer;

a first electrode located at an upper end of the second channel layer and insulated from the second gate electrode;

a second pole surrounding the second channel layer;

the second transistor includes:

a third channel layer disposed along the vertical direction;

A first electrode located at an upper end of the third channel layer;

a second pole located at the lower end of the third channel layer;

and a third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer.
The ferroelectric memory of claim 1, wherein the second electrode is exposed at an upper end of the first ferroelectric capacitor, a gate of the first transistor forms an upper end and a lower end of the first transistor, and a first pole of the second transistor forms a lower end of the second transistor; wherein the first transistor is located above the first ferroelectric capacitor, the second transistor is located above the first transistor, and the upper side is a side far away from the substrate.
The ferroelectric memory according to claim 9, wherein,

the first transistor includes:

a first channel layer disposed along the vertical direction;

a first gate oxide layer surrounded by the first channel layer;

a first gate penetrating the first gate oxide and protruding from upper and lower ends of the first gate oxide;

a first pole and a second pole surrounding the first channel layer;

The second transistor includes:

a third channel layer disposed along the vertical direction;

a second pole located at the upper end of the third channel layer;

a first electrode located at a lower end of the third channel layer;

and a third gate surrounding the third channel layer, wherein a third gate oxide layer is provided between the third gate and the third channel layer.
The ferroelectric memory of any one of claims 1-10, wherein the ferroelectric memory comprises a plurality of word lines; the first ferroelectric capacitor includes a plurality of ferroelectric capacitors stacked in the vertical direction, wherein first electrodes of different ones of the plurality of ferroelectric capacitors are connected to different ones of the plurality of word lines, the plurality of ferroelectric capacitors sharing the second electrode.
The ferroelectric memory of claim 11, wherein the plurality of ferroelectric capacitors comprises:

a columnar electrode extending in the vertical direction, the columnar electrode serving as the second electrode;

a ferroelectric layer surrounding the columnar electrode;

a plurality of electrode layers surrounding the ferroelectric layer, wherein adjacent two electrode layers are separated by an insulating material, different ones of the plurality of electrode layers serving as first electrodes of different ones of the plurality of ferroelectric capacitors.
A transistor, comprising:

a channel layer disposed in a vertical direction;

a gate oxide layer surrounded by the channel layer;

a gate electrode, a part of which is surrounded by the gate oxide layer and another part of which protrudes from the lower end of the gate oxide layer;

a first electrode positioned at the upper end of the channel layer, and insulated from the grid electrode;

a second pole surrounding the channel layer and spaced from the first pole;

the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate.
The transistor of claim 13, wherein the channel layer is made of an N-type lightly doped semiconductor material, the first pole comprising a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of an N-type heavily doped semiconductor material, the N-type heavily doped region being in contact with the channel layer.
A transistor, comprising:

a channel layer disposed in a vertical direction;

a gate oxide layer surrounded by the channel layer;

a gate penetrating the gate oxide layer and protruding from upper and lower ends of the gate oxide layer;

A first pole and a second pole surrounding the channel layer, a space being present between the first pole and the second pole;

the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate.
The transistor of claim 15, wherein the channel layer is made of an N-type lightly doped semiconductor material, the first pole comprising a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of an N-type heavily doped semiconductor material, the N-type heavily doped region being in contact with the channel layer.
A transistor, comprising:

a channel layer disposed in a vertical direction; the insulator is filled in the channel layer, and the vertical direction is perpendicular to the surface of the substrate where the transistor is located;

a third electrode positioned at the upper end of the channel layer;

a fourth electrode positioned at the lower end of the channel layer;

a gate surrounding the channel layer, wherein a gate oxide layer is provided between the gate and the channel layer, a space exists between the gate and the third electrode, and a space exists between the gate and the fourth electrode; the vertical direction is perpendicular to the surface of the substrate where the transistor is located, the upper end is the end far away from the substrate, and the lower end is the end close to the substrate;

The third pole acts as a first pole of the transistor and the fourth pole acts as a second pole of the transistor; alternatively, the third pole serves as the second pole of the transistor and the fourth pole serves as the first pole of the transistor; or alternatively.
The transistor of claim 17, wherein the channel layer is made of an N-type lightly doped semiconductor material, the third electrode and/or the fourth electrode comprising a metal electrode and an N-type heavily doped region, wherein the N-type heavily doped region is made of an N-type heavily doped semiconductor material, the N-type heavily doped region being in contact with the channel layer.