WO2023134161A1

WO2023134161A1 - Transistor and manufacturing method therefor

Info

Publication number: WO2023134161A1
Application number: PCT/CN2022/111498
Authority: WO
Inventors: 罗杰
Original assignee: 北京超弦存储器研究院
Priority date: 2022-01-14
Filing date: 2022-08-10
Publication date: 2023-07-20
Also published as: CN116207132B; CN116207132A

Abstract

A transistor and a manufacturing method therefor. The transistor comprises at least one sub-transistor unit. Each sub-transistor unit comprises a gate electrode layer and a semiconductor layer which are arranged on a substrate, the gate electrode being insulated from the semiconductor layer. The semiconductor layer comprises a first part and a second part, the first part being located on the side of the gate electrode layer away from the substrate, the orthographic projection of the first part on the substrate overlapping the orthographic projection of at least part of the gate electrode layer on the substrate, the second part being located on the side of the gate electrode layer close to the substrate, and the orthographic projection of the second part on the substrate overlapping the orthographic projection of at least part of the gate electrode layer on the substrate.

Description

Transistor and its manufacturing method

This application claims the priority of the Chinese patent application with the application number 202210044694.3 and the title of the invention "Thin Film Transistor and Its Preparation Method" submitted to the China Patent Office on January 14, 2022, the contents of which should be understood to be incorporated by reference In this application.

technical field

Embodiments of the present disclosure relate to but are not limited to the semiconductor field, and specifically relate to a transistor and a manufacturing method thereof.

Background technique

As the integration of the chip becomes higher, the structure of the transistor changes from planar, FinFET to GAA node. The core idea is to maintain the control of the gate electrode layer on the channel (the contact area between the gate electrode layer and the channel), and the transistor device make small. As transistor devices continue to get smaller, the process size becomes smaller, and the manufacturing difficulty increases. The transistor device itself also has performance problems, such as insufficient turn-on current; the gate electrode layer is not easy to turn off, and the leakage increases; the distance between the transistor devices is too close, and the mutual influence increases.

At present, the source, gate electrode layer, and drain of a single transistor made of indium gallium zinc oxide (IGZO) are tiled on the substrate, and the projected area on the substrate is relatively large. The level of integration is not high enough. In addition, indium gallium zinc oxide is quite sensitive to water and oxygen, and a protective layer needs to be formed on the indium gallium zinc oxide to isolate oxygen and water vapor in the air.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

In a first aspect, an embodiment of the present disclosure provides a transistor, including a gate electrode layer and a semiconductor layer disposed on a substrate, the gate electrode layer is insulated from the semiconductor layer, and the semiconductor layer includes a first part and a second part , the first part is located on the side of the gate electrode layer away from the substrate, and the orthographic projection of the first part on the substrate overlaps with the orthographic projection of at least part of the gate electrode layer on the substrate, The second portion is located on a side of the gate electrode layer close to the substrate, and the orthographic projection of the second portion on the substrate overlaps with at least part of the orthographic projection of the gate electrode layer on the substrate .

In an exemplary embodiment, the orthographic projection of at least part of the gate electrode layer on the substrate is the same as the orthographic projection of the first part on the substrate and the orthographic projection of the second part on the substrate overlap.

In an exemplary embodiment, the semiconductor layer further includes a third portion connecting the first portion to the second portion, the third portion, the first portion, and the second It is partially arranged around the gate electrode layer.

In an exemplary embodiment, the first part, the second part and the third part are integrally formed.

In an exemplary embodiment, a first gate insulating layer disposed between the first portion and the gate electrode layer is further included.

In an exemplary embodiment, a second gate insulating layer disposed between the second portion and the gate electrode layer is further included.

In an exemplary embodiment, the gate electrode layer includes a first gate electrode portion and a second gate electrode portion, and the orthographic projection of the first gate electrode portion on the substrate is the same as that of the first portion on the substrate. The orthographic projection of the second portion on the substrate overlaps, and the orthographic projection of the second grid electrode portion on the substrate is both the same as the orthographic projection of the first portion and the second portion on the substrate. The projections do not overlap, and the transistor further includes a first insulating layer, and the first insulating layer is disposed on a side of the second gate electrode part away from the substrate.

In an exemplary embodiment, a first protective layer is further included, and the first protective layer is disposed on a side of the first insulating layer away from the substrate.

In an exemplary embodiment, a groove is provided on a surface of the first portion away from the base, and at least part of the first protection layer is disposed in the groove.

In an exemplary embodiment, the gate electrode layer includes a first gate electrode portion and a second gate electrode portion, and the orthographic projection of the first gate electrode portion on the substrate is the same as that of the first portion on the substrate. The orthographic projection of the second portion on the substrate overlaps, and the orthographic projection of the second grid electrode portion on the substrate is both the same as the orthographic projection of the first portion and the second portion on the substrate. The projections do not overlap, and the transistor further includes a second insulating layer, and the second insulating layer is disposed on a side of the second gate electrode part close to the substrate.

In an exemplary embodiment, a second protective layer is further included, and the second protective layer is disposed on a side of the second insulating layer close to the substrate.

In an exemplary embodiment, it further includes a first source drain and a second source drain, the first source drain and the second source drain are both arranged on the side of the semiconductor layer away from the substrate, The first source-drain and the second source-drain are insulated, and both the first source-drain and the second source-drain are electrically connected to the semiconductor layer.

In an exemplary embodiment, a third insulating layer is further included, the third insulating layer is disposed on the side of the semiconductor layer away from the substrate, the first source and drain and the second source and drain are both disposed On the side of the third insulating layer away from the substrate, a first via hole and a second via hole are arranged in the third insulating layer, and the first source and drain are connected to the first via hole through the first via hole. The semiconductor layer is electrically connected, and the second source and drain are electrically connected to the semiconductor layer through the second via hole.

In a second aspect, an embodiment of the present disclosure further provides a method for manufacturing a transistor, including:

forming a gate electrode layer on the substrate;

forming a semiconductor layer on the substrate;

Wherein, the semiconductor layer includes a first part and a second part that are oppositely arranged, the first part is located on the side of the gate electrode layer away from the substrate, and the orthographic projection of the first part on the substrate is at least partly Orthographic projections of the gate electrode layer on the substrate overlap, the second portion is located on a side of the gate electrode layer close to the substrate, and the orthographic projections of the second portion on the substrate overlap with at least Orthographic projections of parts of the gate electrode layer on the substrate overlap.

In an exemplary embodiment, forming the semiconductor layer on the substrate includes:

sequentially forming a second insulating layer, a gate electrode layer, a first insulating layer, and a first protective layer on the substrate;

At least one notch is formed in the second insulating layer, the gate electrode layer, the first insulating layer, and the first protection layer, and the at least one notch connects the second insulating layer, the gate electrode layer, the first insulating layer, and the side surfaces of the first protective layer are exposed;

Etching and removing at least part of the second insulating layer and at least part of the first insulating layer through the at least one gap, exposing at least part of the top surface and the bottom surface of the gate electrode layer;

A semiconductor thin film is deposited on both the top surface and the bottom surface of the exposed gate electrode layer, so that the semiconductor thin film on the top surface of the exposed gate electrode layer forms a first part of the semiconductor layer, and the exposed gate electrode layer The semiconductor thin film on the bottom surface of the semiconductor layer forms the second part.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings are used to provide an understanding of the technical solution of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solution of the present application, and do not constitute a limitation to the technical solution of the present application.

FIG. 1 is a structural schematic diagram 1 of a transistor in the related art;

FIG. 2 is a second structural schematic diagram of a transistor in the related art;

FIG. 3 is a structural schematic diagram 3 of a transistor in the related art;

FIG. 4 is a first cross-sectional view of a transistor according to an embodiment of the present invention;

FIG. 5 is a first structural schematic diagram of a transistor according to an embodiment of the present invention;

FIG. 6 is a second cross-sectional view of a transistor according to an embodiment of the present invention;

FIG. 7 is a second structural schematic diagram of a transistor according to an embodiment of the present invention;

FIG. 8 is a third cross-sectional view of a transistor according to an embodiment of the present invention;

FIG. 9 is a cross-sectional view four of a transistor according to an embodiment of the present invention;

10 is a schematic diagram of the first insulating film pattern, the second insulating film pattern, the first conductive film pattern, the third insulating film pattern and the fourth insulating film pattern formed on the transistor according to the embodiment of the present invention;

FIG. 11 is a schematic diagram of a transistor according to an embodiment of the present invention after forming a first notch and a second notch;

12 is a cross-sectional view of a transistor according to an embodiment of the present invention after forming a first notch and a second notch;

13 is a schematic diagram of a transistor forming a channel and a second channel according to an embodiment of the present invention;

FIG. 14 is a cross-sectional view of a transistor according to an embodiment of the present invention after forming a channel and a second channel;

15 is a schematic diagram of a transistor according to an embodiment of the present invention after forming a first gate insulating layer and a second gate insulating layer.

Detailed ways

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that an embodiment may be embodied in many different forms. Those skilled in the art can easily understand the fact that the means and contents can be changed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

In this specification, for convenience, "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner" are used , "external" and other words indicating the orientation or positional relationship are used to illustrate the positional relationship of the constituent elements with reference to the drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation , are constructed and operate in a particular orientation and therefore are not to be construed as limitations on the present disclosure. The positional relationship of the constituent elements changes appropriately according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and may be appropriately replaced according to circumstances.

In this specification, unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be interpreted in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components. Those of ordinary skill in the art can understand the meanings of the above terms in the present disclosure according to the situation.

"About" in the present disclosure refers to a numerical value that is not strictly limited, and is within the range of process and measurement errors.

The channel material of the single crystal silicon transistor is single crystal silicon material, and the channel of the single crystal material is a single crystal silicon substrate or epitaxy on the substrate, and the device cannot be separated from the silicon substrate, which limits the further integration of MOS devices.

In indium gallium zinc oxide (IGZO for short) materials, indium conducts electricity through the 5S orbital. The amorphous, amorphous structure of the InGaZnO material is also conductive. At the same time, the content of oxygen in InGaZnO will affect the conductive or insulating properties of its semiconductor. This allows InGaZnO to replace single-crystal silicon as the channel material.

In the prior art, transistors use indium gallium zinc oxide as the semiconductor material, and are mainly of the stop etch type, the back channel etch type and the coplanar type, all of which are planar devices.

FIG. 1 is a first structural schematic diagram of a transistor in the related art. As shown in FIG. 1, the transistor is a blocking etch transistor. The transistor comprises a gate electrode layer 2 stacked on a substrate 1, an insulating layer 3 stacked on the gate electrode layer 2, a first source-drain electrode layer 4 and a second source-drain electrode layer stacked on the insulating layer 3 5. The semiconductor layer 6, at least part of the first source-drain electrode layer 4 and at least part of the second source-drain electrode layer 5 respectively cover both ends of the semiconductor layer 6, the semiconductor layer 6 is provided with a barrier layer 7, at least part of the barrier layer 7 is located Between the first source-drain electrode layer 4 and the semiconductor layer 6 , and at least part of the barrier layer 7 is located between the second source-drain electrode layer 5 and the semiconductor layer 6 . Wherein, the material of the semiconductor layer 6 is indium gallium zinc oxide. The first source-drain electrode layer 4 may be a source electrode, and the second source-drain electrode layer 5 may be a drain electrode.

FIG. 2 is a second structural schematic diagram of a transistor in the related art. As shown in FIG. 2, the transistor is a back channel etching type transistor. The transistor includes a gate electrode layer 2 stacked on a substrate 1, an insulating layer 3 stacked on the gate electrode layer 2, a semiconductor layer 6 stacked on the insulating layer 3, and a first semiconductor layer stacked on the semiconductor layer 6. A source-drain electrode layer 4 and a second source-drain electrode layer 5 . Wherein, the material of the semiconductor layer 6 is indium gallium zinc oxide. The first source-drain electrode layer 4 may be a source electrode, and the second source-drain electrode layer 5 may be a drain electrode.

FIG. 3 is a third structural schematic diagram of a transistor in the related art. As shown in FIG. 3, the transistor is a coplanar transistor. The transistor comprises a gate electrode layer 2 stacked on a substrate 1, an insulating layer 3 stacked on the gate electrode layer 2, a first source-drain electrode layer 4 and a second source-drain electrode layer stacked on the insulating layer 3 5. The semiconductor layer 6 , at least part of the semiconductor layer 6 covers the first source-drain electrode layer 4 , and at least part of the semiconductor layer 6 covers the second source-drain electrode layer 5 . Wherein, the material of the semiconductor layer 6 is indium gallium zinc oxide. The first source-drain electrode layer 4 may be a source electrode, and the second source-drain electrode layer 5 may be a drain electrode.

Transistors in the related art have a planar structure, and the source electrode, the gate electrode layer, and the drain electrode are tiled on the substrate, and the integration degree is not high.

An embodiment of the present invention provides a transistor. The transistor in the embodiment of the present invention includes at least one sub-transistor unit, and a sub-transistor unit includes a gate electrode layer and a semiconductor layer disposed on the substrate, the gate electrode is insulated from the semiconductor layer, and the semiconductor layer includes a first part and a second part. part, the first part is located on the side of the gate electrode layer away from the substrate, and the orthographic projection of the first part on the substrate overlaps with the orthographic projection of at least part of the gate electrode layer on the substrate , the second portion is located on the side of the gate electrode layer close to the substrate, and the orthographic projection of the second portion on the substrate is orthogonal to the orthographic projection of at least part of the gate electrode layer on the substrate stack.

Transistors in the embodiments of the present invention can be implemented with various structures, and the technical solutions of the embodiments of the present invention will be described in detail below through specific embodiments.

FIG. 4 is a first cross-sectional view of a transistor according to an embodiment of the present invention. As shown in FIG. 4 , the transistor of this embodiment includes at least one sub-transistor unit 100 . One sub-transistor unit 100 includes a gate electrode layer 2 and a semiconductor layer 6 disposed on a substrate 1 . The gate electrode layer 2 is insulated from the semiconductor layer 6 . The semiconductor layer 6 includes a first portion 601 and a second portion 602 . Both the first part 601 and the second part 602 extend along a direction parallel to the plane where the substrate 1 is located, the first part 601 is located on the side of the gate electrode layer 2 away from the substrate 1, and the orthographic projection of the first part 601 on the substrate 1 is at least part of the grid The orthographic projections of the electrode layer 2 on the substrate 1 overlap, and the first part 601 forms a first channel; the second part 602 is located on the side of the gate electrode layer 2 close to the substrate 1, and the orthographic projection of the second part 602 on the substrate 1 and At least part of the orthographic projections of the gate electrode layer 2 on the substrate 1 overlap, and the second part 602 forms a second channel. That is, in the thickness direction of the substrate 1 , the second portion 602 and the first portion 601 are sequentially stacked on the substrate 1 .

The transistor in the embodiment of the present invention has a three-dimensional structure, and the integration degree of the transistor is improved by dividing the semiconductor layer into the three-dimensional structure of the first part and the second part. Moreover, the transistor in the embodiment of the present invention arranges the first part and the second part on opposite sides of the gate electrode layer respectively, so as to enhance the control ability of the gate electrode layer to the channel, increase the on-current, and increase the on-off ratio.

In an exemplary embodiment, the orthographic projection of the first part 601 on the substrate 1 overlaps the orthographic projection of the second part 602 on the substrate 1, and at least part of the orthographic projections of the gate electrode layer 2 on the substrate 1 overlap with the first part 601. The orthographic projection on the substrate 1 and the orthographic projection of the second portion 602 on the substrate 1 overlap.

In some embodiments, the orthographic projection of the first part 601 on the substrate 1 and the orthographic projection of the second part 602 on the substrate 1 may not overlap, and the orthographic projection of a part of the gate electrode layer 2 on the substrate 1 is the same as that of the first part 601 on the substrate 1. The orthographic projections on the substrate 1 overlap, and the orthographic projections of a part of the grid electrode layer 2 on the substrate 1 overlap with the orthographic projections of the second part 602 on the substrate 1; or, the orthographic projections of a part of the first part 601 on the substrate 1 overlap with The orthographic projections of the second part 602 on the substrate 1 overlap, the orthographic projections of a part of the first part 601 on the substrate 1 and the orthographic projections of the second part 602 on the substrate 1 do not overlap, and a part of the gate electrode layer 2 is on the substrate 1 The orthographic projection of the first part 601 on the substrate 1 may overlap with the orthographic projection of the second part 602 on the substrate 1; The orthographic projection of 601 on the base 1 and the orthographic projection of the second part 602 on the base 1 overlap; or, the orthographic projection of a part of the second part 602 on the base 1 overlaps the orthographic projection of the first part 601 on the base 1 , the orthographic projection of a part of the second part 602 on the substrate 1 does not overlap with the orthographic projection of the first part 601 on the substrate 1, and the orthographic projection of a part of the gate electrode layer 2 on the substrate 1 can be the same as that of the second part 602 on the substrate 1 The orthographic projection of the first part 601 overlaps with the orthographic projection of the first part 601 on the substrate 1; The orthographic projections on base 1 overlap.

In an exemplary embodiment, the substrate 1 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound. For example, the substrate 1 may be a silicon substrate.

In an exemplary embodiment, the gate electrode layer 2 may extend along a direction parallel to the plane of the substrate 1 . The gate electrode layer 2 may serve as a gate electrode of a sub-transistor unit 100 . The gate electrode layer 2 can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc., can be multilayer metals, such as Mo /Cu/Mo, etc., can also be a stack structure formed of metal and transparent conductive materials, such as ITO/Ag/ITO, etc.

In an exemplary embodiment, the semiconductor layer 6 can be made of amorphous silicon a-Si, polycrystalline silicon p-Si, amorphous indium gallium zinc oxide material a-IGZO, zinc oxynitride ZnON, indium zinc tin oxide IZTO, hexathiophene, Various materials such as polythiophene, that is, the embodiments of the present invention are applicable to transistors manufactured based on amorphous silicon technology, polysilicon technology, oxide technology and organic technology, and may be N-type transistors or P-type transistors. Preferably, the semiconductor layer 6 of this embodiment may use indium zinc tin oxide.

FIG. 5 is a first structural schematic diagram of a transistor according to an embodiment of the present invention; FIG. 6 is a second cross-sectional view of a transistor according to an embodiment of the present invention. Wherein, FIG. 4 may be a cross-sectional view along the B-B direction in FIG. 5 , and FIG. 6 may be a cross-sectional view along the A-A direction in FIG. 5 . In an exemplary embodiment, as shown in FIG. 4, FIG. 5 and FIG. The part 603 , the first part 601 and the second part 602 form a hollow structure, and the hollow structure extends along a direction parallel to the plane where the base 1 is located. At least part of the gate electrode layer 2 is disposed in the hollow structure, and the third part 603 , the first part 601 and the second part 602 of the semiconductor layer 6 surround at least part of the gate electrode layer 2 .

Specifically, as shown in FIG. 4 , FIG. 5 and FIG. 6 , the gate electrode layer 2 includes a top surface 210 , a bottom surface 220 and a side surface 230 opposite to each other. The top surface 210 is located on the side of the bottom surface 220 away from the substrate 1 . The side surface 230 is located between the top surface 210 and the bottom surface 220 , and the side surface 230 connects the top surface 210 and the bottom surface 220 . The first part 601 of the semiconductor layer 6 covers at least part of the top surface 210 of the gate electrode layer 2, the second part 602 of the semiconductor layer 6 covers at least part of the bottom surface 220 of the gate electrode layer 2, and the third part 603 of the semiconductor layer 6 covers at least part of the top surface 210 of the gate electrode layer 2. The side surface 230 of the gate electrode layer 2 .

In an exemplary embodiment, the first portion 601 and the second portion 602 of the semiconductor layer 6 both extend along a direction parallel to the plane of the substrate 1, and the third portion 603 of the semiconductor layer 6 extends along a direction perpendicular to the plane of the substrate 1. Extending, the hollow structure formed by the first part 601 , the second part 602 and the third part 603 is ring-shaped.

The transistor in the embodiment of the present invention can increase the height of the gate electrode layer to increase the relative area between the side surface of the gate electrode layer and the third part of the semiconductor layer, strengthen the control of the gate electrode layer on the conductivity of the channel, and effectively improve the transistor. Drive ability and work stability.

In an exemplary embodiment, the first part 601 , the second part 602 and the third part 603 of the semiconductor layer 6 may be integrally formed. Exemplarily, the first part 601 , the second part 602 and the third part 603 of the semiconductor layer 6 can be prepared by using the same material through the same preparation process. The preparation process is simplified and the production cost is reduced.

In an exemplary embodiment, as shown in FIG. 4 and FIG. 6, a first gate insulating layer 7 is disposed between the first portion 601 and the gate electrode layer 2, and the first gate insulating layer 7 connects the first portion 601 to the gate electrode. Layer 2 is electrically isolated. A second gate insulating layer 8 is disposed between the second portion 602 and the gate electrode layer 2 , and the second gate insulating layer 8 electrically isolates the second portion 602 from the gate electrode layer 2 . A third gate insulating layer is disposed between the third part and the third surface of the gate electrode layer, and the third gate insulating layer electrically isolates the third part from the gate electrode layer.

In an exemplary embodiment, as shown in FIG. 4 and FIG. 6 , the first gate insulating layer 7 surrounds the first portion 601 of the semiconductor layer 6, that is, the first gate insulating layer 7 covers the top surface of the first portion 601, Bottom surface and side surfaces; the second gate insulating layer 8 surrounds the second part 602 of the semiconductor layer 6 , that is, the second gate insulating layer 8 covers the top surface, bottom surface and side surfaces of the second part 602 .

In an exemplary embodiment, the first gate insulating layer 7, the second gate insulating layer 8, and the third gate insulating layer can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., or can be High k materials are used, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., which can be single-layer, multi-layer or composite layer.

In an exemplary embodiment, as shown in FIGS. 5 and 6 , the orthographic projection of the first portion 601 on the substrate 1 overlaps the orthographic projection of the second portion 602 on the substrate 1 . The gate electrode layer 2 includes a first gate electrode part and a second gate electrode part, and the orthographic projection of the first gate electrode part on the substrate overlaps with the orthographic projection of the first part on the substrate and the orthographic projection of the second part on the substrate, The orthographic projections of the second grid electrode portion on the substrate do not overlap with the orthographic projections of the first portion and the second portion on the substrate. The transistor in the embodiment of the present invention further includes a first insulating layer 9 , and the first insulating layer 9 is disposed on the side of the second gate electrode portion of the gate electrode layer 2 away from the substrate 1 .

In an exemplary embodiment, as shown in FIG. 5 and FIG. 6 , the transistor of the embodiment of the present invention further includes a first protective layer 10, the first protective layer 10 is disposed on the side of the first insulating layer 9 away from the substrate 1, and the first The protection layer 10 covers the first insulating layer 9 and the first gate insulating layer 7 on the side of the first portion 601 away from the substrate 1 .

In an exemplary embodiment, as shown in FIG. 4 , a groove is provided on the surface of the first part 601 away from the substrate 1 , at least part of the first protective layer 10 is arranged in the groove, and at least part of the first protective layer 10 is away from the substrate 1 One side surface is flush with the side surface of the semiconductor layer 6 away from the substrate 1 .

In an exemplary embodiment, as shown in FIG. 5 and FIG. 6 , the transistor of the embodiment of the present invention further includes a second insulating layer 11 , and the second insulating layer 11 is disposed on the side of the second gate electrode part close to the substrate.

In an exemplary embodiment, as shown in FIG. 5 and FIG. 6 , the transistor of the embodiment of the present invention further includes a second protective layer 12, the second protective layer 12 is disposed on the side of the second insulating layer 11 close to the substrate 1, and the second The protective layer 12 is located between the second insulating layer 11 and the substrate 1 and between the second gate insulating layer 8 on the side of the second portion 602 close to the substrate 1 and the substrate 1 .

In an exemplary embodiment, the first insulating layer 9, the first protective layer 10, the second insulating layer 11, and the second protective layer 12 may all be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, or the like. High k materials can be used, such as aluminum oxide AlOx, hafnium oxide HfOx, tantalum oxide TaOx, etc., which can be single-layer, multi-layer or composite layer.

FIG. 7 is a second structural schematic diagram of a transistor according to an embodiment of the present invention; FIG. 8 is a third cross-sectional view of a transistor according to an embodiment of the present invention; FIG. 9 is a fourth cross-sectional view of a transistor according to an embodiment of the present invention. Wherein, FIG. 8 is a sectional view along the A-A direction in FIG. 7; FIG. 9 is a sectional view along the B-B direction in FIG. 7. As shown in Figure 7, Figure 8 and Figure 9, the semiconductor layer 6 is provided with a third insulating layer 15 on the side away from the substrate 1, the third insulating layer 15 covers the first protective layer 10 and the semiconductor layer 6, in the third insulating layer 15 A first via hole 13 and a second via hole 14 are provided, and both the first via hole 13 and the second via hole 14 expose the semiconductor layer 6 . The third insulating layer 15 is provided with a first source and drain 31 and a first source and drain 32 on the side away from the substrate 1, and the third insulating layer 15 connects the first source and drain 31 and the second source and drain 32 to the semiconductor layer 6. Galvanic isolation. The first source and drain electrodes 31 are electrically connected to the semiconductor layer 6 through the first via hole 13 , and the second source and drain electrodes 32 are electrically connected to the semiconductor layer 6 through the second via hole 14 .

In an exemplary embodiment, the transistor of the embodiment of the present invention does not limit the formation of the first source-drain 31 and the second source-drain 32, as long as the first source-drain 31 and the second source-drain 32 are electrically connected to the semiconductor layer. Just connect.

In an exemplary embodiment, the first source-drain 31 and the second source-drain 32 of the transistor of the embodiment of the present invention can be made of metal materials, such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloys of the above metals Materials, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc., can be multilayer metals, such as Mo/Cu/Mo, etc., or stacked structures formed of metals and transparent conductive materials, such as ITO/Ag/ITO, etc.

In an exemplary embodiment, the transistor of the embodiment of the present invention includes at least two sub-transistor units 100 stacked on the substrate 1 . The transistor in the embodiment of the present invention can increase the integration degree of the transistor by stacking at least two sub-transistor units 100 in a direction perpendicular to the plane of the substrate 1 .

The embodiment of the present invention also provides a method for manufacturing a transistor, including:

forming a gate electrode layer on the substrate;

forming a semiconductor layer on the substrate;

Wherein, the semiconductor layer includes a first part and a second part, the first part is located on the side of the gate electrode layer away from the substrate, and the orthographic projection of the first part on the substrate is consistent with at least part of the gate electrode layer. The orthographic projection of the electrode layer on the substrate overlaps, the second part is located on a side of the gate electrode layer close to the substrate, and the orthographic projection of the second part on the substrate overlaps with at least part of the Orthographic projections of the gate electrode layer on the substrate overlap.

The technical solution of this embodiment will be further described below by showing the preparation process of the substrate in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., which is a mature preparation process in related technologies. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still needs a patterning process or a photolithography process during the entire production process, it is called a "film" before the patterning process, and it is called a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

10 to 15 are schematic diagrams of the fabrication process of the transistor according to the embodiment of the present invention. Wherein, FIG. 12 is a sectional view along the A-A direction in FIG. 11 ; FIG. 14 is a sectional view along the A-A direction in FIG. 13 . The manufacturing method of the transistor in the embodiment of the present invention specifically includes:

(1) On the substrate 1, deposit the first insulating film pattern, the second insulating film 16 pattern, the first conductive film 17 pattern, the third insulating film 18 pattern and the fourth insulating film 19 pattern sequentially, and the first insulating film 15 covers the substrate 1 all surfaces, the second insulating film 16 covers all surfaces of the first insulating film, the third insulating film 18 covers all surfaces of the second insulating film 16, the fourth insulating film 19 covers all surfaces of the third insulating film 18, and then the first insulating film The thin film forms the second protective layer 12 as shown in FIG. 10 .

(2) On the substrate 1 formed with the aforementioned pattern, through the same etching process, the second insulating film pattern, the first conductive film pattern, the third insulating film pattern and the fourth insulating film pattern are formed into the first gap 20 and the second insulating film pattern. Two notches 21, the first notch 20 and the second notch 21 are located on opposite sides of the second insulating film pattern, the first conductive film pattern, the third insulating film pattern and the fourth insulating film pattern. At this time, the second insulating film forms the second insulating layer 11 , the first conductive film forms the gate electrode layer 2 , the third insulating film forms the first insulating layer 9 , and the fourth insulating film forms the first protection layer 10 . Both the first gap 20 and the second gap 21 expose side surfaces of the second insulating layer 11 , the gate electrode layer 2 , the first insulating layer 9 and the first protection layer 10 , as shown in FIGS. 11 and 12 .

(3) On the substrate 1 formed with the aforementioned pattern, the second insulating layer 11 and the first insulating layer 9 exposed in the first notch 20 and the second notch 21 are etched and removed by an etching process to form a connection between the first and second insulating layers. The first channel 22 and the second channel 23 of the notch 20 and the second notch 21 are respectively located on opposite sides of the gate electrode layer 2 in the thickness direction of the substrate 1 . The first channel 22 is located on the side of the gate electrode layer 2 away from the base; the second channel 23 is located on the side of the gate electrode layer 2 close to the base, the first channel exposes part of the top surface of the gate electrode layer 2, and the second channel exposes part of the gate electrode layer The bottom surface of 2 is exposed, as shown in Fig. 13 and Fig. 14 .

(4) On the substrate 1 formed with the aforementioned pattern, deposit a layer of fifth insulating film on the inner wall of the first channel 22, so that the fifth insulating film forms the first gate insulating layer 7; on the inner wall of the second channel 23 A layer of sixth insulating film is deposited on it, so that the sixth insulating film forms the second gate insulating layer 8, as shown in FIG. 15 .

(5) On the substrate 1 formed with the aforementioned pattern, deposit a semiconductor film in the first notch 20, the second notch 21, the first channel 22 and the second channel 23, so that the semiconductor film forms the semiconductor layer 6, wherein the gate electrode The semiconductor thin film on the top surface of layer 2 forms the first part 601 of semiconductor layer 6; the semiconductor thin film on the bottom surface of gate electrode layer 2 forms the second part 602 of semiconductor layer 6, as shown in Fig. 4, Fig. 5 and Fig. 6 .

(6) On the substrate 1 formed with the aforementioned pattern, form a third insulating layer 15 on the side of the semiconductor layer 6 away from the substrate 1, so that the third insulating layer 15 covers the first protective layer 10 and the semiconductor layer 6, and the third insulating layer A first via hole 13 and a second via hole 14 are formed in the layer 15 , and both the first via hole 13 and the second via hole 14 expose the semiconductor layer 6 . The first source and drain 31 and the second source and drain 32 are formed on the side of the third insulating layer 15 away from the substrate 1, the first source and drain 31 are electrically connected to the semiconductor layer 6 through the first via hole 13, and the second source and drain 32 is electrically connected to the semiconductor layer 6 through the second via hole 14, as shown in FIG. 7 , FIG. 8 and FIG. 9 .

It can be seen from the structure and preparation process of the transistor of the embodiment of the present invention that the transistor of the embodiment of the present invention surrounds the gate electrode layer through the first part and the second part of the semiconductor layer, which enhances the control ability of the gate electrode layer on the channel and increases the conduction. current, increasing the on-off ratio.

The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures may refer to general designs. In the case of no conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

Those skilled in the art should understand that the technical solutions of the present disclosure can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present disclosure, and should be covered by the scope of the claims of the present disclosure.

Claims

A transistor, comprising a gate electrode layer and a semiconductor layer arranged on a substrate, the gate electrode layer is insulated from the semiconductor layer, the semiconductor layer includes a first part and a second part, the first part is located on the gate electrode layer away from the side of the substrate, and the orthographic projection of the first part on the substrate overlaps with the orthographic projection of at least part of the gate electrode layer on the substrate, and the second part is located at the gate electrode The layer is close to the side of the substrate, and the orthographic projection of the second portion on the substrate overlaps with the orthographic projection of at least part of the gate electrode layer on the substrate.
The transistor according to claim 1, wherein the orthographic projection of at least part of the gate electrode layer on the substrate is the same as the orthographic projection of the first part on the substrate and the second part on the substrate. Orthographic overlap on .
The transistor according to claim 1, wherein the semiconductor layer further comprises a third portion connecting the first portion to the second portion, the third portion, the first portion, and The second portion is disposed around the gate electrode layer.
The transistor according to claim 3, wherein the first part, the second part and the third part are integrally formed.
The transistor according to claim 1, further comprising a first gate insulating layer disposed between the first portion and the gate electrode layer.
The transistor according to claim 1, further comprising a second gate insulating layer disposed between the second portion and the gate electrode layer.
The transistor according to claim 2, wherein the gate electrode layer comprises a first gate electrode portion and a second gate electrode portion, and the orthographic projection of the first gate electrode portion on the base is in the same position as the first portion. The orthographic projection on the substrate and the orthographic projection of the second portion on the substrate overlap, and the orthographic projections of the second grid electrode portion on the substrate are both the same as those of the first portion and the second portion on the substrate. Orthographic projections of the substrates do not overlap, and the transistor further includes a first insulating layer, and the first insulating layer is disposed on a side of the second gate electrode part away from the substrate.
The transistor according to claim 7, further comprising a first protective layer, the first protective layer is disposed on a side of the first insulating layer away from the substrate.
The transistor according to claim 8, wherein a groove is disposed on the surface of the first portion away from the substrate, and at least part of the first protection layer is disposed in the groove.
The transistor according to claim 2, wherein the gate electrode layer comprises a first gate electrode portion and a second gate electrode portion, and the orthographic projection of the first gate electrode portion on the base is in the same position as the first portion. The orthographic projection on the substrate and the orthographic projection of the second portion on the substrate overlap, and the orthographic projections of the second grid electrode portion on the substrate are both the same as those of the first portion and the second portion on the substrate. Orthographic projections of the substrates do not overlap, and the transistor further includes a second insulating layer, and the second insulating layer is disposed on a side of the second gate electrode portion close to the substrate.
The transistor according to claim 10, further comprising a second protection layer, the second protection layer being disposed on a side of the second insulating layer close to the substrate.
The transistor according to claim 1, further comprising a first source-drain and a second source-drain, both of the first source-drain and the second source-drain are disposed at a distance between the semiconductor layer and the substrate. side, the first source and drain are insulated from the second source and drain, and both the first source and drain and the second source and drain are electrically connected to the semiconductor layer.
The transistor according to claim 12, further comprising a third insulating layer, the third insulating layer is disposed on the side of the semiconductor layer away from the substrate, the first source and drain and the second source and drain are all arranged on the side of the third insulating layer away from the substrate, the third insulating layer is provided with a first via hole and a second via hole, and the first source and drain are connected to each other through the first via hole. The semiconductor layer is electrically connected, and the second source and drain are electrically connected to the semiconductor layer through the second via hole.
A method of manufacturing a transistor, comprising:

forming a gate electrode layer on the substrate;

forming a semiconductor layer on the substrate;

Wherein, the semiconductor layer includes a first part and a second part that are oppositely arranged, the first part is located on the side of the gate electrode layer away from the substrate, and the orthographic projection of the first part on the substrate is at least partly Orthographic projections of the gate electrode layer on the substrate overlap, the second portion is located on a side of the gate electrode layer close to the substrate, and the orthographic projections of the second portion on the substrate overlap with at least Orthographic projections of part of the gate electrode layer on the substrate overlap.
The method for manufacturing a transistor according to claim 14, wherein forming the semiconductor layer on the substrate comprises:

sequentially forming a second insulating layer, a gate electrode layer, a first insulating layer, and a first protective layer on the substrate;

At least one notch is formed in the second insulating layer, the gate electrode layer, the first insulating layer, and the first protection layer, and the at least one notch connects the second insulating layer, the gate electrode layer, the first insulating layer, and the side surfaces of the first protective layer are exposed;

Etching and removing at least part of the second insulating layer and at least part of the first insulating layer through the at least one gap, exposing at least part of the top surface and the bottom surface of the gate electrode layer;

A semiconductor thin film is deposited on both the top surface and the bottom surface of the exposed gate electrode layer, so that the semiconductor thin film on the top surface of the exposed gate electrode layer forms a first part of the semiconductor layer, and the exposed gate electrode layer The semiconductor thin film on the bottom surface of the semiconductor layer forms the second part.