WO2023133932A1 - Appareil ate fondé sur des paramètres transmis de manière dynamique, et procédé de transmission - Google Patents

Appareil ate fondé sur des paramètres transmis de manière dynamique, et procédé de transmission Download PDF

Info

Publication number
WO2023133932A1
WO2023133932A1 PCT/CN2022/073388 CN2022073388W WO2023133932A1 WO 2023133932 A1 WO2023133932 A1 WO 2023133932A1 CN 2022073388 W CN2022073388 W CN 2022073388W WO 2023133932 A1 WO2023133932 A1 WO 2023133932A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
code
program
module
cvm
Prior art date
Application number
PCT/CN2022/073388
Other languages
English (en)
Chinese (zh)
Inventor
李行
Original Assignee
上海御渡半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海御渡半导体科技有限公司 filed Critical 上海御渡半导体科技有限公司
Publication of WO2023133932A1 publication Critical patent/WO2023133932A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3688—Test management for test execution, e.g. scheduling of test suites
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/31—Programming languages or programming paradigms
    • G06F8/315—Object-oriented languages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/42—Syntactic analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/42—Syntactic analysis
    • G06F8/425—Lexical analysis

Definitions

  • the present invention relates to the field of semiconductor automatic test equipment (Automatic Test Equipment, referred to as ATE), in particular to an ATE device and transmission method based on dynamic transmission parameters.
  • ATE Automatic Test Equipment
  • Chip testing plays an extremely important role in the entire semiconductor industry chain. As the complexity of integrated circuits increases, so does the complexity of testing. Large-scale integrated circuits often require hundreds of voltage, current, and timing tests and millions of functional test steps to ensure the completeness of the device. Correct, this also makes the test cost of the chip higher and higher, and the test cost of some devices even accounts for the vast majority of the chip cost.
  • Automatic test equipment is a collection of test instruments controlled by a high-performance computer. It is a test system composed of a tester and a computer. The computer controls the test hardware by running the instructions of the test program.
  • the semiconductor chip testing machine is used to test the integrity of the function and performance of integrated circuits, and is an important equipment to ensure the quality of integrated circuits in the production process of integrated circuits.
  • the most basic requirement of the test system is to ensure the rapidity, reliability and stability of the test function. Among them, rapidity is particularly important; therefore, how to improve the testing speed of chips is a common topic in the semiconductor testing machine industry.
  • testProgram a test program for ATE.
  • Cpp compiled programming language
  • the program Since it is necessary to continuously modify the debugging test conditions (such as hardware resources, port numbers, input stimulus and signal size, etc.) in the test program, the program needs to be modified for each debugging, and in each test program, different test items Different test procedures need to be changed. Due to the characteristics of the compiled language, once the test program is modified, the entire test needs to be recompiled, linked and executed to take effect for the changed test conditions, which reduces the debugging efficiency and lengthens the development time. If the test program is developed in an interpreted language, most of the codes that are not frequently changed still exist in the test program, so part of the performance will be lost.
  • the debugging test conditions such as hardware resources, port numbers, input stimulus and signal size, etc.
  • the industry urgently needs to provide a method of dynamically passing parameters, which can dynamically load the test conditions that need to be modified during debugging into the test program for execution, so that the test program can take effect for the changed test conditions without recompiling and linking. Effectively improve chip testing efficiency.
  • the purpose of the present invention is to provide a method for improving chip testing efficiency by dynamically passing parameters, which can dynamically load the test conditions that need to be modified when the chip test program is debugged into the test program, so that the test program can be updated without recompiling and linking.
  • the changed test conditions take effect.
  • a device for improving chip testing efficiency by dynamically passing parameters based on an ATE device for dynamically passing parameters, used to measure at least one device under test DUT; it is characterized in that it includes a test program module, a compiler, a variable code module and test execution module; wherein, the test program module includes a fixed code program and a test condition interface program, the variable code module is used to receive a test condition, and the test condition includes at least one dynamically changing parameter; the compiler is used to compile the The program in the test program module forms an executable first machine instruction part, and the test execution module includes a syntax parser ATPL, a virtual machine unit CVM, a scheduling test flow unit and a communication unit; the syntax parser ATPL is sentence by sentence Read the source code of the test condition, first perform lexical analysis and syntax analysis, then convert the source code into an intermediate code and optimize it, and finally interpret the intermediate code into an executable second machine instruction part, which is determined by the virtual The machine unit CVM executes the second machine instruction part; the scheduling test flow unit schedule
  • test conditions include hardware resources, port numbers, input stimuli and/or signal magnitude values of the ATE device.
  • a parameter method of an ATE device based on dynamic parameter transfer comprising:
  • Step S1 dynamically configuring parameters in the test conditions involved in the test program module
  • Step S2 the compiler is used to compile the program in the test program module to form an executable first machine instruction part
  • Step S3 The syntax parser ATPL reads the test condition source code sentence by sentence, first performs lexical analysis and syntax analysis, then converts the source code into intermediate code and optimizes it, and finally interprets the intermediate code as executable
  • Step S4 and execute the second machine instruction part in the corresponding virtual machine unit CVM to form the target code
  • Step S5 The scheduling test flow unit schedules the test flow according to the CVM execution result, and executes an interactive test with the DUT through the communication unit to obtain a test result.
  • step S3 specifically includes:
  • Step S31 lexical analysis, that is, scanning the source file, and splitting the character stream of the source file into individual words (marks);
  • Step S32 grammar analysis, constructing a grammar tree from these tokens according to grammar rules
  • Step S33 Semantic analysis, checking the relationship between each node of the syntax tree, checking whether the semantic rules are violated, and performing necessary optimization on the syntax tree;
  • Step S34 Traversing the nodes of the syntax tree, converting each node into an intermediate code, and assembling them in a specific order, this is intermediate code generation;
  • Step S35 optimizing the intermediate code
  • Step S36 converting the intermediate code into object code
  • Step S37 Optimizing the object code to generate a final object program.
  • the present invention has the following beneficial effects:
  • Modularization is one of the key goals to be achieved when designing the test program. This architecturally mature and efficient approach to testing allows users to write independent components that handle different aspects of testing; and, allows these components to be mixed and matched in various ways to produce a complete test program.
  • the mode of the virtual machine unit CVM plus the parser ATPL allows the information required by the test program to be executed in different compilation modes, decoupling the overall framework, and improving the reusability and scalability of the test program.
  • the readable code formed by the above scheme can greatly improve the programming efficiency and make the code structure better.
  • the present invention does not add configuration file or the file of other DSL syntax, but directly carries out the modification and debugging of parameter and instruction on source file, reduces the learning cost of developer.
  • Advantest Company As an example.
  • the test programming language of Advantest specifies the objects used in the test plan written by the user and the relationship between each object. These program files are converted into C++ codes by the compiler of Advantest Company, and Through their test system, it is packaged into a Windows dynamic link library (DLL) and loaded into the test scheduling software for execution.
  • DLL Windows dynamic link library
  • Advantest's conversion process from test plan description to implementation is divided into two stages: translation and compilation. They need to convert the test programming language into C++ language first, and then proceed to the next step of compilation, linking, loading, execution, etc. steps, the whole process is rather cumbersome.
  • the modes of the syntax parser ATPL and the virtual machine unit CVM are optimized for the test process.
  • the test programming language can be compiled directly through the ATPL parser, and the machine code is generated in the callback function of the syntax tree, and directly executed through the virtual machine unit CVM operation stack.
  • the instruction set does not need to be translated into C++ code and integrated into the project, which significantly improves the test efficiency and saves test time.
  • Figure 1 shows a schematic diagram of the compilation and execution flow of a Cpp-like compiled language
  • FIG. 2 shows the flowchart of ATPL parser in parsing language
  • Figure 3 is a schematic diagram of functional modules of a device for improving chip testing efficiency by dynamically transferring parameters in an embodiment of the present invention
  • Fig. 4 shows that in the embodiment of the present invention, the schematic diagram of the method for improving chip test efficiency by dynamically transferring parameters
  • Fig. 5 shows the schematic diagram of the workflow of the ATPL grammar parser in the embodiment of the present invention
  • the device adopted by the present invention to improve chip testing efficiency by dynamically passing parameters realizes a CVM (Cpp Virtual Machine) virtual machine and an ATPL (Automatic Test Program Language) parser for translating Cpp codes into machine codes Execute directly.
  • CVM Cpp Virtual Machine
  • ATPL Automatic Test Program Language
  • FIG. 1 is a schematic diagram of a compilation and execution flow of a Cpp-like compiled language.
  • the compilation and execution process of a compiled language such as pp includes the following steps:
  • the compiler calls the preprocessor to perform related processing, optimize the source code conversion (including clearing comments, macro definitions, include files, and conditional compilation), and then compile the preprocessed source code into object code (binary machine language), and then by calling the linker plus library files (such as the API provided by the operating system), an executable program is formed so that the machine can execute it. And the object code must match the CPU architecture of the machine, and the library file must match the operating system. If you want to run the source code of the Cpp language on a machine or system with different CPUs, you need to compile it for different CPU architectures and operating systems, so that you can run the program on the machine.
  • Fig. 2 shows the flow diagram of the ATPL grammar parser when parsing the type language.
  • the analytic language mainly has the following steps:
  • Source code (source code) ⁇ interpreter (interpret) ⁇ execution (execute)
  • the source code does not need to be pre-compiled into an executable program.
  • the interpreter reads a sentence of source code, it first performs lexical analysis and syntax analysis, and then converts the source code into an intermediate code (byte code) that the interpreter can execute. Finally, the interpreter interprets the intermediate code It is an executable machine instruction, and executes the instruction in the corresponding virtual machine.
  • Compiled languages such as Cpp need to be compiled, linked, loaded, and executed to execute machine instructions, while analytic languages execute machine instructions directly after syntax analysis, eliminating the steps of compiling, linking, loading, and generating executable files. It is very suitable for debugging chip test conditions. However, if all analytical languages are used, some performance will be lost because the code that is not frequently changed accounts for the vast majority of the test program.
  • the present invention combines the two, and those programs that are not frequently changed can be compiled into machine codes in advance, and codes that need to be frequently changed and debugged, such as test conditions, can be translated into machine codes by an interpreter Finally, the built-in virtual machine executes and obtains the result, which can achieve the effect of dynamic parameter passing, shorten compilation time, and improve debugging efficiency.
  • FIG. 3 is a schematic diagram of functional modules of a device for improving chip testing efficiency by dynamically passing parameters in an embodiment of the present invention.
  • the ATE device based on dynamic transfer parameters is used to measure at least one device under test DUT; it includes a test program module, a compiler, a variable code module and a test execution module; wherein the test program The module includes a fixed code program and a test condition interface program, the variable code module is used to receive a test condition, and the test condition includes at least one dynamically changing parameter; the compiler is used to compile the program in the test program module, Form the executable first machine instruction part, the test execution module includes a grammar parser ATPL, a virtual machine unit CVM, a scheduling test flow unit and a communication unit; the grammar parser ATPL reads the test condition source code sentence by sentence , first perform lexical analysis and syntax analysis, then convert the source code into an intermediate code and perform optimization, and finally interpret the intermediate code into an executable second machine instruction part,
  • the test conditions may include hardware resources, port numbers, input stimuli and/or signal magnitude values of the ATE device.
  • parameters such as hardware resource, port number, input stimulus and/or signal size value of the initialized ATE device can be dynamically adjusted during the test.
  • the virtual machine unit CVM can translate the source program of the programming language Cpp commonly used in the field of chip testing into machine code through the parser ATPL, and execute it inside the virtual machine. By executing these target codes, it provides the input stimulus and test conditions required by the test program, so that developers can easily edit and debug test plans and test items, and the edited test items will take effect in real time when they are executed.
  • FIG. 4 is a schematic diagram of a method for improving chip testing efficiency by dynamically transferring parameters in an embodiment of the present invention. As shown in Figure 4, the method includes the following steps:
  • Step S1 Dynamically configure the parameters in the test conditions involved in the test program module.
  • Step S2 the compiler is used to compile the program in the test program module to form the executable first machine instruction part. That is to say, in the present invention, the test program is modularized, and the fixed part of the program and the part of the program that needs to be frequently modified and debugged are coded in separate files.
  • the above-mentioned fixed part of the test program is compiled into an executable file by the Cpp compiler provided by the system to form the executable first machine instruction part.
  • the other part of the code related to the test conditions does not participate in the compilation, which is very convenient. If you need to modify the code related to the test conditions, you can directly modify it in the corresponding source file. Afterwards, there is no need to compile the test program and run it directly, and the modified test conditions will take effect immediately.
  • Step S3 the syntax parser ATPL reads the test condition source code sentence by sentence, first performs lexical analysis and syntax analysis, then converts the source code into intermediate code that the syntax parser ATPL can execute, and finally The parser ATPL interprets the intermediate code into an executable second machine instruction portion.
  • FIG. 5 is a schematic diagram of the workflow of the ATPL parser in the embodiment of the present invention.
  • the step S3 may specifically include:
  • Step S31 lexical analysis, that is, scanning the source file, and splitting the character stream of the source file into individual words (marks);
  • Step S32 grammar analysis, constructing a grammar tree from these tokens according to grammar rules
  • Step S33 Semantic analysis, checking the relationship between each node of the syntax tree, checking whether the semantic rules are violated, and performing necessary optimization on the syntax tree;
  • Step S34 Traversing the nodes of the syntax tree, converting each node into an intermediate code, and assembling them in a specific order, this is intermediate code generation;
  • Step S35 optimizing the intermediate code
  • Step S36 converting the intermediate code into object code
  • Step S37 Optimizing the object code to generate a final object program.
  • Step S4 and splicing the first machine instruction part and the second machine instruction part through the application program interface API in the corresponding virtual machine unit CVM to form the target code.
  • Step S5 the dispatching test flow unit translates the target code, and executes an interaction test with the device under test (DUT) through the communication unit to obtain a test result.
  • DUT device under test
  • these codes are dynamically loaded into the process through the embedded virtual machine unit CVM plus syntax parser ATPL, translated into target codes, executed in the virtual machine unit CVM, and Obtain calculation results, save the steps of recompiling and linking the entire program, and improve the efficiency of chip testing and debugging.
  • the present invention provides a device and transmission method for improving chip testing efficiency through dynamic transmission of parameters, which provides a method for dynamic parameter transmission, which can dynamically load the test conditions that need to be modified during debugging into the test program for execution , so that the test program can take effect on the changed test conditions without recompiling and linking, which can effectively improve the efficiency of chip testing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Debugging And Monitoring (AREA)

Abstract

Appareil ATE fondé sur des paramètres transmis de manière dynamique, et procédé de transmission. L'appareil ATE comprend un module de programme de test, un compilateur, un module de code variable et un module d'exécution de test ; le module de code variable est utilisé pour recevoir une condition de test ; le compilateur est utilisé pour compiler un programme dans le module de programme de test afin de former une première partie d'instruction de machine exécutable, et le module d'exécution de test comprend un analyseur grammatical ATPL, une unité de machine virtuelle CVM, une unité de planification de flux de test et une unité de communication ; l'analyseur grammatical ATPL lit un code source de condition de test phrase par phrase, effectue d'abord une analyse lexicale et une analyse grammaticale, puis convertit le code source en un code intermédiaire, optimise le code intermédiaire, et interprète finalement le code intermédiaire en une seconde partie d'instruction de machine exécutable, et la seconde partie d'instruction de machine exécutable est exécutée par l'unité de machine virtuelle CVM ; et l'unité de planification de flux de test planifie un flux de test en fonction d'un résultat d'exécution de la CVM, et exécute un test interactif à l'aide d'un DUT de dispositif testé au moyen de l'unité de communication.
PCT/CN2022/073388 2022-01-14 2022-01-24 Appareil ate fondé sur des paramètres transmis de manière dynamique, et procédé de transmission WO2023133932A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210043592.XA CN114490362A (zh) 2022-01-14 2022-01-14 一种基于动态传递参数的ate装置和传输方法
CN202210043592.X 2022-01-14

Publications (1)

Publication Number Publication Date
WO2023133932A1 true WO2023133932A1 (fr) 2023-07-20

Family

ID=81512666

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/073388 WO2023133932A1 (fr) 2022-01-14 2022-01-24 Appareil ate fondé sur des paramètres transmis de manière dynamique, et procédé de transmission

Country Status (2)

Country Link
CN (1) CN114490362A (fr)
WO (1) WO2023133932A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI804363B (zh) * 2022-06-23 2023-06-01 英業達股份有限公司 更新測試程式所需函式庫以進行裝置測試之裝置及方法
CN116580757B (zh) * 2023-07-12 2023-09-22 悦芯科技股份有限公司 一种虚拟ate测试方法及系统

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838980A (en) * 1994-01-18 1998-11-17 Sybase, Inc. Compilation and virtual machine arrangement and process for source code including pre-runtime executable language structure constructs
US20050154949A1 (en) * 2004-01-12 2005-07-14 Lucent Technologies Inc. System for flexible embedded Boundary Scan testing
US20150074653A1 (en) * 2013-09-12 2015-03-12 Teradyne, Inc. Executing code on a test instrument in response to an event
CN105209925A (zh) * 2013-04-16 2015-12-30 爱德万测试公司 在用于编译自动化半导体器件测试的测试计划的开发环境内实施编辑并更新功能性
CN110719212A (zh) * 2018-07-13 2020-01-21 是德科技股份有限公司 用于使用源代码测试网络节点的方法、系统和计算机可读介质
CN110908668A (zh) * 2019-11-21 2020-03-24 深圳市新威尔电子有限公司 用于编译电池检测系统脚本程序的编译器
US20200279064A1 (en) * 2019-03-01 2020-09-03 Synopsys, Inc. Automatic Testbench Generator for Test-Pattern Validation

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838980A (en) * 1994-01-18 1998-11-17 Sybase, Inc. Compilation and virtual machine arrangement and process for source code including pre-runtime executable language structure constructs
US20050154949A1 (en) * 2004-01-12 2005-07-14 Lucent Technologies Inc. System for flexible embedded Boundary Scan testing
CN105209925A (zh) * 2013-04-16 2015-12-30 爱德万测试公司 在用于编译自动化半导体器件测试的测试计划的开发环境内实施编辑并更新功能性
US20150074653A1 (en) * 2013-09-12 2015-03-12 Teradyne, Inc. Executing code on a test instrument in response to an event
CN110719212A (zh) * 2018-07-13 2020-01-21 是德科技股份有限公司 用于使用源代码测试网络节点的方法、系统和计算机可读介质
US20200279064A1 (en) * 2019-03-01 2020-09-03 Synopsys, Inc. Automatic Testbench Generator for Test-Pattern Validation
CN110908668A (zh) * 2019-11-21 2020-03-24 深圳市新威尔电子有限公司 用于编译电池检测系统脚本程序的编译器

Also Published As

Publication number Publication date
CN114490362A (zh) 2022-05-13

Similar Documents

Publication Publication Date Title
US5651111A (en) Method and apparatus for producing a software test system using complementary code to resolve external dependencies
WO2023133932A1 (fr) Appareil ate fondé sur des paramètres transmis de manière dynamique, et procédé de transmission
Hu et al. DeGPT: Optimizing Decompiler Output with LLM
CN117707499A (zh) 基于虚拟化技术的多源模型算法解析器插件及编译算法
CN117411906A (zh) 一种嵌入QuickJS引擎的RTOS的实现方法及系统
Farias et al. ESBMC-Python: A Bounded Model Checker for Python Programs
Lee et al. A New Integrated Software Development Environment Based on SDL, MSC, and CHILL for Large‐scale Switching Systems
CN115373988A (zh) 测试用例的生成方法、测试方法、电子设备及存储介质
CN112100059B (zh) 一种c语言的指针类型分析方法
EP1388063B1 (fr) Systeme et procede d'acquisition d'assertions automatisee dans un environnement de test de compatibilite java
Smith et al. A more agile approach to embedded system development
Stange Model checking for SCCharts
Grigorev et al. String-embedded language support in integrated development environment
Qiao et al. An Efficient DSP Simulator Design Supporting Multi-Core Debugging
CN116301906A (zh) 一种模块化的c语言通用编译器
Yu et al. An Efficient and Secure Inline Assembly Design for VLIW DSP
Rababaah Simple Imperative Model Programming Language for Education–SIMPLE
Kheradmand A formal semantics of P4 and applications
d'Souza Eclipse CDT code analysis and unit testing
Wang et al. DSP Assembler Auto-Generation Technique and ToolChain Integration
Loitzl Supporting Register Pairs in CompCert
d’Souza HAL Id: hal-01939872
de Miguel et al. A Pragmatic Approach to Verification, Validation and Compilation
Guillou et al. A Dynamic to Static DSL Compiler for Image Processing Applications
Chen et al. Essential loss: Bridge the gap between ranking measures and loss functions in learning to rank

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22919578

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE