WO2023133932A1

WO2023133932A1 - Ate apparatus based on dynamically transmitted parameters, and transmission method

Info

Publication number: WO2023133932A1
Application number: PCT/CN2022/073388
Authority: WO
Inventors: 李行
Original assignee: 上海御渡半导体科技有限公司
Priority date: 2022-01-14
Filing date: 2022-01-24
Publication date: 2023-07-20
Also published as: CN114490362A

Abstract

An ATE apparatus based on dynamically transmitted parameters, and a transmission method. The ATE apparatus comprises a test program module, a compiler, a variable code module, and a test execution module; the variable code module is used for receiving a test condition; the compiler is used for compiling a program in the test program module to form an executable first machine instruction part, and the test execution module comprises a grammar parser ATPL, a virtual machine unit CVM, a test flow scheduling unit, and a communication unit; the grammar parser ATPL reads a test condition source code sentence by sentence, firstly performs lexical analysis and grammar analysis, then converts the source code into an intermediate code, optimizes the intermediate code, and finally interprets the intermediate code into an executable second machine instruction part, and the executable second machine instruction part is executed by the virtual machine unit CVM; and the test flow scheduling unit schedules a test flow according to an execution result of the CVM, and executes an interactive test with a tested device DUT by means of the communication unit.

Description

An ATE device and transmission method based on dynamic transmission parameters

cross reference

This application claims the priority of the Chinese patent application with application number CN 202210043592.X filed on January 14, 2022. The content of the above application is incorporated herein by reference.

technical field

The present invention relates to the field of semiconductor automatic test equipment (Automatic Test Equipment, referred to as ATE), in particular to an ATE device and transmission method based on dynamic transmission parameters.

technical background

Chip testing plays an extremely important role in the entire semiconductor industry chain. As the complexity of integrated circuits increases, so does the complexity of testing. Large-scale integrated circuits often require hundreds of voltage, current, and timing tests and millions of functional test steps to ensure the completeness of the device. Correct, this also makes the test cost of the chip higher and higher, and the test cost of some devices even accounts for the vast majority of the chip cost.

Automatic test equipment is a collection of test instruments controlled by a high-performance computer. It is a test system composed of a tester and a computer. The computer controls the test hardware by running the instructions of the test program. The semiconductor chip testing machine is used to test the integrity of the function and performance of integrated circuits, and is an important equipment to ensure the quality of integrated circuits in the production process of integrated circuits. The most basic requirement of the test system is to ensure the rapidity, reliability and stability of the test function. Among them, rapidity is particularly important; therefore, how to improve the testing speed of chips is a common topic in the semiconductor testing machine industry.

At present, the common solution in the industry is to control the chip testing process by writing a test program (TestProgram) for ATE. Due to the performance reasons of the automatic test equipment, the compiled programming language Cpp is generally used for the development of the test program.

Since it is necessary to continuously modify the debugging test conditions (such as hardware resources, port numbers, input stimulus and signal size, etc.) in the test program, the program needs to be modified for each debugging, and in each test program, different test items Different test procedures need to be changed. Due to the characteristics of the compiled language, once the test program is modified, the entire test needs to be recompiled, linked and executed to take effect for the changed test conditions, which reduces the debugging efficiency and lengthens the development time. If the test program is developed in an interpreted language, most of the codes that are not frequently changed still exist in the test program, so part of the performance will be lost.

Therefore, the industry urgently needs to provide a method of dynamically passing parameters, which can dynamically load the test conditions that need to be modified during debugging into the test program for execution, so that the test program can take effect for the changed test conditions without recompiling and linking. Effectively improve chip testing efficiency.

Summary of the invention

The purpose of the present invention is to provide a method for improving chip testing efficiency by dynamically passing parameters, which can dynamically load the test conditions that need to be modified when the chip test program is debugged into the test program, so that the test program can be updated without recompiling and linking. The changed test conditions take effect.

To achieve the above object, the technical scheme of the present invention is as follows:

A device for improving chip testing efficiency by dynamically passing parameters, based on an ATE device for dynamically passing parameters, used to measure at least one device under test DUT; it is characterized in that it includes a test program module, a compiler, a variable code module and test execution module; wherein, the test program module includes a fixed code program and a test condition interface program, the variable code module is used to receive a test condition, and the test condition includes at least one dynamically changing parameter; the compiler is used to compile the The program in the test program module forms an executable first machine instruction part, and the test execution module includes a syntax parser ATPL, a virtual machine unit CVM, a scheduling test flow unit and a communication unit; the syntax parser ATPL is sentence by sentence Read the source code of the test condition, first perform lexical analysis and syntax analysis, then convert the source code into an intermediate code and optimize it, and finally interpret the intermediate code into an executable second machine instruction part, which is determined by the virtual The machine unit CVM executes the second machine instruction part; the scheduling test flow unit schedules the test flow according to the execution result of the CVM, and executes the interaction test with the DUT through the communication unit.

Further, the test conditions include hardware resources, port numbers, input stimuli and/or signal magnitude values of the ATE device.

To achieve the above object, another technical solution of the present invention is as follows:

A parameter method of an ATE device based on dynamic parameter transfer, comprising:

Step S1: dynamically configuring parameters in the test conditions involved in the test program module;

Step S2: the compiler is used to compile the program in the test program module to form an executable first machine instruction part;

Step S3: The syntax parser ATPL reads the test condition source code sentence by sentence, first performs lexical analysis and syntax analysis, then converts the source code into intermediate code and optimizes it, and finally interprets the intermediate code as executable The second machine instruction part of

Step S4: and execute the second machine instruction part in the corresponding virtual machine unit CVM to form the target code;

Step S5: The scheduling test flow unit schedules the test flow according to the CVM execution result, and executes an interactive test with the DUT through the communication unit to obtain a test result.

Further, the step S3 specifically includes:

Step S31: lexical analysis, that is, scanning the source file, and splitting the character stream of the source file into individual words (marks);

Step S32: grammar analysis, constructing a grammar tree from these tokens according to grammar rules;

Step S33: Semantic analysis, checking the relationship between each node of the syntax tree, checking whether the semantic rules are violated, and performing necessary optimization on the syntax tree;

Step S34: Traversing the nodes of the syntax tree, converting each node into an intermediate code, and assembling them in a specific order, this is intermediate code generation;

Step S35: optimizing the intermediate code;

Step S36: converting the intermediate code into object code;

Step S37: Optimizing the object code to generate a final object program.

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

①. Realize the development of modularization. Modularization is one of the key goals to be achieved when designing the test program. This architecturally mature and efficient approach to testing allows users to write independent components that handle different aspects of testing; and, allows these components to be mixed and matched in various ways to produce a complete test program.

Therefore, the mode of the virtual machine unit CVM plus the parser ATPL allows the information required by the test program to be executed in different compilation modes, decoupling the overall framework, and improving the reusability and scalability of the test program.

②, High readability, whether it is the development process or later maintenance, the readable code formed by the above scheme can greatly improve the programming efficiency and make the code structure better.

For this reason, the present invention does not add configuration file or the file of other DSL syntax, but directly carries out the modification and debugging of parameter and instruction on source file, reduces the learning cost of developer.

③. Support online editing and real-time validation. The execution mode of the syntax parser ATPL and virtual machine unit CVM enables developers to edit test conditions online and take real-time validation, which greatly improves the efficiency of debugging and development.

④. Realize process optimization. Take Advantest Company as an example. The test programming language of Advantest specifies the objects used in the test plan written by the user and the relationship between each object. These program files are converted into C++ codes by the compiler of Advantest Company, and Through their test system, it is packaged into a Windows dynamic link library (DLL) and loaded into the test scheduling software for execution.

That is to say, Advantest's conversion process from test plan description to implementation is divided into two stages: translation and compilation. They need to convert the test programming language into C++ language first, and then proceed to the next step of compilation, linking, loading, execution, etc. steps, the whole process is rather cumbersome.

The modes of the syntax parser ATPL and the virtual machine unit CVM are optimized for the test process. The test programming language can be compiled directly through the ATPL parser, and the machine code is generated in the callback function of the syntax tree, and directly executed through the virtual machine unit CVM operation stack. The instruction set does not need to be translated into C++ code and integrated into the project, which significantly improves the test efficiency and saves test time.

Description of drawings

Figure 1 shows a schematic diagram of the compilation and execution flow of a Cpp-like compiled language

Figure 2 shows the flowchart of ATPL parser in parsing language

Figure 3 is a schematic diagram of functional modules of a device for improving chip testing efficiency by dynamically transferring parameters in an embodiment of the present invention

Fig. 4 shows that in the embodiment of the present invention, the schematic diagram of the method for improving chip test efficiency by dynamically transferring parameters

Fig. 5 shows the schematic diagram of the workflow of the ATPL grammar parser in the embodiment of the present invention

Contents of the invention

Below in conjunction with accompanying drawings 1-5, the specific embodiment of the present invention will be described in further detail.

It should be noted that the device adopted by the present invention to improve chip testing efficiency by dynamically passing parameters realizes a CVM (Cpp Virtual Machine) virtual machine and an ATPL (Automatic Test Program Language) parser for translating Cpp codes into machine codes Execute directly.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a compilation and execution flow of a Cpp-like compiled language. As shown in Figure 1, the compilation and execution process of a compiled language such as pp includes the following steps:

Source code→preprocessor→compiler→object code→linker→executables→execute

In this workflow, the compiler calls the preprocessor to perform related processing, optimize the source code conversion (including clearing comments, macro definitions, include files, and conditional compilation), and then compile the preprocessed source code into object code (binary machine language), and then by calling the linker plus library files (such as the API provided by the operating system), an executable program is formed so that the machine can execute it. And the object code must match the CPU architecture of the machine, and the library file must match the operating system. If you want to run the source code of the Cpp language on a machine or system with different CPUs, you need to compile it for different CPU architectures and operating systems, so that you can run the program on the machine.

Please refer to Fig. 2, Fig. 2 shows the flow diagram of the ATPL grammar parser when parsing the type language. As shown in Figure 2, the analytic language mainly has the following steps:

Source code (source code) → interpreter (interpret) → execution (execute)

The source code does not need to be pre-compiled into an executable program. When the program is executed, after the interpreter reads a sentence of source code, it first performs lexical analysis and syntax analysis, and then converts the source code into an intermediate code (byte code) that the interpreter can execute. Finally, the interpreter interprets the intermediate code It is an executable machine instruction, and executes the instruction in the corresponding virtual machine.

Compiled languages such as Cpp need to be compiled, linked, loaded, and executed to execute machine instructions, while analytic languages execute machine instructions directly after syntax analysis, eliminating the steps of compiling, linking, loading, and generating executable files. It is very suitable for debugging chip test conditions. However, if all analytical languages are used, some performance will be lost because the code that is not frequently changed accounts for the vast majority of the test program.

Therefore, the present invention combines the two, and those programs that are not frequently changed can be compiled into machine codes in advance, and codes that need to be frequently changed and debugged, such as test conditions, can be translated into machine codes by an interpreter Finally, the built-in virtual machine executes and obtains the result, which can achieve the effect of dynamic parameter passing, shorten compilation time, and improve debugging efficiency.

Please refer to FIG. 3 . FIG. 3 is a schematic diagram of functional modules of a device for improving chip testing efficiency by dynamically passing parameters in an embodiment of the present invention. As shown in Figure 3, the ATE device based on dynamic transfer parameters is used to measure at least one device under test DUT; it includes a test program module, a compiler, a variable code module and a test execution module; wherein the test program The module includes a fixed code program and a test condition interface program, the variable code module is used to receive a test condition, and the test condition includes at least one dynamically changing parameter; the compiler is used to compile the program in the test program module, Form the executable first machine instruction part, the test execution module includes a grammar parser ATPL, a virtual machine unit CVM, a scheduling test flow unit and a communication unit; the grammar parser ATPL reads the test condition source code sentence by sentence , first perform lexical analysis and syntax analysis, then convert the source code into an intermediate code and perform optimization, and finally interpret the intermediate code into an executable second machine instruction part, and execute the second machine instruction by the virtual machine unit CVM Part: the scheduling test flow unit schedules the test flow according to the CVM execution result, and executes the interaction test with the DUT through the communication unit.

The test conditions may include hardware resources, port numbers, input stimuli and/or signal magnitude values of the ATE device. Different from the prior art, in the embodiment of the present invention, parameters such as hardware resource, port number, input stimulus and/or signal size value of the initialized ATE device can be dynamically adjusted during the test.

That is to say, the virtual machine unit CVM can translate the source program of the programming language Cpp commonly used in the field of chip testing into machine code through the parser ATPL, and execute it inside the virtual machine. By executing these target codes, it provides the input stimulus and test conditions required by the test program, so that developers can easily edit and debug test plans and test items, and the edited test items will take effect in real time when they are executed.

Please refer to FIG. 4 . FIG. 4 is a schematic diagram of a method for improving chip testing efficiency by dynamically transferring parameters in an embodiment of the present invention. As shown in Figure 4, the method includes the following steps:

Step S1: Dynamically configure the parameters in the test conditions involved in the test program module.

Step S2: the compiler is used to compile the program in the test program module to form the executable first machine instruction part. That is to say, in the present invention, the test program is modularized, and the fixed part of the program and the part of the program that needs to be frequently modified and debugged are coded in separate files.

The above-mentioned fixed part of the test program is compiled into an executable file by the Cpp compiler provided by the system to form the executable first machine instruction part.

The other part of the code related to the test conditions does not participate in the compilation, which is very convenient. If you need to modify the code related to the test conditions, you can directly modify it in the corresponding source file. Afterwards, there is no need to compile the test program and run it directly, and the modified test conditions will take effect immediately.

Step S3: the syntax parser ATPL reads the test condition source code sentence by sentence, first performs lexical analysis and syntax analysis, then converts the source code into intermediate code that the syntax parser ATPL can execute, and finally The parser ATPL interprets the intermediate code into an executable second machine instruction portion.

Please refer to FIG. 5 . FIG. 5 is a schematic diagram of the workflow of the ATPL parser in the embodiment of the present invention. As shown in Figure 5, the step S3 may specifically include:

Step S35: optimizing the intermediate code;

Step S36: converting the intermediate code into object code;

Step S37: Optimizing the object code to generate a final object program.

Step S4: and splicing the first machine instruction part and the second machine instruction part through the application program interface API in the corresponding virtual machine unit CVM to form the target code.

Step S5: the dispatching test flow unit translates the target code, and executes an interaction test with the device under test (DUT) through the communication unit to obtain a test result.

That is to say, after the test program is running, these codes are dynamically loaded into the process through the embedded virtual machine unit CVM plus syntax parser ATPL, translated into target codes, executed in the virtual machine unit CVM, and Obtain calculation results, save the steps of recompiling and linking the entire program, and improve the efficiency of chip testing and debugging.

In summary, the present invention provides a device and transmission method for improving chip testing efficiency through dynamic transmission of parameters, which provides a method for dynamic parameter transmission, which can dynamically load the test conditions that need to be modified during debugging into the test program for execution , so that the test program can take effect on the changed test conditions without recompiling and linking, which can effectively improve the efficiency of chip testing.

The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention, so all equivalent structural changes made by using the description and drawings of the present invention should be included in the same reason Within the protection scope of the appended claims of the present invention.

Claims

A kind of ATE device based on dynamic transmission parameter, is used for measuring at least one equipment under test DUT; It is characterized in that, comprises test program module, compiler, variable code module and test execution module; Wherein, described test program module includes A fixed code program and a test condition interface program, the variable code module is used to receive a test condition, and the test condition includes at least one dynamically changing parameter; the compiler is used to compile the program in the test program module to form a The first machine instruction part of execution, the test execution module includes syntax parser ATPL, virtual machine unit CVM, scheduling test flow unit and communication unit; the syntax parser ATPL reads the test condition source code sentence by sentence, first Perform lexical analysis and syntax analysis, then convert the source code into an intermediate code and perform optimization, then interpret the intermediate code into an executable second machine instruction part, and execute the second machine instruction part in the virtual machine unit CVM ; The scheduling test flow unit schedules the test flow according to the CVM execution result, and executes the interaction test with the DUT through the communication unit.
The ATE device based on dynamic transfer parameters according to claim 1, wherein the test conditions include hardware resources, port numbers, input stimulus and/or signal size values of the ATE device.
An ATE device based on dynamic transfer parameters, using the ATE device method described in claim 1 or 2, characterized in that it comprises:

Step S1: dynamically configuring parameters in the test conditions involved in the test program module;

Step S2: the compiler is used to compile the program in the test program module to form an executable first machine instruction part;

Step S3: The syntax parser ATPL reads the test condition source code sentence by sentence, first performs lexical analysis and syntax analysis, then converts the source code into intermediate code and optimizes it, and finally interprets it as an executable second machine instruction section;

Step S4: and execute the second machine instruction part in the corresponding virtual machine unit CVM;

Step S5: The scheduling test flow unit schedules the test flow according to the CVM execution result, and executes an interactive test with the DUT through the communication unit to obtain a test result.
The method for improving chip testing efficiency by dynamically transferring parameters according to claim 3, wherein said step S3 specifically includes:

Step S31: lexical analysis, that is, scanning the source file, and splitting the character stream of the source file into individual words;

Step S32: grammar analysis, constructing a grammar tree from these tokens according to grammar rules;

Step S33: Semantic analysis, checking the relationship between each node of the syntax tree, checking whether the semantic rules are violated, and performing necessary optimization on the syntax tree;

Step S34: Traverse the nodes of the syntax tree, convert each node into an intermediate code, and assemble them in a specific order, which is intermediate code generation;

Step S35: optimizing the intermediate code;

Step S36: converting the intermediate code into object code;

Step S37: Optimizing the object code to generate the final object program.