WO2023133466A1 - Distribution efficace de données d'image pour un réseau de cellules de mémoire de pilote de pixel - Google Patents

Distribution efficace de données d'image pour un réseau de cellules de mémoire de pilote de pixel Download PDF

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Publication number
WO2023133466A1
WO2023133466A1 PCT/US2023/060174 US2023060174W WO2023133466A1 WO 2023133466 A1 WO2023133466 A1 WO 2023133466A1 US 2023060174 W US2023060174 W US 2023060174W WO 2023133466 A1 WO2023133466 A1 WO 2023133466A1
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WIPO (PCT)
Prior art keywords
drivers
pixel
row
driver
array
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PCT/US2023/060174
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English (en)
Inventor
Bo Li
Kaushik Sheth
Edwin Lyle Hudson
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Google Llc
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Publication date
Priority claimed from US17/568,831 external-priority patent/US20220130344A1/en
Priority claimed from US18/067,267 external-priority patent/US20230197029A1/en
Application filed by Google Llc filed Critical Google Llc
Priority to KR1020247025780A priority Critical patent/KR20240132471A/ko
Priority to CN202380020039.7A priority patent/CN118633120A/zh
Publication of WO2023133466A1 publication Critical patent/WO2023133466A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the pixel driver of 6,005,558 and the pixel driver of 7,443,374 have approximately the same effect on an associated liquid crystal layer but accomplish this through means that are otherwise substantially dissimilar.
  • Other pixel drivers relying on one-bit SRAM or DRAM devices may benefit from the implementations described herein.
  • backplanes are not able to simultaneously drive wordlines and bitlines at very high speeds (e.g., frequencies) and/or tight timing tolerances.
  • Known backplanes often have buffer circuits (e.g., arrays of inverters, etc.) and/or timing circuits outside of a pixel driver array that have metal lines, semiconductor device diffusions, connections to transistors, and/or so forth that are prone to variations due to semiconductor processing, temperature, undesirable stray inductances, and/or so forth.
  • the components outside of the pixel driver array of a backplane can respond differently to variations than components inside of the pixel driver array of a backplane.
  • timing, frequency, and so forth of known backplanes are slowed down to increase timing windows to drive pixel displays with image data in a desirable fashion.
  • respective mismatches in the effect of variations on the components inside and outside of a pixel driver array of a backplane can necessitate an increase in, for example, timing windows of the backplane in order for the backplane to properly drive a corresponding pixel display.
  • timing windows are adjusted to account for mismatches in the respective effect of variations on components inside and outside of a pixel driver array of a backplane associated with a pixel display.
  • the technical solution described herein (which can be referred to as Resistive-Capacitive (RC) tracking) includes backplane circuitry configured to eliminate mismatches of the effects of variations on the backplane and, specifically, components inside and outside of the pixel driver array within the backplane due to semiconductor processing, temperature, undesirable stray inductances, and/or so forth. This can be referred to as RC tracking because variations (due to semiconductor processing, temperature, etc.) of components outside of the pixel driver array track the variations of components inside of the pixel driver array.
  • the array of dummy pixel drivers can include only portions (e.g., copied portions) of an actual (or active) pixel driver (e.g., just the data storage element (or a disabled version (e.g., deactivated version) of the data storage element) of a pixel driver).
  • These arrays of dummy pixel drivers e.g., dummy bitline pixel driver array, dummy wordline pixel driver array
  • are outside of the pixel driver array e.g., active pixel driver array
  • Bidirectional clock signal line 111 provides a clock signal from an external control device (not shown) operative to deliver data to the SLM in coordination with the clock. In one embodiment, both rising edge and falling edge clock edges are used.
  • the data storage element 120 can include other circuit elements such as drivers, inverters, and/or so forth. Such circuit elements can be coupled to, for example, conductor 138 and/or conductor 139.
  • the data storage element 120 can be included in a dummy bitline (e.g., within a row select path) and/or in a dummy wordline (e.g., within a data load trigger path).
  • the data storage element 120 can be included in a dummy bitline to be a dummy pixel driver or simulate a pixel driver (or at least a portion thereof) and/or in a dummy wordline to be a dummy pixel driver or simulate a pixel driver (or at least a portion thereof).
  • the data storage element 120 shown in FIG. IB can be modified to be inoperable.
  • the data storage element 120 when modified to be inoperable can be referred to as a disabled data storage element or as a deactivated data storage element.
  • the disabled data storage element may be disabled such that the data storage element cannot be programmed or cannot store information (e.g., cannot be used as a storage element).
  • the wordline 121 can be tied to ground or VSS so that the data storage element does not function properly as an SRAM device.
  • a row decoder is limited to four NAND gates because, if more NAND gates are used, the resultant circuit becomes electrically complex and unacceptably slow.
  • the decoding is separated into predecoders that in turn provide inputs into a series of decoder circuits. As this is well known and attested to, it is not repeated here. See, for example, VLSI-Design of Non-Volatile Memories. G. Campardo, et al, pages 185 - 188, especially the bottom of page 187, Springer Verlag, Berlin et al, 2005, (hereafter Campardo 2005).
  • Voltage level shifter 142a receives a signal from AND gate 116a over terminal 119a
  • voltage level shift 142b receives a signal from AND gate 116b over terminal 119b.
  • Each of all other voltage level shifters (not shown) receives a signal from its respective AND gate over a terminal. All these signals are 0 except for the signal from the one selected row.
  • Voltage level shifters 142a, 142b and all other voltage level shifters (not shown) associated with row drivers are connected to a VDD_WL (VDD WordLine) source over conductorl46.
  • the outputs of voltage level shifters 142a and 142b are connected to inverters 143a and 143b respectively.
  • the outputs of all other voltage level shifters (not shown) that form part of row drivers are in like manner connected to inverters.
  • the output of inverter 143a is asserted on conductor 148a and the output of inverter 143b is asserted on conductor 148b.
  • All other inverters (not shown) are likewise asserted onto conductors and onto feedback conductors.
  • conductor 148a, conductor 148b, and all other conductors driven in a similar manner are wordlines (WLINE) of an array of pixel driver.
  • the array of dummy drivers 198a introduces RC characteristics along the trigger gate line 117 (which can also be referred to as an enable line), when within, for example, a row select path (or dummy bitline) that mirrors the RC characteristics of a bitline within a pixel driver array (e.g., pixel driver array 101 shown in FIG. 1C).
  • the array of dummy drivers 198a can be substantially identical to the configuration of a bitline other than being disabled (e.g., having disabled data storage elements) so that the RC characteristics of the array of dummy drivers 198a replicates the RC characteristics of an active bitline within an active pixel driver array as much as possible.
  • the row drivers 140a, 140b (which can be referred to as a set or section of row drivers) are connecting at a tap 197a-l from the array of dummy drivers 198a (e.g., dummy bitline drivers).
  • inverters are optionally connected between the tap 197a-l and the row drivers 140a, 140b.
  • the row drivers 140a, 140b and the array of dummy drivers 198a can be disposed outside of an active pixel driver array (e.g., pixel driver array 101 shown in FIG. 1A).
  • Another section of row drivers (not shown) can be connected via tap 197a-2 to the array of dummy drivers 198a.
  • the row drivers 140a, 140b can be included in a section of row drivers that includes more than two row drivers.
  • FIG. 1C illustrates an array of dummy drivers 198b parallel to the array of dummy drivers 198a.
  • One or more sections of row drivers can be tapped from the array of dummy drivers 198b.
  • the implementation of arrays of dummy drivers (e.g., parallel arrays of dummy drivers) and sections of row drivers tapped from the arrays of dummy drivers (as described in FIG. 1C) and associated with (e.g., outside of) a pixel driver array is described in more detail in at least FIG. 7B.
  • FIG. ID illustrates column driver 160.
  • Memory cell 163 receives and stores a bit of image data for a plane of image data from an external source.
  • the stored data is asserted on terminal 175 which asserts that data value onto voltage level converter 164.
  • Voltage level converter 164 asserts the converted data voltage level onto terminal 174 which asserts that data voltage onto data terminal D of logic circuit 165.
  • voltage shifter circuit 164 is replaced with a straight through conductor.
  • logic circuit 165 is a circuit with two stable states.
  • the voltage asserted on data terminal D is asserted onto Q and its complement onto terminal Q.
  • the voltage asserted onto terminal Q is asserted onto output terminal 167. Terminal Q is not used.
  • Output terminal 167 in turn asserts the value of terminal Q onto inverter 161a.
  • inverter 161a The output of inverter 161a is asserted onto the input of inverter 161b.
  • the output of inverter 161b holds the same logic value as the input to inverter 161a.
  • inverters 161a and 161b form a buffer operative to isolate column driver 160 from capacitive loading present on the complementary bitlines.
  • the output of inverter 161b is asserted onto bitline 168 and onto the input to inverter 176.
  • the output of inverter 176 is asserted onto bitline 177, which logically forms a complementary bitline pair with bitline 168.
  • a D latch is a level sensitive circuit with nodes comprising a data input node D, a clock node CLK, and output nodes Q and Q.
  • CLK clock node
  • Q output nodes
  • propagation delay also known as path propagation delay.
  • path propagation delay As previously noted, applicant has developed arrays with more than 9.8 million pixels (4096 x 2400). The intersection of each row with each column represents two unique paths.
  • the column driver 160 when included in a dummy wordline (e.g., within a data load trigger path), the column driver 160 (or multiple column drivers) can be connected to an array of dummy drivers 199a (e.g., array of dummy drivers 199a including disabled data storage elements).
  • the disabled data storage elements can be modified versions of the data storage element 120 shown in at least FIG. IB.
  • the array of dummy drivers 199a are illustrated with dashed lines because these elements are optionally included with the column driver 160 when included in a dummy wordline.
  • the array of dummy drivers 199a introduces RC characteristics along the trigger gate line 118 (which can also be referred to as an enable line), when within, for example, a data load trigger path (or dummy wordline) that mirrors the RC characteristics of a wordline within a pixel driver array (e.g., pixel driver array 101 shown in FIG. 1A).
  • the array of dummy drivers 199a can be substantially identical to the configuration of a wordline other than being disabled (e.g., having disabled data storage elements) so that the RC characteristics of the array of dummy drivers 199a replicates the RC characteristics of an active wordline within an active pixel driver array as much as possible.
  • the column driver 160 (which can be included in a set or section of column drivers (not shown)) are connecting at a tap 196a-l from the array of dummy drivers 199a (e.g., dummy wordline drivers).
  • inverters are optionally connected between the tap 196a-l and the column driver 160.
  • the column driver 160 and the array of dummy drivers 199a can be disposed outside of an active pixel driver array (e.g., pixel driver array 101 shown in FIG. 1C).
  • Another section of column drivers (not shown) can be connected via tap 196a-2 to the array of dummy drivers 199a.
  • the column driver 160 can be included in a section of column drivers that includes more than one column driver.
  • a first path is a row select path 261 (also can be referred to as a dummy bitline) combined with the wordline 262 for a row, referred to as the wordline path 260 hereafter.
  • the row select path 261 is a first part of the wordline path 260 and the wordline 262 is a second part of the wordline path 262.
  • the row select path 261 is disposed outside of (e.g., outside of an area of) the pixel driver array 150.
  • the row select path 261 is aligned along a bitline direction (vertical direction as shown in FIG. 2A).
  • the row select path 261 can include an array of dummy drivers and row drivers as shown in, for example, FIG. 1C.
  • Several types of circuits are known that allow a single row of a memory device to be selected.
  • the row is designated by an address location that causes a row decoder to select that particular row before a signal is sent to the row to pull the wordline 262 high.
  • the output of a row decoder enters an AND gate that also is configured to receive a separate trigger signal delivered to all AND gates able to receive the output of the row decoder.
  • the wordline 262 itself forms the second part of the wordline path 260, comprising the physical distance from the row driver (e.g., row driver 140a shown in FIG. 1C) along the wordline 262 to the pixel driver of interest 280.
  • All trigger signal generating circuits also referred to as trigger initiating circuits 250 may function as release timing circuits.
  • a second path is the bitline path 270.
  • the bitline path 270 includes a data load trigger path 271 (e.g., a first part of the bitline path) that delivers a voltage to a circuit in the bitline driver that releases the data stored on the bitline driver to the array of the display and the complementary bitlines (e.g., bitline 272 which is a second part of the bitline path) to the pixel driver of interest 280.
  • the data load trigger path 271 is a first part of the bitline path 270 and the bitline 272 is a second part of the bitline path 270.
  • the data load trigger path 271 is disposed outside of (e.g., outside of an area of) the pixel driver array 150.
  • the data load trigger path 271 also can be referred to as a dummy wordline.
  • the data load trigger path 271 is aligned along a wordline direction (horizontal direction as shown in FIG. 2A).
  • the data load trigger path 271 can include an array of dummy drivers and column drivers as shown in, for example, FIG. IE.
  • a pixel driver array 150 (e.g., SRAM array) that is m columns wide by n rows high is illustrated for discussion of propagation delay.
  • a trigger signal (from the trigger initiating circuit 250) for the release of image data onto the bitlines (e.g., bitline 272) and a trigger signal (from the trigger initiating circuit 250) to activate circuitry associated with the row drivers to pull the wordline 262 high are presumed to originate in the trigger initiating circuit 250 proximate to coordinates (0, 0) in the lower left-hand comer of the pixel driver array 150.
  • trigger signals may originate in more than one location from one or more trigger initiating circuits (e.g., trigger initiating circuit 250).
  • a first location may be proximate to the lower left comer of the pixel driver array 150 in a trigger initiating circuit (similar to trigger initiating circuit 250) and a second location may be proximate to the lower right comer of the pixel driver array 150 in a trigger initiating circuit, and the lower left trigger initiating circuit in the first location may handle the left half of the pixel driver array 150 and the lower right trigger initiating circuit in the second location may handle the right half of the pixel driver array 150.
  • the trigger signal may originate from a location above the pixel driver array 150, on a top left comer of the pixel driver array 150, and/or the top right comer of the pixel driver array 150.
  • the time from when the trigger signal is sent from the trigger initiating circuit 250 adjacent to coordinate (0, 0) along the row select path (e.g., a first part of the wordline path) to the AND gate until the trigger signal arrives at the AND gate adjacent to coordinate (0, y) is depicted as TRi.
  • TRi represents the time required for the trigger signal to propagate from the point adjacent to coordinate (0, 0) to coordinate (0, y) along the row select path.
  • the use of distance to represent time is appropriate because the propagation delay along the row select path has a uniform characteristic when the circuits carrying a signal on that part of the row select path are uniform and repetitive.
  • the second part of the wordline path is the wordline.
  • the wordline for an array of SRAM type memory cells is connected to the gates of pass transistors such as transistors 128 and 129 of data storage element 120 of FIG. IB.
  • the resistance of the wordline and the capacitance of the wordline and of the connections to the pass transistors define the RC characteristic of the wordline and therefore the propagation delay of the wordline.
  • the RC characteristic of the wordline may differ from the RC characteristic of the line on which the trigger signal used as an input to the AND gate at each row driver propagates.
  • pixel driver location (x, y) is at a physical position relative to the origin at (0, 0) of X distance units times x laterally and Y distance units times y vertically.
  • the choice of distance unit is arbitrary, although most modem pixel drivers are specified in microns, or millionths of a meter from center to center.
  • the time required for a signal to propagate from coordinate (0, 0) to coordinate (0, y) is greater than the time required for a signal to propagate from coordinate (0, 0) to coordinate (0, y-1) and less than the time required for a signal to propagate from coordinate (0, 0) to coordinate (0, y+1). This results from the difference in path length along the Y-axis.
  • a first part of the bitline path that brings the trigger signal from the trigger initiating circuit 250 to the column driver extends from coordinates (0, 0) to (x, 0) along the data load trigger path, which is along the X-axis of array 150.
  • the time required for the signal to propagate that distance along the data load trigger path is designated as TBi.
  • the duration of TBi is determined by the RC characteristic of the data load trigger path (e.g., conductors of the data load trigger path) over which the trigger signal propagates.
  • the RC characteristic is in turn determined by the physical characteristics of the data load trigger path, which comprise resistive and capacitive coupling components and the physical characteristics of any transistor nodes along the path, which primarily comprise capacitive coupling components. This may be thought of as a network.
  • the actual voltage of the trigger signal does not affect the RC characteristic of a network.
  • the second part of the bitline path that delivers bitline data to the pixel driver of interest 280 is initiated when the bitline data is released from the column driver.
  • the propagation delay from the time the data is released onto the bitlines for the pixel driver of interest 280 until the data arrives at the pixel driver of interest 280 on the selected bitline depends on the distance from the column driver to the pixel driver of interest in addition to the bitline characteristics, namely the RC delay.
  • the time delay is noted as TB2.
  • TB2 is the time required for the bitline data to propagate along the bitline from coordinate (x, 0) to coordinate (x, y) of the pixel driver of interest 280.
  • the additional delay due to various logic circuits can be lumped together as TB3 (not shown) and treated as a constant value not dependent on the pixel driver position.
  • the wordline path begins with the path from a second trigger initiation (trigger initiating circuit 250) that delivers the trigger signal up the side of the display along the row select path from coordinate (0,0) to coordinate (0,y).
  • the row select path is slightly outside the array but is parallel to the Y -axis as depicted.
  • the additional delay due to various logic circuits can be lumped together as TR3 (not shown) and treated as a constant value not dependent on the pixel driver position.
  • the RC characteristic associated with the path for TRi does not necessarily match the RC characteristic associated with the path for TR2, and that the RC characteristic associated with the path for TBi does not need to match the RC characteristic associated with the path for TB2. If both the RC characteristic and the physical length associated with a first circuit are substantially equal to the RC characteristic and physical length associated with a second circuit, then the propagation delay along the two circuits will be substantially equal.
  • the propagation delays associated with the two physical paths can yield similar propagation delays if the RC characteristics of the two physical paths are substantially the same.
  • the same consideration regarding RC characteristics applies to the case of the path length associated with TR2 and the path length associated with TBi.
  • the difficulty lies in identifying means by which the entire length of the circuit carrying the trigger signal to the row decoder can be RC matched to the bitlines acting as circuits to carry data to the pixel drivers of the selected row.
  • RC matching is the subject of significant development effort in the design of semiconductor devices. Much of the work is devoted to design techniques and practices that reduce the effects of any mismatches in RC matching. While useful for many pure memory designs, techniques such as dividing the wordline into many sub wordlines are less useful in the field of displays based on memory devices at each pixel driver when the goal is to write an entire line of data to the display as rapidly as possible rather than to write a single word to a portion of a row.
  • dummy pixel drivers (or portions thereof) are included in the row select path 261 of the wordline path 260 and dummy pixel drivers (or portions thereof) (e.g., disabled data storage elements 198) are included in the data load trigger path 271 of the bitline path 270.
  • the row select path 261 can include an array of row drivers with disabled data storage elements (e.g., row driver 140a with disabled data storage elements 198a as shown in FIG. 1C).
  • the data load trigger path 271 can include an array of column drivers with disabled data storage elements (e.g., column driver 160 with disabled data storage elements 198 as shown in FIG. IE).
  • the propagation time TRi of a trigger signal along the row select path 261 is substantially equal to the propagation time TB2 a trigger signal along the bitline (e.g., actual pixel drivers) included within the pixel driver array 150.
  • the dummy pixel drivers included in the row select path 261 of the wordline path 260 have an RC characteristic that mirrors an RC characteristic of the bitline (e.g., actual (or active) pixel drivers in the bitline) included within the pixel driver array 150.
  • the propagation time TBi of a trigger signal along the data load trigger path 271 is substantially equal to the propagation time TR2 of a trigger signal along the wordline (e.g., actual pixel drivers) included within the pixel driver array 150.
  • the dummy pixel drivers included in the data load trigger path 271 of the bitline path 270 have an RC characteristic that mirrors an RC characteristic of the wordline (e.g., actual (or active) pixel drivers in the wordline) included within the pixel driver array 150.
  • the equation TRi + TR2 e.g., the wordline path 260
  • TBi + TB2 e.g., the bitline path 270
  • a display controller may be located at a position away from the comer of the array.
  • word lines associated with that display controller may also pass under a section of pixel drivers to reach a portion of an array where the word lines do connect to the memory circuits of pixel drivers. These positions do add to the time required for the word line to pull high at a particular point on the array, but the added time can be taken into account and the added time due to the requirement to pass under another section of pixel drivers is invariant for pixel drivers within that portion of the array. The difference in time to propagate across the pixel drivers of that portion of the display once the signal reaches the closest pixel driver is determined by the RC characteristic of the word line in that section.
  • FIG. 2B depicts a 2 by 2 block of pixels 260 comprising pixel (x, y) 261, pixel (x+I, y) 262, pixel (x, y+1) 263 and (x+I, y+1) 264, that form a part of a pixel displays 150 in FIG. 2A.
  • the depiction emphasizes that the length of the paths to each pixel differs in some way.
  • pixel 262 is on the same row as pixel 261 but one pixel further away from a row driver (not shown) on the left edge of the array.
  • Pixel 263 is located one row directly above pixel 261 which increases the distance from a column driver (not shown) at the base of the part of the pixel display 150.
  • Pixel 264 is located on the row above pixel 261 and one pixel further from the left edge of the the part of the pixel display 150.
  • pixel 262 and pixel 263, depicted as square pixels may appear to have the same path length, other pixel aspect ratios are possible.
  • the pixels may be rectilinear but not square (not shown). In this case the part of the pixel display 150 and row and column drivers will all need to fit into the respective row and column spacings.
  • the pixels may be hexagonal (not shown). In a hexagonal array the pixels of adjoining rows are typically offset one half column from one another although the underlying pixel driver array may be rectilinear. A more specific implementation of FIG. 2A is shown in at least FIG. 7B.
  • FIG. 3 illustrates equivalent circuit 170 for the resistance and capacitance characteristics of a segment of a conductor forming part of a semiconductor, based on a circuit in previously cited Campardo 2005, FIG. 9-10, page 183.
  • Resistors 171a, 171b, and 171c each represent a portion of the resistance on the segments of equivalent circuit 170.
  • the distributed resistance values for resistors 171a, 171b and 171c are each R/3.
  • Each type of conductor has a resistivity p, specified in Q-m (ohm meters).
  • the resistivity of aluminum at 20° C is 2.7 x 10’ 8 Q-m and the resistivity of copper at the same temperature is 1.7 x 10’ 8 Q-m.
  • the three dimensions of a conductor in a VLSI semiconductor are nominally L length, W width and H height.
  • H height is the thickness of the conductor layer on top of the layer below.
  • Capacitors 172a, 172b, 172c and 172d each connected to common ground 173, represent distributed capacitance within the conductor represented by equivalent circuit 170.
  • equivalent circuit 170 with net capacitance C the capacitance for capacitors 172b and 172c are considered to be C/3, The capacitance for end capacitors 172a and 172d are considered to be C/(2*3) or C/6.
  • Arrow 270 indicates the direction of propagation for a signal on the conductor.
  • a conductor may be represented as an equivalent circuit comprising n resistive elements and n+1 capacitive elements.
  • the resistance of each resistor is R/n and the capacitance of all capacitive elements 2 to n is considered to equal C/n.
  • the capacitance of equivalent capacitors 1 and n+1 is considered to equal C/2n.
  • Capacitance in a conductor within a semiconductor has several components that contribute to the total capacitance.
  • One component is referred to as area capacitance is based on a parallel plate model wherein conductors on different levels of a semiconductor are separated by a dielectric medium.
  • Another component is referred to as fringing field capacitance. It’s significance results from the reduction in W width of a conductor to the point where its H height is greater than W width in newer processes with finer design rules.
  • the topic is complex and the subject of a significant amount of advanced research.
  • a reference is Digital Integrated Circuits. A Design Perspective, 2 nd Ed., Rabaey, et al, Pearson Education, Delhi, 2002, pages 136 - 138, (hereafter Rabaey 2002.), the entire contents whereof are incorporated herein by reference.
  • FIGS. 4 A through 5D illustrate implementations (some of which are variations) of the examples described in connection with at least FIGS. 1A-2B and FIGS. 7A-7C.
  • FIG. 4A depicts release signal delivery circuit 180 operative to deliver release signals to the AND gate of a row driver such as AND gates 116a and 116b of row driver 140a, 140b illustrated in FIG. 1C in the present application.
  • Release signal delivery circuit 180 comprises arrays of dummy pixel drivers 181a, 181b and 181c, sample circuits 182a, 182b and 182c, also known as sense circuits, and conductor terminals 183a, 183b and 183c.
  • Modeling in CAD design tools has revealed that it is preferable that the entire pixel driver array be duplicated in the dummy pixel drivers in order to match the C capacitance contributed by the active pixel driver array including the bitlines and wordlines.
  • Arrays of dummy pixel drivers 181a, 181b and 181c each comprise a plurality of dummy pixel drivers, each identical to the active pixel drivers with interconnections such as wordlines and bitlines (not shown) identical to the active pixel drivers of the array of pixel drivers.
  • Sample circuits 182a, 182b and 182c are not found on the active pixel drivers of the array of pixel drivers.
  • Sample circuits 182a, 182b and 182c detect a rising edge of a trigger signal on one of the bitlines (not shown) of dummy pixel drivers 181a, 181b and 181c.
  • Sample circuits 182a, 182b and 182c comprise a rising edge detector circuit and a circuit operative to hold the output signal high for a period of time after the rising edge on the sampled bitline is detected.
  • An alternative name is a sense circuit. The main requirement is that the rising edge detection circuit be able to turn on again when the next rising edge is detected but not remain on the entire time from one rising edge to the next.
  • sense circuits 182a, 182b and 182c also detect the level of the trigger signal and turn the output of each sense circuit to off when the level of the trigger signal falls below a certain level. The output of sense circuits 182a, 182b and 182c are asserted onto conductors 183a, 183b and 183c respectively.
  • Conductors 183a, 183b and 183c each connect to a plurality of AND gates (not shown) each forming part of a row driver such as AND gates 116a and 116b of FIG. 1C at a plurality of terminals such as terminal 184 (one depicted).
  • Arrow 247 indicates the direction of propagation of the release signal in array of dummy pixel driver segments 181a, 181b and 181c.
  • Arrow 251c indicates the direction of propagation within conductor 183c
  • arrow 25 lb indicates the direction of propagation within conductor 183b
  • arrow 25 la indicates the direction of propagation within conductor 183a.
  • a trigger signal source originates in other circuitry (not shown) located below release signal delivery circuit 180.
  • Array of dummy pixel drivers 181a, 181b and 181c operate as a continuous unit.
  • a trigger signal on one of the bitlines of segment of dummy pixel driver array 181c propagates from bottom to top, then continues to propagate on one of the bitlines of dummy pixel driver array 181b and then propagates on one of the bitlines of dummy pixel driver array 181a.
  • the bitlines (not shown) of array of dummy pixel drivers segments 181a, 181b and 181c form a continuous conductor with no circuitry or breaks intervening between segments 181a, 181b and 181c within the individual bitlines.
  • bitlines do connect to the gates of pass transistors (not shown) such as pass transistors 128 and 129 of data storage element 120 shown in FIG. 1C.
  • pass transistors not shown
  • a tap (not shown) on one of the bitlines asserts the value on that bitline (not shown) onto the input to a sense circuit such as sense circuits 182a, 182b and 182c.
  • FIG. 4B depicts segment 190 of a release signal delivery circuit representing one segment of a row release signal circuit similar to release signal delivery circuit 180 of FIG. 4A.
  • Segment 190 comprises array of dummy pixel drivers 191, sense circuit 192, also known as a sample circuit, conductor 193 and a plurality of terminals 194 (one indicated) to connect conductor 193 to the same number of AND gates forming part of a same number of row driver (not shown) similar to row driver 140a of FIG. 1C.
  • the array of dummy pixel drivers is colinear with the array of regular pixel drivers (not shown).
  • Arrow 249 indicates the direction of propagation of the release trigger signal within dummy pixel driver array segment 191.
  • Arrow 248 indicates the direction of propagation of the release sign asserted by circuit element 192 onto conductor 193.
  • segment 190 The structure of segment 190 is important.
  • the direction of propagation of the release trigger signal within dummy pixel driver array segment 190 starts at the bottom and proceeds up as indicated by arrow 249.
  • Sense circuit 192 samples the state of the trigger release signal within dummy pixel driver array 191 and releases a pulse onto conductor 193 corresponding to the state of the trigger release signal.
  • the trigger signal propagates through bitlines (not shown) of dummy pixel driver array 191 at a velocity determined by the RC characteristics of the bitline and the capacitance of the circuit elements attached to it.
  • the output of circuit element 192 propagates onto conductor 193 at a velocity corresponding to the RC characteristics of conductor 193 and the capacitance of the circuit elements (AND gates) attached to it.
  • the data configuration of column driver 234 can be set in a memory cell (not shown) forming a part of column driver 234 in response to a signal from the trigger signal control and generating circuit 231.
  • the data state of the memory cell of column driver 234 may be switched during operation to change the state of the voltage asserted on bitline 235p, thereby acting as a control over the timing of trigger signals on that bitline.
  • Both bitlines 235p and 235n are driven with complementary data in order to match the capacitance of a regular bitline in the array of active pixel drivers.
  • FIG. 4D depicts a detailed block diagram of a single tap circuit 280 after single tap circuit 190 of FIG. 4B.
  • Tap circuit 280 comprises complementary bitlines 28 Ip and 28 In of an array of dummy pixel drivers (not shown), tap 282, sense circuit 283, conductor 284, terminals 285a through 285g, column driver AND gates 286a through 286g and output terminals 287a through 287g.
  • Complementary bitlines 28 Ip and 28 In are operative to deliver a release trigger signal from a control unit (not shown). All trigger signals are released on bitline 28 Ip. In the initial state, bitline 28 In is held high while bitline 28 Ip is held low. When the trigger signal is released on bitline 28 Ip, it is held high and bitline 28 In switches to low. This ensures that the RC characteristic of bitlines 28 Ip and 281 match the RC characteristics of a pair of bitlines in the active array, therefore having substantially the same propagation delay.
  • Tap 282 delivers a signal corresponding to the state of bitline 28 Ip to sense circuit 283.
  • Sense circuit 283 acts as previously described for FIG.
  • Terminal 285a delivers the output of sense circuit 283 to one input port of two-port AND gate 286a wherein two-port AND gate 286a forms a part of a row driver 140a as shown in FIG. 1C.
  • the second input to two-port AND gate 286a comes from the row decoder unit (not shown) as previously described for FIG. 1C.
  • terminals 285b, 285c, 285d, 285e, 285f and 285g deliver the output of sense circuit 283 to one port of two-port AND gates 286b, 286c, 286d, 286e, 286f, and 286g, the other port of those AND gates being connected to a row decoder unit (not shown).
  • the outputs of AND gates 286a through 286g are asserted on output terminals 287a through 287g respectively.
  • terminals 287a through 287g assert the outputs of AND gates 286a through 286g on the input of voltage level shifters forming a part of a row driver (not shown), In one embodiment, terminals 287a through 287g assert the outputs of AND gates 286a through 286g on the input of an inverter forming part of a row driver (not shown). Each row driver asserts its output onto a wordline (not shown). Only one row is selected by the row decoder circuit and therefore only one wordline is held high.
  • Arrow 288 and arrow 289 indicate the direction of propagation of the signal on bitline 28 Ip and on conductor 284 respectively. Because conductor 284 is parallel to bitline 28 Ip with the same direction of propagation for a relatively small number of rows, the net propagation delay on bitline 28 Ip is similar to the net propagation delay on conductor 284.
  • FIG. 5A depicts three segments 201a, 201b and 201c of an array of dummy pixel drivers and associated circuitry 200 operative to provide an associated array of column drivers (not shown) with trigger signals to release data stored on a memory cell onto the bitlines of the associated array of column drivers (not shown) such as column driver 150 160 of FIG. ID. and column driver 162 of FIG. 4C.
  • the wordlines (not shown) of the array of dummy pixel drivers are used as a means for delivering a signal to an associated set of column drivers initiating the release of complementary data onto the bitlines of an array of active pixel drivers.
  • the wordlines of segments 201a, 201b and 201c form a continuous wordline across all sections.
  • a tap on each of segments 201a, 201b and 201c of an array of dummy pixel drivers is connected to circuit elements 202a, 202b and 202c respectively such that a signal present on the tapped wordline of segment.201a is asserted on circuit element 202a, a signal present on the tapped wordline of segment 201b is asserted on circuit element 202b and a signal present on the tapped wordline of segment 201c is asserted on circuit element 202c.
  • circuit elements 202a, 202b and 202c may be sense elements similar to sense elements 237a through 237g of FIG.4C.
  • circuit elements 202a, 202b and 202c are asserted onto conductors 203a, 203b and 203c respectively.
  • the tapped wordlines of segments 201a, 201b and 201c are different wordlines of the array of dummy pixel drivers.
  • Conductors 203a, 203b and 203c each assert the outputs received from circuit elements 202a, 202b and 202c respectively onto a series of column drivers (not shown) over a series of terminals 204 (one indicated).
  • each of terminal 204 is connected to CLK 166 of a corresponding column driver 162 of FIG. 4C.
  • each of terminal 204 is connected to a corresponding gate of load switch 152 of column driver circuit 150 160 of FIG. ID.
  • Conductor 203a is approximately half a pixel driver to a full pixel driver shorter than segment 201a
  • conductor 203b is approximately half a pixel driver to a full pixel driver shorter than segment 201b
  • conductor 203c is approximately half a pixel driver to a full pixel driver shorter than segment 201c.
  • the difference in length serves to allow conductors 203a, 203b and 203c to be substantially colinear without being electrically connected.
  • the signal asserted on conductor 203a by circuit element 202a lags the propagation of the trigger signal asserted on the wordline of segment 201a by a uniform factor determined by the propagation delay attributable to circuit element 202a. This same delay is induced by circuit elements 202b and 202c because the circuit elements are identical. Because all column drivers of the array of active pixel drivers (not shown) are triggered by circuits identical to circuit 202a, the propagation delay across all conductors similar to conductor 203a includes a delay factor substantially equal to the propagation delay due to circuit element 202a.
  • FIG. 5B depicts a single segment 210 of array of dummy pixel drivers 211 and associated circuitry after the three segments of FIG. 5 A.
  • Segment 210 comprises array of dummy pixel drivers 211, a tap of a wordline operative to deliver a signal to the input of circuit element 212, conductor 213 operative to receive a signal from the output of circuit element 212, and a plurality of terminals 214 (one indicated).
  • circuit element 212 is a sense circuit.
  • Each of terminals 214 is operative to assert the signal on conductor 213 on a column driver (not shown) such as those depicted in FIGs. 4A and 4C.
  • segment 210 The structure of segment 210 is important.
  • the direction of propagation of the release trigger signal with dummy pixel driver array segment 210 starts at the left size of array of dummy pixel drivers 211 and moves to the right as indicated by the arrow.
  • the trigger signal propagates through wordlines (not shown) of array of dummy pixel drivers 211 at a velocity corresponding to the RC characteristic of the dummy wordline.
  • a tap on wordlines (not shown) within array of dummy pixel drivers asserts the trigger signal onto circuit element 212 which in turns asserts its output onto conductor 213.
  • the tapped signal propagates on conductor 213 at a velocity corresponding to the RC characteristic of conductor 213 and the capacitance of the circuit elements in the column drivers to which it is attached over plurality of terminals 214 (one shown).
  • conductor 213 is parallel to the wordlines within array of dummy pixel drivers and substantially coextensive, the discrepancy between conductor 213 and the wordlines is not extensive.
  • the previous discussion from FIG. 4B above regarding physical line lengths applies to this case. It is important that the length is relatively short and that a series of taps at regular, although not necessarily equal intervals.
  • the tapped signal propagates a relatively short distance on conductor 213 after which a new tap is made that propagates on a new conductor, as previously depicted for conductors 203c, 203b and 203a for FIG. 5A. This ensures that any propagation differences are not cumulative across the entire wordline in array of dummy pixel drivers 210 compared to the signal asserted on plurality of terminals 214 (one shown).
  • FIG. 5C illustrates a simplified drawing 220 of dummy wordlines 223a and 223b operative to deliver trigger signals to a set of column drivers (not shown) over a set of taps 224a - 224h onto dummy wordline 223a.
  • Dummy wordline 223b is always held low to provide a capacitive load comparable to the load on the wordline in the array of active pixel drivers (not shown) wherein only one wordline is high and the surrounding wordlines are low.
  • Trigger timing control unit 221 delivers a signal to row drivers 222a and 222b over conductor 227 to deliver a signal to initiate a high trigger pulse on dummy wordlines 223a and 223b.
  • dummy wordline 223b is hard wired to a low state.
  • Arrow 246 indicates the direction of propagation of a signal released by trigger control unit 221.
  • Row drivers 222a and 222b assert values on dummy wordlines 223a and 223b of the array of dummy pixel drivers responsive to the signal received from trigger control unit 221.
  • Arrow 252 indicates the direction of propagation of the values asserted on dummy wordline 223a,
  • more than two rows of dummy pixel drivers may form a circuit to deliver signals to release data stored on a plurality of column drivers over more than one of the wordlines of the dummy pixel drivers.
  • the taps may occur on a set of parallel wordlines with at least one intervening wordline that is held low. A wordline between the parallel tapped wordlines is held low.
  • the choice for division into a first set and a second set of taps depends on the requirements of the particular display. If the display operates as a unitary system, then the division can be simple. If the division is into four major vertical stripes, wherein each strip is approximately a quarter of the columns, then a different design is 1 needed. If the division is into four quadrants comprising upper left, upper right, lower left and lower right then yet another design is needed. All can be realized in one design at the price of significant complexity.
  • FIG. 5D depicts a detailed block diagram of a segment 290 of a column driver data release circuit after FIG. 5B.
  • Segment 290 comprises dummy wordlines 291a and 291b, tap 298, sense circuit 292, conductor 293 and column drivers 295a - 295h.
  • Dummy wordlines 291a and 291b together act to form a circuit that substantially matches the RC characteristics of the wordlines of the array of active pixel drivers (not shown), thereby matching the propagation delay between the dummy wordlines and the wordlines of the array of active pixel drivers.
  • Dummy word line 291a is pulled high by a signal from a trigger timing control unit such as unit 221 as described in FIG. 5C.
  • Dummy wordline 291b is present to ensure the capacitance loading on word line 291a is properly matched to a word line pulled high on the array of dummy pixel drivers (not shown).
  • the state of dummy wordline 291a at a given point is asserted over terminal 298 onto sense circuit 292.
  • Sense circuit detects the state of dummy word line291a and asserts a corresponding signal on conductor 293 with any needed signal conditioning.
  • sense circuit 292 detects the leading edge of the signal detected on dummy wordline 291a.
  • the signal asserted on conductor 293 is asserted onto each of column drivers 295a - 295n over terminals 294a - 294h.
  • Column drivers 294a - 294h responsive to the state asserted onto its respective terminal 294a - 294h, releases the data stored on its memory onto complementary bitlines 296a- 296h respectively.
  • Bitlines 296a - 296h each represent a pair of complementary bitlines as described in FIG. 4.
  • Arrow 297 indicates the direction of propagation both on dummy wordline 291a and on conductor 293.
  • the propagation delay on dummy wordline 291a is likely different to that on conductor 293 because the RC of the two lines are not identical.
  • the propagation difference is not likely to be significantly different over a relatively short run.
  • the use of multiple taps on a dummy bitline allows the line length to be equivalent to 32 or 64 pixel driver pitch lengths. For an 8.0 pm pixel driver pitch, this is 0.256 mm or 0.512 mm respectively. A serious propagation delay will not accumulate over such short distances even with a slight RC mismatch.
  • FIG. 6A depicts an arrangement whereby four controller devices 329LN, 329LF, 329RF and 329RN control a single backplane 320.
  • the array of pixel drivers of backplane 320 is divided into four vertical sections, each of which has a controller associated with it.
  • LN means left near
  • LF means left far
  • RF means right far
  • RN means right near.
  • the use of near and far means the relative distance to the row address circuitry found in left row decoder and word line driver 322L or the relative distance to the row address circuitry found in right row decoder and word line driver 322R.
  • the vertical sections comprise left near independent section of pixel drivers 321LN, left far independent section of pixel drivers 32 ILF, right far independent section of pixel drivers 321RF, and right near independent section of pixel drivers 321RN, hereafter referred to as sections. It is possible to make the width of the sections 321LN, 32 ILF, 321RF and 321RN substantially equal, but it is not strictly necessary that the vertical sections be substantially or exactly equal. Engineering considerations may dictate that they not all be equal. It is also possible to make the width of the left side sections combining 321LN and 32 ILF not equal to the width of the right side sections combining 321RN and 321RF for engineering reasons. Note that none of the independent sections of pixel drivers 321LN, 32 ILF, 321RF and 321RN overlap with any of the other independent sections of pixel drivers 321LN, 32 ILF, 321RF or 321RN.
  • Image data preprocessor 330 processes the incoming image data to separate it into data for left near section 321LN, left far section 32 ILF, right far section 321RF and right near section 321RN and delivers that data to display controller 329LN, display controller 329LF, display controller 329RF and display controller 329RN over terminals 332LN, 332LF, 332RF, and 332RN respectively.
  • Display controller 329LN, display controller 329LF, display controller 329RF, and display controller 329RN process the data and schedules it to be written to the required row.
  • the data transferred to the column data registers by each display controller is not limited to the boundaries of each independent segment of pixel drivers with which is associated through the row select assembly.
  • a device termed as a single display controller or display controller assembly wherein each display controller controls a section of a display may be comprised of a number of separate elements, such as multiple semiconductor devices, within the spirit of this invention.
  • Row decoder and word line driver 322L comprises a pair of row decoders and word line drivers; one for display controller 329LM and one for display controller 329LF.
  • Display controller 329LN delivers word line address and a row trigger control signal over line 334LN to row decoder and word line driver 322L.
  • display controller 329LN delivers image data for the addressed row onto a set of bit line drivers over conductor 333LN for left near section 321LN (not shown.)
  • the relative timing requires that data for all pixel drivers of the addressed row be in place before the word line driver pulls the word line for that segment of the row high.
  • Propagation delay can be taken into account as long as the propagation rates across the display and up the display to ensure that the complementary bit lines for that column are in their data state at that row before the word line pulls high at that point on the row.
  • Display controller 329LF delivers word line address and a row trigger signal over line 334LF to the second of two row decoder and word line driver circuits in row decoder and word line drive 322L. At the same time display controller 329LF delivers image data for the addressed row onto a set of bit line drivers over conductor 333LF. The same considerations for propagation delay addressed for display controller 329LN apply to display controller 329LF.
  • Row decoder and word line driver 322R comprises a pair of row decoder and word line driver circuits after the circuits of row decoder and word line driver 322L.
  • Display controller 329RF delivers word line address and a row trigger signal over line 334RF to one of a pair of row decoder and word line driver circuits in row decoder and word line driver 322R.
  • Display controller 329RF delivers image data for right far section 321RF to the bit line drivers over conductor 333RF with the previously noted timing conditions.
  • Display controller 329RN delivers a word line address and a row trigger signal over line 334RN to the second of two row decoder and word line driver circuits in row decoder and word line drive 322R.
  • Display controller 329RN delivers image data for right near section 321RN over conductor 333RN with the previously noted timing conditions.
  • display controllers 329LN, 329LF, 329RF and 329RN operate physically separated trigger circuits similar in function and location.
  • row decoder and word line driver 322L When row decoder and word line driver 322L receives a row address from display controller 329LN on a first row decoder and word line driver circuit, the word line of the row corresponding to the address is held to a state that enables the memory circuits operated by that word line to receive data over the bit lines when a trigger signal is received over the same connection.
  • Dashed line 325LN represents a word line for a first row of near left section 321LN and dashed line 326LN represents a word line for a second row of near left section 321LN. Because section 321LN is near to row decoder and word line driver, word line 325LN and word line 326LN do not extend into left far section 32 ILF. For reasons of constant metal density, a dummy metal structure may be positioned in left far section 32 ILF to improve the planarity of the die forming the backplane, a consideration of importance for liquid crystal and other devices.
  • row decoder and word line driver 322L receives a row address from display controller 329LF on a second row decoder and word line driver circuit, the row corresponding to the address is held high when a trigger signal is received over the same connection.
  • Word line 323LN passes under left near section 321LN without making electrical connection and reaches word line 323LF, which is connected to the SRAM memory cells of each pixel driver in left far section 321LF. Identical considerations hold true for word line segments 324LN and 324LF.
  • the RC value of word line 323 LN combined with word line 323LF will be greater than the RC value of 326LN because of the resistance associated with the length of 324LN that passes under left near section 321LN, although, if the sections are not of equal width, that must also be taken into account.
  • the RC characteristic is part of the definition of transport delay in propagating the change in the word line from low to high and back to low.
  • word line 325RN and 326RN which both connect to a row of pixel drivers in right near section 321RN.
  • word line 323RN passes under right near section 321RN in order to connect to word line segment 323RG, which connects to SRAM memory cells in pixel drivers forming a row of right far section 321RF.
  • word line segment 324RN which connects to word line segment 324RF.
  • FIG. 6B illustrates a more detailed block diagram view of parts of the right half of the system of FIG. 2A.
  • the expanded view comprises display controller 329RF, display controller 329RN, and partial backplane 320R.
  • Partial backplane 320R comprises right far section 321RF, right near section 321RN, row decoder and word line driver (right far section 322RF), and row decoder and word line driver (right near section) 322RN.
  • the relative positions of row decoder and word line driver 322RF and of row decoder and word line driver 322RN is selected for ease of explanation. They may in fact be developed in different layers and stacked vertically, depending on the number of metal layers of the backplane semiconductor. Other arrangements are possible.
  • Right far section 321RF comprises bit line driver 335RF, even row pixel driver 328RF and odd row pixel driver 327RF.
  • Right near section 321RN comprises bit line drive circuit 335RN, even row pixel driver 328RN and odd row pixel driver 327RN.
  • Odd row 339 comprises pixel driver 327RF and pixel driver 327RN, and even row 340 comprises pixel driver 328RF and pixel driver 328RN.
  • dashed line 337 represents the boundary between the pixel drivers of odd row 339 and the pixel drivers of even row 340.
  • Dashed line 338 represents the boundary between the pixel drivers of even row 340 and bit line driver 335RF and bit line driver 335RN.
  • Row decoder and word line driver far 322RF is operative to drive two word lines sets in each row.
  • Word line segment 323RN passes under pixel driver 327RN of odd row 339 to connect to word line segment 327RF where it makes contact with the SRAM memory cell of pixel driver 327RF.
  • Row decoder and word line driver near 322RN drives word line segment 325RN which makes contact with the SRAM memory cell of pixel driver 327RN.
  • Capacitors 372b, 372c and 372d represent the capacitance at nodes where word line segment 323RF intersects with circuit elements, such as pass transistors 128 and 129 of 6-transistor data storage element 120 of FIG. IB.
  • circuit elements such as pass transistors 128 and 129 of 6-transistor data storage element 120 of FIG. IB.
  • a general expectation is that the capacitance due to interaction at the nodes would be significantly greater than the parasitic capacitance due to the presence of other circuit elements nearby, although there are exceptions to this that depend on the specifics of the semiconductor manufacturing process and the design rules associated with the chosen process.
  • Modem semiconductor computer aided design (CAD) software tools allow detailed evaluations to be conducted prior to manufacturing and testing the silicon design.
  • the value of resistance R for a segment of a conductor is illustrated in the discussion of FIG. 3 and is repeated here in simplified form. Applicant refers the reader to that text.
  • all conductors in the same layer of a semiconductor process are typically made of the same material, such as aluminum or copper, and will therefore have a similar resistivity o and height H.
  • the length L and width W can be varied but the resistance per unit length will be the same if the resistivity o and width W are the same.
  • One manner in which the resistance of a wire of a given unit length can be reduced is by increasing the width W.
  • a useful goal is a reduction in the time required for a word line select signal to propagate along a word line after the word line described above comprising word line segment 323RN combined with word line segment 323RF.
  • Word line segment 323RN does not interact with the memory circuits of right near section 321RN of pixel drivers whereas word line segment 323RF interacts with the memory circuits of right far section 321RF of pixel drivers.
  • Word line segment 325RN interacts with the memory circuits of right near section 321RN.
  • the word lines selected for this example address one row of many rows, all of which may be addressed in a similar manner.
  • the time required to propagate across right near section 327RN on word line segment 325RN is determined by the RC characteristic of the line.
  • the signal from word line segment 325RN is not propagated into right far section 321RF because the memory circuits on the same row of right far section 321RF are controlled by a signal on word line segment 323RF received through word line segment 323RN, as previously noted.
  • FIG. 7A illustrates a depiction of the left side of a display 400 with 4 vertical sections of pixel drivers.
  • Left display side 400 comprises leftmost vertical section of pixel drivers 401LN and left of center vertical section of pixel drivers 40 ILF.
  • Left display side 400 further comprises display controller 402LN operative to control vertical section of pixel drivers 401 LN, display control 402LF operative to control vertical section of pixel drivers 40 ILF, row of bit line drivers 412LN operative to deliver complementary bit line data to the pixels of vertical section of pixel drivers 401 LN, and row of bit line drivers 412LF operative to deliver bit line data to the pixel drivers of vertical section of pixel drivers 30 ILF. All segments may be resident in a same physical semiconductor assembly.
  • Left display side 400 comprises row decoder and word line driver assembly 404LN operative to drive the word line of the selected row in vertical section of pixel drivers 401LN and row decoder and word line drive assembly 404LF operative to drive the word line of the selected row in vertical section of pixel drivers 40 ILF.
  • Display controller 402LN and display controller 402LF receive row address and row data information fortheir respective vertical sections from an image data preprocessor such as image data preprocessor 330 of FIG. 6A.
  • Each display controller controls its vertical section of pixel drivers without regard to adjacent display controllers.
  • the display controllers are programmed to operate in a similar manner with respect to rows to be written and are synced to the same clock. As a result, the adjacent vertical sections normally operated within a few clock cycles of each other.
  • the image data for a given row within vertical section of pixel drivers 301LN is loaded by display controller 402 LN onto bit line drivers 406LN1 and 406LN2 of row of bit line drivers 412LN for the pixel drivers of vertical section of pixel drivers 401LN over terminal 410LN.
  • the pixel drivers associated with bit line driver 406LN1 comprise pixel drivers INa, INb, INc, INd and INe
  • the pixel drivers associated with bit line driver 306LN2 comprise pixel driver 2Na, 2Nb, 2Nc, 2Nd and 2Ne.
  • Bit line drive 406LN1 loads the bit line data for the selected pixel driver onto complementary bit lines 413LN1, which are marked with a + (plus) sign or a - (minus) sign for BPOS or BNEG respectively.
  • Bit line drive 406LN2 loads the bit line data for the selected pixel driver onto complementary bit lines 413LN2. As before, the complementary bit lines are marked with a + sign or a - sign.
  • the image data for a given row with vertical section of pixel drivers 40 ILF is loaded by display controller 402 LF onto bit line driver 406LF1 and 406LF2 of row of bit line drivers 412LF for the pixel drivers of vertical section of pixel drivers 40 ILF over terminal 410LF.
  • the pixel drivers associated with bit line driver 406LF1 comprise pixel drivers I Fa, IFb, IFc, IFd and IFe
  • the pixel drivers associated with bit line drive 306LF2 comprise 2Fa, 2Fb, 2Fc, 2Fd and 2Fe.
  • Bit line driver 406LF1 loads the bit line data for the selected pixel driver onto complementary bit lines 413LF1, which are marked with a + (plus) sign or a - (minus) sign for BPOS or BNEG respectively.
  • B bit line driver 306LF2 loads the bit line data for the selected pixel driver onto complementary bit lines 313LF2. As before, the complementary bit lines are marked with a + (plus) sign or a - (minus) sign.
  • Left display side 400 comprises rows 405a, 405b, 405c, 405d and 405e, each of which comprises a left near row decoder and wordline driver in row decoder and word line driver assembly 404LN, a left far row decoder and word line drive in wordline driver assembly 4004LF, two pixel drivers in a left near vertical section and two pixel drivers in a left far vertical section.
  • row 405a comprises left near row decoder and word line driver LNa, left far row decoder and word line drive driver LFa, pixel drivers INa and 2Na of left near section 401LN and pixel drivers IFa and 2Fa of left far section 40 ILF.
  • Rows 405b, 405c, 405d and 405e are organized identically with their constituents.
  • Row select and word line high trigger signals delivered over bus 307LN to row decoder and word line driver assembly 304LN cause the following actions to take place.
  • the row decoder logic in one of row decoder and word line driver LNa, LNb, LNc, LNd and LNe will go high in response to the row select signals delivered to row decoder and word line driver assembly 304LN.
  • the output of the word line driver of each row is applied to the input of a two input AND gate (not shown).
  • the word line trigger signal is applied to the other input of each of the AND gates.
  • Word line driver LNa drives word line 411a, which provides the word line signal to the memory circuits of pixel drivers INa and 2Na of vertical section of pixel drivers 401LN. Word line 411a does not extend into vertical section of pixel drivers 40 ILF.
  • word line drive LNb drives word line 411b, which provides the word line signal to the memory circuits of pixel drivers INb and 2Nb of vertical section of pixel drivers 401LN.
  • Word line drivers LNc, LNd, and LN3 drive word lines 411c, 41 Id and 41 le respectively, which provide word line signal to the memory circuits of the pixel drivers of their respective rows.
  • FIG. 7B an SRAM array 420 that is m columns wide by n rows high is illustrated for discussion of propagation delay.
  • FIG. 7B illustrates how the dummy pixel driver arrays shown and described in connection with at least FIGS. 1C and IE can be implemented in connection with a pixel driver array 150.
  • the row select path 261 (of the wordline path 260) includes several parallel dummy pixel driver arrays 261A-2, 261B-2 and 261C-2 (e.g., each including disabled data storage elements). For simplicity, only three dummy pixel driver arrays 261A-2, 261B-2 and 261C-2 are shown.
  • the dummy pixel driver arrays 261A-2, 261B-2 and 261C-2 have lengths the same as the lengths of the bitlines in the pixel driver array 150 so as to replicate the RC characteristics of the bitlines in the pixel driver array 150.
  • Sections (or segments) of row drivers 261A-1, 261B-1, 261C-1 (which correspond with portions of the wordlines A, B, and C (marked with double-sided arrows) of the pixel driver array 150) are tapped, respectively, from the dummy pixel driver arrays 261A-2, 261B-2, and 261C-2.
  • the sections of row drivers 261A-1, 261B-1, 261C-1 and the dummy pixel driver arrays 261A-2, 261B-2, and 261C-2 are disposed outside of the pixel driver array 150.
  • the dummy pixel driver array 261A-2 can be used, along with a section of row drivers 261A-1 (e.g., row driver 140a, 140b shown in FIG. 1C) tapped from the dummy pixel driver arrays 261A-2 (e.g., dummy pixel driver array 198a shown in FIG. 1C) to drive wordlines A (marked with a double-sided arrow).
  • the section of row drivers 261A-1 corresponds with the wordlines A.
  • the section of row drivers 261B-1 is tapped from the dummy pixel driver array 261B-2
  • the section of row drivers 261C-1 is tapped from the dummy pixel driver array 261C-2.
  • the connections are not shown in FIG. 7B, the sections of row drivers 261A-1, 261B-1, 261C-1 are connected to and configured to drive the various wordlines in the pixel driver array 150.
  • a dashed arrow illustrates one potential path for a trigger signal TRA through the dummy pixel driver array 261A-2 and the section of row drivers 261A-1 to drive a wordline associated with pixel of interest 280 in wordlines A.
  • the dummy pixel driver arrays 261A-2, 261B-2, 261C-2 are aligned as close as possible to the pixel driver array 150 so that the RC characteristics can be matched as closely as possible.
  • the dummy pixel driver arrays 261A-2, 261B- 2, 261C-2 are disposed between the pixel driver array 150 and the sections (or segments) of row drivers 261A-1, 261B-1, 261C-1.
  • each section of 8 row drivers can each be tapped to one of 16 dummy pixel driver arrays (which are arranged in parallel as shown in FIG. 7B). Accordingly, each one of the 16 dummy pixel driver arrays can be tapped 8 times with 8 different sections of row drivers (only one tap and one section of row drivers is shown for each dummy pixel driver array in FIG. 7B).
  • This configuration can drive 1024 different wordlines within a pixel driver array.
  • the load data trigger path 271 (of the bitline path 270) includes several parallel dummy pixel driver arrays 271D-2, 271E-2 and 271F-2 (e.g., each including disabled data storage elements). For simplicity, only three dummy pixel driver arrays 271D-2, 271E- 2 and 271F-2 are shown.
  • the dummy pixel driver arrays 271D-2, 271E-2 and 271F-2 have lengths the same as the lengths of the wordlines in the pixel driver array 150 so as to replicate the RC characteristics of the wordlines in the pixel driver array 150.
  • Sections (or segments) of column drivers 271D-1, 271E-1, 271F-1 (which correspond with portions of the wordlines D, E, and F (marked with double-sided arrows) of the pixel driver array 150) are tapped, respectively, from the dummy pixel driver arrays 271D-2, 271E-2, and 271F-2.
  • the sections of column drivers 271D-1, 271E-1, 271F-1 and the dummy pixel driver arrays 271D-2, 271E-2, and 271F-2 are disposed outside of the pixel driver array 150.
  • the dummy pixel driver array 271D-2 can be used, along with a section of column drivers 271D-1 (e.g., column driver 160 shown in FIG. IE) tapped from the dummy pixel driver arrays 271D-2 (e.g., dummy pixel driver array 199a shown in FIG. IE) to drive wordlines D (marked with a double-sided arrow).
  • the section of column drivers 271D-1 corresponds with the wordlines D.
  • the section of column drivers 271E-1 is tapped from the dummy pixel driver array 271E-2
  • the section of column drivers 271F-1 is tapped from the dummy pixel driver array 271F-2.
  • the connections are not shown in FIG. 7B, the sections of column drivers 271D-1, 271E-1, 271F-1 are connected to and configured to drive the various bitlines in the pixel driver array 150.
  • a dashed arrow illustrates one potential path for a trigger signal TRB through the dummy pixel driver array 271D-2 and the section of column drivers 271D-1 to drive a bitline associated with pixel of interest 280 in bitlines D.
  • the dummy pixel driver arrays 271D-2, 271E-2, 271F-2 are aligned as close as possible to the pixel driver array 150 so that the RC characteristics can be matched as closely as possible.
  • the dummy pixel driver arrays 271D-2, 271E- 2, 271F-2 are disposed between the pixel driver array 150 and the sections (or segments) of column drivers 271D-1, 271E-1, 271F-1.
  • the configuration shown in FIG. 7B includes column drivers tapped along only portions of the dummy pixel driver array 271D-1 of the load data trigger path 271, which can reduce RC effects (compared with including column drivers along the entirety of the dummy pixel driver array 271D-1).
  • column drivers 271D-1 are tapped along an upper portion only of the dummy pixel driver array 271D-1 (to drive the bitlines D in the right portion of the pixel driver array 150) and column drivers are not tapped along a left portion of the dummy pixel driver array 271D-1.
  • dummy pixel driver array 271F-2 has column drivers 271F-1 along a left portion of the dummy pixel driver array 271F-1 (to drive the wordlines F in the left portion of the pixel driver array 150).
  • FIG. 7C depicts a case wherein the display is divided into vertical sections 441 and 442. Any of the features described in connection with FIGS.
  • SRAM array 440 comprises an array of pixel drivers, each comprising a memory cell, of m columns by n rows.
  • the display comprises four vertical sections, of which the present example shows a left half. While the example emphasizes one pixel driver at coordinate (x, y) it is understood that pixel drivers at all coordinates must operate as the example does in order for the solution to be a general one.
  • the calculations for this example are an extension of those developed for FIG. 2A.
  • the differences are in the presence on the word line of an extended section underneath a vertical section wherein the word line does not interact with the pixel drivers above it and a similarly long section caused by the display controller for that vertical section needing to reach the left edge of the display.
  • the latter is required since the area comprising the array of pixel drivers must be continuous and cannot have gaps in it to accommodate other types of circuitry.
  • the general approach in this embodiment is to make the time required for the word line high signal to propagate from the word line driver at coordinate (0, y) to the target pixel driver at coordinates (x, y) equal to the time required for the bit line trigger signal to propagate from the circuit near coordinates (0, 0) to the bit line driver at coordinate (x, 0).
  • a second part of the current approach is to make the time required for the word line trigger signal to propagate from the circuit near coordinates (0, 0) to the row decoder and word line select circuit at coordinate (0, y) substantially equal to the time required for the complementary bit line data to propagate up complementary bit lines 443 to the target pixel driver at coordinates (x, y).
  • Signal TRi represents the propagation time for a word line trigger signal.
  • a word line trigger signal requiring time TRi to propagate originates in a circuit positioned near coordinate (0, 0) and is delivered to an AND gate (not shown) in the row decoder and word line circuit for each row.
  • the second input to the AND gate is the signal from the row decoder circuit of the row select circuitry. Since only one row is selected, only one AND gate has its logic satisfied and holds the word line for that row high.
  • wordline driver output is pulled high, the word line signal propagates down word line 444 beginning at coordinate (0, y).
  • the first segment requires time TR4 to propagate across vertical section 441 of array 440.
  • Wordline 444 does not interact with any of the pixel drivers of vertical section 441 but wordline 344 does interact with all of the pixel drivers of vertical section 442, thereby creating a condition where the RC characteristic of the part of word line 444 with vertical section 441 is different to the RC characteristic of the part of word line 444 within vertical section 442.
  • the output of a bit line memory data cell is asserted on a tri-state buffer.
  • a tristate buffer has one data input, which is the pixel driver data from the bit line memory cell, and an enable signal in the form of a bit line trigger signal. Before the bit line trigger signal is asserted on the enable terminal, the output of the tri-state buffer floats. This effectively prevents the new bit line data from encountering a word line that is still high from the previous row write sequence. All bit line drivers in all of the various embodiments of this disclosure may operate in this manner.
  • the portion of word line 444 that serves the pixel drivers of vertical section 442 does interact with all the pixel drivers found along row y associated with coordinates (x, y).
  • the time TR2 required for the word line signal to propagate to coordinate (x, y) from coordinate (m’, y), the point at which it enters vertical section 442, should be the same as time TB 1, the time required for the bit line trigger signal to propagate from a point adjacent to coordinate (m’, 0) to coordinate (x, 0), the location of the bit line driver.
  • Circumstances under which a shortened bit line driver trigger circuit delivers a trigger signal along a trigger circuit parallel to a part, but not all, of the lower base of vertical section 441 is conceived and can be accommodated by compensating delays generated by other circuits.
  • bit line circuits 443 In the case of the propagation of the complementary bit line data on the bit line, a similar approach can be taken with respect to the propagation of the word line trigger signal.
  • the structure of the complementary bit lines 443 is determined by the data requirements for the SRAM memory cell and by the pitch of the pixel drivers. Again it is possible to use an identical structure to deliver the word line release signal to the row decoder and word line drive circuits. This case is simpler because bit line circuits 443 only propagate through active pixel drivers and has the potential to interact with a pixel driver on any row, although it will in a given instance only interact with the one for which the word line signal is high.
  • Example 1 A backplane forming part of a display system operative to drive an array of pixel drivers, the backplane comprising a plurality of rows and a plurality of columns of pixel drivers, wherein each pixel driver comprises a memory circuit operative to hold a bit of image data and each pixel driver operative to apply a drive waveform responsive to the image data state of the memory circuit, and wherein the backplane further comprises at least one row decoder for each row of the array of pixel drivers wherein each row decoder is operative to drive a single word line circuit arrayed on a single row segment to select the memory circuits of the pixel drivers to receive data over bit lines, and wherein the number of row segments for each row equals the number of row decoders for each row, and wherein the set of row decoder circuits comprises at least one row decoder circuit for each row of pixel drivers is arrayed along a side of the array of pixel drivers, and wherein a row decoder control circuit located near the
  • Example 3 The backplane of example 2, wherein the word line driver circuit comprises a memory circuit, an optional level shifter, a bistable logic circuit operative to receive an input from the level shifter and to receive a second input from a trigger signal circuit and operative to assert an output to an associated word line.
  • the word line driver circuit comprises a memory circuit, an optional level shifter, a bistable logic circuit operative to receive an input from the level shifter and to receive a second input from a trigger signal circuit and operative to assert an output to an associated word line.
  • Example 4 The backplane of example 3, wherein the trigger signal circuit over which the column driver control circuit sends trigger signals to the column driver circuits, comprises a series of conductor circuits that each tap the circuit over which the trigger signal is asserted and delivers those signals to the second inputs of a plurality of bistable logic circuits, and wherein the conductor circuits are substantially parallel to the circuit over which the column driver control circuit sends trigger signals with propagation in the same direction.
  • Example 5 The backplane of example 4, wherein each of the conductor circuits that tap the circuit over which the trigger signal is sent comprises a sample circuit positioned between the tap point on the circuit on which the trigger signal is asserted and the series of points on the conductor circuit at which it connects to the second input of the bistable logic circuits, wherein the sample circuit comprises a rising edge detector circuit element and an output circuit operative to hold its output high for a period of time sufficient to enable the column driver circuit to assert its output on a bit line and short enough to ensure the bistable logic circuit does not have a signal present on its second input when the next data is written to the memory circuit of the column driver.
  • Example 6 The backplane of example 1, where the word line driver circuit operative to control the word line for a single row segment comprises a logic circuit operative to release a signal when two valid inputs are received, an optional voltage level shifter and an optional isolating inverter circuit, and wherein the two inputs to the logic circuit are a signal from the row decoder circuit for the row and a release signal received over a conductor from a release timing circuit, thereby enabling the output of the selected row to place the word line controlled by the word line driver circuit to be placed in state so that the memory circuits of the pixel drivers attached to that word line are placed in a state to receive data asserted over bit lines from a group of column drivers associated with those bit lines.
  • Example 7 The backplane of example 6, wherein the logic circuit comprises one of an AND gate, a level sensitive D flip-flop, or an edge sensitive D latch.
  • Example 9 The backplane of example 7, wherein each of the plurality of shorter parallel conductors comprises a sample circuit positioned between the tap point on the main conductor and the inputs to the subset of the logic circuits.
  • Example 10 The backplane of example 6, wherein the conductor over which the release signal is received is a bit line of at least one column of dummy pixel drivers substantially identical to the active pixel drivers and bit lines of the active array, and wherein the release signal to a dummy column driver circuit is controlled and generated by a control circuit that is operative to assert a timing release signal on the memory circuit of a dummy column driver circuit substantially identical to the active column driver circuit and wherein the memory circuit is set to a data state such that the signal propagating on the conductor is configured to satisfy the input requirements of the logic circuit for release of its signal.
  • Example 17 The backplane of example 1, wherein the word line high signal operates at a lower voltage than the upper supply voltage for the array of pixel drivers.
  • Example 1A An apparatus, comprising: a pixel driver of interest within a pixel driver array; a wordline path including a row select path and a wordline, the row select path including a plurality of row drivers and a first plurality of dummy pixel drivers; and a bitline path including a data load trigger path and a bitline, the wordline and the bitline intersecting at the pixel driver of interest within the pixel driver array, the data load trigger path includes a column driver and a second plurality of dummy pixel drivers.
  • Example 3A The apparatus of any of examples 1A or 2A, wherein the first plurality of dummy pixel drivers are simulated by a plurality of disabled data storage elements.
  • Example 7A The apparatus of any of examples 1A to 6A, wherein the row select path is aligned orthogonal to the wordline and aligned parallel to the bitline.
  • Example 8A The apparatus of any of examples 1A to 7A, wherein the wordline follows the row select path within the wordline path, and the bitline follows the data load trigger path within the bitline path.
  • Example 9A The apparatus of any of examples 1A to 8A, wherein the row select path is disposed outside of the pixel driver array and the wordline is disposed within the pixel driver array.
  • Example 10A The apparatus of any of examples 1A to 9A, wherein the data load trigger path is disposed outside of the pixel driver array and the bitline is disposed within the pixel driver array.
  • Example 11A The apparatus of any of examples 1A to 10A, wherein the row select path within the wordline path is aligned parallel to the bitline.
  • Example 12A The apparatus of any of examples 1A to 11A, wherein the data load trigger path within the bitline path is aligned parallel to the wordline.
  • Example 15 A The apparatus of example 14A, wherein the first row select path portion includes a section of row drivers with dummy pixel drivers and a section of dummy pixel drivers without row drivers.
  • the implementations described herein enable the development of a large scale array of pixel drivers based on memory elements with a predictable delay from the initiation of writing of a pixel driver to the writing of the pixel driver for both bitlines and wordlines by using design techniques to reduce time discrepancies between the time of arrival of the rising wordline and the time of arrive of data to be written on the bitlines.
  • the design techniques described herein when implemented, will result in accurate time tracking to all pixel drivers of the array and not to just a small subset in one location.
  • Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof.
  • ASICs application specific integrated circuits
  • These various implementations can include implementation in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.
  • These computer programs include machine instructions for a programmable processor, and can be implemented in a high-level procedural and/or object-oriented programming language, and/or in assembly/machine language.
  • machine-readable medium As used herein, the terms “machine-readable medium”
  • “computer-readable medium” refers to any computer program product, apparatus and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal.
  • machine-readable signal refers to any signal used to provide machine instructions and/or data to a programmable processor.
  • the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer.
  • a display device e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor
  • a keyboard and a pointing device e.g., a mouse or a trackball
  • Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.
  • the computing system can include clients and servers.
  • a client and server are generally remote from each other and typically interact through a communication network.
  • the relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.
  • a non-transitory computer-readable medium stores instructions that, when executed by a processor on a receiving computing device, causes the receiving computing device to perform any of the methods disclosed herein.
  • a computing device can be configured with at least one processor and memory storing instructions that, when executed by the at least one processor, performs any of the methods disclosed herein.

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Abstract

La présente invention concerne une conception de fond de panier pour délivrer des données d'image d'une manière efficace à une cellule de mémoire faisant partie d'un pilote de pixel, qui comprend une conception de ligne de mot et une conception de distribution de signal de libération de registre de données de colonne, mises en correspondance de vitesse, et une conception de distribution de ligne de bit complémentaire qui est mise en correspondance de vitesse avec un circuit de signal de décodeur de rangée opérationnel pour extraire un pilote de ligne de mot vers un état pour permettre aux circuits de mémoire de cette rangée de recevoir des données provenant des pilotes de colonne pour chaque colonne. La mise en correspondance de vitesse est efficace sur une plage de températures de fonctionnement car les conceptions de circuit sont sensiblement identiques.
PCT/US2023/060174 2022-01-05 2023-01-05 Distribution efficace de données d'image pour un réseau de cellules de mémoire de pilote de pixel WO2023133466A1 (fr)

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CN202380020039.7A CN118633120A (zh) 2022-01-05 2023-01-05 针对像素驱动器存储器单元格的阵列的高效图像数据递送

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US17/568,831 US20220130344A1 (en) 2020-06-29 2022-01-05 Efficient image data delivery for an array of pixel memory cells
US18/067,267 US20230197029A1 (en) 2020-06-29 2022-12-16 Larger backplane suitable for high speed applications
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