WO2023130797A1 - 异常检测电路及方法 - Google Patents
异常检测电路及方法 Download PDFInfo
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- WO2023130797A1 WO2023130797A1 PCT/CN2022/125669 CN2022125669W WO2023130797A1 WO 2023130797 A1 WO2023130797 A1 WO 2023130797A1 CN 2022125669 W CN2022125669 W CN 2022125669W WO 2023130797 A1 WO2023130797 A1 WO 2023130797A1
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- the present disclosure relates to the technical field of electronic power, and in particular, to an abnormality detection circuit and method.
- the factory often adopts multiple induction heating equipment assembly line operations to form a product assembly line for the induction heating welding process.
- assembly line several induction heating equipment equipped with different induction coils are selected according to different welding workpieces and different processes. Since one piece of equipment stops working, the entire product assembly line will stop, which requires that the operation stability of several induction heating equipment working together must be very high.
- the power supply frequency detection function of the induction heating equipment is affected, and some peaks caused by interference will be detected as frequency counts, which will cause the detected frequency to be higher than the actual frequency. When the power supply frequency does not actually increase but the detected frequency increases, the system will wrongly perform power supply frequency abnormality protection.
- an abnormality detection circuit including:
- XOR logic module used to input the power supply frequency detection signal and a square wave signal with the same frequency and phase as the power supply frequency detection signal, and perform XOR logic processing to generate a sampling signal; wherein, the duty cycle of the square wave signal Equal to the duty cycle of the supply voltage when the frequency is normal;
- a difference detection module the input end of which is connected to the XOR logic module, for converting the sampling signal into a DC signal and outputting it to a digital signal processor;
- the digital signal processor is configured to judge whether the power supply frequency is abnormal according to the voltage value carried by the direct current signal.
- the XOR logic module includes:
- An exclusive OR gate chip the first pin of which is connected to the first voltage source, one end of the second pin of which is input with the power supply frequency detection signal, and the other end is connected to the first exclusive OR gate element inside the exclusive OR gate chip.
- One input terminal, one end of its third pin is input to the square wave signal, the other end is connected to the second input end of the first XOR gate element, and one end of its fourth pin is connected to the first XOR gate
- the output end of the element, the other end is connected to the difference detection module for outputting the sampling signal, and its fifth pin is grounded;
- the first capacitor the first end of which is connected between the first pin of the exclusive OR gate chip and the first voltage source, and the second end of which is grounded.
- the XOR gate chip also includes:
- the sixth pin one end of which is connected to the ground wire, is used to input a 0V voltage signal, and the other end is connected to the first input end of the second XOR gate element in the XOR gate chip;
- the seventh pin one end of which is input with the power supply frequency detection signal, and the other end is connected with the second input end of the second XOR gate element;
- the eighth pin one end of which is connected to the output end of the second XOR gate element, and the other end is connected to the second pin, for outputting the power supply frequency detection signal processed by the second XOR gate element to the second pin.
- the XOR gate chip also includes:
- the ninth pin one end of which is connected to the ground wire, is used to input a 0V voltage signal, and the other end is connected to the first input end of the third XOR gate element in the XOR gate chip;
- the tenth pin one end of which is input with the square wave signal, and the other end is connected with the second input end of the third XOR gate element;
- the eleventh pin one end of which is connected to the output end of the third XOR gate element, and the other end is connected to the third pin, for outputting the square wave signal processed by the third XOR gate element to the third pin.
- the circuit also includes:
- a voltage conversion module the input terminal of which inputs the power supply frequency detection signal and the square wave signal respectively, and its output terminal is connected to the exclusive OR logic module for converting the power supply frequency detection signal and the voltage value carried by the square wave signal After conversion, output to the XOR gate chip.
- the voltage conversion module includes:
- a voltage conversion chip the first pin of which is connected to a third voltage source, the second pin of which inputs a power supply frequency detection signal, the third pin of which inputs a square wave signal of the same frequency and phase as the power supply frequency detection signal, and the fourth pin of which
- the pin is connected to the first end of the first resistor, the fifth pin is connected to the first end of the second resistor, the second end of the first resistor and the second end of the second resistor are both grounded, and the sixth pin is connected to the first end of the second resistor.
- the pin outputs the converted power supply frequency detection signal, and its seventh pin outputs the converted square wave signal.
- the difference detection module includes:
- Optocoupler chip its first pin is connected to the fourth pin of the XOR gate chip through the third resistor, its second pin is grounded, and between the first pin and the second pin of the optocoupler chip Connect the fourth resistor, the third pin of which is grounded, the fourth pin is connected to the digital signal processor through the fifth resistor, and the fifth pin is connected to the second voltage source;
- a second capacitor whose first end is connected between the fifth pin of the optocoupler chip and the second voltage source, and whose second end is grounded;
- the first end of the third capacitor is connected between the fifth resistor and the digital signal processor, and the second end is grounded.
- the digital signal processor is specifically used for:
- an electrical device including the abnormality detection circuit in any of the above embodiments.
- the electrical consumer is an induction heating device.
- an anomaly detection method which is applied to the above-mentioned anomaly detection circuit, and the method includes:
- the wave signal is generated after logical processing and conversion, and the duty cycle of the square wave signal is equal to the duty cycle of the power supply voltage when the frequency is normal;
- Whether the power supply frequency is abnormal is judged according to the voltage value carried by the direct current signal.
- judging whether the power supply frequency is abnormal according to the voltage value carried by the DC signal includes:
- the method before acquiring the DC signal generated based on the power supply frequency detection signal and a square wave signal of the same frequency and phase as the power supply frequency detection signal, the method further includes:
- a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the anomaly detection method of any of the above-mentioned embodiments is implemented.
- FIG. 1 is a structural block diagram of an abnormality detection circuit according to some embodiments of the present disclosure
- FIG. 2 is a structural diagram of an XOR logic module according to some embodiments of the present disclosure
- FIG. 3 is a structural diagram of a difference detection module according to some embodiments of the present disclosure.
- FIG. 4 is a structural diagram of a voltage conversion module according to some embodiments of the present disclosure.
- FIG. 5 is a flowchart of an anomaly detection method according to some embodiments of the present disclosure.
- Fig. 6 is a flowchart of an anomaly detection method according to some other embodiments of the present disclosure.
- first, second, third, etc. may be used to describe XOR gate elements in the embodiments of the present disclosure, these XOR gate elements should not be limited to these terms. These terms are only used to distinguish different XOR gate elements.
- the first XOR gate element may also be referred to as the second XOR gate element, and similarly, the second XOR gate element may also be referred to as the first XOR gate element. door element.
- the words “if”, “if” as used herein may be interpreted as “at” or “when” or “in response to determining” or “in response to detecting”.
- the phrases “if determined” or “if detected (the stated condition or event)” could be interpreted as “when determined” or “in response to the determination” or “when detected (the stated condition or event) )” or “in response to detection of (a stated condition or event)”.
- Embodiments of the present disclosure provide an abnormality detection circuit and method to solve the problem that equipment falsely reports abnormal power supply frequency due to interference spikes, which in turn leads to unnecessary stoppage of the entire production line.
- FIG. 1 is a structural block diagram of an abnormality detection circuit according to some embodiments of the present disclosure. As shown in FIG. 1 , the abnormality detection circuit includes: an exclusive OR logic module 10 , a difference detection module 20 and a digital signal processor 30 .
- the XOR logic module 10 is used to input the power supply frequency detection signal and the square wave signal with the same frequency and phase as the power supply frequency detection signal, and performs XOR logic processing to generate a sampling signal; wherein, the duty cycle of the above square wave signal is equal to the normal frequency When the duty cycle of the power supply voltage is normal, for example, if the duty cycle of the power supply voltage is 50% when the frequency is normal, then the duty cycle of the above square wave signal is also 50%.
- the input end of the difference detection module 20 is connected to the XOR logic module, and the difference detection module 20 is used to convert the sampling signal into a DC signal and output it to the digital signal processor.
- the digital signal processor 30 is used for judging whether the power supply frequency is abnormal according to the voltage value carried by the DC signal.
- the power supply frequency detection signal and the square wave signal of the same frequency and phase as the power supply frequency detection signal are subjected to exclusive OR logic processing through the exclusive OR logic module 10 to generate a sampling signal, and then the sampling signal is generated through the difference detection module 20.
- the signal is converted into a DC signal, output to a digital signal processor, and finally the digital signal processor 30 judges whether the power supply frequency is abnormal according to the voltage value carried by the DC signal, which can avoid false alarms of abnormal power supply frequency caused by interference peaks, and improve protection against abnormal power supply frequency accuracy.
- FIG. 2 is a structural diagram of an XOR logic module according to some embodiments of the present disclosure. As shown in FIG. 2 , the XOR logic module includes: an XOR gate chip U1 and a first capacitor C1.
- the first pin Vcc of the exclusive OR gate chip U1 is connected to the first voltage source, one end of the second pin 1A inputs the power supply frequency detection signal ZERO, and the other end is connected to the first exclusive OR gate element inside the exclusive OR gate chip U1 (Fig. not shown in the figure), one end of its third pin 1B inputs the square wave signal PWM, and the other end is connected to the second input end of the first XOR gate element (not shown in the figure), and its fourth One end of the pin 1Y is connected to the output end of the first XOR gate element, and the other end is connected to the difference detection module 20 for outputting the sampling signal ADF, and its fifth pin GND is grounded; the first end of the first capacitor C1 is connected to the XOR gate element. Between the first pin Vcc of the OR chip U1 and the first voltage source, the second end is grounded.
- the power supply frequency detection signal ZERO and the square wave signal PWM are always synchronized, and the sampling signal ADF is a signal with a voltage value of zero.
- the power supply frequency detection signal ZERO will change, the power supply frequency detection signal ZERO and the square wave signal PWM are no longer synchronized, and the sampling signal ADF is a square wave signal with a certain duty cycle.
- the XOR gate chip U1 also includes: a sixth pin 2B, a seventh pin 2A, an eighth pin Pin 2Y.
- One end of the sixth pin 2B is connected to the ground wire for inputting a 0V voltage signal, and the other end is connected to the first input end of the second exclusive OR gate element (not shown in the figure) in the exclusive OR gate chip U1; the seventh pin One end of the pin 2A inputs the power supply frequency detection signal ZERO, and the other end is connected to the second input end of the second exclusive OR gate element; one end of the eighth pin 2Y is connected to the output end of the second exclusive OR gate element, and the other end is connected to the second lead
- the pin 1A is used to output the power supply frequency detection signal processed by the second XOR gate element to the second pin 1A.
- the above-mentioned square wave signal may not be a standard square wave waveform.
- the above-mentioned XOR gate chip U1 also includes: the ninth pin 3A, the tenth pin 3B and the first Eleven pin 3Y.
- One end of the ninth pin 3A is connected to the ground wire for inputting a 0V voltage signal, and the other end is connected to the first input end of the third XOR gate element in the exclusive OR gate chip U1; one end of the tenth pin 3B inputs a square wave Signal PWM, the other end is connected to the second input end of the third XOR gate element (not shown in the figure); one end of the eleventh pin 3Y is connected to the output end of the third XOR gate element, and the other end is connected to the third pin 1B, for outputting the square wave signal processed by the third XOR gate element to the third pin 1B.
- Fig. 3 is a structural diagram of a difference detection module according to some embodiments of the present disclosure.
- the difference detection module includes: an optocoupler chip U2, a second capacitor C2, and a third capacitor C3.
- the first pin 1 of the optocoupler chip U2 is connected to the fourth pin 1Y of the exclusive OR gate chip U1 through the third resistor R3 to input the sampling signal ADF, the second pin 2 of which is grounded, and the first pin 1 of the optocoupler chip U2
- the fourth resistor R4 is connected between the pin 1 and the second pin 2, the third pin 3 of which is grounded, the fourth pin 4 is connected to the digital signal processor 30 through the fifth resistor R5 to output a DC signal AD_F, and the fifth pin Pin 5 is connected to the second voltage source;
- the first end of the second capacitor C2 is connected between the fifth pin 5 of the optocoupler chip U2 and the second voltage source, and its second end is grounded;
- the first end of the third capacitor C3 It is connected between the fifth resistor R
- the working voltage of the exclusive OR gate chip U1 is different from the voltage value carried by the square wave signal PWM and the power supply frequency detection signal ZERO signal, for example, the working voltage of the exclusive OR gate chip U1 is 5V, and the square wave signal PWM and the power supply frequency detection signal ZERO The voltage value carried by the signal is 3.3V.
- the above circuit also includes: a voltage conversion module 40, and the input terminals of the voltage conversion module 40 input the power supply frequency detection signal ZERO and the square wave signal respectively.
- PWM the output end of which is connected to the exclusive OR logic module, which is used to convert the voltage value carried by the power supply frequency detection signal ZERO and the square wave signal PWM, and then output to the exclusive OR gate chip U1.
- FIG. 4 is a structural diagram of a voltage conversion module according to an embodiment of the present disclosure.
- the voltage conversion module 40 includes: a voltage conversion chip U3, the first pin OE of the voltage conversion chip U3 is connected to a third voltage source, and The second pin A0 inputs the power supply frequency detection signal, its third pin A1 inputs a square wave signal PWM with the same frequency and phase as the power supply frequency detection signal ZERO, and its fourth pin A2 is connected to the first end of the first resistor R1, which The fifth pin A3 is connected to the first end of the second resistor R2, the second end of the first resistor R1 and the second end of the second resistor R2 are both grounded, and the sixth pin Y0 outputs the converted power supply frequency detection signal ZERO , its seventh pin Y1 outputs the converted square wave signal PWM.
- the digital signal processor 30 is specifically used to: determine whether the voltage value carried by the DC signal is zero; when the voltage value carried by the DC signal is not zero, determine that the power supply frequency is abnormal; When the carried voltage value is zero, it is determined that the power supply frequency is normal.
- embodiments of the present disclosure provide a hardware circuit for judging the authenticity of power supply frequency fluctuations.
- ZERO is the power supply frequency detection signal
- PWM is a square wave signal with the same frequency, the same phase, and the same duty cycle as that of the power supply voltage when the frequency is normal.
- the voltage value carried by the above two signals before conversion is 3.3V.
- the output power supply frequency detection signal The voltage value carried by ZERO and square wave signal PWM is 5V. This process converts the voltage value of the signal to 5V and can improve the signal driving ability.
- the Output 0V voltage if the duty cycle of the two signals is different, then output a square wave signal with a certain duty cycle.
- This square wave signal is input to the pre-stage of the optocoupler chip U3 (such as IC_ACPL_P480 chip) of the difference detection circuit, and after optocoupler isolation, it is input to the filter circuit of the difference detection circuit for DC conversion, and the square wave signal with a certain duty cycle Convert to DC signal AD_F.
- the DC voltage signal AD_F is input into the analog-to-digital conversion chip to be converted into a digital quantity, and then input to the digital signal processor 30 .
- the control program adds a level of fluctuation authenticity judgment. If the voltage value carried by the DC signal AD_F detected by the digital signal processor 30 is not 0, it means that the system actually has an abnormal power supply frequency at this time. At this time, the alarm frequency is abnormal, and the induction heating equipment is controlled to shut down. If the detected voltage value of AD_F is 0, it means that the system does not actually have abnormal power supply frequency at this time, and the induction heating equipment should keep running at this time.
- Some embodiments of the present disclosure further provide an electrical device, including the abnormality detection circuit of any of the above embodiments.
- the electrical consumer is an induction heating device.
- FIG. 5 is a flowchart of a power supply frequency abnormality detection method according to some embodiments of the present disclosure, as shown in FIG. 5 As shown, the method includes: steps S101-S102.
- step S101 a DC signal generated based on the power supply frequency detection signal and a square wave signal of the same frequency and phase as the power supply frequency detection signal is acquired.
- the above-mentioned DC signal is generated by the power supply frequency detection signal and the square wave signal with the same frequency and phase as the power supply frequency detection signal after logic processing and conversion.
- the duty cycle of the square wave signal is equal to the power supply voltage when the frequency is normal duty cycle.
- step S102 it is determined whether the power supply frequency is abnormal according to the voltage value carried by the above-mentioned direct current signal.
- the abnormal power supply frequency detection method of this embodiment obtains a DC signal generated based on the power supply frequency detection signal and a square wave signal of the same frequency and phase as the power supply frequency detection signal, and then judges whether the power supply frequency is abnormal by the voltage value carried by the above DC signal , which can avoid false alarms of abnormal power supply frequency caused by interference peaks, and improve the accuracy of abnormal power supply frequency protection.
- judging whether the power supply frequency is abnormal according to the voltage value carried by the direct current signal includes: judging whether the voltage value carried by the direct current signal is zero; if not, determining that the power supply frequency is abnormal; if yes, then It is determined that the power supply frequency is normal.
- the above scheme is that when the frequency of the power supply frequency detection signal is abnormal, it is necessary to further judge whether the frequency abnormality of the power supply frequency detection signal is caused by an interference spike or an abnormal power supply frequency. If the frequency of the power supply frequency detection signal is normal, the power supply frequency must be Normally, there is no need to perform subsequent steps.
- the above method further includes: judging the frequency of the power supply frequency detection signal Whether it is abnormal; if not, directly determine that the power supply frequency is normal; if yes, trigger acquisition of a DC signal generated based on the power supply frequency detection signal and a square wave signal of the same frequency and phase as the power supply frequency detection signal.
- Fig. 6 is a flow chart of an abnormality detection method according to some other embodiments of the present disclosure, wherein the electrical device mentioned above is an induction heating device, as shown in Fig. 6 , the method includes: steps S1-S4.
- step S1 it is judged whether the frequency of the power supply frequency detection signal is abnormal; if not, step S2 is performed, and if yes, step S3 is performed.
- step S2 it is determined that the power supply frequency is normal, and the induction heating equipment is controlled to operate normally.
- step S3 it is judged whether the voltage value of the DC signal generated based on the power supply frequency detection signal and the square wave signal with the same frequency and phase as the power supply frequency detection signal is 0; if yes, then perform step S2, if not, then perform step S4 .
- step S4 it is determined that the power supply frequency is abnormal, and the induction heating equipment is controlled to stop running.
- the generated sampling signal ADF is a square wave signal with a certain duty cycle. The voltage value of the signal is not 0; if the frequency of the power supply frequency detection signal is abnormal due to interference peaks, then the duty cycle of the power supply frequency detection signal will not change, and the power supply frequency detection signal and the power supply frequency detection signal The square wave signal with the same frequency and phase is completely synchronized.
- the generated sampling signal ADF is a 0V voltage signal. Therefore, the final signal generated based on the power supply frequency detection signal and the square wave signal with the same frequency and phase The voltage value of the DC signal is 0.
- a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the above-mentioned method for detecting an abnormal power supply frequency of an electric device is implemented.
- circuit embodiments are only illustrative, and the modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
- each implementation can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware.
- the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic discs, optical discs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.
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Abstract
一种异常检测电路及方法。其中，该电路包括：异或逻辑模块(10)，用于输入供电频率检测信号和与供电频率检测信号同频同相的方波信号，并进行异或逻辑处理，生成采样信号；其中，方波信号的占空比等于频率正常时供电电压的占空比；差异检测模块(20)，其输入端连接异或逻辑模块(10)，用于将采样信号转换为直流信号，输出至数字信号处理器(30)；数字信号处理器(30)，用于根据直流信号携带的电压值判断供电频率是否异常。
Description
相关申请的交叉引用
本申请是以CN申请号为202210022734.4，申请日为2022年1月10日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
本公开涉及电子电力技术领域，具体而言，涉及一种异常检测电路及方法。
工厂内经常采取多台感应加热设备流水线式作业，形成一条感应加热焊接工序的产品流水线，在流水线中根据焊接工件不同、工艺不同选择数台搭载不同感应线圈的感应加热设备。由于一台设备停止工作后，整条产品流水线会因此停线，这就需要协同工作的数台感应加热设备的运行稳定性一定要很高。工厂内各工业级用电设备众多，功率大，负荷量高，导致厂内电网中谐波干扰多，电能质量差，并且感应加热设备工作时周围电磁场环境复杂。此时感应加热设备的供电频率检测功能受到影响，会把一些干扰造成的尖峰检测成频率计数，这将导致检测出的频率比实际的频率要高。在供电频率没有真实变高而检测出的频率变高时，系统会错误的进行供电频率异常保护。
发明内容
根据本公开的一些实施例，提供的一种异常检测电路，包括：
异或逻辑模块，用于输入供电频率检测信号和与所述供电频率检测信号同频同相的方波信号，并进行异或逻辑处理，生成采样信号；其中，所述方波信号的占空比等于频率正常时供电电压的占空比；
差异检测模块，其输入端连接所述异或逻辑模块，用于将所述采样信号转换为直流信号，输出至数字信号处理器；
所述数字信号处理器，用于根据所述直流信号携带的电压值判断供电频率是否异常。
在一些实施例中，所述异或逻辑模块包括：
异或门芯片，其第一引脚连接第一电压源，其第二引脚的一端输入所述供电频率 检测信号，另一端连接所述异或门芯片内部的第一异或门元件的第一输入端，其第三引脚的一端输入所述方波信号，另一端连接所述第一异或门元件的第二输入端，其第四引脚的一端连接所述第一异或门元件的输出端，另一端连接所述差异检测模块，用于输出所述采样信号，其第五引脚接地；
第一电容，其第一端连接至所述异或门芯片的第一引脚和所述第一电压源之间，第二端接地。
在一些实施例中，所述异或门芯片还包括：
第六引脚，其一端连接地线，用于输入0V电压信号，另一端连接所述异或门芯片内的第二异或门元件的第一输入端；
第七引脚，其一端输入所述供电频率检测信号，另一端连接所述第二异或门元件的第二输入端；
第八引脚，其一端连接所述第二异或门元件的输出端，另一端连接所述第二引脚，用于将所述第二异或门元件处理后的供电频率检测信号输出至所述第二引脚。
在一些实施例中，所述异或门芯片还包括：
第九引脚，其一端连接地线，用于输入0V电压信号，另一端连接所述异或门芯片内的第三异或门元件的第一输入端；
第十引脚，其一端输入所述方波信号，另一端连接所述第三异或门元件的第二输入端；
第十一引脚，其一端连接所述第三异或门元件的输出端，另一端连接所述第三引脚，用于将所述第三异或门元件处理后的方波信号输出至所述第三引脚。
在一些实施例中，所述电路还包括：
电压转换模块，其输入端分别输入供电频率检测信号和所述方波信号，其输出端连接所述异或逻辑模块，用于将所述供电频率检测信号和所述方波信号携带的电压值进行转换后，输出至所述异或门芯片。
在一些实施例中，所述电压转换模块包括：
电压转换芯片，其第一引脚连接第三电压源，其第二引脚输入供电频率检测信号，其第三引脚输入与所述供电频率检测信号同频同相的方波信号，其第四引脚连接第一电阻的第一端，其第五引脚连接第二电阻的第一端，所述第一电阻的第二端和所述第二电阻的第二端均接地，其第六引脚输出转换后的供电频率检测信号，其第七引脚输出转换后的方波信号。
在一些实施例中，所述差异检测模块包括：
光耦芯片，其第一引脚通过第三电阻连接所述异或门芯片的第四引脚，其第二引脚接地，所述光耦芯片的第一引脚和第二引脚之间连接第四电阻，其第三引脚接地，第四引脚通过第五电阻连接所述数字信号处理器，第五引脚连接第二电压源；
第二电容，其第一端连接至所述光耦芯片的第五引脚和所述第二电压源之间，其第二端接地；
第三电容，其第一端连接至所述第五电阻和所述数字信号处理器之间，其第二端接地。
在一些实施例中，所述数字信号处理器具体用于：
判断所述直流信号携带的电压值是否为零；
在所述直流信号携带的电压值不为零时，判定所述供电频率异常；
在所述直流信号携带的电压值为零时，判定所述供电频率正常。
根据本公开的另一些实施例，提供的一种用电设备，包括上述任意实施例中的异常检测电路。
在一些实施例中，所述用电设备为感应加热设备。
根据本公开的又一些实施例，提供的一种异常检测方法，应用于上述异常检测电路，所述方法包括：
获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号；其中，所述直流信号为供电频率检测信号和与所述供电频率检测信号同频同相的方波信号经过以后逻辑处理，再经过转换后生成的，所述方波信号的占空比等于频率正常时供电电压的占空比；
根据所述直流信号携带的电压值判断供电频率是否异常。
在一些实施例中，根据所述直流信号携带的电压值判断供电频率是否异常，包括：
判断所述直流信号携带的电压值是否为零；
在所述直流信号携带的电压值不为零时，则判定所述供电频率异常；
在所述直流信号携带的电压值为零时，则判定所述供电频率正常。
在一些实施例中，获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号之前，所述方法还包括：
判断所述供电频率检测信号的频率是否异常；
如果否，则直接确定所述供电频率正常；
如果是，则触发获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号。
根据本公开的再一些实施例，提供的一种计算机可读存储介质，其上存储有计算机程序，所述程序被处理器执行时实现上述任意实施例的异常检测方法。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
图1为根据本公开的一些实施例的异常检测电路的结构框图；
图2为根据本公开的一些实施例的异或逻辑模块的结构图；
图3为根据本公开的一些实施例的差异检测模块的结构图；
图4为根据本公开的一些实施例的电压转换模块的结构图；
图5为根据本公开的一些实施例的异常检测方法的流程图；
图6为根据本公开另的一些实施例的异常检测方法的流程图。
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作在一些实施例中详细描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
在本公开实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本公开。在本公开实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义，“多种”一般包含至少两种。
应当理解，本文中使用的术语“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应当理解，尽管在本公开实施例中可能采用术语第一、第二、第三等来描述异或门元件，但这些异或门元件不应限于这些术语。这些术语仅用来将不同异或门元件区分开。例如，在不脱离本公开实施例范围的情况下，第一异或门元件也可以被称为第二异或门元件，类似地，第二异或门元件也可以被称为第一异或门元件。
取决于语境，如在此所使用的词语“如果”、“若”可以被解释成为“在……时”或“当……时”或“响应于确定”或“响应于检测”。类似地，取决于语境，短语“如果确定”或“如果检测(陈述的条件或事件)”可以被解释成为“当确定时”或“响应于确定”或“当检测(陈述的条件或事件)时”或“响应于检测(陈述的条件或事件)”。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的商品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种商品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的商品或者装置中还存在另外的相同要素。
发明人发现：在供电频率没有真实变高而检测出的频率变高时，系统会错误的进行供电频率异常保护，该现象频繁出现时，会导致感应加热设备的运行稳定性下降，特别是需要协同工作的数台感应加热设备中有一台误保护关机，整条产线就不能工作。随之带来了停产停线，工期延误，工件损坏等经济损失的问题。
本公开实施例中提供一种异常检测电路及方法，以解决干扰尖峰导致设备误报供电频率异常，进而导致整条产线不必要的停线的问题。
下面结合附图详细说明本公开的一些实施例。
本公开的一些实施例提供一种异常检测电路。图1为根据本公开一些实施例的异常检测电路的结构框图，如图1所示，异常检测电路包括：异或逻辑模块10、差异检测模块20和数字信号处理器30。
异或逻辑模块10用于输入供电频率检测信号和与供电频率检测信号同频同相的方波信号，并进行异或逻辑处理，生成采样信号；其中，上述方波信号的占空比等于频率正常时供电电压的占空比，例如，如果频率正常时供电电压的占空比为50％，则上述方波信号的占空比也为50％。
差异检测模块20的输入端连接异或逻辑模块，差异检测模块20用于将采样信号转换为直流信号，输出至数字信号处理器。
数字信号处理器30用于根据直流信号携带的电压值判断供电频率是否异常。
本实施例的异常检测电路，通过异或逻辑模块10将供电频率检测信号和与供电频率检测信号同频同相的方波信号进行异或逻辑处理，生成采样信号，然后通过差异检测模块20将采样信号转换为直流信号，输出至数字信号处理器，最终通过数字信号处理器30根据直流信号携带的电压值判断供电频率是否异常，能够避免干扰尖峰导致的供电频率异常误报，提高供电频率异常保护的准确性。
图2为根据本公开的一些实施例的异或逻辑模块的结构图，如图2所示，所述异或逻辑模块包括：异或门芯片U1、第一电容C1。
异或门芯片U1的第一引脚Vcc连接第一电压源，其第二引脚1A的一端输入供电频率检测信号ZERO，另一端连接异或门芯片U1内部的第一异或门元件(图中未示出)的第一输入端，其第三引脚1B的一端输入方波信号PWM，另一端连接第一异或门元件(图中未示出)的第二输入端，其第四引脚1Y的一端连接第一异或门元件的输出端，另一端连接差异检测模块20，用于输出采样信号ADF，其第五引脚GND接地；第一电容C1的第一端连接至异或门芯片U1的第一引脚Vcc和第一电压源之间，第二端接地。
当供电频率发生异常，且异常是由干扰尖峰导致时，供电频率检测信号ZERO与方波信号PWM始终同步，采样信号ADF为携带的电压值为零的信号，当供电频率异常，且异常是供电自身频率波动导致时，供电频率检测信号ZERO的占空比会发生变化，供电频率检测信号ZERO与方波信号PWM不再同步，采样信号ADF为具有一定占空比的方波信号。
由于供电频率检测信号可能并非是标准的方波波形，为了获得标准的方波波形，在一些实施例中，异或门芯片U1还包括：第六引脚2B、第七引脚2A、第八引脚2Y。第六引脚2B的一端连接地线，用于输入0V电压信号，另一端连接异或门芯片U1内的第二异或门元件(图中未示出)的第一输入端；第七引脚2A的一端输入供电频率检测信号ZERO，另一端连接第二异或门元件的第二输入端；第八引脚2Y的一端连接第二异或门元件的输出端，另一端连接第二引脚1A，用于将第二异或门元件处理后的供电频率检测信号输出至第二引脚1A。
上述方波信号可能并非是标准的方波波形，为了获得标准的方波波形，在另一些实施例中，上述异或门芯片U1还包括：第九引脚3A、第十引脚3B和第十一引脚3Y。第九引脚3A的一端连接地线，用于输入0V电压信号，另一端连接异或门芯片U1内 的第三异或门元件的第一输入端；第十引脚3B的一端输入方波信号PWM，另一端连接第三异或门元件(图中未示出)的第二输入端；第十一引脚3Y一端连接第三异或门元件的输出端，另一端连接第三引脚1B，用于将第三异或门元件处理后的方波信号输出至第三引脚1B。
图3为根据本公开一些实施例的差异检测模块的结构图，为了实现差异检测，差异检测模块包括：光耦芯片U2、第二电容C2、第三电容C3。光耦芯片U2的第一引脚1通过第三电阻R3连接异或门芯片U1的第四引脚1Y，以输入采样信号ADF，其第二引脚2接地，光耦芯片U2的第一引脚1和第二引2脚之间连接第四电阻R4，其第三引脚3接地，第四引脚4通过第五电阻R5连接数字信号处理器30，以输出直流信号AD_F，第五引脚5连接第二电压源；第二电容C2的第一端连接至光耦芯片U2的第五引脚5和第二电压源之间，其第二端接地；第三电容C3的第一端连接至第五电阻R5和数字信号处理器30之间，其第二端接地。第五电阻R5和第三电容C3构成滤波电路用于将进入光耦芯片U2的检测信号进行转换，生成直流信号AD_F。
由于异或门芯片U1的工作电压与方波信号PWM和供电频率检测信号ZERO信号携带的电压值不同，例如，异或门芯片U1的工作电压为5V，方波信号PWM和供电频率检测信号ZERO信号携带的电压值为3.3V，为了使异或门芯片U1输入的电压为5V，上述电路还包括：电压转换模块40，电压转换模块40的输入端分别输入供电频率检测信号ZERO和方波信号PWM，其输出端连接异或逻辑模块，用于将供电频率检测信号ZERO和方波信号PWM携带的电压值进行转换后，输出至异或门芯片U1。
图4为根据本公开实施例的电压转换模块的结构图，如图4所示，电压转换模块40包括：电压转换芯片U3，压转换芯片U3的第一引脚OE连接第三电压源，其第二引脚A0输入供电频率检测信号，其第三引脚A1输入与供电频率检测信号ZERO同频同相的方波信号PWM，其第四引脚A2连接第一电阻R1的第一端，其第五引脚A3连接第二电阻R2的第一端，第一电阻R1的第二端和第二电阻R2的第二端均接地，其第六引脚Y0输出转换后的供电频率检测信号ZERO，其第七引脚Y1输出转换后的方波信号PWM。
为了准确判断供电频率是否发生了异常，数字信号处理器30具体用于：判断直流信号携带的电压值是否为零；在直流信号携带的电压值不为零时，判定供电频率异常；在直流信号携带的电压值为零时，判定供电频率正常。
综上所述，如图1～图4所示，本公开的实施例提供了用于供电频率波动真实性判断的硬件电路。ZERO为供电频率检测信号，PWM为数字信号处理器DSP根据目前检测出的供电频率检测信号，发出的频率相同、相位相同、占空比与频率正常时供电电压的占空比相同的方波信号。将这两个信号输入电压转换模块的电压转换芯片(例如IC_74HCT241芯片)进行电压转换，例如，转换前上述两个信号携带的电压值均为3.3V，经过电压转换后，输出的供电频率检测信号ZERO和方波信号PWM携带的电压值为5V，此过程将信号的电压值转换为5V并可提升信号驱动能力。将供电频率检测信号ZERO和方波信号PWM信号分别输入异或门芯片(例如IC_HC86芯片)的第一异或门元件和第二异或门元件，先分别与地线输出的0V电压信号做异或逻辑处理，此过程可使信号的上升沿、下降沿变陡，使其变为标准的方波波形。再将处理后的供电频率检测信号ZERO和方波信号PWM信号输入异或门芯片的第三异或门元件做异或逻辑处理，由于两信号频率、相位相同，如果占空比也相同，将输出0V电压，若两信号占空比不同则输出具有一定占空比的方波信号。将此方波信号输入到差异检测电路的光耦芯片U3(例如IC_ACPL_P480芯片)前级，经过光耦隔离后输入差异检测电路的滤波电路进行直流转换，将该具有一定占空比的方波信号转换为直流信号AD_F。将该直流电压信号AD_F输入模数转换芯片转换为数字量，再输入到数字信号处理器30。在检测到频率异常的时候，控制程序增加一级波动真实性判断，若数字信号处理器30检测到的直流信号AD_F携带的电压值不为0时，表示系统此时真实的出现供电频率异常，此时报频率异常，控制感应加热设备关机。若检测的AD_F的电压值为0，则表示系统此时并没有真实的出现供电频率异常，此时感应加热设备应保持开机运行状态。通过增加实现供电频率波动真实性判断功能的电路及增加的控制判断方法来判断加热电源设备的供电频率是否真实出现了波动，还是因为干扰问题导致感应加热设备的供电频率检测功能错误的把频率值检测偏高，导致了系统进行了供电频率异常保护。以此解决因干扰导致感应加热设备频繁误保护进而关机的问题，提高感应加热设备运行的稳定性。
根据本公开的一些实施例还提供一种用电设备，包括上述任意实施例的异常检测电路。在一些实施例中，所述用电设备为感应加热设备。
根据本公开的一些实施例还提供一种异常检测方法，应用于上述实施例中的异常检测电路，图5为根据本公开的一些实施例的供电频率异常检测方法的流程图，如图5所示，该方法包括：步骤S101～S102。
在步骤S101中，获取基于供电频率检测信号和与供电频率检测信号同频同相的方波信号生成的直流信号。
例如，上述直流信号为供电频率检测信号和与供电频率检测信号同频同相的方波信号经过以后逻辑处理，再经过转换后生成的，所述方波信号的占空比等于频率正常时供电电压的占空比。
在步骤S102中，根据上述直流信号携带的电压值判断供电频率是否异常。
本实施例的供电频率异常检测方法，通过获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号，然后上述直流信号携带的电压值判断供电频率是否异常，能够避免干扰尖峰导致的供电频率异常误报，提高供电频率异常保护的准确性。
在一些实施例中，根据所述直流信号携带的电压值判断供电频率是否异常，具体包括：判断直流信号携带的电压值是否为零；如果否，则判定所述供电频率异常；如果是，则判定所述供电频率正常。
上述方案为供电频率检测信号的频率异常时，需要进一步判断供电频率检测信号的频率异常是干扰尖峰导致的，还是供电频率异常导致的，而如果供电频率检测信号的频率正常，则供电频率一定是正常的，不需要执行后续步骤，因此，获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号之前，上述方法还包括：判断供电频率检测信号的频率是否异常；如果否，则直接确定供电频率正常；如果是，则触发获取基于供电频率检测信号和与供电频率检测信号同频同相的方波信号生成的直流信号。
图6为根据本公开另一些实施例的异常检测方法的流程图，其中，上述用电设备为感应加热设备，如图6所示，该方法包括：步骤S1～S4。
在步骤S1中，判断供电频率检测信号的频率是否异常；如果否，则执行步骤S2，如果是，则执行步骤S3。
在步骤S2中，确定供电频率正常，控制感应加热设备正常运行。
在步骤S3中，判断基于供电频率检测信号和与供电频率检测信号同频同相的方波信号生成的直流信号的电压值是否为0；如果是，则执行步骤S2，如果否，则执行步骤S4。
在步骤S4中，确定供电频率异常，控制感应加热设备停止运行。
如果供电频率检测信号的频率异常，是由于供电频率异常导致的，那么，供电频 率检测信号的占空比也将发生变化，供电频率检测信号和与供电频率检测信号同频同相的方波信号不再同步，经过异或门芯片后，生成的采样信号ADF为具有一定占空比的方波信号，因此，最终基于供电频率检测信号和与供电频率检测信号同频同相的方波信号生成的直流信号的电压值不为0；如果供电频率检测信号的频率异常，是由于干扰尖峰导致的，那么，供电频率检测信号的占空比将不会发生变化，供电频率检测信号和与供电频率检测信号同频同相的方波信号完全同步，经过异或门芯片后，生成的采样信号ADF为0V电压信号，因此，最终基于供电频率检测信号和与供电频率检测信号同频同相的方波信号生成的直流信号的电压值为0。
根据本公开的一些实施例，还提供一种计算机可读存储介质，其上存储有计算机程序，所述程序被处理器执行时实现上述用电设备供电频率异常检测方法。
以上所描述的电路实施例仅仅是示意性的，其中所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。
Claims (15)
- 一种异常检测电路，包括：异或逻辑模块，用于输入供电频率检测信号和与所述供电频率检测信号同频同相的方波信号，并进行异或逻辑处理，生成采样信号，其中，所述方波信号的占空比等于频率正常时供电电压的占空比；差异检测模块，其输入端连接所述异或逻辑模块，用于将所述采样信号转换为直流信号，输出至数字信号处理器；所述数字信号处理器，用于根据所述直流信号携带的电压值判断供电频率是否异常。
- 根据权利要求1所述的电路，其中，所述异或逻辑模块包括：异或门芯片，其第一引脚连接第一电压源，其第二引脚的一端输入所述供电频率检测信号，另一端连接所述异或门芯片内部的第一异或门元件的第一输入端，其第三引脚的一端输入所述方波信号，另一端连接所述第一异或门元件的第二输入端，其第四引脚的一端连接所述第一异或门元件的输出端，另一端连接所述差异检测模块，用于输出所述采样信号，其第五引脚接地；第一电容，其第一端连接至所述异或门芯片的第一引脚和所述第一电压源之间，第二端接地。
- 根据权利要求2所述的电路，其中，所述异或门芯片还包括：第六引脚，其一端连接地线，用于输入0V电压信号，另一端连接所述异或门芯片内的第二异或门元件的第一输入端；第七引脚，其一端输入所述供电频率检测信号，另一端连接所述第二异或门元件的第二输入端；第八引脚，其一端连接所述第二异或门元件的输出端，另一端连接所述第二引脚，用于将所述第二异或门元件处理后的供电频率检测信号输出至所述第二引脚。
- 根据权利要求2所述的电路，其中，所述异或门芯片还包括：第九引脚，其一端连接地线，用于输入0V电压信号，另一端连接所述异或门芯片内的第三异或门元件的第一输入端；第十引脚，其一端输入所述方波信号，另一端连接所述第三异或门元件的第二输入端；第十一引脚，其一端连接所述第三异或门元件的输出端，另一端连接所述第三引脚，用于将所述第三异或门元件处理后的方波信号输出至所述第三引脚。
- 根据权利要求1所述的电路，还包括：电压转换模块，其输入端分别输入所述供电频率检测信号和所述方波信号，其输出端连接所述异或逻辑模块，用于将所述供电频率检测信号和所述方波信号携带的电压值进行转换后，输出至所述异或门芯片。
- 根据权利要求5所述的电路，其中，所述电压转换模块包括：电压转换芯片，其第一引脚连接第三电压源，其第二引脚输入供电频率检测信号，其第三引脚输入与所述供电频率检测信号同频同相的方波信号，其第四引脚连接第一电阻的第一端，其第五引脚连接第二电阻的第一端，所述第一电阻的第二端和所述第二电阻的第二端均接地，其第六引脚输出转换后的所述供电频率检测信号，其第七引脚输出转换后的所述方波信号。
- 根据权利要求2所述的电路，其中，所述差异检测模块包括：光耦芯片，其第一引脚通过第三电阻连接所述异或门芯片的第四引脚，其第二引脚接地，所述光耦芯片的第一引脚和第二引脚之间连接第四电阻，其第三引脚接地，第四引脚通过第五电阻连接所述数字信号处理器，第五引脚连接第二电压源；第二电容，其第一端连接至所述光耦芯片的第五引脚和所述第二电压源之间，其第二端接地；第三电容，其第一端连接至所述第五电阻和所述数字信号处理器之间，其第二端接地。
- 根据权利要求1所述的电路，其中，所述数字信号处理器具体用于：判断所述直流信号携带的电压值是否为零；在所述直流信号携带的电压值不为零时，判定所述供电频率异常；在所述直流信号携带的电压值为零时，判定所述供电频率正常。
- 一种用电设备，包括：权利要求1至8中任一项所述的异常检测电路。
- 根据权利要求9所述的用电设备，其中，所述用电设备为感应加热设备。
- 一种异常检测方法，应用于权利要求1至8中任一项所述的电路，其中，所述方法包括：获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号，其中，所述直流信号为供电频率检测信号和与所述供电频率检测信号 同频同相的方波信号经过以后逻辑处理，再经过转换后生成的，所述方波信号的占空比等于频率正常时供电电压的占空比；根据所述直流信号携带的电压值判断供电频率是否异常。
- 根据权利要求11所述的方法，其中，根据所述直流信号携带的电压值判断供电频率是否异常，包括：判断所述直流信号携带的电压值是否为零；如果否，则判定所述供电频率异常；如果是，则判定所述供电频率正常。
- 根据权利要求12所述的方法，其中，获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号之前，所述方法还包括：判断所述供电频率检测信号的频率是否异常；如果否，则直接确定所述供电频率正常；如果是，则触发获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号。
- 根据权利要求11所述的异常检测方法，其中，所述获取基于供电频率检测信号和与所述供电频率检测信号同频同相的方波信号生成的直流信号包括：接收供电频率检测信号和与所述供电频率检测信号同频同相的方波信号，并进行异或逻辑处理，生成采样信号；将所述采样信号转换为直流信号。
- 一种计算机可读存储介质，其上存储有计算机程序，其中，所述程序被处理器执行时实现如权利要求11至14中任一项所述的方法。
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