WO2023130788A1

WO2023130788A1 - Semiconductor structure and preparation method therefor

Info

Publication number: WO2023130788A1
Application number: PCT/CN2022/124248
Authority: WO
Inventors: 吴小飞; 吴公一; 徐亚超
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-01-06
Filing date: 2022-10-10
Publication date: 2023-07-13
Also published as: CN116453961A

Abstract

Disclosed in the present disclosure are a semiconductor structure and a preparation method therefor. The preparation method for the semiconductor structure comprises: providing a substrate, and forming a bonding pad in the substrate; forming a first dielectric layer on the substrate; forming an opening in the first dielectric layer, wherein the opening exposes the bonding pad; and forming a redistribution layer in the opening, wherein the redistribution layer is electrically connected to the bonding pad, and the width of the redistribution layer is smaller than that of the opening.

Description

Semiconductor structure and its preparation method

Cross References to Related Applications

This disclosure claims the priority of the Chinese patent application with the application number 202210012128.4 and the application title "semiconductor structure and its preparation method" submitted to the China Patent Office on January 06, 2022, the entire content of which is incorporated by reference in In this disclosure.

technical field

The present disclosure relates to the technical field of integrated circuit design and manufacture, and in particular to a method for preparing a semiconductor structure and a semiconductor structure.

Background technique

Redistribution Layer (RDL) is to deposit a metal layer and a dielectric layer on the surface of the wafer, and form a corresponding metal wiring pattern, so that the originally designed integrated circuit (Integrated Circuit, IC) line contact position (I/O pad) Rewiring is carried out so that the IC can be adapted to different packages.

However, when the redistribution layer formed by the traditional redistribution technology fills the holes in the dielectric layer, it will form depressions and sidewalls, which is not conducive to the needle sticking of the Wafer Acceptance Test (WAT); The needle card (WAT Probe Card) will be stuck on the side wall of the redistribution layer, bringing out a large amount of redistribution layer debris, causing contamination of the probe card and wafer, and even damage to the probe card.

Contents of the invention

According to various embodiments of the present disclosure, a semiconductor structure and a method of fabricating the same are provided.

According to some embodiments, the first aspect of the present disclosure provides a method for fabricating a semiconductor structure, including: providing a substrate in which pads are formed; forming a first dielectric layer on the substrate; forming an opening in the first dielectric layer, The opening exposes the pad; a redistribution layer is formed in the opening, and the redistribution layer is electrically connected to the pad; the width of the redistribution layer is smaller than the width of the opening.

According to some embodiments, the width of the opening is greater than the width of the pad.

According to some embodiments, the longitudinal section of the opening is an inverted trapezoid; there is a gap between the redistribution layer and the sidewall of the opening, and the redistribution layer does not have a recess and no sidewall.

According to some embodiments, the first dielectric layer includes a silicon oxide layer.

According to some embodiments, before forming the first dielectric layer on the substrate, it also includes the step of forming a passivation layer on the upper surface of the substrate; the first dielectric layer is formed on the upper surface of the passivation layer; the opening penetrates the passivation layer along the thickness direction , to expose the pad.

According to some embodiments, forming the first dielectric layer on the substrate includes: forming a first dielectric material layer on the upper surface of the passivation layer; performing etching on the first dielectric material layer to obtain the first dielectric layer.

According to some embodiments, after forming the first dielectric material layer on the upper surface of the passivation layer, and before performing etching treatment on the first dielectric material layer, further comprising using a dry etching process or a chemical mechanical polishing process to process the first dielectric material. The material layer is thinned.

According to some embodiments, after forming the opening in the first dielectric layer and before forming the redistribution layer in the opening, further comprising: forming a second dielectric layer on the upper surface of the first dielectric layer; forming a second dielectric layer on the upper surface of the second dielectric layer and a transition layer is formed in the opening, and the transition layer is in contact with the pad.

According to some embodiments, forming the second dielectric layer on the upper surface of the first dielectric layer includes: forming a second dielectric material layer on the upper surface of the first dielectric layer and in the opening; removing the second dielectric material layer located in the opening, to A second dielectric layer is obtained.

According to some embodiments, forming the rewiring layer in the opening includes: forming a rewiring material layer on the upper surface of the transition layer; etching the rewiring material layer to obtain the rewiring layer; connect.

According to some embodiments, after forming the redistribution layer in the opening, the method further includes: forming a barrier layer on the surface of the redistribution layer, and the barrier layer covers the upper surface and sidewalls of the redistribution layer.

According to some embodiments, the second aspect of the present disclosure provides a semiconductor structure, the semiconductor structure includes: a substrate, a first dielectric layer and a redistribution layer, the substrate has a pad; the first dielectric layer is located on the substrate; the first dielectric layer There is an opening in the layer, and the opening exposes the pad; the redistribution layer is located in the opening; the redistribution layer is electrically connected to the pad; the width of the redistribution layer is smaller than the width of the opening.

According to some embodiments, the semiconductor structure further includes a passivation layer located on the upper surface of the substrate; the first dielectric layer is located on the upper surface of the passivation layer; the opening penetrates the passivation layer along the thickness direction to expose the pad.

According to some embodiments, the semiconductor structure further includes: a second dielectric layer, a transition layer and a barrier layer, the second dielectric layer is located on the upper surface of the first dielectric layer; the transition layer is located on the upper surface of the second dielectric layer and is located in the opening; The transition layer is in contact with the pad; the barrier layer covers the upper surface and the sidewall of the redistribution layer.

Embodiments of the present disclosure may/at least have the following advantages:

In the semiconductor structure and its manufacturing method provided by the embodiments of the present disclosure, since the redistribution layer does not have recesses and sidewalls, there is extra space for the probe card to contact the redistribution layer during the WAT test, which is beneficial to the WAT test Acupuncture: Since the rewiring layer does not have depressions and side walls, it is beneficial for WAT probes to pierce the needle, and will not cause a large amount of debris pollution on the redistribution layer, which can well protect the probe card and ensure the cleanliness of the probe card and wafer .

To sum up, in the semiconductor structure and its preparation method provided by the embodiments of the present disclosure, the redistribution layer does not have the depressions and sidewalls formed by the traditional RDL technology, which is beneficial for WAT probe needles, and will not cause a large amount of residual contamination of the redistribution layer, which can It protects the probe card very well and ensures the cleanliness of the probe card and wafer.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some implementations of the embodiments of the present disclosure. For example, those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative efforts.

FIG. 1 is a schematic flow diagram of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

2 is a schematic partial cross-sectional view of a substrate provided in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

3 is a schematic partial cross-sectional view of a structure obtained after forming a passivation layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

4 is a schematic partial cross-sectional view of the structure obtained after forming a first dielectric material layer on the upper surface of the passivation layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

5 is a schematic partial cross-sectional view of a structure obtained after forming an opening and a first dielectric layer in a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

6 is a schematic partial cross-sectional view of a structure obtained after forming a second dielectric material layer in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

7 is a schematic partial cross-sectional view of a structure obtained after forming a second dielectric layer in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

8 is a schematic partial cross-sectional view of a structure obtained after forming a transition layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

9 is a schematic partial cross-sectional view of a structure obtained after forming a rewiring material layer in the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

FIG. 10 is a schematic partial cross-sectional view of a structure obtained after forming a redistribution layer in the method for fabricating a semiconductor structure provided in an embodiment of the present disclosure.

Detailed ways

In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the related drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present disclosure will be thorough and complete.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein in the description of the present disclosure are for the purpose of describing specific embodiments only, and are not intended to limit the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer. A layer may be on, adjacent to, connected to, or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. layer. It will be understood that, although the terms first, second, third etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatial terms such as "below", "below", "below", "under", "on", "above", etc., in This may be used for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not to be taken as a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "consists of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more other Presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the application are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. As such, variations from the shapes shown are to be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein but are to include deviations in shapes due to, for example, manufacturing, the regions shown in the figures are schematic in nature and their shapes are not intended to be The actual shapes of the regions of the device are shown and are not intended to limit the scope of the present disclosure.

In one embodiment of the present disclosure, as shown in FIG. 1 , a method for preparing a semiconductor structure is provided, including the following steps:

Step S10: providing a substrate in which pads are formed;

Step S20: forming a first dielectric layer on the substrate;

Step S30: forming an opening in the first dielectric layer, the opening exposes the pad;

Step S40: forming a redistribution layer in the opening, the redistribution layer is electrically connected to the pad; the width of the redistribution layer is smaller than the width of the opening.

In the manufacturing method of the semiconductor structure provided in the above-mentioned embodiments, a first dielectric layer is formed on the substrate with pads, an opening is formed in the first dielectric layer, and the opening exposes the pad in the substrate; and rewiring is formed in the opening layer, and the redistribution layer is electrically connected to the pad; the width of the redistribution layer is smaller than the width of the opening. Compared with the traditional RDL technology, the pad and the first dielectric layer remain unchanged, and the width of the redistribution layer formed in the opening is smaller than the width of the opening. The redistribution layer of the present disclosure does not have the depression and sidewall formed by the traditional RDL technology, and has It is beneficial for WAT probes to stick needles, and will not cause a large amount of debris pollution on the rewiring layer. It can well protect the probe card and ensure the cleanliness of the probe card and the wafer.

As an example, as shown in FIG. 2 , the substrate 10 provided in step S10 may include but not limited to a silicon substrate. An integrated circuit (not shown in the figure) is also formed in the substrate 10 , and the integrated circuit is electrically connected to the pad 101 .

As an example, the number of pads 101 and the number of chips can be set according to actual needs, which is not limited in the present disclosure. Only one pad 101 is illustrated in FIG. 2 .

In one embodiment, step S20 : before forming the first dielectric layer on the substrate, further includes the following step: forming a passivation layer 20 on the upper surface of the substrate 10 , as shown in FIG. 3 .

As an example, the passivation layer 20 may include a single-layer structure, or may include a stacked structure of multiple material layers. The passivation layer 20 may include but not limited to at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.

In one embodiment, step S20: forming the first dielectric layer on the substrate includes the following steps:

Step S21: forming a first dielectric material layer 31 on the upper surface of the passivation layer 20, as shown in FIG. 4;

Step S22: Etching the first dielectric material layer 31 to obtain the first dielectric layer 30, as shown in FIG. 5 .

Specifically, after the first dielectric material layer 31 is processed by an etching process to obtain the first dielectric layer 30 , then the passivation layer 20 is etched to form the opening 301 . It can be understood that the passivation layer 20 and the first dielectric material layer 31 are etched in one step by using an etching process. As an example, the first dielectric layer 30 includes, but is not limited to, a silicon oxide layer.

In one embodiment, step S21: after forming the first dielectric material layer 31 on the upper surface of the passivation layer 20, and before performing etching treatment on the first dielectric material layer 31, further includes using dry etching process or chemical The mechanical grinding process thins the first dielectric material layer 31 .

In one embodiment, the first dielectric layer 30 is formed on the upper surface of the passivation layer 20 ; the opening 301 penetrates through the passivation layer 20 along the thickness direction to expose the pad 101 .

In one embodiment, step S30: forming an opening 301 in the first dielectric layer 30, the opening 301 exposing the pad 101 also includes etching the passivation layer 20 and the opening 101 exposing part of the substrate 10, so that the opening 301 penetrates the passivation The layer 20 extends into the substrate 10 to expose the bonding pad 101 .

Specifically, exposing the pad 101 means that the bottom of the opening 301 extends to the upper surface of the pad 101 to expose the upper surface of the pad 101 .

In one embodiment, please continue to refer to FIG. 5, the width of the opening 301 is greater than the width of the pad 101, that is, the bottom of the opening 301 exposes the entire upper surface of the pad 101, so that the subsequent formation of the repositioning in the opening 301 The width of the wiring layer can be smaller than the width of the opening 301 to ensure that the formed rewiring layer has no recesses and side walls, and there is extra space for the probe card to contact the rewiring layer, which is beneficial for WAT probes to pierce.

In one embodiment, as shown in FIGS. 6-8 , step S30: after forming the opening in the first dielectric layer, and step S40: before forming the redistribution layer in the opening 301, further includes:

Step S301: forming a second dielectric layer 40 on the upper surface of the first dielectric layer 30;

Step S302 : forming a transition layer 50 on the upper surface of the second dielectric layer 40 and in the opening, the transition layer 50 is in contact with the pad 101 .

In one embodiment, step S301: forming the second dielectric layer 40 on the upper surface of the first dielectric layer 30 includes the following steps:

Step S3011: forming a second dielectric material layer 41 on the upper surface of the first dielectric layer 30 and in the opening 301, as shown in FIG. 6 ;

Step S3012: removing the second dielectric material layer 41 located in the opening 301 to obtain the second dielectric layer 40, as shown in FIG. 7;

Specifically, a second dielectric layer 40 is added between the first dielectric layer 30 and the redistribution layer, and the second dielectric layer 40 is used as an etching barrier layer in the process of forming the redistribution layer to avoid contamination of the metal etching chamber. And it can protect the first dielectric layer 30 below the second dielectric layer 40 from being damaged.

As an example, the second dielectric layer 41 can be formed by using but not limited to spin coating process, physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process; the second dielectric layer 40 can include but not limited to polyimide ( Polyimide, PI) layer or polybenzoxazole (Polybenzox, PBO) layer.

As an example, the second dielectric material layer 41 located in the opening 301 may be removed by using but not limited to a photolithography process or a dry etching process. The transition layer 50 formed in FIG. 8 may adopt but not limited to electroplating or magnetron sputtering process, and the transition layer 50 includes but not limited to titanium (Ti) or titanium nitride (TiN) and the like.

In one embodiment, step S40: forming the redistribution layer 60 in the opening 301 includes:

Step S41: forming a rewiring material layer 61 on the upper surface of the transition layer 50, as shown in FIG. 9 ;

Step S42: Etching the rewiring material layer 61 to obtain the rewiring layer 60; the rewiring layer 60 is electrically connected to the pad 101 through the transition layer 50, as shown in FIG. 10 .

As an example, the rewiring layer 60 may be formed by electroplating or magnetron sputtering; the rewiring layer 60 may include but not limited to an aluminum wiring layer or a copper wiring layer, and the like.

As an example, the rewiring material layer 61 located inside the opening 301 may be removed by using but not limited to a wet etching process, so that there is a gap between the rewiring layer 60 remaining in the opening 301 and the sidewall of the opening 301, and the rewiring layer The 60 does not have a recess and a side wall, so that when the probe card performs the WAT test, there is an extra space to contact the redistribution layer 60, which is beneficial to the WAT test.

As an example, the longitudinal section of the opening 301 is an inverted trapezoid, and the gap between the redistribution layer 60 in the opening 301 and the bottom of the opening 301 is greater than the gap between the redistribution layer 60 in the opening 301 and the top of the opening 301 .

In one embodiment, step S40: after forming the redistribution layer 60 in the opening 301, includes

Step S50 : forming a barrier layer 70 on the surface of the redistribution layer 60 .

Specifically, the barrier layer 70 covers the upper surface and sidewalls of the redistribution layer 60, and the lower surface of the barrier layer 70 is in contact with the transition layer 50 to completely seal the redistribution layer 60, so as to avoid the diffusion of the redistribution layer 60. . Barrier layer 70 includes, but is not limited to, a titanium nitride layer.

In an embodiment of the present disclosure, a semiconductor structure is also provided, including:

A substrate 10, with a pad 101 inside the substrate 10;

The first dielectric layer 30 is located on the substrate 10; the first dielectric layer 30 has an opening 301, and the opening 301 exposes the pad 101;

The redistribution layer 60 is located in the opening 301 ; the redistribution layer 60 is electrically connected to the pad 101 ; the width of the redistribution layer 60 is smaller than the width of the opening 301 .

In the semiconductor structure provided in the above embodiments, there is a pad in the substrate; the first dielectric layer is located on the substrate; there is an opening in the first dielectric layer, and the opening exposes the pad; the redistribution layer is located in the opening; the redistribution layer and The pads are electrically connected; the width of the redistribution layer is smaller than the width of the opening. Compared with the traditional RDL technology, the pad and the first dielectric layer remain unchanged, and the width of the redistribution layer formed in the opening is smaller than the width of the opening. The redistribution layer of the present disclosure does not have the depression and sidewall formed by the traditional RDL technology, and has It is beneficial for WAT probes to stick needles, and will not cause a large amount of debris pollution on the rewiring layer. It can well protect the probe card and ensure the cleanliness of the probe card and the wafer.

In one embodiment, the width of the opening 301 is greater than the width of the pad 101 .

In one embodiment, the longitudinal section of the opening 301 is an inverted trapezoid; there is a gap between the redistribution layer 60 and the sidewall of the opening 301, and the redistribution layer does not have a recess or a sidewall, so that the probe is stuck when performing the WAT test. , there is extra space in contact with the redistribution layer, which is conducive to the WAT test needle.

In one embodiment, the semiconductor structure further includes: a passivation layer 20 located on the upper surface of the substrate 10; a first dielectric layer 30 located on the upper surface of the passivation layer 20; an opening 301 penetrates the passivation layer 20 along the thickness direction to expose pad 101.

In one embodiment, the semiconductor structure further includes: a second dielectric layer 40 located on the upper surface of the first dielectric layer 30; a transition layer 50 located on the upper surface of the second dielectric layer 40 and located in the opening 301; the transition layer 50 contact with pad 101.

In one embodiment, the semiconductor structure further includes a barrier layer 70, the barrier layer 70 covers the upper surface and the sidewall of the redistribution layer 60, the lower surface of the barrier layer 70 is in contact with the transition layer 50, and completely seals the redistribution layer 60 , to avoid diffusion of the redistribution layer 60 . Barrier layer 70 includes, but is not limited to, a titanium nitride layer. Before the WAT test, holes can be opened at specified positions on the barrier layer 70 so that the probes can contact the internal redistribution layer 60 through the holes.

Please note that the above-mentioned embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

It should be understood that, unless otherwise specified herein, the execution of the steps is not strictly limited in order, and the steps may be executed in other orders. Moreover, at least a part of the steps may include multiple sub-steps or multiple stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, these sub-steps or stages The order of execution is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

The various technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the various technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present disclosure, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the scope of protection of the disclosed patent should be based on the appended claims.

Claims

A method for preparing a semiconductor structure, comprising:

A substrate is provided, and a pad is formed in the substrate;

forming a first dielectric layer on the substrate;

forming an opening in the first dielectric layer, the opening exposing the pad;

A redistribution layer is formed in the opening, and the redistribution layer is electrically connected to the pad; the width of the redistribution layer is smaller than the width of the opening.
The method for fabricating a semiconductor structure according to claim 1, wherein a width of the opening is greater than a width of the bonding pad.
The method for fabricating a semiconductor structure according to claim 1, wherein the longitudinal section of the opening is an inverted trapezoid; there is a gap between the redistribution layer and the sidewall of the opening.
The method for fabricating a semiconductor structure according to claim 1, wherein the first dielectric layer comprises a silicon oxide layer.
The method for preparing a semiconductor structure according to any one of claims 1-4, wherein, before forming the first dielectric layer on the substrate, further comprising the step of forming a passivation layer on the upper surface of the substrate; The first dielectric layer is formed on the upper surface of the passivation layer; the opening penetrates the passivation layer along the thickness direction to expose the welding pad.
The method for preparing a semiconductor structure according to claim 5, wherein said forming a first dielectric layer on said substrate comprises:

forming a first dielectric material layer on the upper surface of the passivation layer;

Etching the first dielectric material layer to obtain the first dielectric material layer.
The method for preparing a semiconductor structure according to claim 6, wherein, after forming the first dielectric material layer on the upper surface of the passivation layer and before performing etching treatment on the first dielectric material layer, further The method includes thinning the first dielectric material layer by using a dry etching process or a chemical mechanical polishing process.
The method for manufacturing a semiconductor structure according to any one of claims 1-4, wherein, after forming the opening in the first dielectric layer and before forming a rewiring layer in the opening, further comprising:

forming a second dielectric layer on the upper surface of the first dielectric layer;

A transition layer is formed on the upper surface of the second dielectric layer and in the opening, and the transition layer is in contact with the pad.
The method for manufacturing a semiconductor structure according to claim 8, wherein said forming a second dielectric layer on the upper surface of said first dielectric layer comprises:

forming a second dielectric material layer on the upper surface of the first dielectric layer and in the opening;

The layer of second dielectric material located within the opening is removed to obtain the second layer of dielectric material.
The method for fabricating a semiconductor structure according to claim 8, wherein said forming a redistribution layer in said opening comprises:

forming a rewiring material layer on the upper surface of the transition layer;

Etching the rewiring material layer to obtain the rewiring layer; the rewiring layer is electrically connected to the pad through the transition layer.
The method for manufacturing a semiconductor structure according to claim 8, wherein, after forming the rewiring layer in the opening, further comprising:

A barrier layer is formed on the surface of the redistribution layer, and the barrier layer covers the upper surface and the sidewall of the redistribution layer.
A semiconductor structure comprising:

a substrate having a pad therein;

a first dielectric layer located on the substrate; an opening is formed in the first dielectric layer, and the opening exposes the pad;

The redistribution layer is located in the opening; the redistribution layer is electrically connected to the pad; the width of the redistribution layer is smaller than the width of the opening.
The semiconductor structure of claim 12, wherein a width of the opening is greater than a width of the pad.
The semiconductor structure according to claim 12, wherein the longitudinal section of the opening is an inverted trapezoid; there is a gap between the redistribution layer and the sidewall of the opening.
The semiconductor structure according to claim 12, wherein said semiconductor structure further comprises:

The passivation layer is located on the upper surface of the base; the first dielectric layer is located on the upper surface of the passivation layer; the opening penetrates the passivation layer along the thickness direction to expose the pad.
The semiconductor structure according to claim 12, wherein said semiconductor structure further comprises:

a second dielectric layer located on the upper surface of the first dielectric layer;

a transition layer located on the upper surface of the second dielectric layer and located in the opening; the transition layer is in contact with the pad;

The blocking layer covers the upper surface and the sidewall of the redistribution layer.