WO2023125248A1 - 内存带宽的控制方法、装置、电子设备和存储介质 - Google Patents

内存带宽的控制方法、装置、电子设备和存储介质 Download PDF

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WO2023125248A1
WO2023125248A1 PCT/CN2022/141128 CN2022141128W WO2023125248A1 WO 2023125248 A1 WO2023125248 A1 WO 2023125248A1 CN 2022141128 W CN2022141128 W CN 2022141128W WO 2023125248 A1 WO2023125248 A1 WO 2023125248A1
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memory bandwidth
cpu core
preset
occurrences
control
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PCT/CN2022/141128
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English (en)
French (fr)
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王波
薛志宏
李翌
李禄财
李鹏
陈彬
洪坤
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the embodiments of the present application relate to the field of computer technologies, and in particular, to a memory bandwidth control method, device, electronic device, and storage medium.
  • DRAM Dynamic Random Access Memory
  • CPU Central Processing Unit
  • the DRAM controller usually uses a scheduling algorithm to reorder the requests to maximize Improve the overall throughput of DRAM; the above factors all affect the timing predictability of memory-intensive real-time applications.
  • the main purpose of the embodiments of the present application is to provide a memory bandwidth control method, device, electronic device, and storage medium. It aims to avoid the mutual interference of each CPU in the multi-core system and the contention of each CPU core to the DRAM controller, and ensure the determinism of the multi-core system and the timeliness and stability of each CPU core memory access.
  • an embodiment of the present application provides a method for controlling memory bandwidth, which is applied to an operating system corresponding to a multi-core system including CPU cores of each central processing unit, including: detecting the preset evaluation parameters of the CPU cores Describe the number of occurrences of the specified event of the CPU core memory bandwidth occupation situation; when the number of occurrences of the specified event meets the preset control condition, obtain the memory bandwidth control task flow according to the preset memory bandwidth control function and the preset control strategy; run all The memory bandwidth control task flow described above is completed to control the memory bandwidth of the CPU core.
  • an embodiment of the present application also provides a memory bandwidth control device, which is applied to an operating system corresponding to a multi-core system including CPU cores of each central processing unit, and includes: a control detection module for detecting the CPU core Preset evaluation of the number of occurrences of specified events of the CPU core memory bandwidth occupancy; task generation module, for when the number of occurrences of the specified events meets the preset control conditions, according to the preset memory bandwidth control function and preset The control strategy obtains the memory bandwidth control task flow; the memory bandwidth control module is used to run the memory bandwidth control task flow, and complete the memory bandwidth control of the CPU core.
  • an embodiment of the present application further provides an electronic device, including: at least one processor; and a memory connected to the at least one processor in communication; wherein, the memory stores information that can be used by the at least one processor An instruction executed by a processor, the instruction is executed by the at least one processor, so that the at least one processor can execute the above method for controlling memory bandwidth.
  • an embodiment of the present application further provides a computer-readable storage medium storing a computer program, and implementing the above method for controlling memory bandwidth when the computer program is executed by a processor.
  • the control method of the memory bandwidth that this application proposes, in the memory bandwidth control process of each central processing unit CPU core of the multi-core system, detects the number of occurrences of the specified event of the preset evaluation CPU core memory bandwidth occupation of the CPU core; when specified When the number of occurrences of events meets the preset control conditions, obtain the memory bandwidth control task flow according to the preset memory bandwidth control function and preset control strategy; run the memory bandwidth control task flow to complete the memory bandwidth control of the CPU core;
  • the core performs independent memory bandwidth occupancy detection, and memory bandwidth control is performed when the memory bandwidth occupancy reaches a certain condition, so as to avoid affecting the memory access time of other CPUs due to the excessive occupancy of memory bandwidth by one CPU, and avoid mutual interference between CPUs and various CPUs in a multi-core system.
  • the CPU checks the contention of the DRAM controller, thereby ensuring the determinism of the multi-core system and the timeliness and stability of the memory access of each CPU core, and solves the problem of the multi-core system caused by the contention of each CPU core to the DRAM controller in the prior art. Determinism, causing problems of memory access time jitter and memory access delay.
  • FIG. 1 is a flow chart of a memory bandwidth control method provided in an embodiment of the present application
  • FIG. 2 is a flowchart of a method for controlling memory bandwidth provided in an embodiment of the present application
  • FIG. 3 is a flowchart of a method for controlling memory bandwidth provided in an embodiment of the present application
  • FIG. 4 is a flowchart of a method for controlling memory bandwidth provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a device for controlling memory bandwidth provided in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.
  • Intel Corporation proposed a hardware-based memory resource isolation solution Resource Director Technology, which includes Memory Bandwidth Allocation (Memory Bandwidth Allocation, referred to as MBA) technology and memory bandwidth monitoring (Memory Bandwidth Monitoring, referred to as MBM) technology; ARM also proposed Memory System Resource Partitioning and Monitoring technology to solve the performance degradation of some key applications caused by the competition of shared resources in the process of CPU memory access Or the problem of overall system performance degradation.
  • MBM Memory Bandwidth Monitoring
  • ARM also proposed Memory System Resource Partitioning and Monitoring technology to solve the performance degradation of some key applications caused by the competition of shared resources in the process of CPU memory access Or the problem of overall system performance degradation.
  • the solutions of Intel and ARM depend on hardware, and currently only the latest part of the hardware supports them; This problem cannot be solved by using the hardware solutions mentioned in Intel's Resource Director Technology technology and ARM's Memory System Resource Partitioning and Monitoring technology.
  • the memory bandwidth control method mentioned in this application is a general memory bandwidth control method that does not rely on the latest special hardware support and can be implemented in CPU cores that do not support Intel RDT and ARM MSRPM technologies.
  • An embodiment of the present application relates to a method for controlling memory bandwidth, which is applied to an operating system corresponding to a multi-core system including CPU cores of each central processing unit, as shown in FIG. 1 , at least including but not limited to the following steps:
  • Step 101 detecting the number of occurrences of a preset specified event of the CPU core for evaluating the memory bandwidth usage of the CPU core.
  • the specified event for evaluating the CPU core memory bandwidth occupancy may be the last level cache misses event Last Level Cache Misses Events, address translation cache misses event Translation Look-aside Buffer Misses Events, memory management unit data Busy events Data MMU busy Events, Load/Store, Data Cache, and Data Line Fill Buffer (DLFB) Events or Instruction MMU, Data MMU and L2 MMU Events, where the above events can be used independently or in combination.
  • DLFB Data Line Fill Buffer
  • the detection when detecting the number of occurrences of a specified event of the CPU core for evaluating CPU core memory bandwidth usage, the detection may be performed based on the existing hardware of the CPU core, or may be detected based on a software program, specifically The detection method is determined by the specified event that is set to evaluate the CPU core memory bandwidth usage.
  • the specified event may be composed of multiple hardware events, such as hardware event A and hardware event B to form a specified event, then the number of occurrences of the specified event is equal to the ratio of the number of occurrences of each hardware event to the preset threshold of each hardware event
  • Each hardware event can be the last level cache miss event, address translation cache miss event, memory management unit data busy event, Load/Store, Data Cache, and Data Line Fill Buffer (DLFB) Events or Instruction MMU, Data MMU and L2 MMU Events.
  • DLFB Data Line Fill Buffer
  • a detection cycle can also be set for each CPU core, and the detection of the number of occurrences of the specified event of the CPU core is triggered according to the detection cycle, so that the application can automatically specify the number of events for each CPU core within a detection cycle. Occurrences are detected.
  • Step 102 when the number of occurrences of the specified event satisfies a preset control condition, acquire a memory bandwidth control task flow according to a preset memory bandwidth control function and a preset control policy.
  • the preset control condition is the threshold value of the number of occurrences of the specified event, which is generated according to the memory bandwidth quota of the CPU core and the memory bandwidth control algorithm, and when multiple hardware events are included in the specified event, when generating The weight of each hardware event will be considered when specifying the threshold of the number of occurrences of an event (that is, the threshold of the number of occurrences of a specified event is generated by the threshold of the number of occurrences of each hardware event and the weight of each hardware event); The control conditions will be different due to the memory bandwidth quota of each CPU core; the sum of the actual memory bandwidth quotas of each CPU core in a multi-core system is less than the total memory bandwidth of the multi-core system.
  • control conditions when the number of occurrences of the specified event satisfies the control condition, that is, when the number of occurrences of the specified event reaches the threshold, it is necessary to obtain the memory bandwidth control task flow according to the memory bandwidth control function and the control strategy; this application contains a variety of Each control strategy has its corresponding memory control task flow. After the control strategy of the CPU core is determined, the memory bandwidth control task flow corresponding to the determined control strategy can be awakened through the memory bandwidth control function.
  • the control strategy may be to execute a certain number of no-operation instructions, and the memory bandwidth control task flow corresponding to the control strategy indicates to execute a preset number of no-operation instructions; the control strategy may be to block the current task of the CPU core for a period of time, The memory bandwidth control task flow corresponding to this control strategy is to block the memory access operation of the CPU core within a preset time; the control strategy can be to occupy the global memory bandwidth or the idle memory bandwidth of other CPU cores; the memory bandwidth control task flow corresponding to this control strategy is used for When other CPU cores in the multi-core system have free memory bandwidth, the free memory bandwidth is obtained from other CPU cores for the CPU core to call; the control strategy can be the task of sending the memory bandwidth control signal to the CPU core, and the memory corresponding to the control strategy The bandwidth control task flow is used to send the memory bandwidth control signal to the task of the CPU core, which is processed by the task itself.
  • the acquired memory bandwidth control task flow is set with a priority. After the memory bandwidth control task flow is acquired, the priority of the memory bandwidth control task flow is guaranteed for a preset time length, within the time length Execute the memory bandwidth control task flow.
  • Step 103 running the memory bandwidth control task flow to complete the memory bandwidth control of the CPU core.
  • the obtained memory bandwidth control task flow is executed, and the memory of the CPU core is controlled according to the control policy corresponding to the memory bandwidth control task flow; thereby avoiding that the memory access request of the CPU core is sent through the DRAM controller To the bus, because in the case of multiple requests, the DRAM controller will serially sort the memory access requests of each CPU, resulting in mutual interference between the CPU cores of the multi-core system. This phenomenon is usually called Called "Noisy Neighbors".
  • the number of occurrences of the specified event of the preset evaluation CPU core memory bandwidth occupancy of the CPU core is detected; when the number of occurrences of the specified event satisfies
  • preset control conditions obtain the memory bandwidth control task flow according to the preset memory bandwidth control function and the preset control strategy; run the memory bandwidth control task flow to complete the memory bandwidth control of the CPU core;
  • Bandwidth occupancy detection memory bandwidth control is performed when the memory bandwidth occupancy reaches a certain condition, to avoid affecting the memory access time of other CPUs due to excessive memory bandwidth occupation of one CPU, and to avoid mutual interference between CPUs in a multi-core system and each CPU checking the DRAM controller contention, thereby ensuring the determinism of the multi-core system and the timeliness and stability of each CPU core memory access, which solves the uncertainty of the multi-core system caused by the contention of each CPU core to the DRAM controller in the prior art, resulting in memory Access time jitter
  • An embodiment of the present application relates to a method for controlling memory bandwidth, which is applied to an operating system corresponding to a multi-core system including CPU cores of each central processing unit, as shown in FIG. 2 , including:
  • Step 201 when the specified event is an address translation cache miss event, detect the number of occurrences of the specified event of the CPU core for evaluating CPU core memory bandwidth usage through a preset detection task flow.
  • the overhead required due to address mapping is high.
  • the conversion process is as follows: the first access to memory is to access the page table, and take out the physical page corresponding to the virtual page.
  • the second access to memory is to access the actual memory address.
  • modern CPUs include a special Cache to track recently used address translations. This is the Translation Look-aside Buffer (TLB for short).
  • TLB Translation Look-aside Buffer
  • the number of occurrences of address translation cache miss events of the CPU core can be obtained by detecting the task flow.
  • Step 202 when the number of occurrences of the specified event satisfies a preset control condition, acquire a memory bandwidth control task flow according to a preset memory bandwidth control function and a preset control policy.
  • the specified event when the specified event is an address translation cache miss event, when the number of occurrences of the specified event meets the preset control condition, it can jump to the memory bandwidth control function, and obtain the memory bandwidth control function in combination with the control strategy
  • the task flow the method for obtaining the task flow is roughly the same as step 102 of the embodiment of the present application, and will not be described here one by one; wherein, the memory bandwidth control function mentioned in this step can be implemented based on the TLB Miss processing function.
  • Step 203 running the memory bandwidth control task flow to complete the memory bandwidth control of the CPU core.
  • this step is substantially the same as step 103 in the embodiment of the present application, and details are not repeated here.
  • a software program can also be used to detect the occurrence times of specified events of each CPU core, which only depends on the hardware event counter or performance timer function of the CPU core, and does not depend on Other additional hardware functions make this application widely applicable and low in cost.
  • An embodiment of the present application relates to a method for controlling memory bandwidth, which is applied to an operating system corresponding to a multi-core system including CPU cores of each central processing unit, as shown in FIG. 3 , including:
  • Step 301 when the specified event is a CPU core last-level cache miss event, detect the number of occurrences of the specified event of the CPU core for evaluating CPU core memory bandwidth usage through a performance counter of the CPU core.
  • cache hit ratio is a key performance indicator of CPU core performance.
  • the last level of cache is called Last Level Cache; behind the last level of cache is memory.
  • L1 closest first-level cache
  • cache Hit cache hit
  • Cache Miss miss
  • L1 closest first-level cache
  • the ratio of cache misses has a great impact on the performance of the CPU, especially when the last level cache misses, the damage to performance is particularly serious.
  • This damage mainly has two aspects of performance impact: the first aspect is that the speed of the CPU core is affected.
  • the memory access delay is many times (for example, five times) that of the last-level cache, which in turn affects the computing speed of the CPU core.
  • the second aspect is about memory bandwidth. If the last level of cache misses, bandwidth resources can only be obtained from memory. The count of last-level cache misses is actually the count of memory accesses, because CPU core memory accesses always go through the last-level cache and will not skip the last-level cache. So every last-level cache miss results in a memory access; the converse is also true: every memory access is due to a last-level cache miss.
  • the memory bandwidth of a system is limited, which is likely to become a performance bottleneck. Fetching data from memory consumes memory bandwidth. Therefore, if the last level cache miss frequency is high, then the use of memory bandwidth can be significant. When the memory bandwidth usage is high, the memory access latency will rise sharply. Therefore, the number of occurrences of last-level cache miss events can be used to evaluate CPU core memory bandwidth usage.
  • performance measuring counters Performance Measuring Counters, PMC for short
  • PMC Performance Measuring Counters
  • Step 302 according to the number of occurrences of the specified event reported by the performance counter of the CPU core at a preset period, it is judged whether the number of occurrences of the specified event satisfies the control condition.
  • the performance counter of the CPU core after the performance counter of the CPU core detects the number of occurrences of the specified event, it does not perform task processing on the number of occurrences of the specified event, but reports to the memory bandwidth control system, and the memory bandwidth control system according to the CPU The number of occurrences of the specified event reported by the performance counter of the core is used to determine whether the number of occurrences of the specified event meets the control condition.
  • Step 303 according to whether the performance counter of the CPU core reports an interrupt trigger instruction, it is judged whether the number of occurrences of the specified event satisfies the control condition.
  • the performance counter of the CPU core is also provided with a control condition for the number of occurrences of the specified event. After detecting the number of occurrences of the specified event, the performance counter of the CPU core judges whether the number of occurrences of the specified event satisfies the control condition , when the number of occurrences of a given event meets the control condition, an interrupt trigger command is generated, and the interrupt trigger command is reported to the memory bandwidth control system. After receiving the interrupt trigger command, the memory bandwidth control system considers that the number of occurrences of the specified event meets the control conditions.
  • Step 304 when the number of occurrences of the specified event satisfies the preset control condition, acquire the memory bandwidth control task flow according to the preset memory bandwidth control function and the preset control strategy.
  • the specified event is a CPU core last-level cache miss event
  • a memory bandwidth control interrupt will be triggered, and the memory bandwidth control function can be jumped to , combined with the control strategy to obtain the memory bandwidth control task flow
  • the method of obtaining the task flow is roughly the same as step 102 of the embodiment of the present application, and will not be described here one by one; wherein, the memory bandwidth control function mentioned in this step is preferably interrupt processing function, and other functions for terminating or suspending the memory bandwidth control process of the CPU core can also be used.
  • Step 305 running the memory bandwidth control task flow to complete the memory bandwidth control of the CPU core.
  • this step is substantially the same as step 103 in the embodiment of the present application, and details are not repeated here.
  • step 302 and step 303 are two parallel methods, and one of them can be selected.
  • the detection of the number of occurrences of the specified event of the CPU core can also be performed based on the PMC register of the existing CPU hardware, without adding additional hardware to support, so that the application of the present application wide and low cost.
  • An embodiment of the present application relates to a method for controlling memory bandwidth, which is applied to an operating system corresponding to a multi-core system including CPU cores of each central processing unit, as shown in FIG. 4 , including:
  • step 401 the memory bandwidth quota of the CPU core is obtained, and a control condition is generated according to a preset control algorithm and the memory bandwidth quota.
  • the memory bandwidth quota of the CPU core needs to be obtained, and then the memory bandwidth quota of the CPU core is converted into a threshold of occurrence times of specified events according to a preset control algorithm , that is, the control condition.
  • a preset control algorithm that is, the control condition.
  • Step 402 detecting the number of occurrences of a preset specified event of the CPU core for evaluating the memory bandwidth usage of the CPU core.
  • this step is substantially the same as step 101 in the embodiment of the present application, and details are not repeated here.
  • Step 403 when the number of occurrences of the specified event satisfies the control condition, acquire the memory bandwidth control task flow according to the preset memory bandwidth control function and the preset control strategy.
  • this step is substantially the same as step 102 in the embodiment of the present application, and details are not repeated here.
  • Step 404 running the memory bandwidth control task flow to complete the memory bandwidth control of the CPU core.
  • this step is substantially the same as step 103 in the embodiment of the present application, and details are not repeated here.
  • each CPU core before detecting the number of occurrences of specified events for evaluating the CPU core memory bandwidth occupancy of each CPU core, each CPU core may be generated according to the memory bandwidth quota of each CPU core.
  • the control conditions of the number of occurrences of the specified event, so that when the application judges the number of occurrences of the specified event to each CPU, the judgment control conditions adopted are all corresponding to each CPU, thereby improving the memory bandwidth control of each CPU by the application. accuracy of judgment.
  • step division of the above various methods is only for the sake of clarity of description. During implementation, it can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. ; Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but not changing the core design of the algorithm and process are all within the scope of protection of this patent.
  • FIG. 5 is a schematic diagram of the memory bandwidth control device described in this embodiment, including: a control detection module 501, a task generation module 502 and a memory bandwidth control Module 503.
  • the control detection module 501 is used to detect the number of occurrences of the specified event of the preset evaluation CPU core memory bandwidth occupancy of the CPU core;
  • a task generation module 502 configured to obtain a memory bandwidth control task flow according to a preset memory bandwidth control function and a preset control strategy when the number of occurrences of a specified event satisfies a preset control condition;
  • the memory bandwidth control module 503 is configured to run the memory bandwidth control task flow, and complete the memory bandwidth control on the CPU core.
  • the operating system mentioned in the embodiment of the present application may be a partitioned operating system of a multi-core system, or may be a general-purpose operating system of a multi-core system.
  • this embodiment is a system embodiment corresponding to the above method embodiment, and this embodiment can be implemented in cooperation with the above method embodiment.
  • the relevant technical details and technical effects mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition.
  • the relevant technical details mentioned in this embodiment can also be applied in the above embodiments.
  • modules involved in this embodiment are logical modules.
  • a logical unit can be a physical unit, or a part of a physical unit, or multiple physical units. Combination of units.
  • units that are not closely related to solving the technical problem proposed in the present application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.
  • An embodiment of the present application relates to an electronic device, as shown in FIG. 6 , including: at least one processor 601; and a memory 602 communicatively connected to the at least one processor 601; wherein, the memory 602 stores An instruction that can be executed by the at least one processor 601, the instruction is executed by the at least one processor 601, so that the at least one processor 601 can execute the method for controlling memory bandwidth in the foregoing embodiments.
  • the memory and the processor are connected by a bus, and the bus may include any number of interconnected buses and bridges, and the bus connects one or more processors and various circuits of the memory together.
  • the bus may also connect together various other circuits such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art and therefore will not be further described herein.
  • the bus interface provides an interface between the bus and the transceivers.
  • a transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing means for communicating with various other devices over a transmission medium.
  • the data processed by the processor is transmitted on the wireless medium through the antenna, further, the antenna also receives the data and transmits the data to the processor.
  • the processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management, and other control functions. Instead, memory can be used to store data that the processor uses when performing operations.
  • One embodiment of the present application relates to a computer-readable storage medium storing a computer program.
  • the above method embodiments are implemented when the computer program is executed by the processor.
  • a storage medium includes several instructions to make a device ( It may be a single-chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), magnetic disk or optical disc, etc. can store program codes. medium.

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Abstract

本申请涉及计算机技术领域，特别涉及一种内存带宽的控制方法、装置、电子设备和存储介质。应用在多核系统对应的操作系统上，方法包括：检测CPU核的预设评估CPU核内存带宽占用情况的指定事件的发生次数；当指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和控制策略获取内存带宽控制任务流；运行内存带宽控制任务流，完成对CPU核的内存带宽控制。

Description

内存带宽的控制方法、装置、电子设备和存储介质
相关申请
本申请要求于2021年12月30日申请的、申请号为202111682780.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及计算机技术领域，特别涉及一种内存带宽的控制方法、装置、电子设备和存储介质。
背景技术
在多核系统中，内存是一个关键的共享资源，存储器请求的处理时间是高度可变的，因为它取决于动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)控制器的状态。具体来说由于来自一个中央处理器(Central Processing Unit，简称CPU)核的存储器访问也可能受来自其他CPU核的请求的影响，DRAM控制器通常采用调度算法对请求进行重新排序，以最大限度地提高DRAM的整体吞吐量；上述因素都会影响内存密集型实时应用的时间可预测性。
然而，用于安全关键航空电子系统的多核分区操作系统平台上，CPU核之间的竞争是多核分区隔离的主要障碍。各CPU核之间的竞争是由于硬件资源的隐性共享(如：由内存控制器和主存储器引发)；且各CPU核对DRAM控制器的争用会导致多核系统的不确定性，造成内存访问抖动和内存访问延迟的问题。
发明内容
本申请实施例的主要目的在于提出一种内存带宽的控制方法、装置、电子设备和存储介质。旨在避免多核系统中各CPU的相互干扰以及各CPU核对DRAM控制器的争用，保证多核系统的确定性和各CPU核内存访问的时效性及稳定性。
为实现上述目的，本申请实施例提供了一种内存带宽的控制方法，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，包括：检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数；当所述指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流；运行所述内存带宽控制任务流，完成对所述CPU核的内存带宽控制。
为实现上述目的，本申请实施例还提供一种内存带宽的控制装置，应用包含各中央处理器CPU核的多核系统对应的操作系统上，包括：控制检测模块，用于检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数；任务生成模块，用于当所述指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流；内存带宽控制模块，用于运行所述内存带宽控制任务流，完成对所述CPU核的内存带宽控制。
为实现上述目的，本申请实施例还提供了一种电子设备，包括：至少一个处理器；以及，与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行上述的内存带宽的控制方法。
为实现上述目的，本申请实施例还提供了一种计算机可读存储介质，存储有计算机程序，所述计算机程序被处理器执行时实现上述的内存带宽的控制方法。
本申请提出的内存带宽的控制方法，在多核系统的各中央处理器CPU核的内存带宽控制过程中，检测CPU核的预设的评估CPU核内存带宽占用情况的指定事件的发生次数；当指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流；运行内存带宽控制任务流，完成对CPU核的内存带宽控制；通过对各CPU核进行独立的内存带宽占用检测，在内存带宽占用达到一定条件时进行内存带宽控制，避免因为一个CPU超额占用内存带宽而影响其他CPU的内存访问时间，避免多核系统中各CPU的相互干扰以及各CPU核对DRAM控制器的争用，进而保证多核系统的确定性和各CPU核内存访问的时效性及稳定性，解决了现有技术中各CPU核对DRAM控制器的争用会导致多核系统的不确定性，造成内存访问时间抖动和内存访问延迟的问题。
附图说明
图1是本申请实施方式提供的内存带宽的控制方法的流程图；
图2是本申请实施方式提供的内存带宽的控制方法的流程图；
图3是本申请实施方式提供的内存带宽的控制方法的流程图；
图4是本申请实施方式提供的内存带宽的控制方法的流程图；
图5是本申请实施方式提供的内存带宽的控制装置的结构示意图；
图6是本申请实施方式提供的电子设备的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
用于安全关键航空电子系统的多核分区操作系统平台上，CPU核之间的竞争是分区间时间隔离的主要障碍。核心之间的争用是由于硬件资源的隐性共享，比如由内存控制器和主存储器引发，这种现象通常被称为“吵闹邻居”，如果保持现有分区隔离方案不变，则可能破坏分区之间的时间隔离性，使得一个分区程序的执行时间受其他分区影响，导致最后期限错过，甚至导致系统故障。针对“CPU核之间的竞争是分区间时间隔离的主要障碍”这一问题，Intel公司提出了基于硬件的内存资源隔离解决方案Resource Director Technology技术，其中包含了内存带宽分配(Memory Bandwidth Allocation，简称MBA)技术和内存带宽监测(Memory Bandwidth Monitoring，简称MBM)技术；ARM公司也提出了Memory System Resource Partitioning and Monitoring技术用于解决CPU访存过程中共享资源的竞争带来的某些关键应用性能下降或者系统整体性能下降的问题。但Intel公司和ARM公司的方案依赖于硬件，目前只有最新的部分硬件支持；在航空电子领域，由于研发周期和适航的要求，采用的CPU硬件往往是远远落后于主流硬件的，因此目前无法利用Intel公司的Resource Director Technology技术和ARM公司的Memory System Resource Partitioning and Monitoring技术提及的硬件方案解决该问题。
本申请提及的内存带宽的控制方法是一种通用的内存带宽的控制方法，不依赖最新的特殊硬件支持，可以在不支持Intel RDT和ARM MSRPM技术的CPU核中实施。
本申请的一个实施例涉及一种内存带宽的控制方法，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，如图1所示，至少包括但不限于以下步骤：
步骤101，检测CPU核的预设的评估CPU核内存带宽占用情况的指定事件的发生次数。
在一示例实施中，评估CPU核内存带宽占用情况的指定事件可以是最后一级缓存未命中事件Last Level Cache Misses Events、地址变换高速缓存未命中事件Translation Look-aside Buffer Misses Events、内存管理单元数据繁忙事件Data MMU busy Events、Load/Store,Data Cache,and Data Line Fill Buffer(DLFB)Events或Instruction MMU,Data MMU and L2 MMU Events，其中，以上事件可以独立使用，也可以组合使用。
在一示例实施中，在对CPU核的评估CPU核内存带宽占用情况的指定事件的发生次数进行检测时，可以基于CPU核现有的硬件进行检测，也可以基于软件程序的方式进行检测，具体的检测方式由设定的评估CPU核内存带宽占用情况的指定事件决定。
在一示例实施中，指定事件可以由多个硬件事件组成，如硬件事件A和硬件事件B组成指定事件，那么指定事件的发生次数等于各硬件事件的发生次数与各硬件事件的预设阈值的乘积的累加和，如：指定事件的发生次数＝硬件事件A的发生次数*硬件事件A的预设阈值+硬件事件B的发生次数*硬件事B件的预设阈值，其中，指定事件中的各硬件事件可以是最后一级缓存未命中事件、地址变换高速缓存未命中事件、内存管理单元数据繁忙事件、Load/Store,Data Cache,and Data Line Fill Buffer(DLFB)Events或Instruction MMU,Data MMU and L2 MMU Events。
在一示例实施中，还可以为各CPU核设置一个检测周期，根据检测周期触发对CPU核的指定事件的发生次数的检测，使得本申请可以自动对各CPU核在一个检测周期内指定事件的发生次数进行检测。
步骤102，当指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流。
在一示例实施中，预设的控制条件是指定事件的发生次数的阈值，是根据CPU核的内存带宽配额和内存带宽控制算法生成的，而在指定事件中包含多个硬件事件时，在生成指定事件的发生次数的阈值时会考虑各硬件事件的权值(即指定事件的发生次数的阈值由各硬件事件的发生次数阈值和各硬件事件的权值生成)；多核系统中各CPU核的控制条件会由于各CPU核的内存带宽配额而不相同；多核系统中各CPU核的实际内存带宽配额的总和小于多核系统的总内存带宽。
在一示例实施中，在一检测周期中，当检测周期内的指定事件的发生次数均未满足控制条件时，则需要根据CPU核的内存带宽配额和内存带宽控制算法调整下一个检测周期内的控制条件。在一示例实施中，当指定事件的发生次数满足控制条件时，也就是指定事件的发生次数达到阈值时，需要根据内存带宽控制函数和控制策略获取内存带宽控制任务流；本申请包含有多种内控制策略，各控制策略都有其对应的存控制任务流，在该CPU核的控制策略确定好之后，可以通过内存带宽控制函数唤醒与确定好的控制策略对应的内存带宽控制任务流。
在一示例实施中，控制策略可以为执行一定数量空操作指令，该控制策略对应的内存带宽控制任务流指示执行预设数量的空操作指令；控制策略可以为阻塞CPU核的当前任务一段 时间，该控制策略对应的内存带宽控制任务流为在预设时间内阻塞CPU核的内存访问操作；控制策略可以为占用全局或者其他CPU核空闲的内存带宽；该控制策略对应的内存带宽控制任务流用于当多核系统中的其他CPU核存在空闲内存带宽时，从其他CPU核中获取空闲内存带宽供CPU核调用；控制策略可以为将内存带宽控制信号发送给CPU核的任务，该控制策略对应的内存带宽控制任务流用于将内存带宽控制信号发送给CPU核的任务，由任务自行处理。
在一示例实施中，所获取的内存带宽控制任务流设置有优先级，当获取到内存带宽控制任务流之后，通过内存带宽控制任务流的优先级保证一个预先设置的时间长度，在时间长度内执行该内存带宽控制任务流。
步骤103，运行内存带宽控制任务流，完成对CPU核的内存带宽控制。
在一示例实施中，运行所获取的内存带宽控制任务流，根据该内存带宽控制任务流对应的控制策略对CPU核的内存进行控制；从而避免避免该CPU核的内存访问请求通过DRAM控制器送到总线上，因为在存在多个请求的情况下，DRAM控制器会对各个CPU的内存访问请求进行串行排序，从而导致的多核系统的各CPU核之间存在相互干扰，这种现象通常被称为“吵闹邻居”。
此处需要注意的是，本申请提及的包含各中央处理器CPU核的多核系统对应的操作系统中，对各CPU核的内存带宽控制是单独进行的。
本申请实施例，在多核系统的各中央处理器CPU核的内存带宽控制过程中，检测CPU核的预设的评CPU核内存带宽占用情况的指定事件的发生次数；当指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流；运行内存带宽控制任务流，完成对CPU核的内存带宽控制；通过对各CPU核进行独立的内存带宽占用检测，在内存带宽占用达到一定条件时进行内存带宽控制，避免因为一个CPU超额占用内存带宽而影响其他CPU的内存访问时间，避免多核系统中各CPU的相互干扰以及各CPU核对DRAM控制器的争用，进而保证多核系统的确定性和各CPU核内存访问的时效性及稳定性，解决了现有技术中各CPU核对DRAM控制器的争用会导致多核系统的不确定性，造成内存访问时间抖动和内存访问延迟的问题。
本申请的一个实施例涉及一种内存带宽的控制方法，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，如图2所示，包括：
步骤201，当指定事件为地址变换高速缓存未命中事件时，通过预设的检测任务流检测CPU核的评估CPU核内存带宽占用情况的指定事件的发生次数。
在一示例实施中，由于地址映射(从虚拟地址转换成物理地址)需要的开销开大。转换过程如下：第一次访问内存是访问页表，取出虚拟页对应的物理页。第二次访问内存是访问实际内存地址。为了提高效率，现代CPU都包含了一个特殊Cache来跟踪最近使用过的地址变换，这个就是地址变换高速缓存(Translation Look-aside Buffer，简称TLB)。
在一示例实施中，对于TLB Miss由软件负责处理的系统，如PPC-e500内核寄存器，可以通过检测任务流来获取CPU核的地址变换高速缓存未命中事件的发生次数。
步骤202，当指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流。
在一示例实施中，当指定事件为地址变换高速缓存未命中事件时，在指定事件的发生次 数满足预设控制条件时，则会可以跳转到内存带宽控制函数，结合控制策略获取内存带宽控制任务流，获取任务流的方法与本申请实施例的步骤102大致相同，此处不一一赘述；其中，本步骤所提及的内存带宽控制函数可以是基于TLB Miss处理函数实现。
步骤203，运行内存带宽控制任务流，完成对CPU核的内存带宽控制。
在一示例实施中，本步骤与本申请实施例的步骤103大致相同，此处不一一赘述。
本申请实施例，在其他实施例的基础之上还可以使用软件程序来对各CPU核的指定事件的发生次数进行检测，只依赖于CPU核的硬件事件计数器或者性能计时器功能，不依赖于其他额外硬件功能，使得本申请的适用面广且成本低。
本申请的一个实施例涉及一种内存带宽的控制方法，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，如图3所示，包括：
步骤301，当指定事件为CPU核最后一级缓存未命中事件时，通过CPU核的性能计数器检测CPU核的评估CPU核内存带宽占用情况的指定事件的发生次数。
在一示例实施中，缓存命中率是CPU核性能的一个关键性能指标。CPU里面有好几级缓存Cache，每一级缓存都比后一级缓存访问速度快，最后一级缓存称为Last Level Cache；最后一级缓存的后面就是内存。当CPU需要访问一块数据或者指令时，它会首先查看最靠近的一级缓存(L1)；如果数据存在，那么就是缓存命中(Cache Hit)，否则就是不命中(Cache Miss)，此时需要继续查询下一级缓存。缓存不命中的比例对CPU的性能影响很大，尤其是最后一级缓存的不命中时，对性能的损害尤其严重。这个损害主要有两方面的性能影响：第一个方面是CPU核的速度受影响。在最后一级缓存没命中时便会继续访问内存，内存的访问延迟是最后一级缓存的延迟的很多倍(比如五倍)，进而影响CPU核的计算速度。第二个方面是关于内存带宽。如果最后一级缓存没有命中，那么就只能从内存里面获取带宽资源。最后一级缓存不命中的计数，其实就是对内存访问的计数，因为CPU核对内存的访问总是要经过最后一级缓存，不会跳过最后一级缓存的。所以每一次最后一级缓存未命中，就会导致一次内存访问；反之也是成立的：每一次内存访问都是因为最后一级缓存没有命中。而一个系统的内存带宽是有限制的，很有可能会成为性能瓶颈。从内存里取数据，就会占用内存带宽。因此，如果最后一级缓存未命中频次很高，那么对内存带宽的使用就会很大。内存带宽使用率很高的情况下，内存的存取延迟会急剧上升。因此，可以使用最后一级缓存未命中事件的发生次数来评估CPU核内存带宽占用情况。
在一示例实施中，可以使用CPU核中的性能计数器(Performance Measuring Counters，简称PMC)来对最后一级缓存未命中事件的发生次数进行检测。
步骤302，根据预设周期CPU核的性能计数器上报的指定事件的发生次数，判断指定事件的发生次数是否满足控制条件。
在一示例实施中，CPU核的性能计数器在检测到指定事件的发生次数之后，并不会对指定事件的发生次数进行任务处理，而是上报至内存带宽控制系统中，内存带宽控制系统根据CPU核的性能计数器上报的指定事件的发生次数来判断该指定事件的发生次数是否满足控制条件。
步骤303，根据CPU核的性能计数器是否上报中断触发指令，判断指定事件的发生次数是否满足控制条件。
在一示例实施中，CPU核的性能计数器中也设置有指定事件的发生次数的控制条件，在 检测到指定事件的发生次数之后，由CPU核的性能计数器判断指定事件的发生次数是否满足控制条件，在定事件的发生次数满足控制条件时生成一个中断触发指令，并将中断触发指令上报至内存带宽控制系统，内存带宽控制系统在接收到该中断触发指令之后，便认为指定事件的发生次数满足控制条件。
步骤304，当指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流。
在一示例实施中，当指定事件为CPU核最后一级缓存未命中事件时，在指定事件的发生次数满足预设控制条件时，则会触发内存带宽控制中断，可以跳转到内存带宽控制函数，结合控制策略获取内存带宽控制任务流，获取任务流的方法与本申请实施例的步骤102大致相同，此处不一一赘述；其中，本步骤所提及的内存带宽控制函数优选为中断处理函数，其他用于使CPU核的内存带宽控制流程终止或暂停的函数也可使用。
步骤305，运行内存带宽控制任务流，完成对CPU核的内存带宽控制。
在一示例实施中，本步骤与本申请实施例的步骤103大致相同，此处不一一赘述。
此处需要注意的是：步骤302和步骤303是两种并列的方法，可任选其一进行。
本申请实施例，在其他实施例的基础之上还可以基于现有CPU硬件的PMC寄存器进行CPU核的指定事件的发生次数的检测，无需新增额外的硬件来支持，使得本申请的适用面广且成本低。
本申请的一个实施例涉及一种内存带宽的控制方法，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，如图4所示，包括：
步骤401，获取CPU核的内存带宽配额，并根据预设的控制算法和内存带宽配额生成控制条件。
在一示例实施中，在对CPU核进行指定事件的检测之前，需要获取到该CPU核的内存带宽配额，之后根据预设的控制算法将CPU核的内存带宽配额转换为指定事件的发生次数阈值，即控制条件，在后续检测到的指定事件的发生次数满足控制条件时，就说明该CPU核的内存带宽占用情况以达到最大值，需要进行内存带宽控制。
步骤402，检测CPU核的预设的评估CPU核内存带宽占用情况的指定事件的发生次数。
在一示例实施中，本步骤与本申请实施例的步骤101大致相同，此处不一一赘述。
步骤403，当指定事件的发生次数满足控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流。
在一示例实施中，本步骤与本申请实施例的步骤102大致相同，此处不一一赘述。
步骤404，运行内存带宽控制任务流，完成对CPU核的内存带宽控制。
在一示例实施中，本步骤与本申请实施例的步骤103大致相同，此处不一一赘述。
本申请实施例，在其他实施例的基础之上还可以在对各CPU核的评估CPU核内存带宽占用情况的指定事件的发生次数进行检测之前，根据各CPU核的内存带宽配额生成各CPU核的指定事件的发生次数的控制条件，使得本申请对各CPU进行指定事件的发生次数的判断时，所采用的判断控制条件都是各CPU对应的，从而提高本申请对各CPU进行内存带宽控制判断的准确性。
上面各种方法的步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对 算法中或者流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其算法和流程的核心设计都在该专利的保护范围内。
本申请的一个实施例涉及一种内存带宽的控制装置，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，下面对本实施例的内存带宽的控制装置的细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本例的必须，图5是本实施例所述的内存带宽的控制装置的示意图，包括：控制检测模块501，任务生成模块502和内存带宽控制模块503。
控制检测模块501，用于检测CPU核的预设的评估CPU核内存带宽占用情况的指定事件的发生次数；
任务生成模块502，用于当指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流；
内存带宽控制模块503，用于运行内存带宽控制任务流，完成对CPU核的内存带宽控制。
在一示例实施中，本申请实施例提及的操作系统可以是多核系统的分区操作系统，也可以是多核系统的通用操作系统。
不难发现，本实施例为与上述方法实施例对应的系统实施例，本实施例可以与上述方法实施例互相配合实施。上述实施例中提到的相关技术细节和技术效果在本实施例中依然有效，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
值得一提的是，本实施例中所涉及到的各模块均为逻辑模块，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
本申请的一个实施例涉及一种电子设备，如图6所示，包括：至少一个处理器601；以及，与所述至少一个处理器601通信连接的存储器602；其中，所述存储器602存储有可被所述至少一个处理器601执行的指令，所述指令被所述至少一个处理器601执行，以使所述至少一个处理器601能够执行上述各实施例中的内存带宽的控制方法。
存储器和处理器采用总线方式连接，总线可以包括任意数量的互联的总线和桥，总线将一个或多个处理器和存储器的各种电路连接在一起。总线还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路连接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口在总线和收发机之间提供接口。收发机可以是一个元件，也可以是多个元件，比如多个接收器和发送器，提供用于在传输介质上与各种其他装置通信的单元。经处理器处理的数据通过天线在无线介质上进行传输，进一步，天线还接收数据并将数据传送给处理器。
处理器负责管理总线和通常的处理，还可以提供各种功能，包括定时，外围接口，电压调节、电源管理以及其他控制功能。而存储器可以被用于存储处理器在执行操作时所使用的数据。
本申请的一个实施例涉及一种计算机可读存储介质，存储有计算机程序。计算机程序被处理器执行时实现上述方法实施例。
即，本领域技术人员可以理解，实现上述实施例方法中的全部或部分步骤是可以通过程 序来指令相关的硬件来完成，该程序存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (12)

  1. 一种内存带宽的控制方法，其中，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，所述方法包括：
    检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数；
    当所述指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流；
    运行所述内存带宽控制任务流，完成对所述CPU核的内存带宽控制。
  2. 根据权利要求1所述的内存带宽的控制方法，其中，所述检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数，包括：
    当所述指定事件为地址变换高速缓存未命中事件时，通过预设的检测任务流检测所述CPU核的所述指定事件的发生次数。
  3. 根据权利要求1所述的内存带宽的控制方法，其中，所述检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数，包括：
    当所述指定事件为所述CPU核最后一级缓存未命中事件时，通过所述CPU核的性能计数器检测所述CPU核的所述指定事件的发生次数。
  4. 根据权利要求3所述的内存带宽的控制方法，其中，所述方法还包括：
    根据预设周期检测所述CPU核的性能计数器上报的所述指定事件的发生次数，判断所述指定事件的发生次数是否满足所述控制条件；或者，
    根据所述CPU核的性能计数器是否上报中断触发指令，判断所述指定事件的发生次数是否满足所述控制条件；所述中断触发指令是所述CPU核的性能计数器在所述指定事件的发生次数满足所述控制条件时生成的。
  5. 根据权利要求1至权利要求4中任一项所述的内存带宽的控制方法，其中，当所述指定事件包含多个硬件事件时，所述检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数，包括：
    将各所述硬件事件的发生次数与各所述硬件事件的预设权重的乘积的累加和作为所述指定事件的发生次数。
  6. 根据权利要求1至权利要求4中任一项所述的内存带宽的控制方法，其中，所述检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数，之前包括：
    获取所述CPU核的内存带宽配额；
    根据预设的控制算法和所述内存带宽配额生成所述控制条件。
  7. 根据权利要求1至权利要求4中任一项所述的内存带宽的控制方法，其中，所述控制策略，包括：执行预设数量的空操作指令；或，在预设时间内阻塞或切换所述CPU核的进行内存相关访问操作的任务；或，当所述多核系统中的其他CPU核存在空闲内存带宽时，从所述其他CPU核中获取所述空闲内存带宽供所述CPU核调用。
  8. 根据权利要求1至权利要求4中任一项所述的内存带宽的控制方法，其中，所述检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数，包括：
    根据预设的检测周期对所述CPU核的所述指定事件的发生次数进行检测。
  9. 根据权利要求8所述的内存带宽的控制方法，其中，所述方法还包括：当所述检测周期内的所述指定事件的发生次数均未满足所述控制条件时，则根据预设算法调整下一个所述 检测周期内的所述控制条件。
  10. 一种内存带宽的控制装置，其中，应用在包含各中央处理器CPU核的多核系统对应的操作系统上，所述装置包括：
    控制检测模块，用于检测所述CPU核的预设的评估所述CPU核内存带宽占用情况的指定事件的发生次数；
    任务生成模块，用于当所述指定事件的发生次数满足预设控制条件时，根据预设内存带宽控制函数和预设控制策略获取内存带宽控制任务流；
    内存带宽控制模块，用于运行所述内存带宽控制任务流，完成对所述CPU核的内存带宽控制。
  11. 一种电子设备，其中，包括：
    至少一个处理器；以及，
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如权利要求1至9中任一项所述的内存带宽的控制方法。
  12. 一种计算机可读存储介质，存储有计算机程序，其中，所述计算机程序被处理器执行时实现权利要求1至9中任一项所述的内存带宽的控制方法。
PCT/CN2022/141128 2021-12-30 2022-12-22 内存带宽的控制方法、装置、电子设备和存储介质 WO2023125248A1 (zh)

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