WO2023124940A1 - 一种直接存储器访问的嵌入式控制电路、芯片和电子设备 - Google Patents

一种直接存储器访问的嵌入式控制电路、芯片和电子设备 Download PDF

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Publication number
WO2023124940A1
WO2023124940A1 PCT/CN2022/138404 CN2022138404W WO2023124940A1 WO 2023124940 A1 WO2023124940 A1 WO 2023124940A1 CN 2022138404 W CN2022138404 W CN 2022138404W WO 2023124940 A1 WO2023124940 A1 WO 2023124940A1
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Prior art keywords
bus
processor
circuit
module
peripheral
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PCT/CN2022/138404
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English (en)
French (fr)
Inventor
王世好
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合肥市芯海电子科技有限公司
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Publication of WO2023124940A1 publication Critical patent/WO2023124940A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

Definitions

  • the present disclosure relates to the technical field of electronic circuits, in particular to an embedded control circuit with direct memory access, a chip and an electronic device.
  • an embedded controller In an electronic device such as a personal computer, an embedded controller (Embedded Controller, EC for short) manages at least some peripheral devices (peripherals for short).
  • the processor of the electronic device referred to as the host processor for short
  • the processor of the embedded controller need to access these peripherals.
  • no effective solution has been proposed so far for how the host processor and the processor of the embedded controller can access the peripherals more efficiently, conveniently and reliably.
  • the embodiments of the present disclosure provide an embedded control circuit, chip and electronic device for direct memory access, so as to realize peripheral device access.
  • an embedded control circuit including: a bus interface circuit for communicating with a host processor; a processor; one or more peripheral modules; a circuit system connected to the bus interface circuit; The first bus is connected between one or more peripheral modules and the circuit system; the second bus is connected between one or more peripheral modules and the processor; wherein: the circuit system is configured to: through the bus interface circuit Communicating with the host processor, accessing one or more peripheral modules through the first bus based on commands from the host processor; the processor is configured to access the one or more peripheral modules through the second bus.
  • the embedded control circuit further includes: a third bus connected between the processor and the circuit system.
  • the processor is configured to send interrupt information of one or more peripheral modules to the circuit system through the third bus; the circuit system is configured to send the interrupt information to the host processor through the bus interface circuit.
  • the processor is configured to configure the permission of the circuitry to access the one or more peripheral modules through the third bus.
  • the circuitry is configured to access one or more peripheral modules based on preconfigured permissions.
  • the embedded control circuit further includes: an interrupt signal line connected between the processor and the circuit system.
  • the circuitry is configured to transmit the interrupt signal to the processor via the interrupt signal line.
  • the circuitry is configured to transmit an interrupt signal to the processor via the interrupt signal line if a register of the peripheral module accessed by the host processor is configured to be restricted from access.
  • the circuit system is configured to: receive the write command of the host processor through the bus interface circuit, and write data to the register of the peripheral module corresponding to the write command through the first bus based on the write command; and/or through The bus interface circuit receives the read command from the host processor, and reads data from the register of the peripheral module corresponding to the read command through the first bus based on the read command.
  • the circuit system includes: a receiving circuit, configured to receive the bus command sent by the bus interface circuit; a parsing circuit, configured to parse the received bus command to obtain the target address; a first controller, configured to The registers of the peripheral module corresponding to the target address are accessed.
  • the parsing circuit when the bus command is a write command, the parsing circuit also obtains target data; wherein, the first controller is configured to: write the target data to the register of the peripheral module corresponding to the target address.
  • the circuit system further includes: a generating circuit configured to generate a bus command; a sending circuit configured to send the generated bus command to the bus interface circuit, so that the generated bus command is received by the host processor.
  • the first controller is further configured to: send the data read from the target address to the generating circuit, so that the generating circuit generates a corresponding bus command, and the sending circuit sends the generated bus command to the bus Interface Circuit.
  • the circuit system further includes: a second controller configured to receive information sent by the processor through the third bus.
  • the second controller is further configured to receive the interrupt information sent by the processor through the third bus, and send the interrupt information to the generating circuit, so that the generating circuit generates a corresponding bus command, and the sending circuit sends the interrupt information to The generated bus commands are sent to the bus interface circuit.
  • the circuit system further includes a security control module connected to the first controller and the second controller; wherein the second controller is further configured to receive permission information sent by the processor through the third bus, Write the authority information into the security control module; the first controller is also configured to determine the authority to access the target address based on the authority information in the security control module.
  • the bus interface circuit includes: a bus interface or a plurality of bus interfaces.
  • a peripheral access method is provided, which is applied to an embedded control circuit, and the embedded control circuit includes: a bus interface circuit, a processor, one or more peripheral modules, and a circuit system, wherein,
  • the method for accessing peripherals includes: the circuit system communicates with a host processor through a bus interface circuit, and accesses one or more peripheral modules through a first bus based on commands from the host processor, wherein the first bus is connected to one or more peripheral modules. between the module and the circuit system; the processor accesses one or more peripheral modules through the second bus, wherein the second bus is connected between the one or more peripheral modules and the processor.
  • a chip including the embedded control circuit of the embodiment of the present disclosure.
  • an electronic device including: the embedded control circuit of the embodiment of the present disclosure or the chip of the embodiment of the present disclosure.
  • the embedded control circuit integrates peripheral modules, and a circuit system is set in the embedded control circuit.
  • the circuit system can communicate with the host processor through the bus interface circuit, based on the host processing
  • the command of the processor accesses one or more peripheral modules through the first bus; the processor can access one or more peripheral modules through the second bus.
  • the peripheral module is integrated in the embedded control circuit, the address of the peripheral module can be opened to the host processor, and the host processor uses the address of the peripheral module to access the peripheral module without modifying the bus interface circuit, which is convenient for embedded control Integrated peripheral modules in the circuit.
  • FIG. 1 shows a schematic block diagram of an embedded control circuit based on a shared interface in an exemplary embodiment of the present disclosure
  • FIG. 2 shows a schematic block diagram of a peripheral module 130 of an exemplary embodiment of the present disclosure
  • FIG. 3 shows a schematic block diagram of an embedded control circuit based on an eSPI bus and a shared interface according to an exemplary embodiment of the present disclosure
  • FIG. 4 shows a schematic block diagram of an embedded control circuit for direct memory access in an exemplary embodiment of the present disclosure
  • FIG. 5 shows a flowchart of a direct memory access peripheral access method according to an exemplary embodiment of the present disclosure
  • FIG. 6 shows a schematic block diagram of a circuit system 440 of an exemplary embodiment of the present disclosure
  • FIG. 7 shows a schematic block diagram of an embedded control circuit using an eSPI bus and direct memory access according to an exemplary embodiment of the present disclosure
  • FIG. 8 shows a schematic block diagram of a circuit system 740 of an exemplary embodiment of the present disclosure
  • FIG. 9 shows a schematic block diagram of an embedded control circuit based on a direct memory access and sharing interface according to an exemplary embodiment of the present disclosure
  • FIG. 10 shows a flowchart of a method for accessing peripherals based on direct memory access and shared interfaces according to an exemplary embodiment of the present disclosure
  • FIG. 11 shows a schematic block diagram of an embedded control circuit based on a direct memory access and sharing interface using an eSPI bus according to an exemplary embodiment of the present disclosure
  • FIG. 12 shows a schematic block diagram of an embedded control circuit of a dual-bus interface in an exemplary embodiment of the present disclosure
  • Fig. 13 shows a schematic block diagram of an embedded control circuit of an LPC-eSPI dual-bus interface according to an exemplary embodiment of the present disclosure.
  • the term “comprise” and its variations are open-ended, ie “including but not limited to”.
  • the term “based on” is “based at least in part on”.
  • the term “one embodiment” means “at least one embodiment”; the term “another embodiment” means “at least one further embodiment”; the term “some embodiments” means “at least some embodiments.”
  • Relevant definitions of other terms will be given in the description below. It should be noted that concepts such as “first” and “second” mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the sequence of functions performed by these devices, modules or units or interdependence.
  • the embodiment of the present disclosure relates to the improvement of the technical scheme of integrating the peripheral module in the embedded controller and accessing the peripheral module by the host processor and the processor of the embedded controller.
  • Some embodiments of the present disclosure relate to an embedded control circuit based on a shared interface, where a peripheral module is integrated in the embedded control circuit, the peripheral module includes two interfaces, and the host processor accesses the bus interface circuit and one interface of the peripheral module The peripheral module, the processor of the embedded control circuit accesses the peripheral module through another interface.
  • at least one peripheral module includes an interface unit for connecting peripherals.
  • at least one peripheral module corresponds to an interface unit for connecting peripherals, which is connected to the processor independently of the peripheral modules.
  • Some embodiments of the present disclosure relate to an embedded control circuit for direct memory access, where peripheral modules are integrated in the embedded control circuit, a circuit system is set in the embedded control circuit, and the host processor accesses the peripheral device through the bus interface circuit and the circuit system module, the processor of the embedded control circuit can access the peripheral module through the line between it and the peripheral module.
  • the peripheral module when the peripheral module is integrated in the embedded control circuit, the address of the peripheral module is opened to the host processor, and the host processor uses the address of the peripheral module to access the peripheral module without modifying the bus interface circuit. It is convenient to integrate peripheral modules in embedded control circuits.
  • Some embodiments of the present disclosure relate to an embedded control circuit with shared interface and direct memory access, and peripheral modules are integrated in the embedded control circuit.
  • Some peripheral modules are peripheral modules that include two interfaces.
  • the host processor can access the peripheral modules through one interface of these peripheral modules through the bus interface circuit.
  • the processor of the embedded control circuit can access the peripheral modules through the other interface of these peripheral modules.
  • Other peripheral modules are peripheral modules with direct memory access through circuitry, the host processor accesses the peripheral modules through the bus interface circuit and the circuitry, and the processor of the embedded control circuit can access these peripheral modules.
  • the bus interface circuit may include interface circuits of at least two bus protocols, and the bus interface selection circuit selects one of the interface circuits of at least two bus protocols to communicate with the host. Processor communication.
  • first bus only distinguish the transmission lines between different devices in some embodiments, which Different buses may be used, or at least part of the lines and interfaces may be shared through a bus matrix or the like. This disclosure does not limit it.
  • the embodiment of the present disclosure provides an embedded control circuit based on a shared interface.
  • FIG. 1 shows a schematic block diagram of an embedded control circuit based on a shared interface in an exemplary embodiment of the present disclosure.
  • the embedded control circuit 100 includes: a bus interface circuit for communicating with a host processor 110 , a processor 120 , a peripheral module 130 , a first bus 140 and a second bus 150 .
  • a plurality of peripheral modules 130 are shown in FIG. 1, labeled as peripheral modules 130-1 through 130-n.
  • the first bus 140 is connected between the first interface of the peripheral module 130 and the bus interface circuit 110
  • the second bus 150 is connected between the second interface of each peripheral module 130 and the processor 120 .
  • the bus interface circuit 110 accesses the peripheral module 130 through the first bus 140 .
  • the processor 120 accesses the peripheral module 130 through the second bus 150 . Since the host processor and the processor 120 use different buses, the access to the peripheral modules does not interfere with each other, which can increase the bus bandwidth and improve the access speed. For example, the host processor can access the peripheral module 130 - 1 through the first bus 140 , while the processor 120 can access the peripheral module 130 - n through the second bus 150 .
  • bus interface circuit 110 includes a bus interface or a plurality of bus interfaces.
  • the bus interface circuit 110 is operable to use one of the plurality of bus interfaces for communication. This implementation does not limit this.
  • the bus interface circuit 110 can communicate with the host processor according to the bus protocol.
  • the eSPI bus can be used between the embedded control circuit 100 and the host processor, the embedded control circuit 100 is a slave device (eSPI slave) in the eSPI bus, and the host processor is used as a master device (eSPI slave) in the eSPI bus.
  • the bus interface 110 can be an eSPI slave module. This embodiment does not limit it.
  • the first bus 140 may include any bus compatible with the bus interface circuit 110, and examples of the first bus 140 may include a local bus (local bus), an advanced extensible interface (Advanced eXtensible Interface, referred to as AXI) Bus, Advanced Peripheral Bus (Advanced Peripheral Bus, APB for short), etc., are not limited in this implementation.
  • AXI Advanced extensible interface
  • APB Advanced Peripheral Bus
  • the second bus 150 may include any bus compatible with the processor 120, and examples of the second bus 150 may include a local bus (local bus), an advanced extensible interface (Advanced eXtensible Interface, referred to as AXI) bus , Advanced Peripheral Bus (Advanced Peripheral Bus, APB for short), etc., which are not limited in this implementation.
  • AXI Advanced extensible interface
  • APB Advanced Peripheral Bus
  • the I/O interface corresponding to each peripheral module 130 is defined on the bus interface circuit 110 .
  • an interface may also be referred to as a port, and is collectively referred to as an interface in the description of the present disclosure.
  • the peripheral module 130 may include some circuit modules of various peripheral devices. Examples of peripheral devices include mouse, keyboard, USB, PD/TYPE-C, breathing light, ambient light and so on. This implementation does not limit this.
  • the peripheral module 130 may include an interface unit for connecting peripherals.
  • the peripheral module 130 comprising an interface unit for connecting peripherals acquires data from the peripherals connected to the interface unit, and/or provides data to the peripherals connected to it, and the peripheral module 130 communicates with the host Communication between processors may not go through the processor 120 .
  • the processor 120 can read and/or write to the peripheral module 130 through the second bus 150 , for example, configured as parameters of the peripheral module 130 .
  • the host processor can read and/or write the peripheral module 130 through the bus interface circuit 110 and the first bus 140, for example, write data to the peripheral module 130 to be sent by a peripheral connected thereto, or read data from the peripheral module 130 130 reads data from its connected peripherals, or configures parameters of the peripheral module 130, etc.
  • the peripheral module 130 including an interface unit for connecting peripherals include a serial interface module (such as a UART serial port, etc.), and the serial interface module includes an interface unit that is used to connect a serial communication physical interface (such as a UART Connector).
  • the serial interface module and serial communication physical interface can adopt serial communication interface standards such as RS-232C, RS-422, RS-423 and RS-485.
  • the interface unit corresponding to the peripheral module 130 for connecting peripherals is connected to the processor 120 independently of the peripheral module 130 .
  • the processor 120 may provide data from the peripheral module 130 to the interface unit corresponding to the peripheral module 130, or provide data from the interface unit to the peripheral module 130 corresponding to the interface unit.
  • the host processor can provide data to the peripheral module 130, and the data provided by the host processor to the peripheral module 130 can be provided to the corresponding interface unit of the peripheral module 130 via the processor 120; the processor 120 can provide the data of the interface unit to The peripheral module 130 corresponding to the interface unit, the host processor can obtain the data from the peripheral module 130 .
  • the processor 120 can be connected to an interface unit independent of the peripheral module 130 through a fast bus or the like.
  • An example of an interface unit for connecting peripherals connected to the processor 120 independently of the peripherals module 130 includes a keyboard interface unit.
  • the keyboard controller located on the keyboard detects the pressing and release of the key, and sends the keyboard code to the keyboard interface unit, and the processor 120 detects that the keyboard interface unit receives the keyboard code, and the processor 120 provides the keyboard code to the keyboard
  • part of the peripheral module 130 includes an interface unit for connecting to a peripheral, the part of the peripheral module 130 obtains data from the peripheral connected to the interface unit, and/or provides data to the connected peripheral, Communications between the peripheral module 130 and the host processor may not go through the processor 120 .
  • the interface units for connecting peripherals corresponding to some peripheral modules 130 are connected to the processor 120 independently of the peripheral modules 130 .
  • the processor 120 may provide data from the peripheral module 130 to the interface unit corresponding to the peripheral module 130, or provide data from the interface unit to the peripheral module 130 corresponding to the interface unit.
  • the host processor can provide data to the peripheral module 130, and the data provided by the host processor to the peripheral module 130 can be provided to the corresponding interface unit of the peripheral module 130 via the processor 120; the processor 120 can provide the data of the interface unit to The peripheral module 130 corresponding to the interface unit, the host processor can obtain the data from the peripheral module 130 .
  • the peripheral module 130 includes a keyboard module and a serial interface module, wherein the interface unit (called the keyboard interface unit) of the keyboard module is independent from the keyboard module, the keyboard interface unit is connected to the processor 120, and the serial interface module Including the interface unit used to connect the serial communication physical interface.
  • the interface unit called the keyboard interface unit
  • the serial interface module receives the data sent by the host processor through the bus interface circuit 110, and sends the data through the serial communication physical interface; receives data through the serial communication physical interface, and the data received by the serial interface module serial communication physical interface
  • the data is sent to the host processor through the bus interface circuit 110, and the data transmission is not processed by the processor 120.
  • the processor 120 can configure the serial interface module through the second bus 150 , or the host processor can configure the serial interface module through the bus interface circuit 110 and the first bus 140 .
  • the processor 120 may provide data from the keyboard module to the keyboard interface unit, or provide data from the keyboard interface unit to the keyboard module.
  • the host processor can provide data to the keyboard module, and the data provided by the host processor to the keyboard module can be provided to the keyboard interface unit through the processor 120; the processor 120 can provide the data of the keyboard interface unit to the keyboard module 130, and the host processor can provide This data is obtained from the keyboard module 130 .
  • the processor 120 obtains the keyboard code from the keyboard interface unit, provides the keyboard code to the keyboard module, and the host processor reads the keyboard code from the keyboard module through the bus interface circuit 110 .
  • the bus interface circuit 110 is configured to receive a write command from the host processor, and write data to the register of the peripheral module 130 corresponding to the write command through the first bus 140 . In some embodiments, the bus interface circuit 110 is configured to receive a read command from the host processor, and read data from the register of the peripheral module 130 corresponding to the read command through the first bus 140 .
  • the processor 120 is configured to read data from registers of the peripheral module 130 through the second bus 150 . In some embodiments, the processor 120 is configured to write data to the registers of the peripheral module 130 through the second bus 150 .
  • the peripheral module 130 communicates with the peripheral through the processor 120, and the processor 120 is used to receive the input of the peripheral, and send the corresponding peripheral module 130 to the corresponding peripheral through the second bus 150 based on the received input. Register write data.
  • the peripheral module 130 may include one or more registers 131 that are controlled by the processor 120 (via the second bus 150) and the host processor (via the bus interface circuit 110 and first bus 140) for reading and/or writing.
  • the processor 120 reads and/or writes one or more registers 131 of the peripheral module 130 through the second interface of the peripheral module 130 .
  • the bus interface circuit 110 reads and/or writes one or more registers 131 of the peripheral module 130 through the first interface of the peripheral module 130 .
  • the peripheral module 130 can set one or more registers 131 based on its functions, and examples of the registers 131 of the peripheral module 130 can include: configuration registers, status registers, control registers, read data registers, or write data registers.
  • the peripheral module 130 may include one or more functional circuits 132 , and the one or more functional circuits together with the peripheral implement the functions of the peripheral.
  • the peripheral module 130 include a serial interface module, the serial interface module is used to connect to a serial communication physical interface, the functional circuit of the serial interface module includes a level conversion circuit, and the level conversion circuit is based on the serial communication interface standard. Flat conversion.
  • Another example of the peripheral module 130 includes a light-emitting unit control module, which is used to connect one or more light-emitting units (such as light-emitting diodes).
  • the functional circuit of the light-emitting unit control module may include a controller, and the controller controls one or more light-emitting units.
  • the plurality of light emitting units emit light.
  • the peripheral module 130 includes: an arbitration logic circuit 133 connected to the first bus 140 and the second bus 150 .
  • the arbitration logic circuit 133 is used to arbitrate access requests from the processor 120 and the host processor (via the bus interface circuit 110).
  • the arbitration logic circuit 133 is configured to connect to the arbitration control register 134 to provide the arbitration logic circuit 133 with an arbitration policy.
  • the processor 120 is also connected to the arbitration control register 134 to write an arbitration policy into the arbitration control register 134 .
  • the arbitration control register 134 is located outside the peripheral module 130, which is not limited in this embodiment.
  • the arbitration logic circuit 133 disconnects the second interface of the peripheral module 130 from the second bus 150 when the peripheral module 130 is accessed by the host processor. As an implementation manner, the arbitration logic circuit 133 disconnects the first interface of the peripheral module 130 from the first bus 140 when the peripheral module 130 is accessed by the processor 120 . Arbitration can be avoided every time the host processor and the processor 120 access, and the efficiency problem and potential function problem caused by the complex arbitration logic of the single bus can be avoided.
  • the arbitration logic circuit 133 connects the second interface of the peripheral module to the second bus 150 when the peripheral module 130 is released by the host processor. As an implementation manner, the arbitration logic circuit 133 connects the first interface of the peripheral module 130 to the second bus 150 when the peripheral module 130 is released by the processor 120 .
  • the peripheral module 130 communicates at least part of the information with the processor 120 and/or the host processor (via the bus interface circuit 110 ) through an interrupt.
  • the peripheral module 130 further includes: a first interrupt unit 135 .
  • the first interrupt unit 135 can be used to send write-related interrupt information. This embodiment does not limit it.
  • the first interrupt unit 135 is configured to: send first interrupt information to the bus interface circuit 110 after data is written into the register 131 of the peripheral module 130 by the processor 120 .
  • the bus interface circuit 110 transmits the first interrupt information to the host processor, and can read and/or write the register 131 of the peripheral module 130 in response to a command of the host processor.
  • the second interrupt information is sent to the processor 120 .
  • the processor 120 may read and/or write the register 131 of the peripheral module 130 in response to the second interrupt information.
  • the first interrupt unit 135 is configured to: send first interrupt information to the bus interface circuit 110 after the register 131 of the peripheral module 130 is written with data by a peripheral connected thereto.
  • the bus interface circuit 110 transmits the first interrupt information to the host processor, and can read and/or write the register 131 of the peripheral module 130 in response to a command from the host processor.
  • the peripheral module 130 and its connected peripherals send data.
  • At least one peripheral module 130 further includes: a second interrupt unit 136 .
  • the first interrupt unit 135 can be used to send read-related interrupt information. This embodiment does not limit it.
  • the second interrupt unit 136 is configured to send third interrupt information to the host processor after the data written by the host processor in the register 131 of the peripheral module 130 is read by the processor 120 . And/or, after the data written by the processor 120 in the register 131 of the peripheral module 130 is read by the host processor, the fourth interrupt information is sent to the processor 120 .
  • the processor 120 is used to: detect whether the register of the peripheral module 130 is written with data by the host processor; The second bus 150 reads data from the registers of the corresponding peripheral modules 130 . In some cases, the processor 120 may send the read data to a peripheral interface unit connected thereto and corresponding to the peripheral module.
  • the bus interface circuit 110 is further configured to set the first flag bit of the register corresponding to the peripheral module 130 as read after reading data from the register of the peripheral module 130 .
  • the processor 120 is further configured to query the first flag bit of the register of the peripheral module 130, and determine whether the data in the register of the corresponding peripheral module 130 is read by the host processor based on the first flag bit .
  • the embedded control circuit based on the shared structure of the exemplary embodiment of the present disclosure is described below, and the communication between the host processor and the embedded control circuit is performed through the eSPI bus.
  • FIG. 3 shows a schematic block diagram of an embedded control circuit based on an eSPI bus and a shared interface in an exemplary embodiment of the present disclosure.
  • the embedded control circuit 300 includes: eSPI slave module 310 , processor 320 , peripheral module 330 , first bus 340 and second bus 350 .
  • FIG. 3 shows a plurality of peripheral modules 330, including a keyboard module 330-1, a mouse module 330-2, a serial port module 330-3, and other peripherals 330-n.
  • the first bus 340 is connected between the first interface of the keyboard module 330-1, the mouse module 330-2, the serial port module 330-3, and other peripherals 330-n and the eSPI slave module 310, and the second bus 350 is connected Between the second interface of the peripheral module 330 and the processor 320 .
  • the eSPI slave module 310 accesses the peripheral module 330 through the first bus 340 .
  • the processor 320 accesses the peripheral module 330 through the second bus 350 .
  • the embedded control circuit 300 passes through the eSPI interface between the host processor and the embedded control circuit 300 and the IO interface that is located on the embedded control circuit 300 and can be accessed by the host processor (this interface is defined on the eSPI slave module, which is address accessible by the host processor) to manage peripherals.
  • the keyboard module 330-1, the mouse module 330-2, the serial port module 330-3, and other peripherals 330-n have two interfaces, which are respectively connected to the first bus 340 (such as the local bus 1) and on the second bus 350 (eg local bus 2).
  • the read/write operations of the first bus 340 and the second bus 350 to the register are arbitrated by the access arbitration logic circuit, the arbitration strategy (selection priority) is selected by the arbitration control register, and the arbitration control is connected to an arbitration control register outside the module , the arbitration control register is configured by the processor 320 .
  • a bus matrix 352 is used for connection.
  • the processor 320 is connected to the bus matrix 352, and the second bus 350 (through the bridge 351) is connected to the bus matrix 352, and the second bus 350 is connected to the second interface of the peripheral module 330, and then the processor 320 communicates with the second bus matrix 352 through the bus matrix 352.
  • Bus 352 accesses peripheral modules 330 .
  • the peripheral module 330 corresponds to and is independent of the peripheral module 330 and the interface unit (such as a keyboard interface unit) connected to the processor 320 is connected to the bus matrix 352 through a bus such as a fast bus, and then the processor 320 and the interface unit are connected to the bus matrix 352 through a bus.
  • the matrix 352 communicates with an associated bus.
  • the register of the serial port module 330-3 has two interfaces, one interface is connected to the host processor through the first bus 340, so that the host processor can configure or operate the serial port through this interface, and one interface is connected through the second bus 340 350 is connected to the processor 320, so that the processor 320 of the embedded control circuit 300 can configure and access the serial port through this interface.
  • the access arbitration mechanism gives the host processor or the processor 320 a higher access priority according to the configuration.
  • the serial port module 330 - 3 acquires data from and/or provides data to peripheral devices connected to its interface unit, and the communication between the serial port module 330 - 3 and the host processor may not go through the processor 120 .
  • the host processor reads and/or writes to the serial port module 330-3, for example, writes data to the serial port module 330-3 to be sent by a peripheral device connected to it, or reads data from the serial port module 330-3 from its connection Peripheral data, or configure the parameters of the serial port module 330-3, etc.
  • the keyboard interface unit corresponding to the keyboard module 330 - 1 is independent of the keyboard module 330 - 1 and connected to the processor 320 .
  • the processor 320 obtains the keyboard code corresponding to the action of the keyboard key through the keyboard interface unit, and writes the keyboard code into the keyboard module 330 through the bus matrix 352, the bridge 351, and the second bus 350 -1 in the register.
  • the keyboard module 330-1 generates an interrupt from the module 310 through the eSPI and reports it to the host processor.
  • the host processor receives the interrupt, initiates a read operation, reads the keyboard code value in the register of the keyboard module 330-1, sets the code value has been read flag, and clears the corresponding register.
  • the keyboard module 330-1 generates an interrupt, notifying the processor 320 that the host processor has read the keyboard code value. If there is no interrupt, the processor 320 can query the Status flag of the keyboard module 330-1 to determine whether the keyboard code value has been read by the host processor.
  • An embodiment of the present disclosure provides an embedded control circuit for direct memory access.
  • FIG. 4 shows a schematic block diagram of an embedded control circuit for direct memory access in an exemplary embodiment of the present disclosure.
  • the embedded control circuit 400 includes: a bus interface circuit 410 for communicating with a host processor, Processor 420 , one or more peripheral modules 430 , circuitry 440 , first bus 450 and second bus 460 .
  • the embedded control circuit may include one or more peripheral modules 430 , for example, peripheral modules 430 - 1 to 430 - n are shown in FIG. 4 .
  • circuitry 440 is connected to bus interface circuit 410 .
  • the first bus 450 is connected between the peripheral module 430 and the circuit system 440 ;
  • the second bus 460 is connected between the peripheral module 430 and the processor 420 .
  • the circuit system 440 communicates with the host processor through the bus interface circuit 410 , and accesses the peripheral module 430 through the first bus 450 based on the commands of the host processor.
  • the processor 420 is configured to access the peripheral module 430 through the second bus 460 .
  • the I/O interface of the peripheral module 430 may not be defined in the bus interface circuit 410, and the circuit system 440 is configured to access the peripheral module 430 through the first bus 450 based on the command of the host processor. Integrating (eg adding) the peripheral module 430 in the circuit may not modify the bus interface circuit.
  • the circuit system 440 may use a direct memory access (DMA) command to access the peripheral module 430 .
  • DMA direct memory access
  • bus interface circuit 410 includes a bus interface or a plurality of bus interfaces.
  • the bus interface circuit 410 is operable to use one of the plurality of bus interfaces for communication. This implementation does not limit this.
  • the bus interface circuit 410 can communicate with the host processor according to the bus protocol.
  • the eSPI bus can be used between the embedded control circuit 400 and the host processor, the embedded control circuit 400 is a slave device (eSPI slave) in the eSPI bus, and the host processor is used as a master device (eSPI slave) in the eSPI bus. master), the bus interface circuit 410 can be an eSPI slave module. This embodiment does not limit it.
  • the first bus 450 may include any bus compatible with the peripheral module 430 and the circuit system 440.
  • Examples of the first bus 450 may include a local bus, an AXI bus, APB, AHB, etc., which are not made in this implementation. limited.
  • the circuit system 440 may serve as a master device (master) of the first bus 450
  • the peripheral module 430 may serve as a slave device (slave) of the first bus 450 .
  • the peripheral module 430 can respond to various bus commands sent by the circuit system 440 .
  • the second bus 460 may include any bus compatible with the peripheral module 430 and the processor 420, and examples of the second bus 460 may include a local bus, an AXI bus, APB, AHB, etc., which are not made in this implementation. limited.
  • the processor 420 may serve as a master of the second bus 460
  • the peripheral module 430 may serve as a slave of the second bus 460 .
  • the peripheral module 430 can respond to various bus commands sent by the processor 420 .
  • the embedded control circuit 400 can use a bus matrix, through which the circuit system 440, the processor 420 and the peripheral module 430 can be accessed in parallel to improve access efficiency and reduce power consumption.
  • the circuit system 440 can communicate with the host processor through the bus interface circuit 410, access the peripheral module 430 through the first bus 450 based on the command of the host processor, and the processor 420 can access the peripheral module 430 through the second bus 460 Set module 430 .
  • FIG. 5 shows a flow chart of a peripheral device access method for direct memory access according to an exemplary embodiment of the present disclosure.
  • the peripheral device access method includes step S501 and step S502.
  • step S501 the circuit system 440 communicates with the host processor through the bus interface circuit 410 , and accesses the peripheral module 430 through the first bus 450 based on a command from the host processor.
  • the processor 420 accesses the peripheral module 430 through the second bus 460 .
  • step S502 the processor 420 writes data to the register of the peripheral module 430 through the second bus 460 . In some embodiments, in step S502 , the processor 420 reads data from the register of the peripheral module 430 through the second bus 460 .
  • the circuit system 440 is configured to: receive a write command from the host processor through the bus interface circuit 410 , and write data to the register of the peripheral module 430 corresponding to the write command through the first bus 450 based on the write command.
  • the circuit system 440 receives the write command of the host processor through the bus interface circuit 410, and writes data to the register of the peripheral module 430 corresponding to the write command through the first bus 450 based on the write command. .
  • the circuit system 440 is configured to: receive a read command from the host processor through the bus interface circuit 410 , and read data from the register of the peripheral module 430 corresponding to the read command through the first bus 450 based on the read command.
  • the circuit system 440 receives the read command of the host processor through the bus interface circuit 410, and reads data from the register of the peripheral module 430 corresponding to the read command through the first bus 450 based on the read command. .
  • the embedded control circuit 400 further includes: a third bus 470 connected between the processor 420 and the circuit system 440 .
  • Information can be transmitted between the circuit system 440 and the processor 420 through the third bus 470. Examples of information may include configuration of the circuit system 440 by the processor 420, interrupt information of the peripheral module 430 sent by the processor 420 to the host processor, etc. , which is not limited in this implementation.
  • the processor 420 may serve as a master device (master) of the third bus 470
  • the circuit system 440 may serve as a slave device (slave) of the third bus 470 .
  • the circuit system 440 can respond to various bus commands sent by the processor 420 .
  • the embedded control circuit 400 further includes: an interrupt signal line 480 connected between the processor 420 and the circuit system 440 .
  • the interrupt signal line 480 may be configured to transmit any interrupt signal between the processor 420 and the circuit system 440 , which is not limited in this embodiment.
  • the circuit system 440 is configured to transmit an interrupt signal to the processor 420 through the interrupt signal line 480 .
  • circuitry 440 is configured to access peripheral module 430 based on preconfigured permissions.
  • each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment.
  • the processor 420 configures the authority of the circuit system 440 to access the peripheral module 430 through the third bus 470 .
  • the circuitry 440 is configured to access the peripheral module 430 based on the permission information configured by the processor 420 .
  • the circuitry 440 is configured to access the peripheral module 430 based on pre-configured permissions, and when the registers of the peripheral module 430 accessed by the host processor are configured to prohibit access, the interrupt signal line 480 An interrupt signal is transmitted to the processor 420 to notify the processor 420 that the host processor requests access to a prohibited register.
  • the bus interface circuit 410 receives write commands from the host processor and sends the write commands to the circuitry 440 .
  • the circuit system 440 receives the write command, and parses the write command to obtain the target address and the data to be written.
  • the circuit system 440 judges whether the target address is an address that allows writing. If the target address is an address that allows writing, the circuit system 440 writes the above data into the register of the peripheral module 430 corresponding to the target address through the first bus 450 .
  • circuitry 440 transmits an interrupt signal to processor 420 via interrupt signal line 480 to notify processor 420 that the host processor requests access to the write-prohibited register.
  • the bus interface circuit 410 receives a read command from the host processor and sends the read command to the circuitry 440 .
  • the circuit system 440 receives the read command and parses the read command to obtain the target address.
  • the circuit system 440 determines whether the target address is an address that is allowed to be read. If the target address is an address that is allowed to be read, the circuit system 440 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450 . After the read data, the circuit system 440 generates a bus command corresponding to the read command, and sends the bus command to the bus interface circuit 410 .
  • the bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data.
  • circuitry 440 transmits an interrupt signal to processor 420 via interrupt signal line 480 to notify processor 420 that the host processor requests access to the read-prohibited register.
  • the processor 420 sends the interrupt information of the peripheral module 430 to the circuit system 440 through the third bus 470 . Further, the circuit system 440 sends the interrupt information to the host processor through the bus interface circuit 410 .
  • the processor 420 sends the interrupt information of the peripheral module 430 to the host processor is described as follows.
  • the processor 420 detects interrupt information of the peripheral module 430 .
  • the processor 420 sends the detected interruption information to the circuit system 440 through the third bus 470 .
  • the circuit system 440 generates a bus command corresponding to the interrupt information, and sends the generated bus command to the bus interface circuit 410 .
  • the bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the interrupt information.
  • the host processor responds to the embedded control circuit based on the interrupt information.
  • the host processor initiates a process of writing data to the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process of reading data from the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information.
  • FIG. 6 shows a schematic block diagram of a circuit system 440 of an exemplary embodiment of the present disclosure.
  • the circuit system 440 includes: a receiving circuit 441 configured to receive a bus command sent by the bus interface circuit 410; an analysis circuit 442, connected to the receiving circuit 441, configured to parse the received bus command to obtain the target address; the first controller 443, connected to the parsing circuit 442, configured to access the register of the peripheral module 430 corresponding to the target address.
  • the parsing circuit 442 parses the bus command according to the bus interface protocol used by the bus interface circuit 410 .
  • the bus command includes a write command
  • the parsing circuit 442 parses the bus command to obtain target data
  • the target address is an address to be written.
  • the first controller 443 is configured to: write target data into the register of the peripheral module 430 corresponding to the target address.
  • the bus interface circuit 410 receives the write command from the host processor, and sends the write command to the receiving circuit 441 .
  • the receiving circuit 441 receives the write command and sends the write command to the parsing circuit 442 .
  • the parsing circuit 442 parses the write command to obtain the target address and the data to be written.
  • the first controller 443 writes the above data into the register of the peripheral module 430 corresponding to the target address through the first bus 450 .
  • the bus command includes a read command
  • the target address obtained by parsing the bus command by the parsing circuit 422 is the address to be read.
  • the circuit system 440 further includes a buffer module 444, which is connected between the receiving circuit 441 and the parsing circuit 442, and is used for buffering the received bus command for the parsing circuit 442 to parse the bus command .
  • a buffer module 444 which is connected between the receiving circuit 441 and the parsing circuit 442, and is used for buffering the received bus command for the parsing circuit 442 to parse the bus command .
  • the bus interface circuit 410 receives the write command from the host processor, and sends the write command to the receiving circuit 441 .
  • the receiving circuit 441 receives the write command, and the receiving circuit 441 buffers the write command into the buffer module 444 .
  • the parsing circuit 442 obtains the write command from the buffer module 444, and the parsing circuit 442 parses the write command to obtain the target address and the data to be written.
  • the first controller 443 writes the above data into the register of the peripheral module 430 corresponding to the target address through the first bus 450 .
  • the circuit system 440 further includes: a generating circuit 445 configured to generate a bus command; a sending circuit 446 connected to the generating circuit 445 and configured to send the generating circuit to the bus interface circuit 410 445 generated bus commands so that the generated bus commands are received by the host processor.
  • the first controller 443 is also configured to send the data read from the target address to the generating circuit 445, so that the generating circuit 445 generates a corresponding bus command, and the sending circuit 446 sends the generated bus command sent to the bus interface circuit 410.
  • the bus interface circuit 410 receives the read command from the host processor and sends the read command to the receiving circuit 441 .
  • the receiving circuit 441 receives the read command and sends the read command to the parsing circuit 442 .
  • the parsing circuit 442 parses the read command to obtain the target address.
  • the first controller 443 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450 .
  • the first controller 443 sends the read data to the generation circuit 445 .
  • the generating circuit 445 generates a bus command corresponding to the read command, and sends the bus command to the sending circuit 446 .
  • the sending circuit 446 sends the bus command to the bus interface circuit 410 .
  • the bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data.
  • the circuit system 440 further includes: a second controller 447 configured to receive information sent by the processor 420 through the third bus 470 .
  • the second controller 447 is further configured to receive the interrupt information sent by the processor 420 through the third bus 470, and send the interrupt information to the generation circuit 445, so that the generation circuit 445 generates a corresponding bus command, And the generated bus command is sent to the bus interface circuit 410 by the sending circuit 446 , so as to send the interrupt information to the host processor through the bus interface circuit 410 .
  • the processor 420 sends the interrupt information of the peripheral module 430 to the host processor is described as follows.
  • the processor 420 detects interrupt information of the peripheral module 430 .
  • the processor 420 sends the detected interrupt information to the generating circuit 445 through the third bus 470 .
  • the generating circuit 445 generates a bus command corresponding to the interrupt information.
  • the transmission circuit 446 transmits the bus command generated by the generation circuit 445 to the bus interface circuit 410 .
  • the bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the interrupt information.
  • the host processor responds to the embedded control circuit based on the interrupt information.
  • the host processor initiates a process of writing data to the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process of reading data from the register of the peripheral module 430 corresponding to the interrupt information based on the interrupt information.
  • the circuit system 440 further includes: a security control module 448 connected to the first controller 443 and the second controller 447 .
  • the security control module 448 is configured to provide permission information.
  • the first controller 443 is further configured to determine the authority to access the target address based on the authority information in the security control module 448 .
  • the second controller 447 is further configured to receive the permission information sent by the processor 420 through the third bus 470 , and write the permission information into the security control module 448 .
  • each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment.
  • the bus interface circuit 410 receives the write command from the host processor, and sends the write command to the receiving circuit 441 .
  • the receiving circuit 441 receives the write command and sends the write command to the parsing circuit 442 .
  • the receiving circuit 441 may cache the write command in the buffer module 444 , and the parsing circuit 442 obtains the write command from the buffer module 444 .
  • the parsing circuit 442 parses the write command to obtain the target address and the data to be written.
  • the first controller 443 judges whether the target address is an address that allows writing. Write the above data.
  • the first controller 443 may access the security control module 448, acquire permission information from the security control module 448, and determine whether the target address is an address that is allowed to be written based on the permission information. In some examples, when the target address is an address prohibited from writing, the first controller 443 transmits an interrupt signal to the processor 420 through the interrupt signal line 480, so that the processor 420 knows that the host processor requests to write to the prohibited address. address to write data.
  • the bus interface circuit 410 receives the read command from the host processor and sends the read command to the receiving circuit 441 .
  • the receiving circuit 441 receives the read command and sends the read command to the parsing circuit 442 , in some examples, the receiving circuit 441 buffers the read command into the buffer module 444 , and the parsing circuit 442 obtains the read command from the buffer module 444 .
  • the parsing circuit 442 parses the read command to obtain the target address.
  • the first controller 443 judges whether the target address is an address that allows reading.
  • the first controller 443 accesses the security control module 448, obtains permission information from the security control module 448, and determines whether the target address is permission based on the permission information. address to read. If the target address is an address that is allowed to be read, the first controller 443 reads data from the register of the peripheral module 430 corresponding to the target address through the first bus 450 . The first controller 443 sends the read data to the generating circuit 445 . The generating circuit 445 generates a bus command corresponding to the read command, and sends the bus command to the sending circuit 446 . The sending circuit 446 sends the bus command to the bus interface circuit 410 .
  • the bus interface circuit 410 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data.
  • the first controller 443 transmits an interrupt signal to the processor 420 through the interrupt signal line 480, so that the processor 420 is informed that the host processor requests to read the read prohibited address. fetched address.
  • the embedded control circuit for direct memory access in the exemplary embodiment of the present disclosure is described below by taking the eSPI bus as an example, and the host processor communicates with the embedded control circuit through the eSPI bus.
  • FIG. 7 shows a schematic block diagram of an embedded control circuit using an eSPI bus and direct memory access according to an exemplary embodiment of the present disclosure.
  • the embedded control circuit 700 includes: eSPI slave module 710 , processor 720 , one or more peripheral modules 730 , circuitry 740 .
  • the embedded control circuit may include one or more peripheral modules 730, for example, peripheral modules 730-1 to 730-n are shown in FIG. 7 .
  • the circuit system 740 is connected to the eSPI slave module 710, and the eSPI slave module 710 communicates with the host processor using the eSPI protocol.
  • the eSPI slave module 710, the processor 720, and the peripheral module 730 are connected through a bus matrix 750.
  • the bus matrix adopts an AHB bus.
  • the bus between the eSPI slave module 710, the processor 720, and the peripheral module 730 may include data lines, control lines and address lines.
  • the circuit system 740 accesses the peripheral module 730 through the bus matrix 750 .
  • the circuit system 740 acts as the master device (master) of the AHB bus
  • the peripheral module 730 acts as the slave device of the AHB bus
  • the peripheral module 730 responds to each of the circuit system 740 A bus command.
  • the processor 720 accesses the peripheral module 730 through the bus matrix 750 .
  • the processor 720 acts as the master device (master) of the AHB bus
  • the peripheral module 730 acts as the slave device (slave) of the AHB bus
  • the peripheral module 730 responds to the processor Various bus commands of 720.
  • the processor 720 accesses the circuit system 740 through the bus matrix 750 .
  • the processor 720 acts as a master device (master) of the AHB bus
  • the circuit system 740 acts as a slave device (slave) of the AHB bus
  • the circuit system 740 responds to each of the processor 720 A bus command.
  • the processor 720 accesses the circuit system 740 through the bus matrix 750 to configure the access authority of the circuit system 740 to the peripheral module 730 .
  • the processor 720 accesses the circuit system 740 through the bus matrix 750 to send interrupt information of the peripheral module 730 to the host processor.
  • an interrupt signal line 760 is connected between the processor 720 and the circuit system 740 .
  • Circuitry 740 is capable of sending an interrupt signal to circuitry 740 via interrupt signal line 760 .
  • FIG. 8 shows a schematic block diagram of a circuit system 740 of an exemplary embodiment of the present disclosure.
  • the circuit system 740 includes: an eSPI command receiving module 741 configured to receive a bus command sent by the eSPI slave module 710;
  • the command buffering module 744 is connected with the eSPI command receiving module 741 for buffering the received eSPI command;
  • the eSPI command parsing module 742 is connected with the eSPI command receiving module 741 and is configured to parse the received eSPI command to obtain the target address;
  • AHB The master interface 743 is connected with the eSPI command analysis module 742 and configured to access the registers of the peripheral module 730 corresponding to the target address.
  • the eSPI command includes a write command, and the eSPI command parsing module 742 parses the eSPI command to obtain target data, and the target address is the address to be written.
  • the AHB master interface 743 is configured to: write target data to the register of the peripheral module 730 corresponding to the target address.
  • the eSPI slave module 710 receives a write command from the host processor, and sends the write command to the eSPI command receiving module 741 .
  • the eSPI command receiving module 741 receives the write command, and writes the write command into the command buffer module 744 .
  • the eSPI command parsing circuit 742 obtains the write command from the command buffer module 744, and parses the target address and the data to be written from the write command.
  • the AHB master interface 743 writes the above data into the register of the peripheral module 730 corresponding to the target address through the bus matrix 750.
  • the circuit system 740 also includes: an eSPI command generating module 745 configured to generate an eSPI command; an eSPI command sending module 746 connected to the eSPI command generating module 745 and configured to send an eSPI command to the eSPI slave module 710 The eSPI command generated by the generating module 745, so that the generated eSPI command is received by the host processor.
  • eSPI commands include read commands.
  • the AHB master interface 743 is also configured to: after reading the data, send the data read from the target address to the eSPI command generation module 745, so that the corresponding eSPI command is generated by the eSPI command generation module 745, and the eSPI command transmission module 746 sends the generated eSPI command to the eSPI slave module 710 .
  • the AHB master interface 743 After the AHB master interface 743 reads data from the target address, the AHB master interface 743 sends the read data to the eSPI command generation module 745.
  • the eSPI command generating module 745 generates an eSPI command corresponding to the read command, and sends the eSPI command to the eSPI command sending module 746 .
  • the eSPI command sending module 746 sends the eSPI command to the eSPI slave module 710 .
  • the eSPI slave module 710 sends the eSPI command to the host processor, so that the host processor receives the eSPI command to obtain the read data.
  • the circuit system 740 further includes: an AHB slave interface 747 configured to receive information sent by the processor 720 through the bus matrix 750 .
  • the AHB slave interface 747 is configured to receive the interrupt information sent by the processor 720 through the bus matrix 750, and send the interrupt information to the eSPI command generating module 745, so that the eSPI command generating module 745 generates a corresponding eSPI command, and the eSPI command sending module 746 sends the generated eSPI command to the eSPI slave module 710 , thereby sending interrupt information to the host processor through the eSPI slave module 710 .
  • the processor 720 sends the interrupt information of the peripheral module 730 to the host processor is described as follows.
  • the processor 720 detects interrupt information of the peripheral module 730 .
  • the processor 720 sends the detected interrupt information to the eSPI command generation module 745 through the bus matrix.
  • the eSPI command generation module 745 generates an eSPI command corresponding to the interrupt information.
  • the eSPI command sending module 746 sends the eSPI command generated by the eSPI command generating module 745 to the eSPI slave module 710 .
  • the eSPI slave module 710 sends the eSPI command to the host processor, so that the host processor receives the eSPI command to obtain interrupt information.
  • the host processor responds to the embedded control circuit based on the interrupt information.
  • the host processor initiates a process of writing data to the register of the peripheral module 730 corresponding to the interrupt information based on the interrupt information.
  • the host processor initiates a process of reading data from the register of the peripheral module 730 corresponding to the interrupt information based on the interrupt information.
  • the circuit system 740 further includes: a security control module 748, connected to the AHB master interface 743 and the AHB slave interface 747.
  • the security control module 748 is configured to provide permission information.
  • the AHB master interface 743 is also configured to determine the authority to access the target address based on the authority information in the security control module 748.
  • the AHB slave interface 747 is also configured to receive the permission information sent by the processor 720 through the bus matrix 750, and write the permission information into the security control module 748.
  • each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment.
  • the eSPI slave module 710 receives a write command from the host processor, and sends the write command to the eSPI command receiving module 741 .
  • the eSPI command receiving module 741 receives the write command, and the write command is cached in the command buffer module 744 .
  • the eSPI command parsing module 742 obtains the write command from the command buffer module 744, and parses the write command to obtain the target address and the data to be written.
  • the AHB master interface 743 can access the security control module 748, obtain permission information from the security control module 448, and determine whether the target address is an address that allows writing based on the permission information.
  • the AHB master interface 743 When the target address is an address that allows writing, the AHB master interface 743 writes the above-mentioned data to the register of the peripheral module 730 corresponding to the target address through the bus matrix 750. In the case that the target address is a write-prohibited address, the AHB master interface 743 transmits an interrupt signal to the processor 720 through the interrupt signal line 760, so that the processor 720 knows that the host processor requests to write data to the write-prohibited address.
  • the eSPI slave module 710 receives a read command from the host processor, and sends the read command to the eSPI command receiving module 741 .
  • the eSPI command receiving module 741 receives the read command, and buffers the read command into the command buffer module 744 .
  • the eSPI command parsing module 742 obtains the read command from the command buffer module 744, and parses the read command to obtain the target address.
  • the AHB master interface 743 accesses the security control module 748, obtains authority information from the security control module 748, and determines whether the target address is an address that is allowed to be read based on the authority information.
  • the AHB master interface 743 reads data from the register of the peripheral module 730 corresponding to the target address through the bus matrix 750.
  • the AHB master interface 743 sends the read data to the eSPI command generation module 745.
  • the eSPI command generating module 745 generates an eSPI command corresponding to the read command, and sends the eSPI command to the eSPI command sending module 746 .
  • the eSPI command sending module 746 sends the eSPI command to the eSPI slave module 710 .
  • the eSPI slave module 710 sends the eSPI command to the host processor, so that the host processor receives the eSPI command to obtain the read data.
  • the AHB master interface 743 transmits an interrupt signal to the processor 720 through the interrupt signal line 760, so that the processor 720 knows that the host processor requests to read the address that is prohibited from being read.
  • the circuit system 740 also includes: an interrupt control 749, connected to the interrupt signal line 760, for responding to the command of the AHB master interface 743 and/or the AHB slave interface 747, through the interrupt signal line 760 to the processing
  • the device 720 transmits an interrupt signal.
  • the processor 720 detects an interrupt of the peripheral module 730 .
  • the processor 720 writes the interrupt information into the shared register of the eSPI slave module 710 through the AHB slave interface 747.
  • Exemplary interrupt information includes interrupt status and interrupt ID.
  • eSPI receives the write information from the module 710, and sends an alarm by pulling down the IO pin or a dedicated Alert signal.
  • the host processor receives the alarm signal and queries the cause of the alarm event through the GET_STATUS command.
  • the eSPI slave module 710 receives the GET_STATUS command, and sends the interrupt information in the shared register to the host processor through the eSPI packet.
  • the host processor determines the cause of the alarm based on the interrupt information, and the host processor initiates a GET_PC or GET_NP command to read data.
  • the eSPI slave module 710 receives the command, the circuit system 740 converts the command into a DMA operation, reads the data back from the register of the corresponding peripheral module 730, and the eSPI slave module 710 uploads the command to the host processor through the eSPI packet.
  • the keyboard scanning module detects and keeps the key code of the pressed button, and initiates an interrupt to the processor 720, and the processor 720 queries the interrupt ID from the keyboard scanning module, the reason for the interruption (or interrupt status) is that after the operator has a button operation, the processor 720 writes the interrupt ID and the interrupt status into the shared register of the eSPI slave module 710 through the AHB slave interface 747, and after the eSPI receives the write information from the module 710, Alarm by pulling down IO pin or dedicated Alert signal. After the host processor receives the alarm signal, it queries the cause of the alarm event through the GET_STATUS command.
  • the eSPI After receiving the GET_STATUS command from the module 710, the eSPI sends the interrupt ID and interrupt status in the shared register to the host processor through the eSPI packet.
  • the host processor initiates a GET_PC/NP command to read the keycode of the operator pressing the key.
  • the circuit system 740 converts the command into a DMA operation. Read back the keycode held by the keyboard scanning module, and send an eSPI packet from the module 710 through eSPI to upload to the host processor.
  • the description of writing data to the peripheral module 730 based on eSPI is as follows.
  • the host processor sends the write command.
  • the eSPI slave module 710 receives the write command, and the circuit system 740 obtains the write address and data from the write command, and writes the data into the register of the peripheral module 730 corresponding to the write address.
  • the host processor when the host processor wants to send the light effect data to the ambient light for display, the host processor first initiates a data write operation and initiates a write data packet, and the eSPI receives the packet from the module 710, and the circuit system 740 decodes it. After the package finds that it is a write command to a certain register of the ambient light, it converts the command into a DMA operation, and writes the data from the host processor into the specified address of the ambient light, so that the ambient light changes the display state and completes the processing of the host The display effect required by the device.
  • the ambient light may be interrupted during work, such as when there is no data to display (the data cache is empty), and for example, when the ambient light displays an error.
  • the ambient light When the ambient light generates an interrupt, like the keyboard, it sends an interrupt to the processor 720, and the processor 720 then sends an alarm to the host processor from the module 710 through eSPI, and the host processor queries the cause of the alarm and reads relevant data.
  • Embodiments of the present disclosure provide an embedded control circuit based on a direct memory access and sharing interface.
  • FIG. 9 shows a schematic block diagram of an embedded control circuit based on a direct memory access and shared interface according to an exemplary embodiment of the present disclosure.
  • the embedded control circuit 900 includes: Bus interface circuit 910 , processor 920 , one or more first peripheral modules 931 , one or more second peripheral modules 932 , circuit system 940 ; first bus 951 , second bus 952 and third bus 961 .
  • the plurality of first peripheral modules 931 are marked as 931-1 to 931-n in FIG. 9
  • the plurality of second peripheral modules 931 are marked as 932-1 to 932-m in FIG. 9 .
  • this embodiment does not limit the number of the first peripheral module 931 and the second peripheral module 932
  • the embedded control circuit 900 may include any number of the first peripheral module 931 and the second peripheral module 932 .
  • the embedded control circuit 900 further includes: a fourth bus 962 connected between the processor 920 and the circuit system 940 to transmit information between the processor 920 and the circuit system 940 .
  • the embedded control circuit 900 further includes: an interrupt signal line connected between the processor 920 and the circuit system 940 .
  • the interrupt signal line may be configured to transmit any interrupt signal between the processor 920 and the circuit system 940 , which is not limited in this embodiment.
  • the circuit system 940 is configured to transmit an interrupt signal to the processor 920 through the interrupt signal line 980 . Refer to FIG. 4 and its description, which will not be described in detail in this embodiment.
  • Each of the first peripheral modules 931 includes a first interface and a second interface.
  • the first bus 951 is connected between the first interface of each first peripheral module 931 and the bus interface circuit 910 .
  • the second bus 952 is connected between the second interface of each first peripheral module 931 and the processor 920 .
  • the bus interface circuit 910 is provided with an I/O interface corresponding to each first peripheral module 931 .
  • the bus interface circuit 910 is configured to access the first peripheral module 931 through the first bus 951 .
  • the processor 920 is configured to access the first peripheral module 931 through the second bus 952 .
  • the third bus 961 is connected between the second peripheral module 932 and the circuit system 940 .
  • the third bus 961 is also connected between the second peripheral module 932 and the processor 920 .
  • the circuit system 940 is configured to communicate with the host processor through the bus interface circuit 910 , and access the second peripheral module 932 through the third bus 961 based on the commands of the host processor.
  • the circuit system 940 acts as a master device of the third bus 961
  • the second peripheral module 932 acts as a slave device of the third bus 961
  • the second peripheral module 932 can respond to various bus commands of the circuit system 940 .
  • the processor 920 accesses the second peripheral module 932 through the third bus 961 .
  • the processor 920 can be used as the master device of the third bus 961
  • the second peripheral module 932 can be used as the slave device of the third bus 961
  • the second peripheral module 932 can respond to various buses of the processor 920. Order.
  • At least part of the first bus 951, the second bus 952, the third bus 961 and the fourth bus 962 can adopt a bus matrix, and the bus interface circuit 910, the processor 920, the first peripheral module 931, the second The two peripheral modules 932 and at least part of the circuit system 940 are accessed through the bus matrix.
  • the first peripheral module 931 may refer to the descriptions of FIG. 1 , FIG. 2 and FIG. 3 mentioned above in this disclosure, and details are not repeated here.
  • the circuit system 940 and the second peripheral module 932 may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 in the present disclosure, and details are not repeated here.
  • the host processor can access the first peripheral module 931 through the bus interface circuit 910 and the first bus 951 .
  • the host processor can also access the second peripheral module 932 through the bus interface circuit 910, the circuitry 940 and the third bus 961.
  • An embodiment in which the embedded control circuit 900 distinguishes the host processor's access to the first peripheral module 931 and the second peripheral module 932 will be described below.
  • the bus interface circuit 910 is configured to: determine whether the host processor accesses the first peripheral module 931 or the second peripheral module 932 based on the target address of the access, and when the host processor accesses the first peripheral module In the case of 931, the first peripheral module 931 is accessed through the first bus 951; in the case of the host processor accessing the second peripheral module 932, the access command of the host processor is forwarded to the circuit system 940.
  • the circuit system 940 accesses the second peripheral module 932 through the third bus 961 based on an access command of the host processor.
  • the circuit system 940 is configured to: determine whether the second peripheral module 932 is accessed by the host processor based on the target address of the access; The command of the processor accesses the second peripheral module 932 through the third bus 961 .
  • each first peripheral module 931 is configured to: determine whether the host processor accesses itself based on the target address of the access; .
  • FIG. 10 shows a flowchart of a method for accessing peripherals based on direct memory access and shared interfaces according to an exemplary embodiment of the present disclosure, which is applied to the embedded control circuit 900 shown in FIG. 9 .
  • the method for accessing peripherals includes steps S1001 to S1004. It should be understood that although step numbers are marked in FIG. 10 , the sequence of steps S1001 to S1004 is not limited in this embodiment.
  • step S1001 the bus interface circuit 910 accesses the first peripheral module 931 through the first bus 951 .
  • the bus interface circuit 910 accessing the first peripheral module 931 through the first bus 951 includes reading and/or writing registers of the first peripheral module 931 .
  • the first bus 951 is connected between the bus interface circuit 910 and the first interface of the first peripheral module 931, and the bus interface circuit 910 passes through the first bus 951 and the first interface of the first peripheral module 931 Registers of the first peripheral module 931 are accessed.
  • step S1001 the bus interface circuit 910 receives a write command from the host processor, and writes data to the register of the first peripheral module 931 corresponding to the write command through the first bus 951 .
  • the bus interface circuit 910 may also receive a read command from the host processor, and read data from the register of the first peripheral module 931 corresponding to the read command through the first bus 951 .
  • step S1002 the circuit system 940 communicates with the host processor through the bus interface circuit 910 , and accesses the second peripheral module 932 through the third bus 961 based on a command from the host processor.
  • the circuit system 940 receives the write command of the host processor through the bus interface circuit 910, and based on the write command, writes to the register of the second peripheral module 932 corresponding to the write command through the third bus 961 data.
  • the circuit system 940 can also receive a read command from the host processor through the bus interface circuit 910 , and read data from the register of the second peripheral module 932 corresponding to the read command through the third bus 961 based on the read command.
  • circuitry 940 accesses second peripheral module 932 based on preconfigured permissions.
  • each target address can be configured to allow reading and writing, or allow reading and prohibit writing, or allow writing and prohibit reading, which is not limited in this embodiment.
  • the processor 920 configures the authority of the circuit system 940 to access the second peripheral module 932 through the fourth bus 962 connected between the processor 920 and the circuit system 940 .
  • the circuit system 940 accesses the second peripheral module 932 based on the permission information configured by the processor 920 .
  • the bus interface circuit 910 receives write commands from the host processor and sends the write commands to the circuitry 940 .
  • the circuit system 940 receives the write command, and parses the write command to obtain the target address and the data to be written.
  • the circuit system 940 judges whether the target address is an address that allows writing. If the target address is an address that allows writing, the circuit system 940 writes to the register of the second peripheral module 932 corresponding to the target address through the third bus 961. the above data.
  • the circuit system 940 transmits an interrupt signal to the processor 920 through the interrupt signal line between the circuit system 940 and the processor 920, so as to notify the processor 920 that the host process device requests access to write-prohibited registers.
  • Bus interface circuit 910 receives read commands from the host processor and sends the read commands to circuitry 940 .
  • the circuit system 940 receives the read command and parses the read command to obtain the target address.
  • the circuit system 940 determines whether the target address is an address that is allowed to be read. If the target address is an address that is allowed to be read, the circuit system 940 reads data from the register of the second peripheral module 932 corresponding to the target address through the third bus 961 . After reading the data, the circuit system 940 generates a bus command corresponding to the read command, and sends the bus command to the bus interface circuit 910 .
  • the bus interface circuit 910 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the read data.
  • the circuit system 940 transmits an interrupt signal to the processor 920 through the interrupt signal line between the circuit system 940 and the processor 920, so as to notify the processor 920 that the host process device requests access to registers that are prohibited from being read.
  • step S1003 the processor 920 accesses the first peripheral module 931 through the second bus 952 .
  • the processor 920 reads data from the register of the first peripheral module 931 through the second bus 952 .
  • the processor 920 can also write data to the register of the first peripheral module 931 through the second bus 952 .
  • step S1004 the processor 920 accesses the second peripheral module 932 through the third bus 961 .
  • accessing the second peripheral module 932 by the processor 920 through the third bus 961 may include: accessing by the processor 920 to read and/or write registers of the second peripheral module 932 through the third bus 961 .
  • the processor 920 sends the interrupt information of the second peripheral module 932 to the circuit system 940 through the bus between it and the circuit system 940 .
  • Interrupt information is sent by circuitry 940 through bus interface circuit 910 to the host processor.
  • the processor 920 sends the interrupt information of the second peripheral module 932 to the host processor is described as follows.
  • the processor 920 detects interrupt information of the second peripheral module 932 .
  • the processor 920 sends the detected interrupt information to the circuit system 940 through the bus between it and the circuit system 940 .
  • the circuit system 940 generates a bus command corresponding to the interrupt information, and sends the generated bus command to the bus interface circuit 910 .
  • the bus interface circuit 910 sends the bus command to the host processor, so that the host processor receives the bus command to obtain the interrupt information.
  • the host processor responds to the embedded control circuit based on the interrupt information.
  • the host processor initiates a process of writing data to the register of the second peripheral module 932 corresponding to the interrupt information based on the interrupt information. In some examples, the host processor initiates a process of reading data from the register of the second peripheral module 932 corresponding to the interrupt information based on the interrupt information.
  • the embedded control circuit of the exemplary embodiment of the present disclosure will describe the direct memory access and shared interface.
  • the host processor communicates with the embedded control circuit through the eSPI bus.
  • FIG. 11 shows a schematic block diagram of an embedded control circuit based on a direct memory access and sharing interface using an eSPI bus according to an exemplary embodiment of the present disclosure.
  • the embedded control circuit 1100 includes: eSPI slave module 1110 for processor communication, processor 1120 , one or more first peripheral modules 1131 , one or more second peripheral modules 1132 , circuit system 1140 and bus matrix 1150 .
  • the plurality of first peripheral modules 1131 are marked as 1131-1 to 1131-n in FIG. 11
  • the plurality of second peripheral modules 1132 are marked as 1132-1 to 1132-m in FIG. 11 .
  • a bus matrix is used, and this embodiment will be described below in conjunction with FIG. 11 .
  • Each of the first peripheral modules 1131 includes a first interface and a second interface. (local bus) is connected between the first interface of each first peripheral module 1131 and the eSPI slave module 1110.
  • the second interface of each first peripheral module 1131 is connected to the APB bus, and the processor 1120 is connected to the bus matrix 1150.
  • the APB bus is connected to the bus matrix through the first bridge and the first fast bus, and then each first peripheral The second interface of the module 1131 is connected with the processor 1120 .
  • the eSPI slave module 1110 is configured to access the first peripheral module 1131 through a local bus.
  • the processor 1120 is configured to access the first peripheral module 1131 through the bus matrix, the first express bus, the first bridge and the APB bus.
  • the circuit system 1140 is connected to the DMA bus, the DMA bus is connected to the bus matrix 1150, the second peripheral module 1132 is connected to the second fast bus, and the second fast bus is connected to the bus matrix, and then between the second peripheral module 1132 and the circuit system 1140 are connected through the DMA bus, the bus matrix 1150 and the second fast bus.
  • the processor 1120 is connected to the bus matrix, and the bus matrix 1150 and the second fast bus are used between the second peripheral module 1132 and the processor 1120 .
  • the circuit system 1140 is configured to communicate with the host processor through the eSPI slave module 1110 , and access the second peripheral module 1132 through the DMA bus, the bus matrix 1150 and the second fast bus based on the command of the host processor.
  • the circuit system 1140 acts as a master device
  • the second peripheral module 1132 acts as a slave device
  • the second peripheral module 1132 can respond to various bus commands of the circuit system 1140 .
  • the processor 1120 accesses the second peripheral module 1132 through the bus matrix 1150 and the second fast bus.
  • the processor 1120 may act as a master device
  • the second peripheral module 1132 may act as a slave device
  • the second peripheral module 1132 may respond to various bus commands of the processor 1120 .
  • some second peripheral modules 1132 can be directly connected to the second fast bus, such as the second peripheral module 1132-1 shown in FIG. Type C interface, etc.
  • Some second peripheral modules 1132 can be connected to the second fast bus through the second bridge, such as the second peripheral modules 1132-2 to 1132-m shown in Figure 11, the second peripheral modules 1132-2 to 1132- Examples of m include an ambient light control module, a breathing light control module, and the like. It should be understood that this embodiment does not limit whether the second peripheral module 1132 is connected to the second fast bus through a bridge.
  • the first peripheral module 1131 may refer to the descriptions of FIG. 1 , FIG. 2 and FIG. 3 in the present disclosure, and details are not repeated here.
  • the circuit system 1140 and the second peripheral module 1132 may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 in the present disclosure, and details are not repeated here.
  • the host processor can access the first peripheral module 1131 through the eSPI slave module 1110 and the local bus.
  • the host processor can also access the second peripheral module 1132 through the eSPI slave module 1110, the circuitry 1140, the DMA bus, the bus matrix 1150, and the second fast bus.
  • An embodiment in which the embedded control circuit 1100 distinguishes the host processor's access to the first peripheral module 1131 and the second peripheral module 1132 will be described below.
  • the eSPI slave module 1110 is configured to: determine whether the host processor accesses the first peripheral module 1131 or the second peripheral module 1132 based on the target address of the access, and when the host processor accesses the first peripheral module In the case of 1131, access the first peripheral module 1131 through the local bus; in the case of the host processor accessing the second peripheral module 1132, forward the access command of the host processor to the circuit system 1140.
  • the circuit system 1140 accesses the second peripheral module 1132 through the DMA bus, the bus matrix 1150 and the second fast bus based on an access command of the host processor.
  • the circuit system 1140 is configured to: determine whether the second peripheral module 1132 is accessed by the host processor based on the target address of the access; The command of the processor accesses the second peripheral module 1132 through the DMA bus, the bus matrix 1150 and the second fast bus.
  • each first peripheral module 1131 is configured to: determine whether the host processor accesses itself based on the target address of the access; .
  • An embodiment of the present disclosure provides an embedded control circuit with a dual-bus interface.
  • Fig. 12 shows a schematic block diagram of an embedded control circuit of a dual-bus interface in an exemplary embodiment of the present disclosure.
  • the embedded control circuit 1200 includes: one or more peripheral modules 1230; a processor 1220 , connected with one or more peripheral modules 1230; first bus interface circuit 1211, connected with one or more peripheral modules 1230; second bus interface circuit 1212, connected with one or more peripheral modules 1230; bus interface
  • the selection circuit 1213 is configured to communicate with the host processor, and is operable to connect the first bus interface circuit 1211 or the second bus interface circuit 1212 to the host processor.
  • the first bus interface circuit 1211 or the second bus interface circuit 1212 can use various types of bus interfaces to communicate with the host processor, including but not limited to LPC bus, SPI bus, eSPI bus and so on.
  • the first bus interface circuit 1211 can be an LPC circuit
  • the second bus interface circuit 1212 can be an eSPI circuit, so that the embedded control circuit 1200 can communicate with the host processor through the LPC bus protocol or the eSPI bus protocol.
  • the first bus interface circuit 1211 and the second bus interface circuit 1212 may use any combination of two bus protocols, which is not limited in this embodiment.
  • the bus interface selection circuit 1213 is configured to connect the first bus interface circuit 1211 or the second bus interface circuit 1212 to the host processor based on the initialization configuration. After initial configuration, the embedded control circuit 1200 is configured to communicate with the host processor through one of the first bus interface circuit 1211 and the second bus interface circuit 1212 . The bus interface selection circuit 1213 connects one of the first bus interface circuit 1211 and the second bus interface circuit 1212 to the host processor based on the initial configuration, thereby communicating with the host processor through the configured bus interface circuit.
  • the peripheral module 1230 includes: one or more first peripheral modules, each of the one or more first peripheral modules includes a first interface and a second interface. Between the first interface of each first peripheral module and the first bus interface circuit and the second bus interface circuit, the first bus is connected; between the second interface of each first peripheral module and the processor, through Second bus connection.
  • the first bus interface circuit 1211 and the second bus interface circuit 1212 are configured to access one or more first peripheral modules through the first bus.
  • the processor 1220 is configured to access one or more first peripheral modules through the second bus.
  • the peripheral module 1230 includes: one or more second peripheral modules.
  • the embedded control circuit also includes: a circuit system.
  • the one or more second peripheral modules are connected to the circuit system through the third bus.
  • One or more second peripheral modules are connected to the processor 1120 through a third bus.
  • the circuit system is configured to communicate with the host processor through the first bus interface circuit 1211 or the second bus interface circuit 1212, and access one or more second peripheral modules through the third bus based on the command of the host processor; the processor 1220 , configured to access one or more second peripheral modules through the third bus.
  • circuit system and the second peripheral module may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 mentioned above in this disclosure, and details are not repeated here.
  • the peripheral module 1230 includes one or more first peripheral modules and one or more second peripheral modules.
  • the host processor can access the first peripheral module through the first bus interface circuit 1211 or the second bus interface circuit 1212 and the first bus.
  • the host processor can also access the second peripheral module through the first bus interface circuit 1211 or the second bus interface circuit 1212, the circuit system and the third bus.
  • the embedded control circuit 1200 distinguishes between the host processor's access to the first peripheral module and the second peripheral module will be described below.
  • the first bus interface circuit 1211 and/or the second bus interface circuit 1212 are configured to: determine whether the host processor is accessing the first peripheral module or the second peripheral module based on the target address of the access; When the host processor accesses one or more first peripheral modules, access one or more first peripheral modules through the first bus; when the host processor accesses one or more second peripheral modules, The host processor's access command is forwarded to the circuitry. The circuitry accesses the second peripheral module through the third bus.
  • the circuit system is configured to: determine whether the host processor accesses one or more second peripheral modules based on the target address of the access; when the host processor accesses the one or more second peripheral modules, In some cases, one or more second peripheral modules are accessed through the third bus based on commands from the host processor.
  • the embedded control circuit of the exemplary embodiment of the present disclosure is described below by taking the LPC and eSPI bus as examples, and the host processor communicates with the embedded control circuit through the eSPI or LPC bus.
  • Fig. 13 shows the schematic block diagram of the embedded control circuit of the LPC-eSPI dual-bus interface of the exemplary embodiment of the present disclosure
  • the embedded control circuit 1300 includes: a peripheral module; a processor 1320, and Peripheral module connection; LPC slave module 1311, connected with one or more peripheral modules; eSPI slave module 1312, connected with one or more peripheral modules; LPC-eSPI interface selector 1313, configured to communicate with the host processor communicate, and operatively connect the LPC slave module 1311 or the eSPI slave module 1312 to a host processor; circuitry 1340.
  • the peripheral modules include: one or more first peripheral modules 1331 and one or more second peripheral modules 1332, marked as first peripheral modules 1331-1 to 1331-n in FIG. Modules 1332-1 to 1332-m are provided.
  • the LPC-eSPI interface selector 1313 is configured to connect the LPC slave module 1311 or the eSPI slave module 1312 to the host processor based on the initial configuration.
  • the embedded control circuit 1300 is configured to communicate with the host processor through a bus interface circuit in the LPC slave module 1311 and the eSPI slave module 1312 .
  • the LPC-eSPI interface selector 1313 connects one bus interface circuit in the LPC slave module 1311 and the eSPI slave module 1312 to the host processor based on the initial configuration, thereby communicating with the host processor through the configured bus interface circuit.
  • each first peripheral module 1331 includes a first interface and a second interface.
  • the first interface of each first peripheral module 1331 is connected to the LPC slave module 1311 and the eSPI slave module 1312 through a local bus (local bus).
  • the second interface of each first peripheral module 1331 is connected to the processor through the APB bus, the first bridge, the first fast bus and the bus matrix 1350 .
  • the LPC slave module 1311 and the eSPI slave module 1312 access one or more first peripheral modules 1331 through the local bus.
  • the processor 1320 accesses the first peripheral module 1331 through the first fast bus, the first bridge and the APB bus of the bus matrix 1350 .
  • the second peripheral module 1332 and the circuit system 1340 are connected through a DMA bus, a bus matrix 1350 and a second fast bus.
  • the second peripheral module 1332 is connected to the processor 1320 through a bus matrix 1350 and a second fast bus.
  • the circuit system 1340 communicates with the host processor through the LPC slave module 1311 or the eSPI slave module 1312, the command based on the host processor passes through the DMA bus, the bus matrix and the second fast bus second peripheral module 1332, and the processor 1320 passes through the bus matrix 1350 .
  • the second fast bus accesses the second peripheral module 1332 .
  • the processor 1320 can also access the circuit system 1340 through the bus matrix 1350, the first bridge, and the APB bus. Information can be transmitted between the processor 1320 and the circuit system 1340 through the bus matrix 1350 , the first bridge, and the APB bus. For example, the processor 1320 can transmit permission information for accessing the second peripheral module 1332 to the circuit system 1340 on this line.
  • circuit system 1340 and the second peripheral module 1332 may refer to the descriptions of FIG. 4 , FIG. 6 , FIG. 7 and FIG. 8 in the present disclosure, and details are not repeated here.
  • the host processor can access the first peripheral module 1331 through the LPC slave module 1311 or the eSPI slave module 1312 and the local bus.
  • the host processor can also access the second peripheral module 1332 through the LPC slave module 1311 or the eSPI slave module 1312, the circuitry 1340 and the DMA bus, the bus matrix 1350, and the second fast bus.
  • An embodiment in which the embedded control circuit 1300 distinguishes the host processor's access to the first peripheral module 1331 and the second peripheral module 1332 will be described below.
  • the LPC slave module 1311 and/or the eSPI slave module 1312 are configured to: determine whether the host processor accesses the first peripheral module 1331 or the second peripheral module 1332 based on the target address of the access; In the case that the processor accesses one or more first peripheral modules 1331, one or more first peripheral modules 1331 are accessed through the first bus; when the host processor accesses one or more second peripheral modules 1332 , forward the access command of the host processor to the circuit system 1340 .
  • the circuit system 1340 accesses the second peripheral module 1332 through the DMA bus, the bus matrix 1350 and the second fast bus.
  • the circuit system 1340 is configured to: determine whether the host processor accesses one or more second peripheral modules 1332 based on the target address of the access; In the case of the module 1332, one or more second peripheral modules 1332 are accessed through the DMA bus, the bus matrix 1350, and the second fast bus based on commands from the host processor.
  • each first peripheral module 1331 is configured to: determine whether the host processor accesses itself based on the target address of the access; .
  • the exemplary implementation of the present disclosure also provides a chip, which may include the aforementioned embedded control circuit of the present disclosure.
  • the solutions of the present disclosure may be integrated into an electronic device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GP) devices; mobile phones; cellular phones; smart phones; Session Initiation Protocol (SIP) phones; tablets; phablets; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants ( PDA); monitor; computer monitor; television; tuner; radio; satellite radio; music player; digital music player; portable music player; digital video player; video player; digital video disc (DVD) Players; Portable Digital Video Players; Motor Vehicles; Vehicle Components; Avionics Systems; Unmanned Aerial Vehicles; and Multicopters.
  • GPS global positioning system

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Abstract

本公开提供一种直接存储器访问的嵌入式控制电路、芯片和电子设备，嵌入式控制电路，包括：用于与主机处理器通信的总线接口电路；处理器；一个或多个外设模块；电路系统，与总线接口电路连接；第一总线，连接在一个或多个外设模块与电路系统之间；第二总线，连接在一个或多个外设模块与处理器之间；其中：电路系统被配置为：通过总线接口电路与主机处理器通信，基于主机处理器的命令通过第一总线访问一个或多个外设模块；处理器被配置为通过第二总线访问一个或多个外设模块。通过本公开，在嵌入式控制电路中集成外设模块时，可不修改总线接口电路，便于在嵌入式控制电路中集成外设模块。

Description

一种直接存储器访问的嵌入式控制电路、芯片和电子设备 技术领域
本公开涉及电子电路技术领域，尤其涉及一种直接存储器访问的嵌入式控制电路、芯片和电子设备。
背景技术
个人计算机等电子设备中，由嵌入式控制器(Embedded Controller，简称为EC)管理至少部分外围设备(简称为外设)。电子设备的处理器(简称为主机处理器)和嵌入式控制器的处理器需要访问这些外设。相关技术中，主机处理器和嵌入式控制器的处理器如何更高效、便捷、可靠地访问外设，目前尚未提出有效的解决方案。
发明内容
有鉴于此，本公开实施例提供了一种直接存储器访问的嵌入式控制电路、芯片和电子设备，以实现外设访问。
根据本公开的一方面，提供了一种嵌入式控制电路，包括：用于与主机处理器通信的总线接口电路；处理器；一个或多个外设模块；电路系统，与总线接口电路连接；第一总线，连接在一个或多个外设模块与电路系统之间；第二总线，连接在一个或多个外设模块与处理器之间；其中：电路系统被配置为：通过总线接口电路与主机处理器通信，基于主机处理器的命令通过第一总线访问一个或多个外设模块；处理器被配置为通过第二总线访问一个或多个外设模块。
在一些实施例中，嵌入式控制电路，还包括：第三总线，连接在处理器与电路系统之间。
在一些实施例中，处理器被配置为通过第三总线向电路系统发送一个或多个外设模块的中断信息；电路系统被配置为通过总线接口电路向主机处理器发送中断信息。
在一些实施例中，处理器被配置为通过第三总线配置电路系统访问一个或多个外设模块的权限。
在一些实施例中，电路系统被配置为：基于预先配置的权限访问一个或多个外设模块。
在一些实施例中，嵌入式控制电路，还包括：中断信号线，连接在处理器与电路系统之间。
在一些实施例中，电路系统被配置为通过中断信号线向处理器传输中断信号。
在一些实施例中，电路系统被配置为：在主机处理器访问的外设模块的寄存器被配置 为禁止访问的情况下，通过中断信号线向处理器传输中断信号。
在一些实施例中，电路系统，被配置为：通过总线接口电路接收主机处理器的写命令，基于写命令通过第一总线向写命令对应的外设模块的寄存器写入数据；和/或通过总线接口电路接收主机处理器的读命令，基于读命令通过第一总线从读命令对应的外设模块的寄存器读取数据。
在一些实施例中，电路系统包括：接收电路，被配置为接收总线接口电路发送的总线命令；解析电路，被配置为解析接收的总线命令，得到目标地址；第一控制器，被配置为对目标地址对应的外设模块的寄存器进行访问。
在一些实施例中，在总线命令为写命令时，解析电路还得到目标数据；其中，第一控制器被配置为：向目标地址对应的外设模块的寄存器写入目标数据。
在一些实施例中，电路系统，还包括：生成电路，被配置为生成总线命令；发送电路，被配置为向总线接口电路发送生成的总线命令，以使生成的总线命令被主机处理器接收。
在一些实施例中，第一控制器还被配置为：将从目标地址读取的数据发送给生成电路，以由生成电路生成对应的总线命令，并由发送电路将生成的总线命令发送给总线接口电路。
在一些实施例中，电路系统，还包括：第二控制器，被配置为通过第三总线接收处理器发送的信息。
在一些实施例中，第二控制器，还被配置为通过第三总线接收处理器发送的中断信息，将中断信息发送给生成电路，以由生成电路生成对应的总线命令，并由发送电路将生成的总线命令发送给总线接口电路。
在一些实施例中，电路系统，还包括安全控制模块，与第一控制器和第二控制器连接；其中，第二控制器，还被配置为通过第三总线接收处理器发送的权限信息，将权限信息写入安全控制模块；第一控制器，还被配置为基于安全控制模块中的权限信息确定访问目标地址的权限。
在一些实施例中，总线接口电路包括：一个总线接口或多个总线接口。
根据本公开的另一方面，提供了一种外设访问方法，应用于嵌入式控制电路，嵌入式控制电路包括：总线接口电路、处理器、一个或多个外设模块和电路系统，其中，外设访问方法包括：由电路系统通过总线接口电路与主机处理器通信，基于主机处理器的命令通过第一总线访问一个或多个外设模块，其中，第一总线连接在一个或多个外设模块与电路系统之间；由处理器通过第二总线访问一个或多个外设模块，其中，第二总线连接在一个或多个外设模块与处理器之间。
根据本公开的又一方面，提供了一种芯片，包括本公开实施例的嵌入式控制电路。
根据本公开的再一方面，提供了一种电子设备，包括：本公开实施例的嵌入式控制电路或本公开实施例的芯片。
本公开实施例中提供的一个或多个技术方案，嵌入式控制电路中集成外设模块，在嵌入式控制电路中设置电路系统，电路系统可通过总线接口电路与主机处理器通信，基于主机处理器的命令通过第一总线访问一个或多个外设模块；处理器可通过第二总线访问一个或多个外设模块。在嵌入式控制电路中集成外设模块时，可将外设模块的地址开放给主机处理器，主机处理器使用外设模块的地址访问外设模块，可不修改总线接口电路，便于在嵌入式控制电路中集成外设模块。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的更多细节、特征和优点被公开，在附图中：
图1示出了本公开示例性实施例的基于共享接口的嵌入式控制电路的示意性框图；
图2示出了本公开示例性实施例的外设模块130的示意性框图；
图3示出了本公开示例性实施例的基于eSPI总线和共享接口的嵌入式控制电路的示意性框图；
图4示出了本公开示例性实施例直接存储器访问的嵌入式控制电路的示意性框图；
图5示出了本公开示例性实施例的直接存储器访问的外设访问方法的流程图；
图6示出了本公开示例性实施例的电路系统440的示意性框图；
图7示出了本公开示例性实施例的使用eSPI总线和直接存储器访问的嵌入式控制电路的示意性框图；
图8示出了本公开示例性实施例的电路系统740的示意性框图；
图9示出了本公开示例性实施例的基于直接存储器访问和共享接口的嵌入式控制电路的示意性框图；
图10示出了本公开示例性实施例的基于直接存储器访问和共享接口的外设访问方法的流程图；
图11示出了本公开示例性实施例的使用eSPI总线的基于直接存储器访问和共享接口的嵌入式控制电路的示意性框图；
图12示出了本公开示例性实施例的双总线接口的嵌入式控制电路的示意性框图；
图13示出了本公开示例性实施例的LPC-eSPI双总线接口的嵌入式控制电路的示意性框图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
应当理解，本公开的方法实施方式中记载的各个步骤可以按照不同的顺序执行，和/或并行执行。此外，方法实施方式可以包括附加的步骤和/或省略执行示出的步骤。本公开的范围在此方面不受限制。
本文使用的术语“包括”及其变形是开放性包括，即“包括但不限于”。术语“基于”是“至少部分地基于”。术语“一个实施例”表示“至少一个实施例”；术语“另一实施例”表示“至少一个另外的实施例”；术语“一些实施例”表示“至少一些实施例”。其他术语的相关定义将在下文描述中给出。需要注意，本公开中提及的“第一”、“第二”等概念仅用于对不同的装置、模块或单元进行区分，并非用于限定这些装置、模块或单元所执行的功能的顺序或者相互依存关系。
需要注意，本公开中提及的“一个”、“多个”的修饰是示意性而非限制性的，本领域技术人员应当理解，除非在上下文另有明确指出，否则应该理解为“一个或多个”。
本公开实施例涉及在嵌入式控制器中集成外设模块，对主机处理器和嵌入式控制器的处理器访问外设模块的技术方案的改进。
本公开的一些实施例，涉及基于共享接口的嵌入式控制电路，嵌入式控制电路中集成外设模块，外设模块包括两个接口，主机处理器通过总线接口电路和外设模块的一个接口访问外设模块，嵌入式控制电路的处理器通过另一个接口访问外设模块。在一些实施例中，至少一个外设模块包括用于连接外设的接口单元。在一些实施例中，至少一个外设模块对应的用于连接外设的接口单元，独立于外设模块而与处理器连接。
本公开的一些实施例，涉及直接存储器访问的嵌入式控制电路，嵌入式控制电路中集成外设模块，在嵌入式控制电路中设置电路系统，主机处理器通过总线接口电路和电路系统访问外设模块，嵌入式控制电路的处理器可通过其与外设模块之间的线路访问外设模块。在这些实施例中，在嵌入式控制电路中集成外设模块时，将外设模块的地址开放给主机处理器，主机处理器使用外设模块的地址访问外设模块，可不修改总线接口电路，便于在嵌入式控制电路中集成外设模块。
本公开的一些实施例，涉及共享接口和直接存储器访问的嵌入式控制电路，嵌入式控制电路中集成外设模块。一些外设模块为包括两个接口的外设模块，主机处理器可通过总线接口电路经这些外设模块的一个接口访问外设模块，嵌入式控制电路的处理器可经这些 外设模块的另一个接口访问外设模块。另一些外设模块为通过电路系统进行直接存储器访问的外设模块，主机处理器通过总线接口电路和电路系统访问外设模块，嵌入式控制电路的处理器可访问这些外设模块。
本公开的一些实施例，涉及嵌入式控制电路的总线接口电路，总线接口电路可包括至少两种总线协议的接口电路，通过总线接口选择电路选择至少两种总线协议的接口电路中的一个与主机处理器通信。
应当理解，本公开中提及的“第一总线”、“第二总线”、“第三总线”和“第四总线”等，在一些实施例中仅区分不同装置之间的传输线路，其可采用不同的总线，也可以通过总线矩阵等方式共用至少部分线路和接口。本公开对此不作限定。
在本公开的后续描述中，本公开的实施例可进行任意组合。下面对本公开的示例性实施例进行描述。
本公开实施例提供了一种基于共享接口的嵌入式控制电路。
图1示出了本公开示例性实施例的基于共享接口的嵌入式控制电路的示意性框图，如图1所示，嵌入式控制电路100，包括：用于与主机处理器通信的总线接口电路110、处理器120、外设模块130、第一总线140和第二总线150。图1中示出了多个外设模块130，标示为外设模块130-1至130-n。其中，第一总线140连接在外设模块130的第一接口与总线接口电路110之间，第二总线150连接在每个外设模块130的第二接口与处理器120之间。总线接口电路110通过第一总线140访问外设模块130。处理器120通过第二总线150访问外设模块130。由于主机处理器和处理器120分别使用不同的总线，对外设模块的访问互不干扰，可增加总线带宽，提高访问速度。例如，主机处理器通过第一总线140访问外设模块130-1，同时处理器120可通过第二总线150访问外设模块130-n。
在本实施例中，可采用各种类型的总线接口与主机处理器通信，包括但不限于LPC(Low Pin Count，简称为LPC)总线、串行外围接口(Serial Peripheral Interface，简称为SPI)总线、增强型串行外围接口(Enhanced Serial Peripheral Interface，简称为eSPI)总线等。总线接口电路110包括一个总线接口或多个总线接口。总线接口电路110可操作地将多个总线接口中的一个总线接口用于通信。本实施对此不作限定。在本实施例中，总线接口电路110与主机处理器之间可按照总线协议通信。作为一种示例，嵌入式控制电路100与主机处理器之间可使用eSPI总线，嵌入式控制电路100为eSPI总线中的从设备(eSPI slave)，主机处理器作为eSPI总线中的主设备(eSPI master)，总线接口110可为eSPI从模块。本实施例对此不作限定。
在本实施例中，第一总线140可包括与总线接口电路110兼容的任何总线，第一总线 140的示例可包括本地总线(local bus)、高级可拓展接口(Advanced eXtensible Interface，简称为AXI)总线、高级外围总线(Advanced Peripheral Bus，简称为APB)等，本实施对此不作限定。
在本实施例中，第二总线150可包括与处理器120兼容的任何总线，第二总线150的示例可包括本地总线(local bus)、高级可拓展接口(Advanced eXtensible Interface，简称为AXI)总线、高级外围总线(Advanced Peripheral Bus，简称为APB)等，本实施对此不作限定。
在本实施例中，在总线接口电路110上定义每个外设模块130对应的I/O接口。在本公开中，接口也可称为端口，在本公开的描述中统称为接口。
在本实施例中，外设模块130可包括各种外围设备的部分电路模块，外围设备的示例包括鼠标、键盘、USB、PD/TYPE-C、呼吸灯、氛围灯等。本实施对此不作限定。
在一些实施例中，外设模块130可包括用于连接外设的接口单元。作为一种实施方式，包括用于连接外设的接口单元的外设模块130，从与其接口单元连接的外设获取数据，和/或向与其连接的外设提供数据，外设模块130与主机处理器之间的通信可不经过处理器120。在本实施例中，处理器120可通过第二总线150对外设模块130进行读和/或写，例如，配置为外设模块130的参数等。主机处理器可通过总线接口电路110和第一总线140对外设模块130进行读和/或写，例如，向外设模块130写入要通过其连接的外设发送的数据，或者从外设模块130读取来自其连接的外设的数据，或配置外设模块130的参数等。包括用于连接外设的接口单元的外设模块130的示例包括串行接口模块(例如UART串口等)，串行接口模块包括接口单元，该接口单元用于连接串行通信物理接口(例如UART连接器)。串行接口模块和串行通信物理接口可采用RS-232C、RS-422、RS-423和RS-485等串行通信接口标准。
在一些实施例中，外设模块130对应的用于连接外设的接口单元，独立于外设模块130而与处理器120连接。处理器120可从外设模块130向外设模块130对应的接口单元发提供数据，或者从接口单元向接口单元对应的外设模块130提供数据。主机处理器可向外设模块130提供数据，主机处理器向外设模块130提供的数据可经处理器120提供给外设模块130对应的接口单元；处理器120可将接口单元的数据提供给接口单元对应的外设模块130，主机处理器可从外设模块130获取该数据。一般的，处理器120可通过快速总线等与独立于外设模块130的接口单元连接。独立于外设模块130而与处理器120连接的用于连接外设的接口单元的示例包括键盘接口单元。作为一种示例，位于键盘上的键盘控制器检测按键的按下和释放，向键盘接口单元发送键盘码，处理器120检测到键盘接口单元接收 到键盘码，处理器120将键盘码提供给键盘接口单元对应的外设模块130。
在一些实施例中，部分外设模块130包括用于连接外设的接口单元，该部分外设模块130从与其接口单元连接的外设获取数据，和/或向与其连接的外设提供数据，外设模块130与主机处理器之间的通信可不经过处理器120。部分外设模块130对应的用于连接外设的接口单元，独立于外设模块130而与处理器120连接。处理器120可从外设模块130向外设模块130对应的接口单元发提供数据，或者从接口单元向接口单元对应的外设模块130提供数据。主机处理器可向外设模块130提供数据，主机处理器向外设模块130提供的数据可经处理器120提供给外设模块130对应的接口单元；处理器120可将接口单元的数据提供给接口单元对应的外设模块130，主机处理器可从外设模块130获取该数据。
作为一种示例，外设模块130包括键盘模块和串行接口模块，其中，键盘模块的接口单元(称为键盘接口单元)与键盘模块独立，键盘接口单元与处理器120连接，串行接口模块包括用于连接串口通信物理接口的接口单元。
在该示例中，串行接口模块接收主机处理器通过总线接口电路110发送的数据，通过串口通信物理接口发送该数据；通过串口通信物理接口接收数据，串行接口模块串口通信物理接口接收的数据通过总线接口电路110发送给主机处理器，数据的传输不经过处理器120处理。处理器120可通过第二总线150对串行接口模块进行配置，或者，主机处理器可通过总线接口电路110和第一总线140配置串行接口模块。
在该示例中，处理器120可从键盘模块向键盘接口单元发提供数据，或者从键盘接口单元向键盘模块提供数据。主机处理器可向键盘模块提供数据，主机处理器向键盘模块提供的数据可经处理器120提供给键盘接口单元；处理器120可将键盘接口单元的数据提供给键盘模块130，主机处理器可从键盘模块130获取该数据。例如由处理器120从键盘接口单元获取键盘码，将键盘码提供给键盘模块，主机处理器通过总线接口电路110从键盘模块读取键盘码。
在一些实施例中，总线接口电路110，被配置为接收主机处理器的写命令，通过第一总线140向写命令对应的外设模块130的寄存器写入数据。在一些实施例中，总线接口电路110被配置为接收主机处理器的读命令，通过第一总线140从读命令对应的外设模块130的寄存器读取数据。
在一些实施例中，处理器120被配置为通过第二总线150从外设模块130的寄存器读取数据。在一些实施例中，处理器120被配置为通过第二总线150向外设模块130的寄存器写入数据。
在一些实施例中，外设模块130通过处理器120与外设通信，处理器120用于接收外 设的输入，通过第二总线150基于接收到的输入向外设对应的外设模块130的寄存器写入数据。
在一些实施例中，如图2所示，外设模块130可包括一个或多个寄存器131，该一个或多个寄存器131由处理器120(通过第二总线150)和主机处理器(通过总线接口电路110和第一总线140)读和/或写。处理器120通过外设模块130的第二接口对外设模块130的一个或多个寄存器131进行读和/或写。总线接口电路110通过外设模块130的第一接口对外设模块130的一个或多个寄存器131进行读和/或写。外设模块130可基于其功能设置一个或多个寄存器131，外设模块130的寄存器131的示例可包括：配置寄存器、状态寄存器、控制寄存器、读数据寄存器、或写数据寄存器等。
在一些实施例中，如图2所示，外设模块130可包括一个或多个功能电路132，该一个或多个功能电路与外设共同实现外设的功能。外设模块130的示例包括串行接口模块，串行接口模块用于连接串行通信物理接口，串行接口模块的功能电路包括电平转换电路，电平转换电路基于串行通信接口标准进行电平转换。外设模块130的另一示例包括发光单元控制模块，发光单元控制模块用于连接一个或多个发光单元(例如发光二极管)，发光单元控制模块的功能电路可包括控制器，控制器控制一个或多个发光单元发光。
在一些实施例中，如图2所示，外设模块130，包括：仲裁逻辑电路133，连接至第一总线140和第二总线150。仲裁逻辑电路133用于以仲裁来自处理器120和主机处理器(通过总线接口电路110)的访问请求。
作为一种实施方式，如图2所示，仲裁逻辑电路133用于连接仲裁控制寄存器134，以向仲裁逻辑电路133提供仲裁策略。作为一种实施方式，处理器120还与仲裁控制寄存器134连接，以向仲裁控制寄存器134写入仲裁策略。作为一种示例，仲裁控制寄存器134位于外设模块130外部，本实施例对此不作限定。
作为一种实施方式，仲裁逻辑电路133在外设模块130被主机处理器访问时，将外设模块130的第二接口与第二总线150断开。作为一种实施方式，仲裁逻辑电路133在外设模块130被处理器120访问时，将外设模块130的第一接口与第一总线140断开。可避免每次主机处理器和处理器120访问都需要仲裁，可避免单总线由于复杂的仲裁逻辑带来的效率问题和潜在的功能问题。
作为一种实施方式，仲裁逻辑电路133在外设模块130被主机处理器释放时，将外设模块的第二接口与第二总线150连接。作为一种实施方式，仲裁逻辑电路133在外设模块130被处理器120释放时，将外设模块130的第一接口与第二总线150连接。
外设模块130通过中断方式与处理器120和/或主机处理器(通过总线接口电路110) 传输至少部分信息。
在一些实施例中，如图2所示，外设模块130，还包括：第一中断单元135。第一中断单元135可用于发送写相关的中断信息。本实施例对此不作限定。
作为一种实施方式，第一中断单元135被配置为：在外设模块130的寄存器131被处理器120写入数据后，向总线接口电路110发送第一中断信息。总线接口电路110向主机处理器传输第一中断信息，并可响应于主机处理器的命令对外设模块130的寄存器131进行读和/或写。和/或，在外设模块130的寄存器131被主机处理器写入数据后，向处理器120发送第二中断信息。处理器120响应于第二中断信息，可对外设模块130的寄存器131进行读和/或写。
作为另一种实施方式，第一中断单元135被配置为：在外设模块130的寄存器131被其连接的外设写入数据后，向总线接口电路110发送第一中断信息。总线接口电路110向主机处理器传输第一中断信息，并可响应于主机处理器的命令对外设模块130的寄存器131进行读和/或写。在一些情况下，在外设模块130的寄存器131被主机处理器写入数据后，外设模块130其连接的外设发送数据。
在一些实施例中，如图2所示，至少一个外设模块130，还包括：第二中断单元136。第一中断单元135可用于发送读相关的中断信息。本实施例对此不作限定。
作为一种实施方式，第二中断单元136被配置为在外设模块130的寄存器131中由主机处理器写入的数据被处理器120读取后，向主机处理器发送第三中断信息。和/或，在外设模块130的寄存器131中由处理器120写入的数据被主机处理器读取后，向处理器120发送第四中断信息。
在一些实施例中，处理器120用于：检测外设模块130的寄存器是否被主机处理器写入数据；在检测到外设模块130的寄存器被主机处理器写入数据的情况下，通过第二总线150从相应的外设模块130的寄存器读取数据。在一些情况下，处理器120可将读取的数据发送给与其连接的并与该外设模块对应的外设接口单元。
在一些实施例中，总线接口电路110还被配置为在从外设模块130的寄存器中读取数据后，将对应外设模块130的寄存器的第一标志位设置为已读。在一些实施例中，处理器120还被配置为查询外设模块130的寄存器的第一标志位，基于第一标志位判断相应的外设模块130的寄存器中的数据是否被主机处理器读取。
下面以eSPI总线为例，对本公开示例性实施例的基于共享结构的嵌入式控制电路进行描述，主机处理器与嵌入式控制电路之间通过eSPI总线进行通信。
图3示出了本公开示例性实施例的基于eSPI总线和共享接口的嵌入式控制电路的示意 性框图，如图3所示，嵌入式控制电路300，包括：用于与主机处理器通信的eSPI从模块310、处理器320、外设模块330、第一总线340和第二总线350。图3中示出了多个外设模块330，分别为键盘模块330-1、鼠标模块330-2、串口模块330-3，以及其他外设330-n。其中，第一总线340连接在键盘模块330-1、鼠标模块330-2、串口模块330-3，以及其他外设330-n的第一接口与eSPI从模块310之间，第二总线350连接在外设模块330的第二接口与处理器320之间。eSPI从模块310通过第一总线340访问外设模块330。处理器320通过第二总线350访问外设模块330。
嵌入式控制电路300通过主机处理器和嵌入式控制电路300之间的eSPI接口以及位于嵌入式控制电路300上并能够被主机处理器访问到的IO接口(这个接口定义在eSPI从模块上，是主机处理器可访问的地址)管理外设。
在本实施例中，键盘模块330-1、鼠标模块330-2、串口模块330-3，以及其他外设330-n具有2个接口，分别连接在第一总线340(例如本地总线1)和第二总线350(例如本地总线2)上。第一总线340和第二总线350对寄存器的读/写操作，经过访问仲裁逻辑电路仲裁，仲裁策略(选择优先级)由仲裁控制寄存器选择，仲裁控制连入到模块外部的一个仲裁控制寄存器中，该仲裁控制寄存器由处理器320进行配置。
在本实施例中，如图3所示，使用总线矩阵352进行连接。处理器320连接至总线矩阵352，第二总线350(通过桥351)连接至总线矩阵352，第二总线350连接至外设模块330的第二接口，进而处理器320通过总线矩阵352和第二总线352访问外设模块330。外设模块330对应且独立于外设模块330而与处理器320连接的接口单元(例如键盘接口单元)通过例如快速总线等总线连接到总线矩阵352，进而处理器320与接口单元之间通过总线矩阵352和相关总线进行通信。
以串口为例，串口模块330-3的寄存器具有2个接口，一个接口通过第一总线340连接主机处理器，使主机处理器可通过该接口对串口进行配置或操作，一个接口通过第二总线350连接处理器320，使嵌入式控制电路300的处理器320能够通过这个接口对串口进行配置和访问。当主机处理器和处理器320同时通过两个不同接口配置或操作串口的寄存器时，访问仲裁机制根据配置，给主机处理器或者给处理器320更高的访问优先权。
示例性的串口工作过程说明如下。串口模块330-3从与其接口单元连接的外设获取数据，和/或向与其连接的外设提供数据，串口模块330-3与主机处理器之间的通信可不经过处理器120。主机处理器对串口模块330-3进行读和/或写，例如，向串口模块330-3写入要通过其连接的外设发送的数据，或者从串口模块330-3读取来自其连接的外设的数据，或配置串口模块330-3的参数等。
示例性的键盘工作过程说明如下。键盘模块330-1对应的键盘接口单元独立于键盘模块330-1，而与处理器320连接。电脑操作人员按下键盘某个按键，处理器320通过键盘接口单元获得键盘按键动作对应的键盘码，把键盘码通过总线矩阵352、桥(bridge)351、第二总线350写入到键盘模块330-1内的寄存器中。键盘模块330-1通过eSPI从模块310产生中断，上报给主机处理器。主机处理器收到中断，发起读操作，把键盘模块330-1的寄存器中的键盘码值读走，设置码值已被读走标志位，并清除相应的寄存器。键盘模块330-1产生中断，通知处理器320主机处理器已把键盘码值读走。如果不用中断，处理器320可查询键盘模块330-1的Status标志位，判断键盘码值是否被主机处理器读走。
本公开实施例提供了一种直接存储器访问的嵌入式控制电路。
图4示出了本公开示例性实施例直接存储器访问的嵌入式控制电路的示意性框图，如图4所示，嵌入式控制电路400包括：用于与主机处理器通信的总线接口电路410、处理器420、一个或多个外设模块430、电路系统440、第一总线450和第二总线460。本实施例中，嵌入式控制电路可包括一个或多个外设模块430，示例性的如图4中示出了外设模块430-1至430-n。
如图4所示，电路系统440与总线接口电路410连接。第一总线450连接在外设模块430与电路系统440之间；第二总线460连接在外设模块430与处理器420之间。其中，电路系统440通过总线接口电路410与主机处理器通信，基于主机处理器的命令通过第一总线450访问外设模块430。处理器420被配置为通过第二总线460访问外设模块430。本实施例中，可不在总线接口电路410定义外设模块430的I/O接口，电路系统440被配置为基于主机处理器的命令通过第一总线450访问外设模块430，因而在嵌入式控制电路中集成(例如新增)外设模块430可不修改总线接口电路。
在本实施例中，电路系统440访问外设模块430可采用直接存储器访问(DMA)命令。
在本实施例中，可采用各种类型的总线接口与主机处理器通信，包括但不限于LPC总线、SPI总线、eSPI总线等。总线接口电路410包括一个总线接口或多个总线接口。总线接口电路410可操作地将多个总线接口中的一个总线接口用于通信。本实施对此不作限定。在本实施例中，总线接口电路410与主机处理器之间可按照总线协议通信。作为一种示例，嵌入式控制电路400与主机处理器之间可使用eSPI总线，嵌入式控制电路400为eSPI总线中的从设备(eSPI slave)，主机处理器作为eSPI总线中的主设备(eSPI master)，总线接口电路410可为eSPI从模块。本实施例对此不作限定。
在本实施例中，第一总线450可包括与外设模块430和电路系统440兼容的任何总线，第一总线450的示例可包括本地总线、AXI总线、APB、AHB等，本实施对此不作限定。 在本实施例中，电路系统440可作为第一总线450的主设备(master)，外设模块430可作为第一总线450的从设备(slave)。外设模块430可响应电路系统440发来的各种总线命令。
在本实施例中，第二总线460可包括与外设模块430和处理器420兼容的任何总线，第二总线460的示例可包括本地总线、AXI总线、APB、AHB等，本实施对此不作限定。在本实施例中，处理器420可作为第二总线460的主设备(master)，外设模块430可作为第二总线460的从设备(slave)。外设模块430可响应处理器420发来的各种总线命令。
在一些实施例中，嵌入式控制电路400可使用总线矩阵，通过总线矩阵，可以让电路系统440、处理器420和外设模块430进行并行访问，提升访问效率，同时也降低功耗。
在本实施例中，电路系统440能够通过总线接口电路410与主机处理器通信，基于主机处理器的命令通过第一总线450访问外设模块430，并且处理器420能够通过第二总线460访问外设模块430。图5示出了本公开示例性实施例的直接存储器访问的外设访问方法的流程图，如图5所示，外设访问方法包括步骤S501和步骤S502。在步骤S501中，由电路系统440通过总线接口电路410与主机处理器通信，基于主机处理器的命令通过第一总线450访问外设模块430。在步骤S502，由处理器420通过第二总线460访问外设模块430。
在一些实施例中，在步骤S502中，处理器420通过第二总线460向外设模块430的寄存器写入数据。在一些实施例中，在步骤S502中，由处理器420通过第二总线460从外设模块430的寄存器读取数据。
在一些实施例中，电路系统440被配置为：通过总线接口电路410接收主机处理器的写命令，基于写命令通过第一总线450向写命令对应的外设模块430的寄存器写入数据。作为一种实施方式，在步骤S501中，由电路系统440通过总线接口电路410接收主机处理器的写命令，基于写命令通过第一总线450向写命令对应的外设模块430的寄存器写入数据。
在一些实施例中，电路系统440被配置为：通过总线接口电路410接收主机处理器的读命令，基于读命令通过第一总线450从读命令对应的外设模块430的寄存器读取数据。作为一种实施方式，在步骤S501中，由电路系统440通过总线接口电路410接收主机处理器的读命令，基于读命令通过第一总线450从读命令对应的外设模块430的寄存器读取数据。
在一些实施例中，如图4所示，嵌入式控制电路400，还包括：第三总线470，连接在处理器420与电路系统440之间。电路系统440与处理器420之间可通过第三总线470传输信息，信息的示例可包括处理器420对电路系统440的配置、处理器420向主机处理器发送的外设模块430的中断信息等，本实施对此不作限定。作为一种实施方式，处理器420 可作为第三总线470的主设备(master)，电路系统440可作为第三总线470的从设备(slave)。电路系统440可响应处理器420发来的各种总线命令。
在一些实施例中，如图4所示，嵌入式控制电路400还包括：中断信号线480，连接在处理器420与电路系统440之间。中断信号线480可被配置为传输处理器420与电路系统440之间的任何中断信号，本实施例对此不作限定。作为一种实施方式，电路系统440被配置为通过中断信号线480向处理器420传输中断信号。
在一些实施例中，电路系统440被配置为基于预先配置的权限访问外设模块430。在本实施例中，每个目标地址可被配置允许读和写，或者允许读取和禁止写入，或者允许写入和禁止读取，本实施对此不作限定。作为一种实施方式，处理器420通过第三总线470配置电路系统440访问外设模块430的权限。电路系统440被配置为基于处理器420配置的权限信息访问外设模块430。
在一些实施例中，电路系统440被配置为基于预先配置的权限访问外设模块430，并在主机处理器访问的外设模块430的寄存器被配置为禁止访问的情况下，通过中断信号线480向处理器420传输中断信号，以通知处理器420主机处理器请求访问禁止访问的寄存器。
作为一种实施方式，在权限控制下在权限控制下向外设模块430写入数据的示例说明如下。总线接口电路410接收主机处理器的写命令，并将写命令发送给电路系统440。电路系统440接收写命令，从写命令中解析得到目标地址和待写入的数据。电路系统440判断目标地址是否为允许写入的地址，在目标地址为允许写入的地址的情况下，电路系统440通过第一总线450向目标地址对应的外设模块430的寄存器写入上述数据。在一些示例中，在目标地址为禁止写入的地址的情况下，电路系统440通过中断信号线480向处理器420传输中断信号，以通知处理器420主机处理器请求访问禁止写入的寄存器。
作为一种实施方式，在权限控制下从外设模块430读取数据的示例说明如下。总线接口电路410接收主机处理器的读命令，并将读命令发送给电路系统440。电路系统440接收读命令，并从读命令中解析得到目标地址。电路系统440判断目标地址是否为允许读取的地址。在目标地址为允许读取的地址的情况下，电路系统440通过第一总线450从目标地址对应的外设模块430的寄存器读取数据。电路系统440在读取的数据后，生成读命令对应的总线命令，向总线接口电路410发送该总线命令。总线接口电路410向主机处理器发送该总线命令，以使主机处理器接收总线命令以获得读取的数据。在一些示例中，在目标地址为禁止读取的地址的情况下，电路系统440通过中断信号线480向处理器420传输中断信号，以通知处理器420主机处理器请求访问禁止读取的寄存器。
在一些实施例中，处理器420通过第三总线470向电路系统440发送外设模块430的 中断信息。进一步的，电路系统440通过总线接口电路410向主机处理器发送该中断信息。
作为一种实施方式，处理器420向主机处理器发送外设模块430的中断信息的示例说明如下。处理器420检测外设模块430的中断信息。处理器420通过第三总线470将检测到的中断信息发送给电路系统440。电路系统440生成中断信息对应的总线命令，向总线接口电路410发送生成的该总线命令。总线接口电路410向主机处理器发送该总线命令，以使主机处理器接收总线命令以获得中断信息。作为一种示例，主机处理器获取到中断信息后，基于中断信息响应嵌入式控制电路。在一些示例中，主机处理器基于中断信息发起向中断信息对应的外设模块430的寄存器写入数据的过程。在一些示例中，主机处理器基于中断信息发起从中断信息对应的外设模块430的寄存器读取数据的过程。
图6示出了本公开示例性实施例的电路系统440的示意性框图，如图6所示，电路系统440包括：接收电路441，被配置为接收总线接口电路410发送的总线命令；解析电路442，与接收电路441连接，被配置为解析接收的总线命令，得到目标地址；第一控制器443，与解析电路442连接，被配置为对目标地址对应的外设模块430的寄存器进行访问。在本实施例中，解析电路442根据总线接口电路410使用的总线接口协议解析总线命令。
在一些实施例中，总线命令包括写命令，解析电路442解析总线命令还得到目标数据，目标地址为待写入的地址。第一控制器443被配置为：向目标地址对应的外设模块430的寄存器写入目标数据。
作为一种实施方式，向外设模块430写入数据的示例说明如下。总线接口电路410接收主机处理器的写命令，并将写命令发送给接收电路441。接收电路441接收写命令，并将写命令发送给解析电路442。解析电路442从写命令中解析得到目标地址和待写入的数据。第一控制器443通过第一总线450向目标地址对应的外设模块430的寄存器写入上述数据。
在一些实施例中，总线命令包括读命令，解析电路422解析总线命令得到的目标地址为待读取的地址。
在一些实施例中，如图6所示，电路系统440还包括缓冲模块444，连接在接收电路441与解析电路442之间，用于缓存接收到的总线命令，以供解析电路442解析总线命令。
作为一种实施方式，向外设模块430写入数据的示例说明如下。总线接口电路410接收主机处理器的写命令，并将写命令发送给接收电路441。接收电路441接收写命令，接收电路441将写命令缓存到缓冲模块444。解析电路442从缓冲模块444获取写命令，解析电路442从写命令中解析得到目标地址和待写入的数据。第一控制器443通过第一总线450向目标地址对应的外设模块430的寄存器写入上述数据。
在一些实施例中，如图6所示，电路系统440还包括：生成电路445，被配置为生成总 线命令；发送电路446，与生成电路445连接，被配置为向总线接口电路410发送生成电路445生成的总线命令，以使生成的总线命令被主机处理器接收。
在一些实施例中，第一控制器443还被配置为将从目标地址读取的数据发送给生成电路445，以由生成电路445生成对应的总线命令，并由发送电路446将生成的总线命令发送给总线接口电路410。
作为一种实施方式，从外设模块430读取数据的示例说明如下。总线接口电路410接收主机处理器的读命令，并将读命令发送给接收电路441。接收电路441接收读命令，并将读命令发送给解析电路442。解析电路442从读命令中解析得到目标地址。第一控制器443通过第一总线450从目标地址对应的外设模块430的寄存器读取数据。第一控制器443将读取的数据发送给生成电路445。生成电路445生成读命令对应的总线命令，并将该总线命令发送给发送电路446。发送电路446向总线接口电路410发送该总线命令。总线接口电路410向主机处理器发送该总线命令，以使主机处理器接收总线命令以获得读取的数据。
在一些实施例中，如图6所示，电路系统440还包括：第二控制器447，被配置为通过第三总线470接收处理器420发送的信息。
在一些实施例中，第二控制器447，还被配置为通过第三总线470接收处理器420发送的中断信息，将中断信息发送给生成电路445，以由生成电路445生成对应的总线命令，并由发送电路446将生成的总线命令发送给总线接口电路410，从而通过总线接口电路410向主机处理器发送中断信息。
作为一种实施方式，处理器420向主机处理器发送外设模块430的中断信息的示例说明如下。处理器420检测外设模块430的中断信息。处理器420通过第三总线470将检测到的中断信息发送给生成电路445。生成电路445生成中断信息对应的总线命令。发送电路446向总线接口电路410发送生成电路445生成的该总线命令。总线接口电路410向主机处理器发送该总线命令，以使主机处理器接收总线命令以获得中断信息。作为一种示例，主机处理器获取到中断信息后，基于中断信息响应嵌入式控制电路。在一些示例中，主机处理器基于中断信息发起向中断信息对应的外设模块430的寄存器写入数据的过程。在一些示例例中，主机处理器基于中断信息发起从中断信息对应的外设模块430的寄存器读取数据的过程。
在一些实施例中，电路系统440还包括：安全控制模块448，与第一控制器443和第二控制器447连接。安全控制模块448被配置为提供权限信息。第一控制器443，还被配置为基于安全控制模块448中的权限信息确定访问目标地址的权限。作为一种实施方式，第二控制器447，还被配置为通过第三总线470接收处理器420发送的权限信息，将权限信息写 入安全控制模块448。在本实施例中，每个目标地址可被配置允许读和写，或者允许读取和禁止写入，或者允许写入和禁止读取，本实施对此不作限定。
作为一种实施方式，在权限控制下向外设模块430写入数据的示例说明如下。总线接口电路410接收主机处理器的写命令，并将写命令发送给接收电路441。接收电路441接收写命令，并将写命令发送给解析电路442，作为一种示例，接收电路441可将写命令缓存到缓冲模块444，解析电路442从缓冲模块444获取写命令。解析电路442从写命令中解析得到目标地址和待写入的数据。第一控制器443判断目标地址是否为允许写入的地址，在目标地址为允许写入的地址的情况下，第一控制器443通过第一总线450向目标地址对应的外设模块430的寄存器写入上述数据。在一些示例中，第一控制器443可访问安全控制模块448，从安全控制模块448获取权限信息，基于权限信息确定目标地址是否为允许写入的地址。在一些示例中，在目标地址为禁止写入的地址的情况下，第一控制器443通过中断信号线480向处理器420传输中断信号，以使处理器420获知主机处理器请求向禁止写入的地址写入数据。
作为一种实施方式，在权限控制下从外设模块430读取数据的示例说明如下。总线接口电路410接收主机处理器的读命令，并将读命令发送给接收电路441。接收电路441接收读命令，并将读命令发送给解析电路442，在一些示例中，接收电路441将读命令缓存到缓冲模块444，解析电路442从缓冲模块444获取读命令。解析电路442从读命令中解析得到目标地址。第一控制器443判断目标地址是否为允许读取的地址，在一些示例中，第一控制器443访问安全控制模块448，从安全控制模块448获取权限信息，基于权限信息确定目标地址是否为允许读取的地址。在目标地址为允许读取的地址的情况下，第一控制器443通过第一总线450从目标地址对应的外设模块430的寄存器读取数据。第一控制器443将读取的数据发送给生成电路445。生成电路445生成读命令对应的总线命令，并将该总线命令发送给发送电路446。发送电路446向总线接口电路410发送该总线命令。总线接口电路410向主机处理器发送该总线命令，以使主机处理器接收总线命令以获得读取的数据。在一些示例中，在目标地址为禁止读取的地址的情况下，第一控制器443通过中断信号线480向处理器420传输中断信号，以使处理器420获知主机处理器请求读取禁止读取的地址。
下面以eSPI总线为例，对本公开示例性实施例的直接存储器访问的嵌入式控制电路进行描述，主机处理器与嵌入式控制电路之间通过eSPI总线进行通信。
图7示出了本公开示例性实施例的使用eSPI总线和直接存储器访问的嵌入式控制电路的示意性框图，如图7所示，嵌入式控制电路700包括：用于与主机处理器通信的eSPI从模块710、处理器720、一个或多个外设模块730、电路系统740。本实施例中，嵌入式控 制电路可包括一个或多个外设模块730，示例性的如图7中示出了外设模块730-1至730-n。
如图7所示，电路系统740与eSPI从模块710连接，eSPI从模块710使用eSPI协议与主机处理器通信。eSPI从模块710、处理器720、外设模块730通过总线矩阵750连接，在本实施例中，总线矩阵上采用AHB总线。本实施例中eSPI从模块710、处理器720、外设模块730之间的总线可包括数据线、控制线和地址线。
在本实施例中，电路系统740通过总线矩阵750访问外设模块730。在电路系统740与外设模块730之间的AHB总线上，电路系统740作为AHB总线的主设备(master)，外设模块730作为AHB总线的从设备，外设模块730响应电路系统740的各种总线命令。
在本实施例中，处理器720通过总线矩阵750访问外设模块730。在处理器720与外设模块730之间的AHB总线上，处理器720作为AHB总线的主设备(master)，外设模块730作为AHB总线的从设备(slave)，外设模块730响应处理器720的各种总线命令。
在本实施例中，处理器720通过总线矩阵750访问电路系统740。在处理器720与电路系统740之间的AHB总线上，处理器720作为AHB总线的主设备(master)，电路系统740作为AHB总线的从设备(slave)，电路系统740响应处理器720的各种总线命令。作为一种实施方式，处理器720通过总线矩阵750访问电路系统740，以配置电路系统740对外设模块730的访问权限。作为另一种实施方式，处理器720通过总线矩阵750访问电路系统740，以向主机处理器发送外设模块730的中断信息。
在本实施例中，处理器720与电路系统740之间连接有中断信号线760。电路系统740能够通过中断信号线760向电路系统740发送中断信号。
图8示出了本公开示例性实施例的电路系统740的示意性框图，如图8所示，电路系统740包括：eSPI命令接收模块741，被配置为接收eSPI从模块710发送的总线命令；命令缓冲模块744，与eSPI命令接收模块741连接，用于缓存接收到的eSPI命令；eSPI命令解析模块742，与eSPI命令接收模块741连接，被配置为解析接收的eSPI命令，得到目标地址；AHB master接口743，与eSPI命令解析模块742连接，被配置为对目标地址对应的外设模块730的寄存器进行访问。
eSPI命令包括写命令，eSPI命令解析模块742解析eSPI命令还得到目标数据，目标地址为待写入的地址。AHB master接口743被配置为：向目标地址对应的外设模块730的寄存器写入目标数据。
作为一种实施方式，向外设模块730写入数据的示例说明如下。eSPI从模块710接收主机处理器的写命令，并将写命令发送给eSPI命令接收模块741。eSPI命令接收模块741接收写命令，并将写命令写入命令缓冲模块744。eSPI命令解析电路742从命令缓冲模块 744获取写命令，从写命令中解析得到目标地址和待写入的数据。AHB master接口743通过总线矩阵750向目标地址对应的外设模块730的寄存器写入上述数据。
如图8所示，电路系统740还包括：eSPI命令生成模块745，被配置为生成eSPI命令；eSPI命令发送模块746，与eSPI命令生成模块745连接，被配置为向eSPI从模块710发送eSPI命令生成模块745生成的eSPI命令，以使生成的eSPI命令被主机处理器接收。
eSPI命令包括读命令。AHB master接口743还被配置为：在读取数据后，将从目标地址读取的数据发送给eSPI命令生成模块745，以由eSPI命令生成模块745生成对应的eSPI命令，并由eSPI命令发送模块746将生成的eSPI命令发送给eSPI从模块710。
作为一种实施方式，从外设模块730读取数据的示例说明如下。AHB master接口743从目标地址读取数据后，AHB master接口743将读取的数据发送给eSPI命令生成模块745。eSPI命令生成模块745生成读命令对应的eSPI命令，并将该eSPI命令发送给eSPI命令发送模块746。eSPI命令发送模块746向eSPI从模块710发送该eSPI命令。eSPI从模块710向主机处理器发送该eSPI命令，以使主机处理器接收eSPI命令以获得读取的数据。
如图8所示，电路系统740还包括：AHB slave接口747，被配置为通过总线矩阵750接收处理器720发送的信息。AHB slave接口747被配置为通过总线矩阵750接收处理器720发送的中断信息，将中断信息发送给eSPI命令生成模块745，以由eSPI命令生成模块745生成对应的eSPI命令，并由eSPI命令发送模块746将生成的eSPI命令发送给eSPI从模块710，从而通过eSPI从模块710向主机处理器发送中断信息。
作为一种实施方式，处理器720向主机处理器发送外设模块730的中断信息的示例说明如下。处理器720检测外设模块730的中断信息。处理器720通过总线矩阵将检测到的中断信息发送给eSPI命令生成模块745。eSPI命令生成模块745生成中断信息对应的eSPI命令。eSPI命令发送模块746向eSPI从模块710发送eSPI命令生成模块745生成的该eSPI命令。eSPI从模块710向主机处理器发送该eSPI命令，以使主机处理器接收eSPI命令以获得中断信息。作为一种示例，主机处理器获取到中断信息后，基于中断信息响应嵌入式控制电路。在一些示例中，主机处理器基于中断信息发起向中断信息对应的外设模块730的寄存器写入数据的过程。在一些示例例中，主机处理器基于中断信息发起从中断信息对应的外设模块730的寄存器读取数据的过程。
在一些实施例中，电路系统740还包括：安全控制模块748，与AHB master接口743和AHB slave接口747连接。安全控制模块748被配置为提供权限信息。AHB master接口743，还被配置为基于安全控制模块748中的权限信息确定访问目标地址的权限。作为一种实施方式，AHB slave接口747，还被配置为通过总线矩阵750接收处理器720发送的权限 信息，将权限信息写入安全控制模块748。在本实施例中，每个目标地址可被配置允许读和写，或者允许读取和禁止写入，或者允许写入和禁止读取，本实施对此不作限定。
作为一种实施方式，在权限控制下向外设模块730写入数据的示例说明如下。eSPI从模块710接收主机处理器的写命令，并将写命令发送给eSPI命接收模块741。eSPI命接收模块741接收写命令，写命令缓存到命令缓冲模块744。eSPI命令解析模块742从命令缓冲模块744获取写命令，从写命令中解析得到目标地址和待写入的数据。AHB master接口743可访问安全控制模块748，从安全控制模块448获取权限信息，基于权限信息确定目标地址是否为允许写入的地址。在目标地址为允许写入的地址的情况下，AHB master接口743通过总线矩阵750向目标地址对应的外设模块730的寄存器写入上述数据。在目标地址为禁止写入的地址的情况下，AHB master接口743通过中断信号线760向处理器720传输中断信号，以使处理器720获知主机处理器请求向禁止写入的地址写入数据。
作为一种实施方式，在权限控制下从外设模块730读取数据的示例说明如下。eSPI从模块710接收主机处理器的读命令，并将读命令发送给eSPI命接收模块741。eSPI命接收模块741接收读命令，将读命令缓存到命令缓冲模块744。eSPI命解析模块742从命令缓冲模块744获取读命令，从读命令中解析得到目标地址。AHB master接口743访问安全控制模块748，从安全控制模块748获取权限信息，基于权限信息确定目标地址是否为允许读取的地址。在目标地址为允许读取的地址的情况下，AHB master接口743通过总线矩阵750从目标地址对应的外设模块730的寄存器读取数据。AHB master接口743将读取的数据发送给eSPI命令生成模块745。eSPI命令生成模块745生成读命令对应的eSPI命令，并将该eSPI命令发送给eSPI命令发送模块746。eSPI命令发送模块746向eSPI从模块710发送该eSPI命令。eSPI从模块710向主机处理器发送该eSPI命令，以使主机处理器接收eSPI命令以获得读取的数据。在目标地址为禁止读取的地址的情况下，AHB master接口743通过中断信号线760向处理器720传输中断信号，以使处理器720获知主机处理器请求读取禁止读取的地址。
如图7和8所示，电路系统740还包括：中断控制749，与中断信号线760连接，用于响应于AHB master接口743和/或AHB slave接口747的命令，通过中断信号线760向处理器720传输中断信号。
作为一种示例，基于eSPI从外设模块读取数据的示例说明如下。处理器720检测外设模块730的中断。在检测到外设模块730与主机处理器相关的中断的情况下，处理器720通过AHB slave接口747把中断信息写入eSPI从模块710的共享寄存器中，示例性的中断信息包括中断状态和中断ID。eSPI从模块710接收该写入信息，通过拉低IO管脚或者专 用的Alert信号报警。主机处理器接收报警信号，通过GET_STATUS命令查询报警事件原因。eSPI从模块710接收GET_STATUS命令，把共享寄存器中的中断信息通过eSPI包发给主机处理器。主机处理器基于中断信息确定报警原因，主机处理器发起GET_PC或GET_NP命令来读数据。eSPI从模块710接收该命令，电路系统740把该命令转化为DMA操作，从相应的外设模块730的寄存器中把数据读回，eSPI从模块710通过eSPI包上传给主机处理器。
例如，对于键盘而言，当操作员按下键盘，键盘扫描模块检测到并保持按下的按键的键码，并发起中断给处理器720，处理器720查询中断ID来自键盘扫描模块、中断原因(或中断状态)是操作员有按键操作后，处理器720通过AHB slave接口747把中断ID和中断状态写入eSPI从模块710的共享寄存器中，eSPI从模块710收到该写入信息后，通过拉低IO管脚或者专用的Alert信号报警。主机处理器收到报警信号后，通过GET_STATUS命令查询报警事件原因，eSPI从模块710收到GET_STATUS命令后，把共享寄存器中的中断ID和中断状态通过eSPI包发给主机处理器。当获知由于操作员按下键盘原因后，主机处理器发起GET_PC/NP命令读操作员按下键的键码，eSPI从模块710收到该命令后，电路系统740把该命令转化为DMA操作，把键盘扫描模块保持的键码读回，并通过eSPI从模块710发送eSPI包上传给主机处理器。
作为一种示例，基于eSPI的向外设模块730写入数据说明如下。主机处理器发送写命令。eSPI从模块710接收写命令，电路系统740从写命令中获取写入地址和数据，向写入地址对应的外设模块730的寄存器写入该数据。
例如，对于氛围灯而言，当主机处理器要把灯效果数据发到氛围灯上显示，主机处理器先发起数据写操作，发起写数据包，eSPI从模块710接收该包，电路系统740解包发现是对氛围灯某个寄存器的写命令后，把该命令转化为DMA操作，把主机处理器传来的数据写入到指定的氛围灯地址中，氛围灯因此改变显示状态，完成主机处理器要求的显示效果。示例性的，氛围灯在工作中可能会产生中断，比如没有数据显示的情况下(数据缓存为空)，又比如氛围灯显示出现错误的情况下。当氛围灯产生中断，和键盘一样，发起中断给处理器720，处理器720进而通过eSPI从模块710向主机处理器报警，主机处理器查询报警原因，并读取相关的数据。
本公开实施例提供了一种基于直接存储器访问和共享接口的嵌入式控制电路。
图9示出了本公开示例性实施例的基于直接存储器访问和共享接口的嵌入式控制电路的示意性框图，如图9所示，嵌入式控制电路900包括：用于与主机处理器通信的总线接口电路910、处理器920、一个或多个第一外设模块931、一个或多个第二外设模块932、 电路系统940；第一总线951、第二总线952和第三总线961。其中，多个第一外设模块931在图9中标记为931-1至931-n，多个第二外设模块931在图9中标记为932-1至932-m。应当理解，本实施例对第一外设模块931和第二外设模块932的数量不作限定，嵌入式控制电路900可包括任意数量的第一外设模块931和第二外设模块932。
在一些实施例中，嵌入式控制电路900还包括：第四总线962，连接在处理器920与电路系统940之间，以在处理器920与电路系统940之间传输信息。
在一些实施例中，嵌入式控制电路900还包括：中断信号线，连接在处理器920与电路系统940之间。中断信号线可被配置为传输处理器920与电路系统940之间的任何中断信号，本实施例对此不作限定。作为一种实施方式，电路系统940被配置为通过中断信号线980向处理器920传输中断信号。可参见图4及其说明，本实施例对此不作赘述。
第一外设模块931中的每个第一外设模块931包括第一接口和第二接口。第一总线951连接在每个第一外设模块931的第一接口与总线接口电路910之间。第二总线952连接在每个第一外设模块931的第二接口与处理器920之间。总线接口电路910上设置每个第一外设模块931对应的I/O接口。总线接口电路910，被配置为通过第一总线951访问第一外设模块931。处理器920被配置为通过第二总线952访问第一外设模块931。
第三总线961连接在第二外设模块932与电路系统940之间。第三总线961还连接在第二外设模块932与处理器920之间。电路系统940，被配置为通过总线接口电路910与主机处理器通信，基于主机处理器的命令通过第三总线961访问第二外设模块932。在本实施例中，电路系统940作为第三总线961的主设备，第二外设模块932作为第三总线961的从设备，第二外设模块932可响应电路系统940的各种总线命令。处理器920通过第三总线961访问第二外设模块932。在本实施例中，处理器920可作为第三总线961的主设备，第二外设模块932可作为第三总线961的从设备，第二外设模块932可响应处理器920的各种总线命令。
在一些实施例中，第一总线951、第二总线952、第三总线961和第四总线962中至少部分可采用总线矩阵，总线接口电路910、处理器920、第一外设模块931、第二外设模块932及电路系统940中至少部分之间通过总线矩阵进行访问。
在本实施例中，第一外设模块931，可参见本公开前述图1、图2和图3的说明，在此不作赘述。在本实施例中，电路系统940和第二外设模块932可参见本公开前述图4、图6、图7和图8的说明，在此不作赘述。
在本实施例中，主机处理器可通过总线接口电路910和第一总线951访问第一外设模块931。主机处理器还可通过总线接口电路910、电路系统940和第三总线961访问第二外 设模块932。下面对嵌入式控制电路900区分主机处理器对第一外设模块931和第二外设模块932的访问的实施例进行说明。
在一些实施例中，总线接口电路910被配置为：基于访问的目标地址确定主机处理器访问的是第一外设模块931还是第二外设模块932，在主机处理器访问第一外设模块931的情况下，通过第一总线951访问第一外设模块931；在主机处理器访问第二外设模块932的情况下，向电路系统940转发主机处理器的访问命令。电路系统940基于主机处理器的访问命令，通过第三总线961访问第二外设模块932。
在一些实施例中，电路系统被940配置为：基于访问的目标地址确定主机处理器访问的是否为第二外设模块932；在主机处理器访问第二外设模块932的情况下，基于主机处理器的命令，通过第三总线961访问第二外设模块932。
在一些实施例中，每个第一外设模块931，被配置为：基于访问的目标地址确定主机处理器访问的是否为自身；在主机处理器访问自身的情况下，响应主机处理器的访问。
图10示出了本公开示例性实施例的基于直接存储器访问和共享接口的外设访问方法的流程图，应用于图9所示的嵌入式控制电路900。该外设访问方法包括步骤S1001至步骤S1004。应当理解，图10中虽然标记了步骤编号，但本实施例对步骤S1001至步骤S1004的顺序不作限定。
在步骤S1001中，由总线接口电路910通过第一总线951访问第一外设模块931。在本实施例中，总线接口电路910通过第一总线951访问第一外设模块931包括对第一外设模块931的寄存器进行读和/或写。在本实施例中，第一总线951连接在总线接口电路910与第一外设模块931的第一接口之间，总线接口电路910通过第一总线951及第一外设模块931的第一接口访问第一外设模块931的寄存器。
作为一种实施方式，在步骤S1001中，总线接口电路910接收主机处理器的写命令，通过第一总线951向写命令对应的第一外设模块931的寄存器写入数据。总线接口电路910还可接收主机处理器的读命令，通过第一总线951从读命令对应的第一外设模块931的寄存器读取数据。
在步骤S1002中，由电路系统940通过总线接口电路910与主机处理器通信，基于主机处理器的命令通过第三总线961访问第二外设模块932。
作为一种实施方式，在步骤S1002中，电路系统940通过总线接口电路910接收主机处理器的写命令，基于写命令通过第三总线961向写命令对应的第二外设模块932的寄存器写入数据。电路系统940还可通过总线接口电路910接收主机处理器的读命令，基于读命令通过第三总线961从读命令对应的第二外设模块932的寄存器读取数据。
在一些实施例中，电路系统940基于预先配置的权限访问第二外设模块932。在本实施例中，每个目标地址可被配置允许读和写，或者允许读取和禁止写入，或者允许写入和禁止读取，本实施对此不作限定。作为一种实施方式，处理器920通过连接在处理器920与电路系统940之间的第四总线962配置电路系统940访问第二外设模块932的权限。电路系统940基于处理器920配置的权限信息访问第二外设模块932。
作为一种实施方式，在权限控制下在权限控制下向第二外设模块932写入数据的示例说明如下。总线接口电路910接收主机处理器的写命令，并将写命令发送给电路系统940。电路系统940接收写命令，从写命令中解析得到目标地址和待写入的数据。电路系统940判断目标地址是否为允许写入的地址，在目标地址为允许写入的地址的情况下，电路系统940通过第三总线961向目标地址对应的第二外设模块932的寄存器写入上述数据。在一些示例中，在目标地址为禁止写入的地址的情况下，电路系统940通过电路系统940与处理器920之间的中断信号线向处理器920传输中断信号，以通知处理器920主机处理器请求访问禁止写入的寄存器。
作为一种实施方式，在权限控制下从第二外设模块932读取数据的示例说明如下。总线接口电路910接收主机处理器的读命令，并将读命令发送给电路系统940。电路系统940接收读命令，并从读命令中解析得到目标地址。电路系统940判断目标地址是否为允许读取的地址。在目标地址为允许读取的地址的情况下，电路系统940通过第三总线961从目标地址对应的第二外设模块932的寄存器读取数据。电路系统940在读取的数据后，生成读命令对应的总线命令，向总线接口电路910发送该总线命令。总线接口电路910向主机处理器发送该总线命令，以使主机处理器接收总线命令以获得读取的数据。在一些示例中，在目标地址为禁止读取的地址的情况下，电路系统940通过电路系统940与处理器920之间的中断信号线向处理器920传输中断信号，以通知处理器920主机处理器请求访问禁止读取的寄存器。
在步骤S1003中，由处理器920通过第二总线952访问第一外设模块931。在本实施例中，处理器920通过第二总线952从第一外设模块931的寄存器读取数据。处理器920还可通过第二总线952向第一外设模块931的寄存器写入数据。
在步骤S1004中，由处理器920通过第三总线961访问第二外设模块932。在一些示例中，由处理器920通过第三总线961访问第二外设模块932可包括：由处理器920通过第三总线961访问对第二外设模块932的寄存器进行读和/或写。
在一些实施例中，由处理器920通过其与电路系统940之间的总线，向电路系统940发送第二外设模块932的中断信息。由电路系统940通过总线接口电路910向主机处理器 发送中断信息。
作为一种实施方式，处理器920向主机处理器发送第二外设模块932的中断信息的示例说明如下。处理器920检测第二外设模块932的中断信息。处理器920通过其与电路系统940之间的总线，将检测到的中断信息发送给电路系统940。电路系统940生成中断信息对应的总线命令，向总线接口电路910发送生成的该总线命令。总线接口电路910向主机处理器发送该总线命令，以使主机处理器接收总线命令以获得中断信息。作为一种示例，主机处理器获取到中断信息后，基于中断信息响应嵌入式控制电路。在一些示例中，主机处理器基于中断信息发起向中断信息对应的第二外设模块932的寄存器写入数据的过程。在一些示例中，主机处理器基于中断信息发起从中断信息对应的第二外设模块932的寄存器读取数据的过程。
下面以eSPI总线为例，对本公开示例性实施例的直接存储器访问和共享接口的嵌入式控制电路进行描述，主机处理器与嵌入式控制电路之间通过eSPI总线进行通信。
图11示出了本公开示例性实施例的使用eSPI总线的基于直接存储器访问和共享接口的嵌入式控制电路的示意性框图，如图11所示，嵌入式控制电路1100包括：用于与主机处理器通信的eSPI从模块1110、处理器1120、一个或多个第一外设模块1131、一个或多个第二外设模块1132、电路系统1140和总线矩阵1150。其中，多个第一外设模块1131在图11中标记为1131-1至1131-n，多个第二外设模块1132在图11中标记为1132-1至1132-m。本实施中采用总线矩阵，下面结合图11对本实施例进行描述。
第一外设模块1131中的每个第一外设模块1131包括第一接口和第二接口。(local bus)连接在每个第一外设模块1131的第一接口与eSPI从模块1110之间。每个第一外设模块1131的第二接口与APB总线连接，处理器1120与总线矩阵1150连接，APB总线经第一桥、第一快速总线连接到总线矩阵，进而将每个第一外设模块1131的第二接口与处理器1120连接。eSPI从模块1110，被配置为通过本地总线访问第一外设模块1131。处理器1120被配置为通过总线矩阵、第一快速总线、第一桥以及APB总线访问第一外设模块1131。
电路系统1140连接到DMA总线，DMA总线连接到总线矩阵1150，第二外设模块1132连接到第二快速总线，第二快速总线连接到总线矩阵，进而第二外设模块1132与电路系统1140之间通过DMA总线、总线矩阵1150和第二快速总线连接。处理器1120连接到总线矩阵，第二外设模块1132与处理器1120之间通过总线矩阵1150和第二快速总线。电路系统1140，被配置为通过eSPI从模块1110与主机处理器通信，基于主机处理器的命令通过DMA总线、总线矩阵1150和第二快速总线访问第二外设模块1132。在本实施例中，电路系统1140作为主设备，第二外设模块1132作为从设备，第二外设模块1132可响应电路系 统1140的各种总线命令。处理器1120通过总线矩阵1150和第二快速总线访问第二外设模块1132。在本实施例中，处理器1120可作为主设备，第二外设模块1132可作为从设备，第二外设模块1132可响应处理器1120的各种总线命令。
在本实施例中，一些第二外设模块1132可直接连接到第二快速总线，例如如图11所示的第二外设模块1132-1，第二外设模块1132的示例可包括PD/Type C接口等。一些第二外设模块1132可通过第二桥连接到第二快速总线，例如如图11所示的第二外设模块1132-2至1132-m，第二外设模块1132-2至1132-m的示例包括氛围灯控制模块、呼吸灯控制模块等。应当理解，本实施例对第二外设模块1132是否经过桥连接到第二快速总线做不限定。
在本实施例中，第一外设模块1131，可参见本公开前述图1、图2和图3的说明，在此不作赘述。在本实施例中，电路系统1140和第二外设模块1132可参见本公开前述图4、图6、图7和图8的说明，在此不作赘述。
在本实施例中，主机处理器可通过eSPI从模块1110和本地总线访问第一外设模块1131。主机处理器还可通过eSPI从模块1110、电路系统1140、DMA总线、总线矩阵1150和第二快速总线访问第二外设模块1132。下面对嵌入式控制电路1100区分主机处理器对第一外设模块1131和第二外设模块1132的访问的实施例进行说明。
在一些实施例中，eSPI从模块1110被配置为：基于访问的目标地址确定主机处理器访问的是第一外设模块1131还是第二外设模块1132，在主机处理器访问第一外设模块1131的情况下，通过本地总线访问第一外设模块1131；在主机处理器访问第二外设模块1132的情况下，向电路系统1140转发主机处理器的访问命令。电路系统1140基于主机处理器的访问命令，通过DMA总线、总线矩阵1150和第二快速总线访问第二外设模块1132。
在一些实施例中，电路系统被1140配置为：基于访问的目标地址确定主机处理器访问的是否为第二外设模块1132；在主机处理器访问第二外设模块1132的情况下，基于主机处理器的命令，通过DMA总线、总线矩阵1150和第二快速总线访问第二外设模块1132。
在一些实施例中，每个第一外设模块1131，被配置为：基于访问的目标地址确定主机处理器访问的是否为自身；在主机处理器访问自身的情况下，响应主机处理器的访问。
本公开实施例提供了一种双总线接口的嵌入式控制电路。
图12示出了本公开示例性实施例的双总线接口的嵌入式控制电路的示意性框图，如图12所示，嵌入式控制电路1200包括：一个或多个外设模块1230；处理器1220，与一个或多个外设模块1230连接；第一总线接口电路1211，与一个或多个外设模块1230连接；第二总线接口电路1212，与一个或多个外设模块1230连接；总线接口选择电路1213，被配 置为与主机处理器通信，并可操作地将第一总线接口电路1211或第二总线接口电路1212连接至主机处理器。
在本实施例中，第一总线接口电路1211或第二总线接口电路1212可采用各种类型的总线接口与主机处理器通信，包括但不限于LPC总线、SPI总线、eSPI总线等。示例性的，第一总线接口电路1211可为LPC电路，第二总线接口电路1212可为eSPI电路，由此嵌入式控制电路1200可通过LPC总线协议或eSPI总线协议与主机处理器通信。应当理解，第一总线接口电路1211和第二总线接口电路1212可采用任意两种总线协议的组合，本实施例对此不作限定。
在一些实施例中，总线接口选择电路1213，被配置为基于初始化配置，将第一总线接口电路1211或第二总线接口电路1212连接至主机处理器。经过初始化配置，将嵌入式控制电路1200配置为通过第一总线接口电路1211和第二总线接口电路1212中的一个总线接口电路与主机处理器通信。总线接口选择电路1213基于初始化配置将第一总线接口电路1211和第二总线接口电路1212中的一个总线接口电路连接至主机处理器，由此通过配置的总线接口电路与主机处理器通信。
在一些实施例中，外设模块1230，包括：一个或多个第一外设模块，一个或多个第一外设模块中的每个第一外设模块包括第一接口和第二接口。每个第一外设模块的第一接口与第一总线接口电路及第二总线接口电路之间，通过第一总线连接；每个第一外设模块的第二接口与处理器之间，通过第二总线连接。第一总线接口电路1211及第二总线接口电路1212，被配置为通过第一总线访问一个或多个第一外设模块。处理器1220，被配置为通过第二总线访问一个或多个第一外设模块。
本实施例中，第一外设模块可参见本公开前述图1、图2和图3的说明，在此不作赘述。
在一些实施例中，外设模块1230包括：一个或多个第二外设模块。嵌入式控制电路还包括：电路系统。一个或多个第二外设模块与电路系统之间，通过第三总线连接。一个或多个第二外设模块与处理器1120之间，通过第三总线连接。电路系统，被配置为通过第一总线接口电路1211或第二总线接口电路1212与主机处理器通信，基于主机处理器的命令通过第三总线访问一个或多个第二外设模块；处理器1220，被配置为通过第三总线访问一个或多个第二外设模块。
在本实施例中，电路系统和第二外设模块可参见本公开前述图4、图6、图7和图8的说明，在此不作赘述。
在一些实施例中，外设模块1230包括一个或多个第一外设模块和一个或多个第二外设模块。在本实施例中，主机处理器可通过第一总线接口电路1211或第二总线接口电路1212 和第一总线访问第一外设模块。主机处理器还可通过第一总线接口电路1211或第二总线接口电路1212、电路系统和第三总线访问第二外设模块。下面对嵌入式控制电路1200区分主机处理器对第一外设模块和第二外设模块的访问的实施例进行说明。
作为一种实施方式，第一总线接口电路1211和/或第二总线接口电路1212被配置为：基于访问的目标地址确定主机处理器访问的是第一外设模块还是第二外设模块；在主机处理器访问一个或多个第一外设模块的情况下，通过第一总线访问一个或多个第一外设模块；在主机处理器访问一个或多个第二外设模块的情况下，向电路系统转发主机处理器的访问命令。电路系统通过第三总线访问第二外设模块。
作为一种实施方式，电路系统被配置为：基于访问的目标地址确定主机处理器访问的是否为一个或多个第二外设模块；在主机处理器访问一个或多个第二外设模块的情况下，基于主机处理器的命令通过第三总线访问一个或多个第二外设模块。
下面以LPC和eSPI总线为例，对本公开示例性实施例的嵌入式控制电路进行描述，主机处理器与嵌入式控制电路之间通过eSPI或LPC总线进行通信。
图13示出了本公开示例性实施例的LPC-eSPI双总线接口的嵌入式控制电路的示意性框图，如图13所示，嵌入式控制电路1300包括：外设模块；处理器1320，与外设模块连接；LPC从模块1311，与一个或多个外设模块连接；eSPI从模块1312，与一个或多个外设模块连接；LPC-eSPI接口选择器1313，被配置为与主机处理器通信，并可操作地将LPC从模块1311或eSPI从模块1312连接至主机处理器；电路系统1340。其中，外设模块包括：一个或多个第一外设模块1331和一个或多个第二外设模块1332，图13中标记为第一外设模块1331-1至1331-n，第二外设模块1332-1至1332-m。
在一些实施例中，LPC-eSPI接口选择器1313，被配置为基于初始化配置，将LPC从模块1311或eSPI从模块1312连接至主机处理器。经过初始化配置，将嵌入式控制电路1300配置为通过LPC从模块1311和eSPI从模块1312中的一个总线接口电路与主机处理器通信。LPC-eSPI接口选择器1313基于初始化配置将LPC从模块1311和eSPI从模块1312中的一个总线接口电路连接至主机处理器，由此通过配置的总线接口电路与主机处理器通信。
在本实施例中，每个第一外设模块1331包括第一接口和第二接口。每个第一外设模块1331的第一接口与LPC从模块1311及eSPI从模块1312之间，通过本地总线(local bus)连接。每个第一外设模块1331的第二接口与处理器之间，通过APB总线、第一桥、第一快速总线以及总线矩阵1350连接。LPC从模块1311及eSPI从模块1312通过本地总线访问一个或多个第一外设模块1331。处理器1320通过总线矩阵1350第一快速总线、第一桥以及APB总线访问第一外设模块1331。
本实施例中，第一外设模块1331可参见本公开前述图1、图2和图3的说明，在此不作赘述。
在本实施例中，第二外设模块1332与电路系统1340之间，通过DMA总线、总线矩阵1350、第二快速总线连接。第二外设模块1332与处理器1320之间，通过总线矩阵1350、第二快速总线连接。电路系统1340通过LPC从模块1311或eSPI从模块1312与主机处理器通信，基于主机处理器的命令通过DMA总线、总线矩阵以及第二快速总线第二外设模块1332，处理器1320通过总线矩阵1350、第二快速总线访问第二外设模块1332。
在一些实施例中，处理器1320还可通过总线矩阵1350、第一桥、APB总线访问电路系统1340。处理器1320与电路系统1340之间可通过总线矩阵1350、第一桥、APB总线传输信息，例如，处理器1320可在该线路上向电路系统1340传输访问第二外设模块1332的权限信息。
在本实施例中，电路系统1340和第二外设模块1332可参见本公开前述图4、图6、图7和图8的说明，在此不作赘述。
在本实施例中，主机处理器可通过LPC从模块1311或eSPI从模块1312和本地总线访问第一外设模块1331。主机处理器还可通过LPC从模块1311或eSPI从模块1312、电路系统1340和DMA总线、总线矩阵1350以及第二快速总线访问第二外设模块1332。下面对嵌入式控制电路1300区分主机处理器对第一外设模块1331和第二外设模块1332的访问的实施例进行说明。
作为一种实施方式，LPC从模块1311和/或eSPI从模块1312被配置为：基于访问的目标地址确定主机处理器访问的是第一外设模块1331还是第二外设模块1332；在主机处理器访问一个或多个第一外设模块1331的情况下，通过第一总线访问一个或多个第一外设模块1331；在主机处理器访问一个或多个第二外设模块1332的情况下，向电路系统1340转发主机处理器的访问命令。电路系统1340通过DMA总线、总线矩阵1350以及第二快速总线访问第二外设模块1332。
作为一种实施方式，电路系统1340被配置为：基于访问的目标地址确定主机处理器访问的是否为一个或多个第二外设模块1332；在主机处理器访问一个或多个第二外设模块1332的情况下，基于主机处理器的命令通过DMA总线、总线矩阵1350以及第二快速总线访问一个或多个第二外设模块1332。
作为一种实施方式，每个第一外设模块1331，被配置为：基于访问的目标地址确定主机处理器访问的是否为自身；在主机处理器访问自身的情况下，响应主机处理器的访问。
本公开示例性实施还提供了一种芯片，可包括本公开前述的嵌入式控制电路。
本公开的方案可被集成到如下电子设备中，该电子设备选自由以下各项组成的组：机顶盒；娱乐单元；导航设备；通信设备；固定位置数据单元；移动位置数据单元；全球定位系统(GPS)设备；移动电话；蜂窝电话；智能电话；会话发起协议(SIP)电话；平板电脑；平板手机；服务器；计算机；便携式计算机；移动计算设备；可穿戴计算设备；台式计算机；个人数字助理(PDA)；监视器；计算机监视器；电视机；调谐器；收音机；卫星无线电；音乐播放器；数字音乐播放器；便携式音乐播放器；数字视频播放器；视频播放器；数字视频光盘(DVD)播放器；便携式数字视频播放器；机动车；车辆组件；航空电子系统；无人机；以及多旋翼飞行器。
以上所述仅为本公开的示例性实施例而已，并不用以限制本公开，凡在本公开实质内容上所作的任何修改、等同替换和简单改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种嵌入式控制电路，包括：
    用于与主机处理器通信的总线接口电路；
    处理器；
    一个或多个外设模块；
    电路系统，与所述总线接口电路连接；
    第一总线，连接在所述一个或多个外设模块与所述电路系统之间；
    第二总线，连接在所述一个或多个外设模块与所述处理器之间；
    其中：
    所述电路系统被配置为：通过所述总线接口电路与所述主机处理器通信，基于所述主机处理器的命令通过所述第一总线访问所述一个或多个外设模块；
    所述处理器被配置为通过所述第二总线访问所述一个或多个外设模块。
  2. 根据权利要求1所述的嵌入式控制电路，其中，还包括：第三总线，连接在所述处理器与所述电路系统之间。
  3. 根据权利要求2所述的嵌入式控制电路，其中，所述处理器被配置为通过所述第三总线向所述电路系统发送所述一个或多个外设模块的中断信息；所述电路系统被配置为通过所述总线接口电路向主机处理器发送所述中断信息。
  4. 根据权利要求2所述的嵌入式控制电路，其中，所述处理器被配置为通过所述第三总线配置所述电路系统访问所述一个或多个外设模块的权限。
  5. 根据权利要求1所述的嵌入式控制电路，其中，所述电路系统被配置为：基于预先配置的权限访问所述一个或多个外设模块。
  6. 根据权利要求1所述的嵌入式控制电路，其中，还包括：中断信号线，连接在所述处理器与所述电路系统之间。
  7. 根据权利要求6所述的嵌入式控制电路，其中，所述电路系统被配置为通过所述中断信号线向所述处理器传输中断信号。
  8. 根据权利要求7所述的嵌入式控制电路，其中，所述电路系统被配置为：在所述主机处理器访问的外设模块的寄存器被配置为禁止访问的情况下，通过所述中断信号线向所述处理器传输中断信号。
  9. 根据权利要求1所述的嵌入式控制电路，其中，所述电路系统，被配置为：
    通过所述总线接口电路接收所述主机处理器的写命令，基于所述写命令通过所述第一总线向所述写命令对应的外设模块的寄存器写入数据；和/或
    通过所述总线接口电路接收所述主机处理器的读命令，基于所述读命令通过所述第一总线从所述读命令对应的外设模块的寄存器读取数据。
  10. 根据权利要求1至9中任一项所述的嵌入式控制电路，其中，所述电路系统包括：
    接收电路，被配置为接收所述总线接口电路发送的总线命令；
    解析电路，被配置为解析接收的总线命令，得到目标地址；
    第一控制器，被配置为对所述目标地址对应的外设模块的寄存器进行访问。
  11. 根据权利要求10所述的嵌入式控制电路，其中，在所述总线命令为写命令时，所述解析电路还得到目标数据；
    其中，所述第一控制器被配置为：向所述目标地址对应的外设模块的寄存器写入所述目标数据。
  12. 根据权利要求10所述的嵌入式控制电路，其中，所述电路系统，还包括：
    生成电路，被配置为生成总线命令；
    发送电路，被配置为向所述总线接口电路发送生成的总线命令，以使生成的总线命令被所述主机处理器接收。
  13. 根据权利要求12所述的嵌入式控制电路，其中，所述第一控制器还被配置为：将从所述目标地址读取的数据发送给所述生成电路，以由所述生成电路生成对应的总线命令，并由所述发送电路将生成的总线命令发送给所述总线接口电路。
  14. 根据权利要求12所述的嵌入式控制电路，其中，所述电路系统，还包括：第二控制器，被配置为通过第三总线接收所述处理器发送的信息。
  15. 根据权利要求14所述的嵌入式控制电路，其中，所述第二控制器，还被配置为通过所述第三总线接收所述处理器发送的中断信息，将所述中断信息发送给所述生成电路，以由所述生成电路生成对应的总线命令，并由所述发送电路将生成的总线命令发送给所述总线接口电路。
  16. 根据权利要求14所述的嵌入式控制电路，其中，所述电路系统，还包括：安全控制模块，与所述第一控制器和所述第二控制器连接；
    其中，所述第二控制器，还被配置为通过第三总线接收所述处理器发送的权限信息，将所述权限信息写入所述安全控制模块；
    所述第一控制器，还被配置为基于所述安全控制模块中的权限信息确定访问所述目标地址的权限。
  17. 根据权利要求1所述的嵌入式控制电路，其中，所述总线接口电路，包括：一个总线接口或多个总线接口。
  18. 一种外设访问方法，应用于嵌入式控制电路，所述嵌入式控制电路包括：总线接口电路、处理器、一个或多个外设模块和电路系统，其中，所述外设访问方法包括：
    由所述电路系统通过所述总线接口电路与所述主机处理器通信，基于所述主机处理器的命令通过第一总线访问所述一个或多个外设模块，其中，所述第一总线连接在所述一个或多个外设模块与所述电路系统之间；
    由所述处理器通过第二总线访问所述一个或多个外设模块，其中，所述第二总线连接在所述一个或多个外设模块与所述处理器之间。
  19. 一种芯片，包括根据权利要求1至17中任一项所述的嵌入式控制电路。
  20. 一种电子设备，包括：根据权利要求1至17中任一项所述的嵌入式控制电路或根据权利要求19所述的芯片。
PCT/CN2022/138404 2021-12-29 2022-12-12 一种直接存储器访问的嵌入式控制电路、芯片和电子设备 WO2023124940A1 (zh)

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114281722B (zh) * 2021-12-29 2024-04-05 合肥市芯海电子科技有限公司 一种双总线接口的嵌入式控制电路、芯片和电子设备
CN114297105B (zh) * 2021-12-29 2024-04-05 合肥市芯海电子科技有限公司 一种直接存储器访问的嵌入式控制电路、芯片和电子设备

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387645A (zh) * 1999-11-05 2002-12-25 模拟装置公司 通讯处理器的总线结构和共享总线判优方法
CN1763734A (zh) * 2005-11-10 2006-04-26 苏州国芯科技有限公司 一种基于amba总线的8051系列微处理器应用系统
US20080065837A1 (en) * 2006-09-07 2008-03-13 Sodick Co., Ltd. Computerized numerical control system with human interface using low cost shared memory
CN102122367A (zh) * 2010-01-07 2011-07-13 上海华虹集成电路有限责任公司 一种大容量sim卡系统架构
CN103885908A (zh) * 2014-03-04 2014-06-25 中国科学院计算技术研究所 一种基于外部设备可访问寄存器的数据传输系统及其方法
CN112035398A (zh) * 2020-08-25 2020-12-04 青岛信芯微电子科技股份有限公司 一种系统级芯片SoC及适用于SoC的数据处理方法
CN114281722A (zh) * 2021-12-29 2022-04-05 合肥市芯海电子科技有限公司 一种双总线接口的嵌入式控制电路、芯片和电子设备
CN114297111A (zh) * 2021-12-29 2022-04-08 合肥市芯海电子科技有限公司 一种嵌入式控制电路、芯片、外设访问方法和电子设备
CN114297105A (zh) * 2021-12-29 2022-04-08 合肥市芯海电子科技有限公司 一种直接存储器访问的嵌入式控制电路、芯片和电子设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260098B1 (en) * 1998-12-17 2001-07-10 International Business Machines Corporation Shared peripheral controller
US6658502B1 (en) * 2000-06-13 2003-12-02 Koninklijke Philips Electronics N.V. Multi-channel and multi-modal direct memory access controller for optimizing performance of host bus
US7089339B2 (en) * 2001-03-16 2006-08-08 National Semiconductor Corporation Sharing of functions between an embedded controller and a host processor
US8607089B2 (en) * 2011-05-19 2013-12-10 Intel Corporation Interface for storage device access over memory bus
CN104636271B (zh) * 2011-12-22 2018-03-30 英特尔公司 访问命令/地址寄存器装置中存储的数据
CN103389963B (zh) * 2012-05-09 2016-08-31 北京兆易创新科技股份有限公司 一种嵌入式系统控制器
CN103914424B (zh) * 2014-04-14 2016-08-03 中国人民解放军国防科学技术大学 基于gpio接口的lpc外设扩展方法及装置
US10452582B2 (en) * 2015-06-08 2019-10-22 Nuvoton Technology Corporation Secure access to peripheral devices over a bus
US11086812B2 (en) * 2015-12-26 2021-08-10 Intel Corporation Platform environment control interface tunneling via enhanced serial peripheral interface
CN105791770A (zh) * 2016-03-14 2016-07-20 路亮 基于arm9的嵌入式视频采集系统
US10916280B2 (en) * 2018-03-15 2021-02-09 Dell Products, L.P. Securely sharing a memory between an embedded controller (EC) and a platform controller hub (PCH)
CN110008162B (zh) * 2019-03-26 2022-05-17 西安微电子技术研究所 一种缓冲接口电路及基于该电路传输数据的方法和应用
US11163659B2 (en) * 2019-04-25 2021-11-02 Intel Corporation Enhanced serial peripheral interface (eSPI) signaling for crash event notification

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1387645A (zh) * 1999-11-05 2002-12-25 模拟装置公司 通讯处理器的总线结构和共享总线判优方法
CN1763734A (zh) * 2005-11-10 2006-04-26 苏州国芯科技有限公司 一种基于amba总线的8051系列微处理器应用系统
US20080065837A1 (en) * 2006-09-07 2008-03-13 Sodick Co., Ltd. Computerized numerical control system with human interface using low cost shared memory
CN102122367A (zh) * 2010-01-07 2011-07-13 上海华虹集成电路有限责任公司 一种大容量sim卡系统架构
CN103885908A (zh) * 2014-03-04 2014-06-25 中国科学院计算技术研究所 一种基于外部设备可访问寄存器的数据传输系统及其方法
CN112035398A (zh) * 2020-08-25 2020-12-04 青岛信芯微电子科技股份有限公司 一种系统级芯片SoC及适用于SoC的数据处理方法
CN114281722A (zh) * 2021-12-29 2022-04-05 合肥市芯海电子科技有限公司 一种双总线接口的嵌入式控制电路、芯片和电子设备
CN114297111A (zh) * 2021-12-29 2022-04-08 合肥市芯海电子科技有限公司 一种嵌入式控制电路、芯片、外设访问方法和电子设备
CN114297105A (zh) * 2021-12-29 2022-04-08 合肥市芯海电子科技有限公司 一种直接存储器访问的嵌入式控制电路、芯片和电子设备

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