WO2023124147A1 - 一种功率模块的衬底设计方法、装置和终端设备 - Google Patents

一种功率模块的衬底设计方法、装置和终端设备 Download PDF

Info

Publication number
WO2023124147A1
WO2023124147A1 PCT/CN2022/114437 CN2022114437W WO2023124147A1 WO 2023124147 A1 WO2023124147 A1 WO 2023124147A1 CN 2022114437 W CN2022114437 W CN 2022114437W WO 2023124147 A1 WO2023124147 A1 WO 2023124147A1
Authority
WO
WIPO (PCT)
Prior art keywords
commutation
unit
path
nodes
substrate
Prior art date
Application number
PCT/CN2022/114437
Other languages
English (en)
French (fr)
Inventor
李武华
周宇
罗皓泽
郑晟
周思展
陈惠斌
Original Assignee
华为数字能源技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为数字能源技术有限公司 filed Critical 华为数字能源技术有限公司
Publication of WO2023124147A1 publication Critical patent/WO2023124147A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/06—Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging

Definitions

  • the present invention relates to the technical field of power modules, in particular to a substrate design method, device and terminal equipment of a power module.
  • heterogeneous components such as snubber capacitors are integrated into the module, which can greatly increase the power density of the power module, but it also makes the substrate design of the power module more and more complicated. Due to the wide application range and multiple power levels of power modules, it is difficult to reuse the substrate design in different application scenarios, and the existing power module substrates rely on manual design, which is time-consuming and labor-intensive.
  • an embodiment of the present application provides a power module substrate design method, device and terminal equipment, using the connection graph model to describe the relative position and connection relationship of the basic layout units, combined with the integer programming algorithm, It can realize the generation of various layouts with variable geometry topology, without manual layout template input; use constraint graphs to describe layout dimensions, including design size constraints, so the generation quality is high, and there is no need for design rule checking in the post-processing link;
  • the optimization goal is to minimize the parasitic inductance of the loop and the difference between the parasitic inductance of the chip branch in the switch unit.
  • the genetic algorithm is used to optimize the geometric layout of the substrate of the power module, which can realize the automatic substrate layout design.
  • an embodiment of the present application provides a method for designing a substrate of a power module, including: obtaining input parameters for designing a substrate of a power module, the input parameters including the circuit topology required for the substrate design of the power module Information;
  • the basic layout unit is the smallest unit of the geometric layout of the substrate constituting the power unit; using the pathfinding model to connect the communication paths of the graph elements of each basic layout unit on the circuit topology, the connection of the substrate of the power module is obtained
  • the graph elements are the nodes and interconnected edges of the connection graph formed by pre-stored basic layout units on the circuit topology
  • the connected path is two nodes in the graph elements of a basic layout unit, or two basic layout units.
  • the graph theory model of the basic layout unit by defining the graph theory model of the basic layout unit, the relative position and connection relationship of the basic layout unit are described, and then the integer programming model is used to determine the circuit topology required for the substrate design of the power module.
  • the optimal connection path in each commutation network, and the nodes and interconnection edges of the line units corresponding to each optimal connection path are established to construct a connection graph. This process does not require the input of manual layout templates and does not rely on experts. Based on experience, realize the independent design of the substrate layout of the power module.
  • the type of the basic layout unit on the circuit topology and each basic layout unit are determined according to the circuit topology information and the pre-stored structure diagram of each basic layout unit
  • the number specifically includes: generating the netlist of the circuit topology according to the information of the circuit topology; calculating the netlist of the circuit topology according to the pre-stored structure diagram of each basic layout unit
  • the types of basic layout units and the quantity of each type of basic layout units include switch units, absorption units, terminal units and line units.
  • the input circuit topology netlist is processed through the pre-stored structure diagrams of various basic layout units, and each basic layout unit in the circuit topology netlist can be identified, and the circuit topology netlist can be obtained.
  • each basic layout unit in the circuit topology netlist can be identified, and the circuit topology netlist can be obtained.
  • the pathfinding model is at least one of an integer programming model and a depth-optimized search model.
  • connection graph in the process of generating the connection graph, there are generally multiple circulation paths in the commutation network between two set nodes, and an integer programming model composed of an integer programming algorithm or a depth-optimized search can be selected.
  • the depth optimization search model formed by the algorithm selects the shortest flow path in the commutation network, which makes the structure of the designed substrate connection diagram of the power module simple and can reduce the manufacturing cost of the power module.
  • the step of using a pathfinding model to connect the connection paths of the graph elements of each basic layout unit on the circuit topology to obtain the connection graph of the substrate of the power module specifically includes: determining the At least one commutation network on the netlist of the circuit topology, and at least one connected path in each commutation network and the length of each connected path, the commutation network refers to two commutation networks on the netlist of the circuit topology A network path between nodes, the two nodes being the two nodes where the two ports of the switch unit are located, and/or the two nodes where the two ports of the absorbing unit are located, and/or two different switches Two nodes at which one port of the unit is located, and/or two nodes at which one port of two different absorbing units is located, and/or two nodes at which one port of one switching unit and one absorbing unit is located; According to the optimization objective, the constraints of the commutation network and the constraints of the nodes on the commutation network, the linear programming model is
  • the basic layout unit generally has a switch unit and a terminal unit, if it also includes an absorber unit, then the commutation path can be constructed according to the switch unit and the absorber unit, through the port of the switch unit and the The port of the absorbing unit constructs each commutation network between the corresponding nodes on the netlist of the circuit topology, and then selects the shortest path of each commutation network, and connects the optimal commutation path of each commutation network, and then connects each The terminal unit is connected to the commutation path, and finally the line nodes and interconnection edges of the commutation path are established to obtain a connection diagram of the substrate of the power module.
  • the absorption unit Since the absorption unit has a greater influence on the parasitic inductance of the commutation circuit and the difference in the parasitic inductance of the chip branch in the switching unit than the terminal unit, it is preferable to construct the commutation path through the switching unit and the absorption unit, which can effectively reduce the parasitic in the commutation circuit. inductance and reduce the parasitic inductance difference of the chip branch in the switching unit.
  • the step of using a pathfinding model to connect the connection paths of the graph elements of each basic layout unit on the circuit topology to obtain the connection graph of the substrate of the power module specifically includes: determining the At least one commutation network on the netlist of the circuit topology, and at least one connected path in each commutation network and the length of each connected path, the commutation network refers to two commutation networks on the netlist of the circuit topology A network path between nodes, the two nodes are two nodes where two ports of the switch unit are located, and/or two nodes where one port of two different switch units is located, and/or two Two nodes where a port of a different terminal unit is located, and/or two nodes where a port of a switch unit and a terminal unit is located; according to the optimization objective, the constraints of the commutation network and the Constraint conditions of the nodes, train the linear programming model, and construct the integer programming model; input at least one connected path in each commutation network and the length of
  • the commutation path can be constructed according to the switch unit and the terminal unit, through the ports of the switch unit and The ports of the terminal unit construct each commutation network between the corresponding nodes on the netlist of the circuit topology, then select the shortest path of each commutation network, and connect the optimal commutation paths of each commutation network, and finally establish the commutation network
  • the line nodes and interconnect edges of the flow path are obtained to obtain the connection graph of the substrate of the power module.
  • the input parameters further include design size constraints of the basic layout unit; the method further includes: determining the original size of each basic layout unit according to the design size constraints;
  • connection diagram of the substrate of the power module is scanned to obtain a size constraint diagram of the connection diagram, and the size constraint
  • the graph is used to define the size of each basic layout unit when constructing the geometric layout according to the connection graph.
  • the original size of each basic layout unit can be calculated, that is, the minimum size, and then combined with the pre-stored scaling variables of each basic layout unit, the lining of the power module Scan the connection diagram at the bottom to obtain the size constraint diagram of the connection diagram, which can limit the size of each basic layout unit of the layout when constructing the geometric layout later, and use the size constraint diagram to describe different sizes.
  • the generated power module substrate template is of high quality and does not need to be checked for design rules in subsequent processing links.
  • the scanning of the circuit topology netlist where the connection diagram of the substrate of the power module is located to obtain the size constraint diagram of the connection diagram specifically includes: Scanning the connection diagram along the first direction to obtain a dimensional constraint diagram of the connection diagram in the first direction; and scanning the connection diagram of the substrate of the power module along the second direction to obtain a dimension constraint diagram of the connection diagram in the second direction
  • the dimensional constraint diagram above; the first direction and the second direction are mutually perpendicular directions.
  • the size constraint diagram in the horizontal direction and the size constraint diagram in the vertical direction of the connection diagram are obtained, and by constructing from two mutually perpendicular directions
  • the size constraint diagram can limit the size of the basic layout unit, so that the size of the geometric layout of the substrate of the constructed power module is the most optimal size, the quality of the template is high, and there is no need for design rule detection in the subsequent processing link .
  • the size constraint graph includes constraint nodes and constraint edges
  • the constraint nodes are scan lines scanning the connection graph of the substrate of the power module
  • the constraint edges are scan lines between scan lines The distance is used to constrain the size of each basic layout unit.
  • constraint nodes generally correspond to line nodes, terminal nodes, switch nodes, or absorption nodes at the edge of the connection graph
  • constraint edges generally correspond to the distance between two adjacent nodes.
  • the connection graph can be split to obtain each area in the connection graph where the basic layout unit can be placed, and then according to the size of the area where the basic layout unit can be placed, it is used as a constraint edge to limit the placement of the basic layout unit.
  • Dimensions, to realize the layout of the connection diagram is to limit the size, so that the size of the geometric layout of the substrate of the constructed power module is the most optimal size.
  • the method further includes: constructing a geometric layout of the substrate of the power module according to the connection diagram of the substrate of the power module and the size constraint diagram of the connection diagram.
  • the number and arrangement position of each basic layout unit can be determined through the connection diagram, and the size of each basic layout unit can be defined through the size constraint diagram , to realize the geometrical layout of the substrate for constructing the power module, and the optimal size of the geometrical layout of the substrate for the constructed power module.
  • the method further includes: detecting the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module, and/or the parasitic inductance of the chip branch in the switch unit, and/or The thermal resistance of the chip in the switch unit; when the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module is less than the first threshold, and/or the parasitic inductance of the chip branch in the switch unit is greater than the second threshold, And/or when the thermal resistance of the chip in the switch unit is less than the third threshold, output the geometric layout of the substrate of the power module.
  • the parasitic inductance of the commutation circuit after constructing the geometric layout of the substrate of the power module, three conditions are required: the parasitic inductance of the commutation circuit, the parasitic inductance of the chip branch in the switching unit, and the thermal resistance of the chip in the switching unit. At least one of the conditions to detect the quality of the geometric layout of the power module substrate, if the parasitic inductance of the commutation circuit is small, or the difference in the parasitic inductance of the chip branch in the switch unit is small, or the chip in the switch unit The thermal resistance of is smaller, indicating that the performance of the designed geometric layout of the detection power module substrate is better.
  • the method further includes: when the parasitic inductance of the commutation loop of the geometric layout of the substrate of the power module is not less than the first threshold, and/or the parasitic inductance of the chip branch in the switch unit When the inductance is not less than the second threshold, and/or the thermal resistance of the chip in the switch unit is not less than the third threshold, the geometric layout of the substrate of the power module is reconstructed.
  • the thermal resistance of the thermal resistance is relatively large, indicating that the performance of the designed geometric layout of the substrate of the detection power module is relatively poor, and it needs to be redesigned.
  • it further includes: inputting the geometric layout of the substrate of the power module into the genetic calculation model, and outputting the target geometric layout, the target geometric layout being the power
  • the geometric layout of the substrate of the module, the setting condition is to reduce the parasitic inductance value of the commutation circuit, and/or reduce the difference value of the parasitic inductance of the chip branch in the switch unit, and/or reduce The thermal resistance of the chip in the switching unit reaches a Pareto-optimized frontier.
  • the parasitic inductance of the commutation circuit is minimized, and/or the difference in the parasitic inductance of the chip branches in the switching unit is minimized, and/or the switching unit
  • the minimum thermal resistance of the chip is the optimization goal.
  • the geometric layout of the substrate of the power module can be input into the genetic calculation model constructed by the genetic algorithm for optimization search, and the minimum parasitic inductance of the commutation circuit and the chip in the switching unit can be obtained.
  • the minimum difference of the parasitic inductance of the branch and the minimum thermal resistance of the chip in the switch unit reach the Pareto optimization frontier as the optimal geometric layout, and then output the geometric layout to obtain the optimal power module lining bottom geometry.
  • an embodiment of the present application provides a substrate design device for a power module, including: a transceiver unit configured to acquire input parameters for designing a substrate of a power module, the input parameters including the substrate design of the power module Information about the required circuit topology; a processing unit configured to determine the type of basic layout unit and each The number of basic layout units, the basic layout unit is the smallest unit of the geometric layout of the substrate constituting the power unit; and using a pathfinding model, connecting the graph elements of each basic layout unit on the circuit topology
  • the connection path of the substrate of the power module is obtained, the graph elements are the nodes and interconnection edges of the connection graph formed by the pre-stored basic layout units in the circuit topology, and the connection path is a basic layout A path between two nodes in the graph elements of a cell, or a node in the graph elements of two basic layout cells.
  • the processing unit is specifically configured to generate a netlist of the circuit topology according to the information of the circuit topology; and calculate The types of basic layout units on the netlist of the circuit topology and the quantity of each type of basic layout units, the types of the basic layout units include switch units, absorption units, terminal units and line units.
  • the pathfinding model is at least one of an integer programming model and a depth-optimized search model.
  • the processing unit is specifically configured to determine at least one commutation network on the netlist of the circuit topology, at least one communication path in each commutation network and the length of each communication path
  • the commutation network refers to a network path between two nodes on the netlist of the circuit topology, and the two nodes are the two nodes where the two ports of the switch unit are located, and/or the two nodes of the absorbing unit Two nodes where two ports are located, and/or two nodes where one port of two different switch units is located, and/or two nodes where one port of two different absorbing units is located, and/or Or two nodes where one port of a switching unit and one absorbing unit is located; according to the optimization objective, the constraints of the commutation network and the constraints of the nodes on the commutation network, the linear programming model is trained to build an integer programming model ; Input at least one connected path in each commutation network and the length of each connected path into the integer programming model to obtain a target commut
  • the processing unit is specifically configured to determine at least one commutation network on the netlist of the circuit topology, at least one communication path in each commutation network and the length of each communication path
  • the commutation network refers to a network path between two nodes on the net list of the circuit topology, and the two nodes are two nodes where the two ports of the switch unit are located, and/or two different Two nodes where one port of the switch unit is located, and/or two nodes where one port of two different terminal units is located, and/or two nodes where one port of a switch unit and a terminal unit is located node; according to the optimization objective, the constraints of the commutation network and the constraints of the nodes on the commutation network, the linear programming model is trained to construct an integer programming model; at least one connected path in each of the commutation networks and The length of each connected path is input into the integer programming model to obtain a target commutation path in each commutation network, and the target commutation path is
  • a commutation path establishing a line node on each network node of the target commutation path in each of the commutation networks, and establishing an interconnection edge on the target commutation path in each of the commutation networks; and output the non-empty nodes and interconnection edges on the netlist of the circuit topology to obtain the connection graph of the substrate of the power module.
  • the input parameters further include design size constraints of basic layout units; the processing unit is further configured to determine the original size of each basic layout unit according to the design size constraints. Size; according to the original size of each basic layout unit and the pre-stored scaling variable of each basic layout unit, scan the connection diagram of the substrate of the power module to obtain a size constraint diagram of the connection diagram, the The size constraint graph is used to limit the size of each basic layout unit when constructing the geometric layout according to the connection graph.
  • the processing unit is specifically configured to scan the connection diagram of the substrate of the power module along the first direction to obtain a size constraint diagram of the connection diagram in the first direction; and The connection diagram of the substrate of the power module is scanned along the second direction to obtain a size constraint diagram of the connection diagram in the second direction; the first direction and the second direction are mutually perpendicular directions.
  • the size constraint graph includes constraint nodes and constraint edges
  • the constraint nodes are scan lines scanning the connection graph of the substrate of the power module
  • the constraint edges are scan lines between scan lines The distance is used to constrain the size of each basic layout unit.
  • the processing unit is further configured to construct a geometric layout of the substrate of the power module according to the connection diagram of the substrate of the power module and the size constraint diagram of the connection diagram.
  • the processing unit is further configured to detect the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module, and/or the parasitic inductance of the chip branch in the switch unit, and /or the thermal resistance of the chip in the switch unit; when the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module is greater than the first threshold value, and/or the parasitic inductance of the chip branch in the switch unit is smaller than the second When the threshold value and/or the thermal resistance of the chip in the switch unit is less than a third threshold value, the geometric layout of the substrate of the power module is output.
  • the processing unit is further configured to: when the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module is not less than the first threshold, and/or the chip branch in the switch unit When the parasitic inductance of the switch unit is not less than the second threshold, and/or the thermal resistance of the chip in the switch unit is not less than the third threshold, the geometric layout of the substrate of the power module is reconstructed.
  • the processing unit is further configured to input the geometric layout of the substrate of the power module into the genetic calculation model, and output the target geometric layout, and the target geometric layout satisfies the set
  • the geometric layout of the substrate of the power module according to the conditions, the set condition is to reduce the parasitic inductance value of the commutation circuit, and/or reduce the parasitic inductance difference value of the chip branch in the switching unit , and/or reduce the thermal resistance of the chip in the switch unit to reach the Pareto optimization frontier.
  • an embodiment of the present application provides a terminal device, including: at least one transceiver; at least one memory; and at least one processor, the processor is configured to execute instructions stored in the memory, so that the terminal device performs the following Embodiments of various possible implementations of the first aspect.
  • an embodiment of the present application provides a computing device, which is characterized by including a memory and a processor, the memory is used to store instructions, and the processor is used to call the instructions stored in the memory, to implement the first Embodiments of various possible implementations of aspects.
  • the embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed in a computer, the computer is made to execute various possible implementation embodiments of the first aspect.
  • an embodiment of the present application provides a computer program product, which is characterized in that the computer program product stores instructions, and when the instructions are executed by a computer, the computer implements the various possible implementations of the first aspect. Example.
  • FIG. 1 is a schematic structural diagram of a terminal device provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a processor provided in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the relationship between the geometric layout, graphic elements and scaling variables of each basic layout unit provided in the embodiment of the present application;
  • FIG. 4 is a flowchart of a process of generating a connection diagram of a substrate of a power module provided in an embodiment of the present application
  • FIG. 5 is a flow chart of the process of generating a connection diagram of another power module substrate provided in the embodiment of the present application.
  • Figure 6 (a) is a schematic diagram of various communication paths in the commutation network between two nodes on the netlist of a circuit topology provided in the embodiment of the present application;
  • Fig. 6(b) is a schematic diagram of various communication paths in the commutation network between two nodes on the netlist of another circuit topology provided in the embodiment of the present application;
  • Fig. 7(a) is a connection diagram of a substrate of a power module provided in the embodiment of the present application.
  • Figure 7(b) is a geometric layout based on the connection diagram shown in Figure 7(a) provided in the embodiment of the present application;
  • Figure 7(c) is a size constraint diagram in the horizontal direction and a size constraint diagram in the vertical direction based on the connection diagram shown in Figure 7(a) provided in the embodiment of the present application;
  • Fig. 8(a) is a dimension constraint diagram in the horizontal direction and a dimension constraint diagram in the vertical direction after mirror-symmetrical expansion along the horizontal direction based on the dimension constraint diagram shown in Fig. 7(c) provided in the embodiment of the present application;
  • Fig. 8(b) is a geometric layout based on the layout shown in Fig. 7(b) provided in the embodiment of the present application after being mirror-symmetrically expanded along the horizontal direction;
  • FIG. 9 is the corresponding geometric layout constructed according to the connection diagrams of the substrates of other 16 different power modules provided in the embodiment of the present application.
  • FIG. 10 is a flow chart of the process of optimizing the substrate layout of the power module through the genetic algorithm provided in the embodiment of the present application;
  • Fig. 11 is a schematic diagram of previous iteration results and Pareto frontier results fitting provided in the embodiment of the present application;
  • Figure 12 is a schematic diagram of the layout and corresponding design parameters of the three frontier results provided in the embodiment of the present application.
  • Fig. 13 is a schematic diagram of the results of the simulation evaluation of the frontier solution C provided in the embodiment of the present application.
  • Fig. 14 is a schematic frame diagram of a power module substrate design device provided in an embodiment of the present application.
  • first and second and the like in the specification and claims herein are used to distinguish different objects, rather than to describe a specific order of objects.
  • first response message and the second response message are used to distinguish different response messages, rather than describing a specific order of the response messages.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • multiple means two or more, for example, multiple processing units refer to two or more processing units, etc.; multiple A component refers to two or more components or the like.
  • the power module refers to the combination of power and electronic devices according to certain functions, and then potted into a module. Due to the differences between power modules and integrated circuits in terms of component types, working modes, and manufacturing processes, it is difficult for existing electronic design automation tools for integrated circuits to meet the design requirements of power modules.
  • the existing automated design methods for power modules are still in their infancy, and there are many defects, such as: the layout template needs to be manually input, resulting in limited degrees of freedom for the generated power modules, and it relies heavily on the experience of experts;
  • the description model does not include line connectivity constraints and design size constraints, resulting in poor manufacturability of the generated power module and low optimization efficiency; when designing the power module, it only pays attention to how to reduce the parasitic inductance of the commutation circuit, and does not take into account the inductance of the switching unit.
  • the optimization of the balance of the parasitic inductance of the chip branch leads to poor performance of the designed power module.
  • this application is based on the graph theory model of the basic layout unit, uses the linear programming algorithm to generate a variety of connected templates of the layout, and then uses the genetic algorithm to calculate the minimum parasitic inductance of the commutation circuit and the chip support in the switch unit.
  • the unit size with the most balanced parasitic inductance of the circuit is achieved, and the independent design of the substrate layout of the power module is realized.
  • FIG. 1 is a schematic structural diagram of a terminal device provided in an embodiment of the present application.
  • the terminal device 100 includes a transceiver 110 , a memory 120 , a processor 130 and a bus 140 .
  • the transceiver 110 , the memory 120 and the processor 130 respectively establish a communication connection through the bus 140 , so as to realize mutual communication between the various modules.
  • the transceiver 110 can implement signal input (reception) and output (transmission).
  • transceiver 110 may include a transceiver or radio frequency chip.
  • the transceiver 110 may also include a communication interface.
  • the terminal device 100 may receive data sent by other devices such as the terminal device and the cloud through the transceiver 110 , and may also send the data processed by the processor 130 to other devices through the transceiver 110 .
  • a program (or an instruction or code) may be stored in the memory 120, and the program may be executed by the processor 130, so that the processor 130 executes a design method of a power module substrate based on a graph theory model.
  • data may also be stored in the memory 120 .
  • the processor 130 can read the data stored in the memory 120, the data can be stored in the same storage address as the program, and the data can also be stored in a different storage address from the program.
  • the processor 130 and the memory 120 can be set separately, or can be integrated together, for example, integrated on a single board or a system on chip (system on chip, SOC).
  • Processor 130 may be a general purpose processor or a special purpose processor.
  • the processor 130 may include a central processing unit (central processing unit, CPU) and/or a baseband processor.
  • the processor 130 may execute a power module substrate design method based on a graph theory model according to the data received by the transceiver 110 and sent by other devices, and generate a power module substrate design solution.
  • the structure shown in the embodiment of the present application does not constitute a specific limitation on the terminal device 100 .
  • the terminal device 100 may include more or fewer components than shown in the figure, or combine certain components, or separate certain components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • FIG. 2 is a schematic structural diagram of a processor provided in an embodiment of the present application.
  • the processor 130 can be divided into a parameter preprocessing module 131 , a connection graph generation module 132 , a constraint graph generation module 133 , a layout generation module 134 , an inductance evaluation module 135 and an optimization processing module 136 according to execution functions.
  • the functions performed by each module are as follows:
  • the processor 130 Before the processor 130 executes the power module substrate design method based on the graph theory model, it needs to obtain the input parameters of the power module substrate design through the transceiver 120, such as configuration information of the power module, constraints on design dimensions, and the like.
  • the input parameters of the substrate design of the power module may be the parameters shown in Table 1, specifically:
  • the circuit topology information required for the substrate design of the power module includes the type of circuit topology, such as half-bridge type, and the constraints of the design size include the size of the chip, the size of the absorbing capacitor, the size of the terminal pad, the metal layer Line width, metal layer spacing, metal layer thickness, solder spacing, bonding spacing, etc.
  • the circuit topology required for the substrate design of the power module is a half-bridge type, the number of chips in parallel is 4, the size of the chip is 5.9 ⁇ 3.1mm, the size of the absorbing capacitor is 6.0 ⁇ 5.0mm, and the terminal pad
  • the size of the metal layer is greater than or equal to 3.0 ⁇ 3.0mm, the line width of the metal layer is greater than or equal to 1.0mm, the distance between the metal layers is 0.7mm, the thickness of the metal layer is 0.3mm, the welding distance is greater than or equal to 1.0mm, and the bonding distance is greater than or equal to 1.0mm. This is just an example, not a limitation of this application.
  • the parameter preprocessing module 131 is used to generate a circuit topology netlist (netlist) according to the circuit topology information required by the substrate design of the power module, and determine the circuit topology by combining the pre-stored structure diagrams of each basic layout unit
  • the circuit topology also known as the circuit diagram, is a set that abstracts the circuit diagram again and consists only of branches and nodes. Each two-terminal component that constitutes the circuit is called a branch, and two Or the connection point of two or more branches is called a node. It discusses the connection relationship and properties of the circuit, that is, the connection relationship between branches and nodes.
  • the circuit topology information required for the substrate design of the power module is input into the parameter preprocessing module 131, and the netlist of the circuit topology is automatically generated, which includes the name of the circuit element, the number of the circuit element, the circuit The port number of the component, the connectivity information of whether the port parts are interconnected, and so on.
  • the basic layout unit is the smallest unit that constitutes a power module.
  • the basic layout units can be divided into switch units, absorption units, terminal units, line units and other units.
  • the basic layout unit is generally composed of a chip set and a metal layer, the chip set includes at least one chip and/or at least one component, each chip or component in the chip set can be electrically connected to the metal layer, And the metal layer is electrically connected to the nodes on the circuit topology to realize the electrical connection between the chip set and the substrate of the power module, which can reduce the difficulty of substrate design of the power module.
  • the parameter preprocessing module 131 is also used to determine the geometric layout structure of various types of basic layout units, graphic elements and scaling variables, etc. information.
  • the geometric layout of the basic layout unit includes at least one metal layer, or also includes a chipset. If a chipset is also included, the chipset includes at least one chip and/or at least one component, each chip or component is arranged in the middle of the metal layer as much as possible, and each chip or component is arranged according to Arrangement of design constraints such as minimum line width, minimum line spacing, and minimum welding spacing.
  • the graph elements of the basic layout unit are composed of nodes and interconnected edges, which are used to generate a connection graph.
  • the scaling variables of the basic layout unit include the scaling variable in the horizontal direction and the scaling variable in the vertical direction, which are used to optimize the size of the basic layout unit along the horizontal direction and the vertical direction.
  • the horizontal direction and the vertical direction are perpendicular to each other. of the two directions.
  • the switch unit consists of a chipset and three metal layers.
  • the chipset is composed of one or more power semiconductor chips, and each power semiconductor chip in the chipset is arranged in parallel on a metal layer, and each power semiconductor chip in the chipset connects each The driving electrodes on the surface of the power semiconductor chip are electrically connected to a metal layer, and the power electrodes on the surface of each power semiconductor chip in the chipset are electrically connected to a metal layer.
  • the geometric layout of the switch unit as shown in FIG. The semiconductor chips are arranged in parallel on the first metal layer; the power semiconductor chips electrically connect the driving electrodes on the surface of each power semiconductor chip to the second metal layer through the interconnection structure on the top; the power electrodes on the surface of each power semiconductor chip are electrically connected to each other. connected to the third metal layer, and the second metal layer is located between the first metal layer and the third metal layer.
  • the chipsets are arranged side by side near the second metal layer, so as to minimize the length of the interconnection structure.
  • the switch unit includes two adjacent nodes and an interconnection edge.
  • two adjacent nodes indicate that the switch unit occupies two adjacent nodes in the circuit topology
  • the interconnection edge indicates the current flow path in the switch unit.
  • the scaling variables of the switch cell include the spacing between the three chips in the chipset, the length and width of the first metal layer, and the length and width of the second metal layer , the length and width of the third metal layer, and so on.
  • the scaling variable of the switch unit refers to the reduction or enlargement of the same proportion according to the scaling variable, so that the whole switch unit is reduced or enlarged, and the shape of the switch unit, the relative position relationship between each chip, and the relative position between each metal layer relationship, chip or component size, will not change.
  • the scaling variable of the switch unit can be divided into scaling variable in the horizontal direction and scaling variable in the vertical direction.
  • the scaling variable in the horizontal direction represents the size of the chipset and the metal layer along the horizontal direction, such as the width of the first metal layer, the width of the first metal layer, the width of the first metal layer, etc.
  • the scaling variable in the vertical direction represents the chip Dimensions of groups and metal layers along the vertical direction, such as the spacing between three chips, the length of the first metal layer, the length of the first metal layer, the length of the first metal layer, and so on.
  • the information of the basic layout unit received by the processor 130 through the transceiver 110 includes data such as the geometric layout structure of the switch unit, the graphic elements of the switch unit, and the scaling variables of the switch unit.
  • the absorption unit consists of a chipset and two metal layers.
  • the chipset is composed of one or more absorbing capacitor elements, and each absorbing capacitor element in the chipset is arranged in parallel in the middle of two metal layers, and the electrodes on each absorbing capacitor element are respectively electrically connected to the two metal layers. layer.
  • the absorbing capacitor element may be a decoupling capacitor made of ceramic, thin film, or silicon material, or may be a damping absorbing element with capacitance and resistance characteristics, which is not limited in this application.
  • the absorption unit includes a chipset, a fourth metal layer and a fifth metal layer.
  • the chipset includes a absorbing capacitor, which is arranged in the middle between the fourth metal layer and the fifth metal layer, and the electrodes on the absorbing capacitor are electrically connected to the fourth metal layer and the fifth metal layer respectively .
  • the absorption unit includes two adjacent nodes and an interconnection edge.
  • two adjacent nodes indicate that the absorbing unit occupies two adjacent nodes in the circuit topology
  • the interconnection edge indicates the current flow path in the absorbing unit.
  • the scaling variables of the absorption unit include the length and width of the fourth metal layer in the chip set, the length and width of the fifth metal layer, and so on.
  • the scaling variable of the absorbing unit refers to reducing or enlarging the absorbing unit in the same proportion according to the scaling variable, so that the overall absorbing unit is reduced or enlarged, and the shape of the absorbing unit, the relative positional relationship between each metal layer, the size of the chip or components , will not change.
  • the scaling variable of the absorbing unit can be divided into a scaling variable in the horizontal direction and a scaling variable in the vertical direction.
  • the scaling variable in the horizontal direction represents the size of the chip set and the metal layer along the horizontal direction, such as the width of the fourth metal layer, the width of the fifth metal layer, etc.
  • the scaling variable in the vertical direction represents the size of the chip set and the metal layer along the vertical direction.
  • Dimensions in the upper direction such as the length of the fourth metal layer, the length of the fifth metal layer, and so on.
  • the information of the basic layout unit received by the processor 130 through the transceiver 110 includes data such as the geometric layout structure of the absorbing unit, the graphic elements of the absorbing unit, and the scaling variables of the absorbing unit.
  • the terminal unit consists of a chipset and a metal layer.
  • the chipset is composed of one or more terminal elements, and the terminal elements have power output terminals such as positive pole, negative pole, and AC, and the output terminals on each terminal element are arranged in the middle of a metal layer, and are connected to the metal layer. layer electrical connection.
  • the terminal unit includes a chipset and a sixth metal layer.
  • the chipset includes a terminal element, and power output terminals such as positive pole, negative pole, and alternating current on the terminal element are arranged on the sixth metal layer and are electrically connected to the sixth metal layer.
  • the terminal unit includes one node in the graph elements of the terminal unit.
  • a node means that the terminal unit occupies a node in the circuit topology.
  • the scaling variables of the terminal unit include the length and width of the sixth metal layer and the like.
  • the scaling variable of the terminal unit means that the terminal unit is reduced or enlarged in the same proportion according to the scaling variable, so that the overall terminal unit is reduced or enlarged, and the shape of the terminal unit, the size of the chip or the component will not change.
  • the scaling variable of the terminal unit can be divided into a scaling variable in the horizontal direction and a scaling variable in the vertical direction.
  • the scaling variable in the horizontal direction represents the size of the chip set and the metal layer along the horizontal direction, such as the width of the sixth metal layer, etc.
  • the scaling variable in the vertical direction represents the size of the chip set and the metal layer along the vertical direction, such as the width of the sixth metal layer, etc. The length of the six metal layers and so on.
  • the information of the basic layout unit received by the processor 130 through the transceiver 110 includes data such as the geometric layout structure of the terminal unit, the graphic elements of the terminal unit, and the scaling variables of the terminal unit.
  • the line unit is composed of a metal layer.
  • the line unit includes one node in the graph elements of the line unit.
  • a node means that the line unit occupies a node in the circuit topology.
  • the scaling variables of the line unit include the length and width of the seventh metal layer and so on.
  • the scaling variable of the line unit refers to reducing or enlarging in the same proportion according to the scaling variable, so that the entire line unit is reduced or enlarged without changing the shape of the line unit.
  • the scaling variable of the line unit may be divided into a scaling variable in the horizontal direction and a scaling variable in the vertical direction.
  • the scaling variable in the horizontal direction represents the size of the metal layer along the horizontal direction, such as the width of the seventh metal layer, etc.
  • the scaling variable in the vertical direction represents the size of the metal layer in the vertical direction, such as the length of the seventh metal layer, etc. wait.
  • the information of the basic layout unit received by the processor 130 through the transceiver 110 includes data such as the geometric layout structure of the line unit, the graphic elements of the line unit, and the scaling variables of the line unit.
  • the size of the metal layer in each type of basic layout unit can be correlated, for example, the size of the sixth metal layer in the terminal unit is the same as the size of the seventh metal layer in the routing unit, and another example
  • the size of the fourth metal layer and the fifth metal layer in the absorption unit are the same, and the size of the sixth metal layer and other metal layers in the terminal unit are the same.
  • the size of the metal layer in each type of basic layout unit may not be correlated, for example, the size of the metal layer in each basic layout unit is different, or even the size of the metal layer in the same type of basic layout unit Not the same.
  • each type of basic layout unit exists in the smallest size.
  • the input parameters are preprocessed by the preprocessing module to obtain the structure, graphic elements and scaling of the geometric layout of the basic layout unit of the substrate constituting the power module.
  • Variables provide a basis for subsequent construction of the connection diagram and optimization of the size of the substrate of the designed power module.
  • connection diagram generation module 132 is used to generate an orthogonal grid whose size does not exceed 2N ⁇ 2N according to the number N of switch units determined in the netlist of the input circuit topology, and then randomly place the diagram of switch units and absorbing units in the grid Elements, and then according to the circuit topology, use the integer programming algorithm to find the connected path with the smallest commutation length, set the path as an interconnection edge, and set the path node as a line unit node, and finally output all non-empty nodes and interconnection edges as a layout template , to obtain the connection diagram of the substrate of the power module.
  • connection diagram generation module 132 constructs the connection diagram of the substrate of the power module, and the specific implementation process is as follows:
  • Step S401 determining at least one commutation network on the netlist of the circuit topology, at least one connection path in each commutation network, and the length of each connection path.
  • the commutation network refers to a network path between two nodes on the netlist of the circuit topology. Specifically:
  • the depth-first search model refers to a storage unit, an electronic device, a cloud server, etc. in which a depth-first search algorithm is stored.
  • each connected path as an integer variable x net,1 ,...,x net,k , and the value range of each integer variable x net,k is
  • the selected two node coordinates are G(1,2) and G(2,0) commutation network A, there can be two connecting paths, respectively ⁇ A1, A2 ⁇ .
  • the selected two node coordinates are G(2,1) and G(0,2) of the converter network B, and there can be three connecting paths, which are respectively ⁇ B1,B2,B3 ⁇ .
  • the two nodes G(1,2) and G(2,0) in Figure 6(a) can be two nodes on the netlist where the two endpoints of the same switch unit are located, and can be The two nodes on the netlist where the two endpoints of the same absorbing unit are located can be two nodes on the netlist where the endpoints of different switch units are located, or they can be two nodes on the netlist where the endpoints of different absorbing units are located. The node can even be two nodes on the netlist where the endpoints of the switching unit and the sinking unit are located. The same is true for the two nodes G(2,1) and G(0,2) in Fig. 6(b), which will not be repeated here.
  • Step S402 building an integer programming model.
  • integer programming is a kind of linear programming, and the linear programming that limits variables to integers is called integer programming.
  • the integer programming model refers to storage units, electronic devices, cloud servers, etc. that store integer programming algorithms.
  • the optimization objective is determined to be the minimum path of the total commutation network, namely
  • constraints for establishing an integer programming model are defined as:
  • Each commutation network is allowed to have only one path, that is,
  • Each grid node accommodates only one path, namely
  • W is the grid width and H is the grid height.
  • Step S403 inputting at least one connected path in each commutation network and the length of each connected path into an integer programming model to obtain a target commutation path in each commutation network.
  • the target commutation path is the shortest commutation path in each commutation network.
  • Fig. 6(a) and Fig. 6(b) as an example, for commutation network A and commutation network B, according to the principle of "minimum path" as the optimization goal, the length l net of the connecting path A1 in commutation network A ,A1 is smaller than the length l net,A2 of the connected path A2, so the priority of the connected path A1 is higher than that of the connected path A2.
  • the length l net,B1 of the connecting path B1 in the commutation network B is smaller than the length l net,B2 of the connecting path B2, and the length l net ,B1 of the connecting path B1 is also smaller than the length l net , B2 of the connecting path B2 , so The priority of the connection path B1 is higher than that of the connection path B2 and the connection path B3.
  • connection path B1 in network B is used as the optimal commutation path of the two commutation networks.
  • the connection path A1 in the commutation network A and the connection path B3 in the commutation network B can be selected as the optimal commutation paths of the two commutation networks, and the connection path A2 in the commutation network A and the commutation network B3 can be selected.
  • the connection path B3 in B is the optimal commutation path of the two commutation networks, and other paths, which are not limited in this application.
  • Step S404 establishing line nodes on each network node of the target commutation path in each commutation network, and establishing interconnection edges on the target commutation path in each commutation network.
  • the line node is the node where the line unit is arranged in the connection graph.
  • connection path A2 in the commutation network A in Fig. 6(a) as an example, after the connection path A1 is determined to be the optimal commutation path of the commutation network A, since the connection relationship of each node in the connection path A2 is G(1,2) ⁇ G(0,2) ⁇ G(0,1) ⁇ G(0,0) ⁇ G(1,0) ⁇ G(1,1) ⁇ G(2,1) ⁇ G (2,0), respectively at nodes G(1,2), G(0,2), G(0,1), G(0,0), G(1,0), G(1,1) , G(2,1) and G(2,0) establish line units.
  • the interconnection edge of each line unit is established.
  • the node connected to this node is G(0,2)
  • the connection edge of node G(1,2) is "G(1,2) ⁇ G (0,2)”
  • the interconnected edges of node G(0,2) are "G(1,2) ⁇ G(0,2)” and "G(0,2) ⁇ G(0,1 )”; other nodes and so on.
  • connection path B3 in the commutation network B in Fig. 6(b) As an example, after the connection path B3 is determined to be the optimal commutation path of the commutation network B, since the connection relationship of each node in the connection path B3 is G(2,1) ⁇ G(2,0) ⁇ G(3,0) ⁇ G(3,1) ⁇ G(3,2) ⁇ G(2,2) ⁇ G(1,2) ⁇ G (0,2), respectively at nodes G(2,1), G(2,0), G(3,0), G(3,1), G(3,2), G(2,2) , G(1,2) and G(0,2) to establish line units.
  • the interconnection edge of each line unit is established.
  • the node connected to this node is G(2,0)
  • the connection edge of node G(2,1) is "G(2,1) ⁇ G (2,0)”
  • the interconnected edges of node G(2,0) are "G(2,1) ⁇ G(2,0)” and "G(2,0) ⁇ G(3,0 )”; other nodes and so on.
  • Step S405 using the depth-optimal search model to establish terminal paths on target commutation paths in each commutation network, and establish terminal nodes and interconnection edges on the terminal paths.
  • the terminal node is a node where the terminal unit is arranged in the connection diagram.
  • Step S406 outputting the non-empty nodes and interconnection edges on the netlist of the circuit topology to obtain the connection graph of the substrate of the power module.
  • Depth first search algorithm is a kind of search algorithm, its principle is to traverse the nodes of the tree along the depth of the tree, and search the branches of the tree as deep as possible. When all edges of a node have been explored, the search will backtrack to the start node of the edge where the node was found. This process continues until all nodes reachable from the source node have been found. If there are undiscovered nodes, select one of them as the source node and repeat the above process, and the whole process is repeated until all nodes are visited.
  • connection path A2 in the commutation network A in Fig. 6(a) as an example, after establishing line units on each node of the connection path A2, according to the depth-first search model constructed by the depth-first search algorithm, each line The interconnection edge of the node is connected with the interconnection edge of the adjacent line node, and the establishment realizes the establishment of connection of each commutation path.
  • the nodes adjacent to node G(1,2) are G(0,2), G(1,1) and G(2,2), and the nodes adjacent to node G(0,2) There are G(0,1) and G(1,2), so node G(1,2) and node G(0,2) are adjacent nodes, and the interconnection edge of node G(1,2) is " G(1,2) ⁇ G(0,2)", and the interconnection edge of node G(0,2) has "G(1,2) ⁇ G(0,2)", so it can be in node G(1 ,2) Establish a terminal unit with the node G(0,2), and connect the node G(1,2) with the interconnection edge of the node G(0,2) to obtain the interconnection edge of the terminal unit; other nodes can be deduced in the same way .
  • the nodes adjacent to node G(2,1) are G(2,0), G(2,2), G(1,1) and G(3,1), and node G(2 ,0)
  • the adjacent nodes are G(2,1), G(1,0) and G(3,0), so node G(2,1) and node G(2,0) are adjacent nodes , and the interconnection edge of node G(2,1) is "G(2,1) ⁇ G(2,0)", and the interconnection edge of node G(2,0) is "G(2,1) ⁇ G (2,0)", so the terminal unit can be established in node G(2,1) and node G(2,0), and the interconnection edge between node G(2,1) and node G(2,0) Connect to get the interconnection edge of the terminal unit; other nodes can be deduced in the same way.
  • connection diagram of the substrate of the constructed power module is as shown in Figure 7 (a) The connection structure shown.
  • the connection diagram includes switch nodes, absorption nodes, terminal nodes and line nodes
  • the switch nodes are the nodes on the connection diagram arranged by the switch unit
  • the absorption nodes are the nodes on the connection diagram arranged by the absorption unit
  • the terminal nodes are the terminal units The node on the connection diagram of the arrangement
  • the line node is the node on the connection diagram of the arrangement of the line unit.
  • connection diagram generation module 132 constructs a connection diagram of the substrate of the power module, and the specific implementation process is as follows:
  • Step S501 determining at least one commutation network on the netlist of the circuit topology, at least one connection path in each commutation network, and the length of each connection path.
  • the commutation network refers to a network path between two nodes on the netlist of the circuit topology. Specifically:
  • each commutation network defined in the netlist of the circuit topology it refers to the switching unit and terminal unit at any position in the netlist of the circuit topology.
  • the same Two ports of the switch unit are located at two nodes on the netlist, one port of two different switch units is located at two nodes on the netlist, one port of two different terminal units is located at two nodes on the netlist node, and all communication paths between two nodes on the netlist where one port of the switch unit and the terminal unit is located, and record the length of each communication path.
  • Step S502 building an integer programming model.
  • the optimization goal is to minimize the path of the total converter network
  • the constraints for establishing the integer programming model are defined as: 1 Each converter network is allowed to have only one path; 2 Each grid node can only accommodate a path. Then, according to the optimization objective, constraints 1 and 2, the linear programming model whose variables are integers is trained to obtain an integer programming model.
  • Step S503 input at least one connected path in each commutation network and the length of each connected path into an integer programming model to obtain a target commutation path in each commutation network.
  • the target commutation path is the shortest commutation path in each commutation network.
  • Step S504 establishing line nodes on each network node of the target commutation path in each commutation network, and establishing interconnection edges on the target commutation path in each commutation network.
  • the line node is the node where the line unit is arranged in the connection graph.
  • Step S505 outputting the non-empty nodes and interconnection edges on the netlist of the circuit topology to obtain the connection diagram of the substrate of the power module.
  • the interconnection edge of each line node is connected with the interconnection edge of the adjacent line node, and the realization of each commutation path to establish a connection.
  • the graph theory model of the basic layout unit by defining the graph theory model of the basic layout unit, the relative position and connection relationship of the basic layout unit are described, and then the integer programming model is used to determine the circuit topology required for the substrate design of the power module.
  • the optimal connection path in each commutation network, and the nodes and interconnection edges of the line units corresponding to each optimal connection path are established to construct a connection graph. This process does not require the input of manual layout templates and does not rely on experts. Based on experience, realize the independent design of the substrate layout of the power module.
  • the graph theory model of the basic layout unit by defining the graph theory model of the basic layout unit, the relative position and connection relationship of the basic layout unit are described, and then the integer programming model is used to determine the circuit topology required for the substrate design of the power module.
  • the optimal connection path in each commutation network, and the nodes and interconnection edges of the line units corresponding to each optimal connection path are established to construct a connection graph. This process does not require the input of manual layout templates and does not rely on experts. Based on experience, realize the independent design of the substrate layout of the power module.
  • the constraint graph generation module 133 is used to determine the original size of each basic layout unit according to the design size constraints, that is, the minimum size of the switch unit, absorber unit, terminal unit and line unit, and then combine each basic layout unit Scaling variable, scan the netlist of the circuit topology where the connection diagram is located in the horizontal direction and vertical direction, and obtain the size constraint diagram in the horizontal direction and the size constraint diagram in the vertical direction respectively.
  • the nodes in the size constraint graph represent scan lines
  • the edges (regions between nodes) in the size constraint graph represent the size and size constraints of layout units between scan lines, and there is at least one edge between adjacent nodes, each The minimum constraint w min,n of each edge is determined by the layout unit with the largest size between them.
  • a fixed edge is added between the two outermost nodes, and the corresponding outer frame size constraint w sum is stored.
  • edges 1 to nedges-1 as free variables, and edges numbered n edges as dependent variables.
  • the value w n ,n ⁇ 1,2,...,n edges -1 ⁇ of the free variable must be greater than or equal to the minimum value constraint of the corresponding edge, that is, w n ⁇ w min,n ;
  • a layout as shown in FIG. 7(b) is generated, and the layout includes two switching units, one absorbing unit and 6 line units.
  • the layout includes two switching units, one absorbing unit and 6 line units.
  • two switching units and one absorbing unit are arranged according to the connecting line as shown in Figure 7(a), and 6 line units are filled in other positions to form a complete layout and make the shape rectangular.
  • the width of side w1 is related to the width of the metal layer in the line unit and the width of the metal layer in the switch unit
  • the side w2 is related to the width of the metal layer in the switch unit and the width of the metal layer in the absorption unit
  • the width of the side w 3 is associated with the width of the metal layer in the absorption unit and the width of the metal layer in the line unit.
  • the length of side h1 is associated with the length of the metal layer in the absorption unit and the length of the metal layer in the line unit
  • the length of side h2 is related to the length of the metal layer in the line unit and the length of the metal layer in the switch unit
  • the lengths are associated
  • the length of side h3 is associated with the length of the metal layer in the line unit
  • the length of side h4 is associated with the length of the metal layer in the line unit and the length of the metal layer in the switch unit.
  • the size constraint diagram in the horizontal direction and the size constraint diagram in the vertical direction of the connection diagram are obtained, and the size constraint diagram can be used to describe different Dimensions contain size constraints, so the substrate template of the generated power module is of high quality, and design rule detection is not required in the subsequent processing link.
  • the layout generation module 134 is used to obtain its own boundary size and position according to the value of the side length of the size constraint graph, and adjust the internal circuit size and component position according to the defined scaling variable, and then traverse the interconnection graph in the connection graph edge, and merge the metal layer lines in the interconnection layout to generate the substrate layout of the power module.
  • the overall size adjustment, internal circuit size adjustment, and component position of the layout shown in FIG. 7(b) can be adjusted. Adjustment, etc., and then use the interconnection edge to electrically connect the metal layers on each basic layout unit to obtain the substrate design circuit diagram of the power module.
  • width of side w1 is associated with the width of the metal layer in the line unit and the width of the metal layer in the switch unit, and the seventh metal layer in the line unit
  • the width can be reduced and enlarged at will according to the scaling variable of the line unit, and the minimum width of the second metal layer and the second metal layer in the switch unit must be greater than or equal to 1.0mm, and the distance between the metal layers must be greater than 0.7mm, so the edge
  • the width of w 1 is at least 2.2 mm; other widths and lengths can be deduced by analogy, which is not limited in this application.
  • the layout generation module 134 can also obtain a layout with a symmetrical structure through mirror symmetry, translation, etc. according to the size constraint diagram shown in FIG. 7( c ).
  • the size constraint graph shown in FIG. 8( a ) is obtained.
  • the size constraint diagram in the horizontal direction is processed with mirror symmetry, and the length w sum in the horizontal direction is twice the length in the horizontal direction shown in FIG. 7( c ).
  • the layout generation module 134 performs mirror symmetry processing on the layout shown in FIG. 7(b) according to the size constraint diagram shown in FIG. 8(a), to obtain the layout shown in FIG. 8(b), Then adjust the overall size of the layout, adjust the internal circuit size, adjust the position of components, etc., and then use the interconnection edge to electrically connect the metal layers on each basic layout unit to obtain the substrate design circuit diagram of the power module.
  • the number and arrangement position of each basic layout unit can be determined through the connection diagram, and the size of each basic layout unit can be limited through the size constraint diagram , to realize the geometrical layout of the substrate for constructing the power module, and the optimal size of the geometrical layout of the substrate for the constructed power module.
  • the inductance evaluation module 135 is used to calculate the parasitic inductance of the commutation circuit of the layout, the parasitic inductance of the chip branch in the switch unit, and the thermal resistance of the chip in the switch unit by using the layout evaluation tool to judge the designed
  • the performance of the layout geometry is good or bad.
  • the inductance evaluation has the following two characteristics: first, the commutation circuit in the layout is defined as the layout line starting from the positive electrode of the absorption capacitor, passing through the metal layer circuit and the power semiconductor chipset, and returning to the negative electrode of the absorption capacitor;
  • the chip branch in the switching unit is defined as the layout line starting from the power semiconductor chip belonging to the same switching unit to the electrode of the absorption capacitor.
  • the inductance evaluation module 135 detects the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module generated by the layout generation module 134, the parasitic inductance of the chip branch in the switch unit, and the heat of the chip in the switch unit. at least one of the three indicators.
  • the inductance evaluation module 135 outputs the geometric layout of the substrate of the power module; when the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module is not less than the first threshold, and/or in the switch unit When the parasitic inductance of the chip branch is not less than the second threshold, and/or the thermal resistance of the chip in the switch unit is not less than the third threshold, the geometric layout of the substrate of the power module can be reconstructed, and instructions can be sent to the connection diagram generation module 132. Regenerate the connection diagram, or send an instruction to the constraint diagram generation module 133 to regenerate the size constraint diagram, or send an instruction to the layout generation module 134 to regenerate the connection diagram
  • the performance of the designed geometric layout for detecting the substrate of the power module is relatively good.
  • the geometric layout of the substrate on which the power module is constructed has a large parasitic inductance of the commutation circuit, or a large difference in the parasitic inductance of the chip branches in the switching unit, or the thermal resistance of the chip in the switching unit is relatively small, It shows that the performance of the designed geometric layout of the substrate of the detection power module is relatively poor and needs to be redesigned.
  • the optimization processing module 136 is used to use the weights of the edges of the size constraint graph as design variables, the minimum size of the basic layout unit and the size of the substrate outer frame as design constraints, input them into the genetic calculation model for optimization processing, and output the optimal Layout of a substrate of a power module.
  • the genetic computing model refers to storage units, electronic devices, cloud servers, etc. that store genetic algorithms.
  • Genetic algorithm is a search algorithm based on natural selection and population genetic mechanism, which simulates the phenomena of reproduction, hybridization and mutation in the process of natural selection and natural inheritance.
  • each possible solution of the problem is encoded into a "chromosome", that is, an individual, and several individuals form a group (all possible solutions).
  • chromosome that is, an individual
  • a fitness value is given. Based on this fitness value, some individuals are selected to generate For the next generation, the selection operation embodies the principle of "survival of the fittest".
  • the genetic algorithm can be regarded as a process of preliminary evolution of a group composed of feasible solutions.
  • the genetic calculation unit 1343 performs iterative optimization, and the specific implementation process is as follows:
  • Step S1001 system input: input connection graph, size constraint graph, design size constraints (or basic layout unit information), and genetic algorithm parameters, such as population size, iteration algebra, crossover/mutation rate and other parameters.
  • the edge weight of the connection graph is used as the design variable
  • the minimum size of the basic layout unit and the size of the substrate frame of the power module are used as the design constraints.
  • Step S1002 initial population: Calculate the DNA of the randomly generated initial population according to the size constraint map. That is to say, randomly select multiple groups of w 1 -w n and h 1 -h m size constraint graph edge length parameters, n represents the number of edges in the size constraint graph in the horizontal direction, m represents the size constraint graph in the vertical direction The number of middle edges.
  • Step S1003 generate a layout: call the layout generation module 134, let the layout generation module 134 according to the length parameters of the edges in the size constraint graph of multiple sets of w 1 -w n and h 1 -h m selected in step S1002, A substrate layout of a corresponding set of generated power modules is generated. Among them, the number of selected groups is related to the number of input populations.
  • Step S1004 fitness evaluation: evaluating the parasitic inductance in the commutation circuit and evaluating the parasitic inductance of the chip branch in the switching unit.
  • the inductance evaluation module 135 is invoked to allow the inductance evaluation module 135 to evaluate the parasitic inductance of the multiple sets of substrate layouts of the generated power modules generated in step S1003, so as to obtain the parasitic inductance in the commutation circuit and the value in the evaluation switch unit.
  • the parasitic inductance of the chip branch is invoked to allow the inductance evaluation module 135 to evaluate the parasitic inductance of the multiple sets of substrate layouts of the generated power modules generated in step S1003, so as to obtain the parasitic inductance in the commutation circuit and the value in the evaluation switch unit.
  • the parasitic inductance of the chip branch is invoked to allow the inductance evaluation module 135 to evaluate the parasitic inductance of the multiple sets of substrate layouts of the generated power modules generated in step S1003, so as to obtain the parasitic in
  • Step S1005 sorting by fitness: calculating Pareto (pareto) grade and congestion degree. Specifically, the commutation circuits corresponding to each group of layouts are sorted according to the minimum parasitic inductance and the minimum difference in the parasitic inductance of the chip branch in the evaluation switch unit, and the commutation circuits are sorted according to the minimum parasitic inductance and the chip branch in the evaluation switch unit. The layout of the top M group with the smallest difference in the parasitic inductance of the circuit is preserved.
  • Step S1006 whether the maximum number of generations is reached: judge whether the maximum number of generations is reached, if not, execute step S1007, if reach the maximum number of generations, execute step S1009.
  • Step S1007 generating offspring: screen out the parent offspring according to the sorting, generate offspring DNA through crossover and mutation, and generate a new population.
  • the length parameters of the edges in the size constraint graphs corresponding to the first M groups of layouts are modified to generate M groups of edge length parameters in the size constraint graphs with different values.
  • the modification of the length parameters of the edges in the size constraint graph is generally modified in one direction, such as increasing the length parameters of the edges in the size constraint graph in the M group, or increasing the length parameters of the edges in the M group Reduced length parameters for edges in size constraint graphs.
  • Step S1008 perform algebraic superposition for one generation, and then execute step S1003.
  • Step S1009 design output: outputting the global pareto frontier design set and previous design sets, that is, the optimal power module substrate layout.
  • connection graph input into the genetic algorithm is the 16 connection graphs shown in Figure 9, the number of initial populations is selected as 30, and the maximum number of iterations is 50, and then iterative optimization is performed according to the steps shown in Figure 10 , the previous iteration results and the finally obtained pareto front are shown in Figure 11, the relationship between the parasitic inductance of the commutation circuit and the parasitic inductance of the chip branch in the switching unit corresponding to five different layouts.
  • the optimization goal is to minimize the difference between the parasitic inductance of the commutation circuit and the parasitic inductance of the chip branch in the switch unit
  • the power module can be
  • the geometric layout of the substrate is input into the genetic calculation model constructed by the genetic algorithm for optimization search, and the minimum parasitic inductance of the commutation circuit and the minimum difference between the parasitic inductance of the chip branch in the switching unit are obtained.
  • the geometric layout of the substrate of the module is used as the optimal geometric layout, and then the geometric layout is output to obtain the optimal geometric layout of the substrate of the power module.
  • this application selects the frontier solution C for simulation verification, and the switching waveform is shown in Figure 13.
  • the design index of the power module includes the voltage peak during the turn-off process, and the current balance during the turn-on and turn-off process.
  • the evaluation results of the frontier solution C are shown here. Its voltage peak is small and the current part is uniform, which verifies the validity of the substrate design scheme of the power module designed in this application.
  • the genetic algorithm is used to optimize the substrate layout of the power module, which can realize automation The design of the substrate layout, and the performance is relatively excellent.
  • Fig. 14 is a schematic frame diagram of a power module substrate design device provided in an embodiment of the present application.
  • the substrate design device of a power module the device 1400 includes a transceiver unit 1401 and a processing unit 1402 .
  • the functions performed by each unit are as follows:
  • the transceiver unit 1401 is used to obtain input parameters for designing the substrate of the power module, the input parameters include information about the circuit topology required for the design of the substrate of the power module; the processing unit 1402 is used to The information of the circuit topology and the pre-stored structure diagram of each basic layout unit determine the type of basic layout unit and the quantity of each basic layout unit on the circuit topology, and the basic layout unit is The minimum unit of the geometric layout of the substrate constituting the power unit; and using a pathfinding model to connect the connection paths of the graph elements of each basic layout unit on the circuit topology to obtain the connection of the substrate of the power module
  • the graph elements are the nodes and interconnected edges of the connection graph formed by pre-stored basic layout units on the circuit topology
  • the connected path is two nodes in the graph elements of a basic layout unit, or two basic layout units.
  • the processing unit 1402 is specifically configured to generate a netlist of the circuit topology according to the information of the circuit topology; and calculate The types of basic layout units on the netlist of the circuit topology and the quantity of each type of basic layout units, the types of the basic layout units include switch units, absorption units, terminal units and line units.
  • the pathfinding model is at least one of an integer programming model and a depth-optimized search model.
  • the processing unit 1402 is specifically configured to determine at least one commutation network on the netlist of the circuit topology, at least one communication path in each commutation network, and the length of each communication path
  • the commutation network refers to a network path between two nodes on the netlist of the circuit topology, and the two nodes are the two nodes where the two ports of the switch unit are located, and/or the two nodes of the absorbing unit Two nodes where two ports are located, and/or two nodes where one port of two different switch units is located, and/or two nodes where one port of two different absorbing units is located, and/or Or two nodes where one port of a switching unit and one absorbing unit is located; according to the optimization objective, the constraints of the commutation network and the constraints of the nodes on the commutation network, the linear programming model is trained to build an integer programming model ; Input at least one connected path in each commutation network and the length of each connected path into the integer programming model to obtain a target
  • the processing unit 1402 is specifically configured to determine at least one commutation network on the netlist of the circuit topology, at least one communication path in each commutation network, and the length of each communication path
  • the commutation network refers to a network path between two nodes on the net list of the circuit topology, and the two nodes are two nodes where the two ports of the switch unit are located, and/or two different Two nodes where one port of the switch unit is located, and/or two nodes where one port of two different terminal units is located, and/or two nodes where one port of a switch unit and a terminal unit is located node; according to the optimization objective, the constraints of the commutation network and the constraints of the nodes on the commutation network, the linear programming model is trained to construct an integer programming model; at least one connected path in each of the commutation networks and The length of each connected path is input into the integer programming model to obtain a target commutation path in each commutation network, and the target commutation
  • a commutation path on each network node of the target commutation path in each of the commutation networks, a line node is established, and on each of the target commutation paths in the commutation network, an interconnection edge is established,
  • the line nodes are nodes arranged by line units; and outputting the non-empty nodes and interconnection edges on the netlist of the circuit topology to obtain the connection graph of the substrate of the power module.
  • the input parameters also include design size constraints of the basic layout unit; the processing unit 1402 is also configured to determine the original size of each basic layout unit according to the design size constraints. Size; according to the original size of each basic layout unit and the pre-stored scaling variable of each basic layout unit, scan the connection diagram of the substrate of the power module to obtain a size constraint diagram of the connection diagram, the The size constraint graph is used to limit the size of each basic layout unit when constructing the geometric layout according to the connection graph.
  • the processing unit 1402 is specifically configured to scan the connection diagram of the substrate of the power module along the first direction to obtain a size constraint diagram of the connection diagram in the first direction; and The connection diagram of the substrate of the power module is scanned along the second direction to obtain a size constraint diagram of the connection diagram in the second direction; the first direction and the second direction are mutually perpendicular directions.
  • the size constraint graph includes constraint nodes and constraint edges
  • the constraint nodes are scan lines scanning the connection graph of the substrate of the power module
  • the constraint edges are scan lines between scan lines The distance is used to constrain the size of each basic layout unit.
  • the processing unit 1402 is further configured to construct the geometric layout of the substrate of the power module according to the connection diagram of the substrate of the power module and the size constraint diagram of the connection diagram.
  • the processing unit 1402 is further configured to detect the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module, and/or the parasitic inductance of the chip branch in the switch unit, and /or the thermal resistance of the chip in the switch unit; when the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module is greater than the first threshold value, and/or the parasitic inductance of the chip branch in the switch unit is smaller than the second When the threshold value and/or the thermal resistance of the chip in the switch unit is less than a third threshold value, the geometric layout of the substrate of the power module is output.
  • the processing unit 1402 is further configured to: when the parasitic inductance of the commutation circuit of the geometric layout of the substrate of the power module is not less than the first threshold, and/or the chip branch in the switch unit When the parasitic inductance of the switch unit is not less than the second threshold, and/or the thermal resistance of the chip in the switch unit is not less than the third threshold, the geometric layout of the substrate of the power module is reconstructed.
  • the processing unit 1402 is further configured to input the geometric layout of the substrate of the power module into the genetic calculation model, and output the target geometric layout, and the target geometric layout satisfies the set
  • the geometric layout of the substrate of the power module according to the conditions, the set condition is to reduce the parasitic inductance value of the commutation circuit, and/or reduce the parasitic inductance difference value of the chip branch in the switching unit , and/or reduce the thermal resistance of the chip in the switch unit to reach the Pareto optimization frontier.
  • an embodiment of the present application provides a terminal device, including: at least one transceiver; at least one memory; and at least one processor, the processor is configured to execute instructions stored in the memory, so that the terminal device performs the following Figures 1 to 13 and the above corresponding protected technical solutions enable the terminal device to have the technical effect of the above protected technical solutions.
  • the embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored.
  • the computer program is executed in the computer, the computer is instructed to execute the above-mentioned steps described in the above-mentioned Figures 1-13 and the corresponding descriptions. Either method.
  • An embodiment of the present application also provides a computer program product, the computer program product stores instructions, and when the instructions are executed by a computer, the computer implements the above-mentioned steps described in Figures 1-13 and the corresponding descriptions. Either method.
  • computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or tapes, etc.), optical disks (e.g., compact discs (compact discs, CDs), digital versatile discs (digital versatile discs, DVDs), etc.), smart cards and flash memory devices (for example, erasable programmable read-only memory (EPROM), card, stick or key drive, etc.).
  • magnetic storage devices e.g., hard disks, floppy disks, or tapes, etc.
  • optical disks e.g., compact discs (compact discs, CDs), digital versatile discs (digital versatile discs, DVDs), etc.
  • smart cards and flash memory devices for example, erasable programmable read-only memory (EPROM), card, stick or key drive, etc.
  • various storage media described herein can represent one or more devices and/or other machine-readable media for storing information.
  • the term "machine-readable medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing and/or carrying instructions and/or data.
  • the power module substrate design apparatus 1400 in FIG. 14 may be fully or partially implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part.
  • the computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, DSL) or wireless (eg, infrared, wireless, microwave, etc.) means.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media.
  • the available medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a high-density digital video disc (digital video disc, DVD)), or a semiconductor medium (for example, a solid state disk (solid state disk) , SSD)) etc.
  • a magnetic medium for example, a floppy disk, a hard disk, a magnetic tape
  • an optical medium for example, a high-density digital video disc (digital video disc, DVD)
  • a semiconductor medium for example, a solid state disk (solid state disk) , SSD)
  • sequence numbers of the above-mentioned processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not The implementation process of the embodiment of the present application constitutes no limitation.
  • the disclosed systems, devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • the functions described above are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for enabling a computer device (which may be a personal computer, a server, or an access network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本申请提供了一种功率模块的衬底设计方法、装置和终端设备，功率模块技术领域。其中，所述方法包括：获取设计功率模块的衬底的输入参数；根据电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定电路拓扑上的基本布图单元的种类和数量；利用寻路模型，连接电路拓扑上各个基本布图单元的图元素的连通路径，得到功率模块的衬底的连接图。本申请中，通过定义基本布图单元的图论模型，描述基本布图单元的相对位置和连接关系，再通过整数规划模型，在电路拓扑上确定出每个换流网络中的最优连通路径，并建立每个最优连通路径相应的线路单元的节点和互联边，从而构建出连接图，此过程无需人工布图模板的输入，实现功率模块的衬底布图自主设计。

Description

一种功率模块的衬底设计方法、装置和终端设备
本申请要求于2021年12月27日提交中国国家知识产权局、申请号为202111619868.6、申请名称为“一种功率模块的衬底设计方法、装置和终端设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及功率模块技术领域，尤其涉及一种功率模块的衬底设计方法、装置和终端设备。
背景技术
随着大容量的新能源发电系统、电动汽车的电驱系统等领域的发展，功率模块的功率密度和芯片的通流能力的需求日益增长，通常将多个芯片封装在功率模块中使用。但是，由于芯片的高速开关和功率模块衬底线路的寄生电感效应，会限制芯片性能，因此降低并均衡功率模块内部的寄生电感，对于提高功率模块的性能和安全性十分重要。
随着功率模块的工艺进步，吸收电容等异质元件被集成到模块中，可以极大地提升功率模块的功率密度，但是也使得功率模块的衬底设计日趋复杂。由于功率模块的应用范围广、功率等级多等特点，不同应用场景下衬底的设计难以复用，而且现有的功率模块的衬底依赖人工的设计，耗时耗力。
发明内容
为了解决上述的问题，本申请的实施例中提供了一种功率模块的衬底设计方法、装置和终端设备，使用连接图模型描述基本布图单元的相对位置和连接关系，结合整数规划算法，可实现变几何拓扑的多样布图生成，无需人工布图模板输入；使用约束图描述布图尺寸，内含设计尺寸约束，因此生成质量高，无需在后处理环节进行设计规则检查；以换流回路的寄生电感最小和开关单元内芯片支路的寄生电感差异最小为优化目标，使用遗传算法对功率模块的衬底的几何布图进行优化计算，可实现自动化的衬底布图设计。
为此，本申请的实施例中采用如下技术方案：
第一方面，本申请实施例提供一种功率模块的衬底设计方法，包括：获取设计功率模块的衬底的输入参数，所述输入参数包括所述功率模块的衬底设计所需要的电路拓扑的信息；
根据所述电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定所述电路拓扑上的基本布图单元的种类和每种基本布图单元的数量，所述基本布图单元是构成所述功率单元的衬底的几何布图的最小单元；利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，所述图元素为预先存储的基本布图单元在电路拓扑上构成连接图的节点和互联边，所述连通路径是一个基本布图单元的图元素中的两个节点、或两个基本布图单元的图元素中的一个节点之间的路径。
在该实施方式中，通过定义基本布图单元的图论模型，描述基本布图单元的相对位置和连接关系，再通过整数规划模型，在功率模块的衬底设计所需要的电路拓扑上确定出每个换流网络中的最优连通路径，以及建立每个最优连通路径相应的线路单元的节点和互联边，从而构建出连接图，此过程无需人工布图模板的输入，可以不依赖专家经验，实现功率模块的 衬底布图自主设计。
在一种实施方式中，所述根据所述电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定所述电路拓扑上的基本布图单元的种类和每种基本布图单元的数量，具体包括：根据所述电路拓扑的信息，生成所述电路拓扑的网表；根据所述预先存储的每种基本布图单元的结构图，计算出所述电路拓扑的网表上的基本布图单元的种类和每一种基本布图单元的数量，所述基本布图单元的种类包括开关单元、吸收单元、端子单元和线路单元。
在该实施方式中，通过预先存储的各种基本布图单元的结构图，对输入的电路拓扑的网表进行处理，可以识别出电路拓扑的网表中各个基本布图单元，得到电路拓扑的网表上具体有几种类型的基本布图单元，以及每种基本布图单元的数量，为后续生成连接图，提供基础，可以降低功率模块的衬底设计难度。
在一种实施方式中，所述寻路模型为整数规划模型和深度优选搜索模型中的至少一种。
在该实施方式中，在生成连接图的过程，对于设定的两个节点之间的换流网络中，一般存在多个流通路径，可以选用如整数规划算法构成的整数规划模型或深度优选搜索算法构成的深度优选搜索模型来选择出换流网络中路径最短的流通路径，使得设计出的功率模块的衬底的连接图的结构简单，可以降低功率模块的制造成本。
在一种实施方式中，所述利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，具体包括：确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或吸收单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的吸收单元的一个端口所处的两个节点、和/或一个开关单元和一个吸收单元的一个端口所处的两个节点；根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；利用深度优选搜索模型，在所述每个换流网络中的目标换流路径上，建立端子路径，以及在所述端子路径上建立端子节点和互联边，所述端子路径为所述端子单元连接到换流网络的路径，所述端子节点为端子单元布置的节点；输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
在该实施方式中，如果基本布图单元中，一般都是有开关单元和端子单元，如果还包括有吸收单元，则可以根据开关单元和吸收单元来构建换流路径，通过开关单元的端口和吸收单元的端口在电路拓扑的网表上对应的节点之间构建各个换流网络，然后选择出每个换流网络的最短路径，并连接各个换流网络的最优换流路径，再将各个端子单元连接到换流路径上，最后建立换流路径的线路节点和互联边，得到功率模块的衬底的连接图。由于吸收单元对换流回路的寄生电感和开关单元内芯片支路的寄生电感差异的影响比端子单元大，所以优选通过开关单元和吸收单元来构建换流路径，可以有效降低换流回路的寄生电感和减小开关单元内芯片支路的寄生电感差异。
在一种实施方式中，所述利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，具体包括：确定所述电路拓扑的网表上 至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的端子单元的一个端口所处的两个节点、和/或一个开关单元和一个端子单元的一个端口所处的两个节点；根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
在该实施方式中，如果基本布图单元中，一般都是有开关单元和端子单元，如果不包括有吸收单元，则可以根据开关单元和端子单元来构建换流路径，通过开关单元的端口和端子单元的端口在电路拓扑的网表上对应的节点之间构建各个换流网络，然后选择出每个换流网络的最短路径，并连接各个换流网络的最优换流路径，最后建立换流路径的线路节点和互联边，得到功率模块的衬底的连接图。通过将有节点的开关单元和端子单元来构建换流路径，可以有效降低换流回路的寄生电感和减小开关单元内芯片支路的寄生电感差异。
在一种实施方式中，所述输入参数还包括基本布图单元的设计尺寸约束条件；所述方法还包括：根据所述设计尺寸约束条件，确定所述每种基本布图单元的原始尺寸；
根据每种基本布图单元的原始尺寸和预先存储的每种基本布图单元的缩放变量，对所述功率模块的衬底的连接图进行扫描，得到连接图的尺寸约束图，所述尺寸约束图用于在根据连接图构建几何布图时，限定所述各个基本布图单元的尺寸。
在该实施方式中，根据设计尺寸的约束条件，可以计算每种基本布图单元的原始尺寸，也即最小尺寸，然后结合预先存储的每种基本布图单元的缩放变量，对功率模块的衬底的连接图进行扫描，得到连接图的尺寸约束图，可以对后续构建几何布图时，对布图的各个基本布图单元的尺寸进行限定，可以使用尺寸约束图来描述不同的尺寸，内含有涉及尺寸约束，所以生成的功率模块的衬底模板质量高，无需在后续处理环节进行设计规则检测。
在一种实施方式中，所述对所述功率模块的衬底的连接图所在的电路拓扑的网表进行扫描，得到连接图的尺寸约束图，具体包括：对所述功率模块的衬底的连接图沿第一方向进行扫描，得到连接图的在第一方向上的尺寸约束图；和对所述功率模块的衬底的连接图沿第二方向进行扫描，得到连接图的在第二方向上的尺寸约束图；所述第一方向与所述第二方向为相互垂直的方向。
在该实施方式中，通过从水平方向上和垂直方向上对连接图进行扫描，得到连接图的水平方向上的尺寸约束图和垂直方向上的尺寸约束图，通过从两个相互垂直的方向构建的尺寸约束图，可以达到对基本布图单元出尺寸进行限定，使得构建的功率模块的衬底的几何布图的尺寸为最优选的尺寸，模板质量高，无需在后续处理环节进行设计规则检测。
在一种实施方式中，所述尺寸约束图包括约束节点和约束边，所述约束节点为对所述功率模块的衬底的连接图进行扫描的扫描线，所述约束边为扫描线之间的距离，用于约束所述各个基本布图单元的尺寸。
在该实施方式中，约束节点一般对应到连接图边缘处的线路节点、端子节点、开关节点、或吸收节点，约束边一般对应到相邻两个节点之间的距离，通过以约束节点作为扫描边，可 以将接连图进行割裂，得到连接图中每个可以放置基本布图单元的区域，然后根据可以放置基本布图单元的区域尺寸，作为约束边，来限定可放置的基本布图单元的尺寸，实现对连接图进行布图是对尺寸的限定，使得构建的功率模块的衬底的几何布图的尺寸为最优选的尺寸。
在一种实施方式中，所述方法还包括：根据所述功率模块的衬底的连接图和所述连接图的尺寸约束图，构建所述功率模块的衬底的几何布图。
在该实施方式中，在构建功率模块的衬底的几何布图过程中，可以通过连接图确定各个基本布图单元的数量和布置的位置，可以通过尺寸约束图限定各个基本布图单元的尺寸，实现构建功率模块的衬底的几何布图，以及构建的功率模块的衬底的几何布图的尺寸最佳。
在一种实施方式中，所述方法还包括：检测所述功率模块的衬底的几何布图的换流回路的寄生电感、和/或开关单元中的芯片支路的寄生电感、和/或开关单元中芯片的热阻；当所述功率模块的衬底的几何布图的换流回路的寄生电感小于第一阈值、和/或开关单元中的芯片支路的寄生电感大于第二阈值、和/或开关单元中芯片的热阻小于第三阈值时，输出所述功率模块的衬底的几何布图。
在该实施方式中，构建出功率模块的衬底的几何布图后，需要从换流回路的寄生电感、开关单元中的芯片支路的寄生电感和开关单元中芯片的热阻这三个条件中至少一个条件，来检测功率模块的衬底的几何布图的好坏，如果换流回路的寄生电感较小，或开关单元中的芯片支路的寄生电感差异较小，或开关单元中芯片的热阻较小，表明设计出的检测功率模块的衬底的几何布图的性能比较好。
在一种实施方式中，所述方法还包括：当所述功率模块的衬底的几何布图的换流回路的寄生电感不小于第一阈值、和/或开关单元中的芯片支路的寄生电感不小于第二阈值、和/或开关单元中芯片的热阻不小于第三阈值时，重新构建所述功率模块的衬底的几何布图。
在该实施方式中，如果构建出功率模块的衬底的几何布图中，出现换流回路的寄生电感较大，或开关单元中的芯片支路的寄生电感差异较大，或开关单元中芯片的热阻较大，表明设计出的检测功率模块的衬底的几何布图的性能比较差，需要重新设计。
在一种实施方式中，还包括：将所述功率模块的衬底的几何布图输入到遗传计算模型中，输出目标几何布图，所述目标几何布图为满足设定条件的所述功率模块的衬底的几何布图，所述设定条件为降低所述换流回路的寄生电感数值、和/或减小所述开关单元中的芯片支路的寄生电感差异值、和/或降低开关单元中芯片的热阻达到帕累托优化前沿。
在该实施方式中，构建出功率模块的衬底的几何布图后，以换流回路的寄生电感最小、和/或开关单元中的芯片支路的寄生电感的差异最小、和/或开关单元中芯片的热阻最小为优化目标，可以将功率模块的衬底的几何布图输入到遗传算法构建的遗传计算模型中进行寻优查找，得到换流回路的寄生电感最小、开关单元中的芯片支路的寄生电感的差异最小和开关单元中芯片的热阻最小三个参数达到帕累托优化前沿，作为最优的几何布图，然后输出该几何布图，得到最佳的功率模块的衬底的几何布图。
第二方面，本申请实施例提供一种功率模块的衬底设计装置，包括：收发单元，用于获取设计功率模块的衬底的输入参数，所述输入参数包括所述功率模块的衬底设计所需要的电路拓扑的信息；处理单元，用于根据所述电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定所述电路拓扑上的基本布图单元的种类和每种基本布图单元的数量，所述基本布图单元是构成所述功率单元的衬底的几何布图的最小单元；和利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，所述 图元素为预先存储的基本布图单元在电路拓扑上构成连接图的节点和互联边，所述连通路径是一个基本布图单元的图元素中的两个节点、或两个基本布图单元的图元素中的一个节点之间的路径。
在一种实施方式中，所述处理单元，具体用于根据所述电路拓扑的信息，生成所述电路拓扑的网表；根据所述预先存储的每种基本布图单元的结构图，计算出所述电路拓扑的网表上的基本布图单元的种类和每一种基本布图单元的数量，所述基本布图单元的种类包括开关单元、吸收单元、端子单元和线路单元。
在一种实施方式中，所述寻路模型为整数规划模型和深度优选搜索模型中的至少一种。
在一种实施方式中，所述处理单元，具体用于确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或吸收单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的吸收单元的一个端口所处的两个节点、和/或一个开关单元和一个吸收单元的一个端口所处的两个节点；根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；利用深度优选搜索模型，在所述每个换流网络中的目标换流路径上，建立端子路径，以及在所述端子路径上建立端子节点和互联边，所述端子路径为所述端子单元连接到换流网络的路径，所述端子节点为端子单元布置的节点；和输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
在一种实施方式中，所述处理单元，具体用于确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的端子单元的一个端口所处的两个节点、和/或一个开关单元和一个端子单元的一个端口所处的两个节点；根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边；和输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
在一种实施方式中，所述输入参数还包括基本布图单元的设计尺寸约束条件；所述处理单元，还用于根据所述设计尺寸约束条件，确定所述每种基本布图单元的原始尺寸；根据每种基本布图单元的原始尺寸和预先存储的每种基本布图单元的缩放变量，对所述功率模块的衬底的连接图进行扫描，得到连接图的尺寸约束图，所述尺寸约束图用于在根据连接图构建几何布图时，限定所述各个基本布图单元的尺寸。
在一种实施方式中，所述处理单元，具体用于对所述功率模块的衬底的连接图沿第一方 向进行扫描，得到连接图的在第一方向上的尺寸约束图；和对所述功率模块的衬底的连接图沿第二方向进行扫描，得到连接图的在第二方向上的尺寸约束图；所述第一方向与所述第二方向为相互垂直的方向。
在一种实施方式中，所述尺寸约束图包括约束节点和约束边，所述约束节点为对所述功率模块的衬底的连接图进行扫描的扫描线，所述约束边为扫描线之间的距离，用于约束所述各个基本布图单元的尺寸。
在一种实施方式中，所述处理单元，还用于根据所述功率模块的衬底的连接图和所述连接图的尺寸约束图，构建所述功率模块的衬底的几何布图。
在一种实施方式中，所述处理单元，还用于检测所述功率模块的衬底的几何布图的换流回路的寄生电感、和/或开关单元中的芯片支路的寄生电感、和/或开关单元中芯片的热阻；当所述功率模块的衬底的几何布图的换流回路的寄生电感大小第一阈值、和/或开关单元中的芯片支路的寄生电感小于第二阈值、和/或开关单元中芯片的热阻小于第三阈值时时，输出所述功率模块的衬底的几何布图。
在一种实施方式中，所述处理单元，还用于当所述功率模块的衬底的几何布图的换流回路的寄生电感不小于第一阈值、和/或开关单元中的芯片支路的寄生电感不小于第二阈值、和/或开关单元中芯片的热阻不小于第三阈值时，重新构建所述功率模块的衬底的几何布图。
在一种实施方式中，所述处理单元，还用于将所述功率模块的衬底的几何布图输入到遗传计算模型中，输出目标几何布图，所述目标几何布图为满足设定条件的所述功率模块的衬底的几何布图，所述设定条件为降低所述换流回路的寄生电感数值、和/或减小所述开关单元中的芯片支路的寄生电感差异值、和/或降低开关单元中芯片的热阻达到帕累托优化前沿。
第三方面，本申请实施例提供一种终端设备，包括：至少一个收发器；至少一个存储器；至少一个处理器，所述处理器用于执行存储器中存储的指令，以使得所述终端设备执行如第一方面各个可能实现的实施例。
第四方面，本申请实施例提供一种计算设备，其特征在于，包括存储器和处理器，所述存储器用于存储指令，所述处理器用于调用所述存储器中存储的指令，实现如第一方面各个可能实现的实施例。
第五方面，本申请实施例提供一种计算机可读存储介质，其上存储有计算机程序，当所述计算机程序在计算机中执行时，令计算机执行如第一方面各个可能实现的实施例。
第六方面，本申请实施例提供一种计算机程序产品，其特征在于，所述计算机程序产品存储有指令，所述指令在由计算机执行时，使得所述计算机实施如第一方面各个可能实现的实施例。
附图说明
下面对实施例或现有技术描述中所需使用的附图作简单地介绍。
图1为本申请实施例中提供的一种终端设备的架构示意图；
图2为本申请实施例中提供的一种处理器的架构示意图；
图3为本申请实施例中提供的各个基本布图单元的几何布图、图元素和缩放变量的关系示意图；
图4为本申请实施例中提供的一种功率模块的衬底的连接图生成过程的流程图；
图5为本申请实施例中提供的另一种功率模块的衬底的连接图生成过程的流程图；
图6(a)为本申请实施例中提供的一种电路拓扑的网表上的两个节点之间的换流网路中 各种连通路径的示意图；
图6(b)为本申请实施例中提供的另一种电路拓扑的网表上的两个节点之间的换流网路中各种连通路径的示意图；
图7(a)为本申请实施例中提供的一种功率模块的衬底的连接图；
图7(b)为本申请实施例中提供的基于图7(a)所示的连接图构建的几何布图；
图7(c)为本申请实施例中提供的基于图7(a)所示的连接图得到水平方向上的尺寸约束图和垂直方向上的尺寸约束图；
图8(a)为本申请实施例中提供的基于图7(c)所示的尺寸约束图沿水平方向镜像对称拓展后的水平方向上的尺寸约束图和垂直方向上的尺寸约束图；
图8(b)为本申请实施例中提供的基于图7(b)所示的布图沿水平方向镜像对称拓展后的几何布图；
图9为本申请实施例中提供的根据其它16种不同功率模块的衬底的连接图构建的对应几何布图；
图10为本申请实施例中提供的通过遗传算法优化功率模块的衬底布图的过程流程图；
图11为本申请实施例中提供的历次迭代结果和帕累托前沿结果拟合示意图；
图12为本申请实施例中提供的三个前沿结果的布图和对应设计参数的示意图；
图13为本申请实施例中提供的前沿解C进行仿真评估的结果示意图；
图14为本申请实施例中提供的一种功率模块的衬底设计装置的框架示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
本文中术语“和/或”，是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。本文中符号“/”表示关联对象是或者的关系，例如A/B表示A或者B。
本文中的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一响应消息和第二响应消息等是用于区别不同的响应消息，而不是用于描述响应消息的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或者两个以上，例如，多个处理单元是指两个或者两个以上的处理单元等；多个元件是指两个或者两个以上的元件等。
功率模块是指将功率电力电子器件按照一定的功能组合，再灌封成一个模块。由于功率模块与集成电路在元件类型、工作模式、制造工艺等方面存在差异，所以现有针对集成电路的电子设计自动化工具，难以满足功率模块的设计要求。另外，现有的针对功率模块的自动化设计方法还处在起步阶段，存在许多缺陷，如：需要人为输入布局模板，导致生成的功率模块的自由度受限，且严重依赖专家的经验；布图描述模型不包括线路连通性约束和设计尺寸约束，导致生成的功率模块可制造性差，优化效率比较低；设计功率模块时只关注如何降低换流回路的寄生电感，并没有考虑到开关单元中的芯片支路的寄生电感均衡性的优化，导 致设计的功率模块性能差。
有基于此，本申请以基本布图单元的图论模型为基础，使用线性规划算法生成多样的布图的连通模板，再使用遗传算法计算换流回路的寄生电感最小和开关单元中的芯片支路的寄生电感最均衡的单元尺寸，实现功率模块的衬底布图自主设计。
图1为本申请实施例中提供的一种终端设备的架构示意图。如图1所示，该终端设备100包括收发器110、存储器120、处理器130和总线140。其中，收发器110、存储器120和处理器130分别通过总线140建立通信连接，实现各个模块之间相互通信。
其中，收发器110可以实现信号的输入(接收)和输出(发送)。例如，收发器110可以包括收发器或射频芯片。收发器110还可以包括通信接口。示例性的，终端设备100可以通过收发器110接收如终端设备、云端等其它设备发送的数据，也可以通过收发器110将处理器130处理后的数据发送至其它设备上。
存储器120上可以存有程序(也可以是指令或者代码)，程序可被处理器130运行，使得处理器130执行基于图论模型的功率模块衬底的设计方法。可选地，存储器120中还可以存储有数据。例如，处理器130可以读取存储器120中存储的数据，该数据可以与程序存储在相同的存储地址，该数据也可以与程序存储在不同的存储地址。本方案中，处理器130和存储器120可以单独设置，也可以集成在一起，例如，集成在单板或者系统级芯片(system on chip，SOC)上。
处理器130可以是通用处理器或者专用处理器。例如，处理器130可以包括中央处理器(central processing unit，CPU)和/或基带处理器。示例性的，处理器130可以根据收发器110接收的其它设备发送的数据，执行基于图论模型的功率模块衬底设计方法，并生成功率模块的衬底的设计方案。
可以理解的是，本申请实施例示意的结构并不构成对终端设备100的具体限定。在本申请另一些实施例中，终端设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
图2为本申请实施例中提供的一种处理器的架构示意图。如图2所示，处理器130可以根据执行功能，划分为参数预处理模块131、连接图生成模块132、约束图生成模块133、布图生成模块134、电感评估模块135和优化处理模块136。其中，各个模块执行的功能具体如下：
处理器130在执行基于图论模型的功率模块的衬底设计方法之前，需要通过收发器120获取功率模块的衬底设计的输入参数，如功率模块的配置信息、设计尺寸的约束条件等等。示例性地，功率模块的衬底设计的输入参数可以为如表1所示的参数，具体为：
表1 功率模块的衬底设计的输入参数
Figure PCTCN2022114437-appb-000001
Figure PCTCN2022114437-appb-000002
其中，功率模块的衬底设计所需要的电路拓扑的信息包括有电路拓扑的类型，如半桥型，设计尺寸的约束条件包括芯片的尺寸、吸收电容的尺寸、端子焊盘的尺寸、金属层线宽、金属层间距、金属层厚度、焊接间距、键合间距等等。可选地，功率模块的衬底设计所需要的电路拓扑选用半桥类型，并联芯片的数量为4个，芯片的尺寸为5.9×3.1mm，吸收电容的尺寸为6.0×5.0mm，端子焊盘的尺寸大于等于3.0×3.0mm，金属层线宽大于等于1.0mm，金属层间距为0.7mm，金属层厚度为0.3mm，焊接间距大于等于1.0mm，键合间距大于等于1.0mm，本申请在此仅作示例，并不作为本申请的限定。
参数预处理模块131用于根据功率模块的衬底设计所需要的电路拓扑的信息，生成电路拓扑的网表(netlist)，并结合预先储存的各个基本布图单元的结构图，确定出电路拓扑的网表上存在的基本布图单元的种类个每种基本布图单元的数量。其中，电路拓扑又称电路的图，是对电路图进行再次抽象、仅由支路(branch)和节点(node)构成的一个集合，构成电路的每一个二端元件称为一条支路，两条或两条以上支路的连接点称为节点。它讨论的是电路的连接关系及其性质，即支路与节点的连接关系。本申请中，功率模块的衬底设计所需要的电路拓扑的信息输入到参数预处理模块131中，会自动生成该电路拓扑的网表，其包括有电路元件的名称、电路元件的编号、电路元件的端口编号、端口件是否互联的连通性信息等等。
基本布图单元，也即构成功率模块的最小单元。本申请中，基本布图单元可以分为开关单元、吸收单元、端子单元、线路单元以及其它单元。其中，基本布图单元一般是由芯片组和金属层构成，芯片组中包括有至少一个芯片和/或至少一个元器件，芯片组中的各个芯片或元器件可以通过电连接在金属层上，并让金属层与电路拓扑上的节点电连接，实现芯片组与功率模块的衬底电连接，可以降低功率模块的衬底设计难度。
参数预处理模块131还用于根据确定基本布图单元的种类和设计尺寸的约束条件，确定出各种类型的基本布图单元的几何布图结构、图元素和缩放变量等基本布图单元的信息。其中，基本布图单元的几何布图中包括至少一个金属层，或者还包括有芯片组。如果还包括有芯片组，则芯片组中包括有至少一个芯片和/或至少一个元器件，每个芯片或元器件尽可能的部署在金属层的中间位置上，且每个芯片或元器件按照线宽最小、线间距最小、焊接间距最小等设计约束条件布置。基本布图单元的图元素是由节点和互联边组成，用于生成连接图。基本布图单元的缩放变量包括有水平方向的缩放变量和垂直方向的缩放变量，用于对基本布图单元沿水平方向的尺寸和垂直方向的尺寸进行优化，水平方向与垂直方向是互为垂直的两个方向。
下面具体介绍各个类型的基本布图单元的信息，具体为：
开关单元包括一个芯片组和三个金属层。其中，芯片组是由一个或多个功率半导体芯片组成，芯片组中的各个功率半导体芯片并联地布置在一个金属层上，芯片组中的各个功率半导体芯片通过其顶部的互连结构，将各个功率半导体芯片表面的驱动电极与一个金属层电连接，芯片组中的各个功率半导体芯片表面的功率电极与一个金属层电连接。
示例性地，如图3所示的开关单元的几何布图，开关单元包括芯片组、第一金属层、第二金属层和第三金属层，芯片组中有三个功率半导体芯片，每个功率半导体芯片并联地布置在第一金属层上；功率半导体芯片通过其顶部的互连结构，将各个功率半导体芯片表面的驱动 电极电连接到第二金属层上；各个功率半导体芯片表面的功率电极电连接到第三金属层上，且第二金属层位于第一金属层和第三金属层中间。优选地，一种开关单元的设计方案中，芯片组在靠近第二金属层的位置上并排布置，使互联结构长度最小。
与图3中的开关单元的几何布图相对应的，开关单元的图元素中，开关单元包括两个相邻的节点和一条互联边。其中，两个相邻的节点表示开关单元在电路拓扑上占用两个相邻的节点，互联边表示开关单元中电流流通路径。
与图3中的开关单元的几何布图相对应的，开关单元的缩放变量包括有芯片组中三个芯片之间的间距、第一金属层的长度和宽度、第二金属层的长度和宽度、第三金属层的长度和宽度等等。其中，开关单元的缩放变量，是指根据缩放变量进行同比例缩小或放大，让开关单元整体进行缩小或放大，而开关单元的形状、各个芯片之间相对位置关系、各个金属层之间相对位置关系、芯片或元器件的尺寸，不会发生变化。
可选地，开关单元的缩放变量可以分为水平方向的缩放变量和垂直方向的缩放变量。其中，水平方向的缩放变量表示芯片组和金属层沿水平方向的尺寸，如第一金属层的宽度、第一金属层的宽度、第一金属层的宽度等等，垂直方向的缩放变量表示芯片组和金属层沿垂直方向的尺寸，如三个芯片之间的间距、第一金属层的长度、第一金属层的长度、第一金属层的长度等等。
因此，处理器130通过收发器110接收到的基本布图单元的信息，包括开关单元的几何布图结构、开关单元的图元素、开关单元的缩放变量等数据。
吸收单元包括一个芯片组和两个金属层。其中，芯片组是由一个或多个吸收电容元件组成，芯片组中的各个吸收电容元件并联地布置在两个金属层的中间位置上，各个吸收电容元件上的电极分别电连接在两个金属层上。可选地，吸收电容元件可以为陶瓷、薄膜和硅材料的去耦电容，也可以为带有电容和电阻特性的阻尼吸收元件，本申请在此不作限定。
示例性地，如图3所示的吸收单元的几何布图，吸收单元包括芯片组、第四金属层和第五金属层。其中，芯片组包括一个吸收电容，该吸收电容布置在第四金属层和第五金属层之间的中间位置上，且吸收电容上的电极分别电连接在第四金属层和第五金属层上。
与图3中的吸收单元的几何布图相对应的，吸收单元的图元素中，吸收单元包括两个相邻的节点和一条互联边。其中，两个相邻的节点表示吸收单元在电路拓扑上占用两个相邻的节点，互联边表示吸收单元中电流流通路径。
与图3中的吸收单元的几何布图相对应的，吸收单元的缩放变量包括有芯片组中第四金属层的长度和宽度、第五金属层的长度和宽度等等。其中，吸收单元的缩放变量，是指根据缩放变量进行同比例缩小或放大，让吸收单元整体进行缩小或放大，而吸收单元的形状、各个金属层之间相对位置关系、芯片或元器件的尺寸，不会发生变化。
可选地，吸收单元的缩放变量可以分为水平方向的缩放变量和垂直方向的缩放变量。其中，水平方向的缩放变量表示芯片组和金属层沿水平方向上的尺寸，如第四金属层的宽度、第五金属层的宽度等等，垂直方向的缩放变量表示芯片组和金属层沿垂直上方向的尺寸，如第四金属层的长度、第五金属层的长度等等。
因此，处理器130通过收发器110接收到的基本布图单元的信息，包括吸收单元的几何布图结构、吸收单元的图元素、吸收单元的缩放变量等数据。
端子单元包括一个芯片组和一个金属层。其中，芯片组是由一个或多个端子元件组成，端子元件上有正极、负极、交流等功率输出端子，每个端子元件上的输出端子布置在一个金属层的中间位置上，并与该金属层电连接。示例性地，如图3所示的端子单元的几何布图，端 子单元包括芯片组和第六金属层。其中，芯片组包括一个端子元件，该端子元件上的正极、负极、交流等功率输出端子布置在第六金属层上，且电连接在第六金属层上。
与图3中的端子单元的几何布图相对应的，端子单元的图元素中端子单元包括一个节点。其中，一个节点表示端子单元在电路拓扑上占用一个节点。
与图3中的端子单元的几何布图相对应的，端子单元的缩放变量包括有第六金属层的长度和宽度等等。其中，端子单元的缩放变量，是指根据缩放变量进行同比例缩小或放大，让端子单元整体进行缩小或放大，而端子单元的形状、芯片或元器件的尺寸，不会发生变化。
可选地，端子单元的缩放变量可以分为水平方向的缩放变量和垂直方向的缩放变量。其中，水平方向的缩放变量表示芯片组和金属层沿水平方向上的尺寸，如第六金属层的宽度等等，垂直方向的缩放变量表示芯片组和金属层沿垂直方向上的尺寸，如第六金属层的长度等等。
因此，处理器130通过收发器110接收到的基本布图单元的信息，包括端子单元的几何布图结构、端子单元的图元素、端子单元的缩放变量等数据。
线路单元是由一个金属层组成。与图3中的线路单元的几何布图相对应的，线路单元的图元素中线路单元包括一个节点。其中，一个节点表示线路单元在电路拓扑上占用一个节点。
与图3中的线路单元的几何布图相对应的，线路单元的缩放变量包括有第七金属层的长度和宽度等等。其中，线路单元的缩放变量，是指根据缩放变量进行同比例缩小或放大，让线路单元整体进行缩小或放大，而线路单元的形状不会发生变化。
可选地，线路单元的缩放变量可以分为水平方向的缩放变量和垂直方向的缩放变量。其中，水平方向的缩放变量表示金属层沿水平方向上的尺寸，如第七金属层的宽度等等，垂直方向的缩放变量表示金属层沿垂直方向上的尺寸，如第七金属层的长度等等。
因此，处理器130通过收发器110接收到的基本布图单元的信息，包括线路单元的几何布图结构、线路单元的图元素、线路单元的缩放变量等数据。
本申请中，每种类型的基本布图单元中的金属层的尺寸之间可以相关联，如端子单元中的第六金属层的尺寸与路线单元中的第七金属层的尺寸相同，再如吸收单元中的第四金属层和第五金属层的尺寸相同，且与端子单元中的第六金属层的尺寸，以及其它金属层的尺寸相同。每种类型的基本布图单元中的金属层的尺寸之间可以不相关联，如每个基本布图单元中的金属层的尺寸不相同，甚至同一类型的基本布图单元的金属层的尺寸也不相同。由于后续生成连接图过程中，需要根据缩放变量进行放大或缩小操作，所以每种类型的基本布图单元中的金属层的尺寸并不作要求。优选地，每种类型的基本布图单元以最小尺寸存在。
本申请实施例中，在设计功率模块的衬底方案之前，通过预处理模块对输入参数进行预处理，得到构成功率模块的衬底的基本布图单元的几何布图的结构、图元素和缩放变量，为后续构建连接图、优化设计出的功率模块的衬底的尺寸提供基础。
连接图生成模块132用于根据输入的电路拓扑的网表中确定的开关单元数量N，生成尺寸不超过2N×2N的正交网格，然后在网格中随机放置开关单元和吸收单元的图元素，再根据电路拓扑，使用整数规划算法寻找换流长度最小的连通路径，并将路径设置为互联边、路径节点设置为线路单元节点，最后将所有非空节点和互联边作为布图模板输出，得到功率模块的衬底的连接图。
如图4所示，如果电路拓扑的网表中包括有吸收单元时，连接图生成模块132构建功率模块的衬底的连接图，具体实现过程如下：
步骤S401，确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少 一条连通路径和每个连通路径的长度。其中，换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径。具体为：
针对电路拓扑的网表中定义的每个换流网络，是指处在电路拓扑的网表中任意位置上的开关单元和吸收单元，利用深度优先搜索模型，获得同一个开关单元的两个端口所处网表上的两个节点、同一个吸收单元的两个端口所处网表上的两个节点、不同两个开关单元的一个端口所处网表上的两个节点、不同两个吸收单元的一个端口所处网表上的两个节点、以及开关单元与吸收单元的一个端口所处网表上的两个节点之间的所有连通路径k条。其中，深度优先搜索模型是指存储有深度优先搜索算法的存储单元、电子设备、云服务器等等。
将每条连通路径定义为整数变量x net,1,…,x net,k，且每个整数变量x net,k的取值范围，为
Figure PCTCN2022114437-appb-000003
同时，记录各个连通路径x net,k的长度l net,1,…,l net,k。
示例性地，如图6(a)所示，选取的两个节点坐标为G(1,2)和G(2,0)的换流网络A，其连通路径可以有两条，分别为{A1,A2}。其中，连通路径A1的路径为：G(1,2)→G(0,2)→G(0,1)→G(1,1)→G(2,1)→G(2,0)，长度l net,A1＝5；连通路径A2的路径为：G(1,2)→G(0,2)→G(0,1)→G(0,0)→G(1,0)→G(1,1)→G(2,1)→G(2,0)，长度l net,A2＝7。
如图6(b)所示，选取的两个节点坐标为G(2,1)和G(0,2)的换流网络B，其连通路径可以有三条，分别为{B1,B2,B3}。其中，连通路径B1的路径为：G(2,1)→G(1,0)→G(1,1)→G(1,2)→G(0,2)，长度l net,B1＝5；连通路径B2的路径为：G(2,1)→G(1,0)→G(0,0)→G(0,1)→G(1,1)→G(1,2)→G(0,2)，长度l net,B2＝7；连通路径B3的路径为：G(2,1)→G(2,0)→G(3,0)→G(3,1)→G(3,2)→G(2,2)→G(1,2)→G(0,2)，长度l net,B3＝7。
本申请中，图6(a)中的两个节点G(1,2)和G(2,0)，可以为同一个开关单元的两个端点所处网表上的两个节点，可以为同一个吸收单元的两个端点所处网表上的两个节点，可以为不同开关单元的端点所处网表上的两个节点，可以为不同吸收单元的端点所处网表上的两个节点，甚至可以为开关单元和吸收单元的端点所处网表上的两个节点。图6(b)中的两个节点G(2,1)和G(0,2)也是如此，在此不再赘述了。
步骤S402，构建整数规划模型。其中，整数规划是线性规划中的一种，将变量限定为整数的线性规划，称为整数规划。整数规划模型是指存储有整数规划算法的存储单元、电子设备、云服务器等等。
在建立整数规划模型之前，确定优化目标为总的换流网络的路径最小，即
Figure PCTCN2022114437-appb-000004
建立整数规划模型的约束条件定义为：
①每个换流网络仅允许有一条路径，即
Figure PCTCN2022114437-appb-000005
②每个网格节点仅容纳一条路径，即
Figure PCTCN2022114437-appb-000006
其中，W为网格宽度，H为网格高度。
然后，根据优化目标、约束条件①和约束条件②，对变量为整数的线性规划模型进行训练，得到整数规划模型。示例性地，仍以图6(a)和图6(b)为例，针对约束条件①，根据公式(3)可以得到，换流网络A的约束条件为：
x A1+x A2＝1；
换流网络B的约束条件为：
x B1+x B2+x B3＝1；
针对约束条件②，根据公式(4)可以得到，由于换流网络A和换流网络B中部分节点交叉，所以每个节点的约束条件为：
G(0,0)：x A2+x B2≤1；
G(0,1)：x A2+x B1+x B2≤1；
G(0,2)：x B≤1；
G(0,3)：x B3≤1；
G(1,0)：x A1+x A2+x B2≤1；
G(1,1)：x A1+x A2+x B1+x B2≤1；
G(1,2)：x A≤1；
G(1,3)：x B3≤1；
G(2,0)：x A≤1；
G(2,1)：x B≤1；
G(2,2)：x B3≤1；
G(2,3)：x B3≤1。
步骤S403，将每个换流网络中的至少一条连通路径和每个连通路径的长度输入到整数规划模型中，得到每个换流网络中的目标换流路径。其中，目标换流路径为每个换流网络中的路径最短的换流路径。具体为：
仍以图6(a)和图6(b)为例，对于换流网络A和换流网络B中，根据优化目标为“路径最小”原则，换流网络A中连通路径A1的长度l net,A1小于连通路径A2的长度l net,A2，所以连通路径A1的优先级高于连通路径A2。同理，换流网络B中连通路径B1的长度l net,B1小于连通路径B2的长度l net,B2，连通路径B1的长度l net,B1也小于连通路径B2的长度l net,B2，所以连通路径B1的优先级高于连通路径B2和连通路径B3。
再基于约束条件①和约束条件②，判断同时选择的换流网络A中连通路径和换流网络B中连通路径是否满足两条约束条件，然后选择出换流网络A中连通路径A1和换流网络B中连通路径B1作为两个换流网络的最优换流路径。可选地，可以选择换流网络A中连通路径A1和换流网络B中连通路径B3作为两个换流网络的最优换流路径、可以选择换流网络A中连通路径A2和换流网络B中连通路径B3作为两个换流网络的最优换流路径、以及其它路径，本申请在此不作限定。
步骤S404，在每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在每个换流网络中的目标换流路径上，建立互联边。其中，线路节点为线路单元布置在连接图中的节点。
以图6(a)中的换流网络A中的连通路径A2为例，在确定连通路径A1为换流网络A的最优换流路径后，由于连通路径A2中的各个节点的连接关系为G(1,2)→G(0,2)→G(0,1)→G(0,0)→G(1,0)→G(1,1)→G(2,1)→G(2,0)，分别在节点G(1,2)、G(0,2)、G(0,1)、G(0,0)、G(1,0)、G(1,1)、G(2,1)和G(2,0)上建立线路单元。
在最优换流路径上的各个节点上建立线路单元后，再建立每个线路单元的互联边。示例性地，以节点G(1,2)为例，与该节点互联的节点为G(0,2)，所以节点G(1,2)的互联边为“G(1,2)→G(0,2)”；同理，节点G(0,2)的互联边为“G(1,2)→G(0,2)”和“G(0,2)→G(0,1)”；其它节点以此类推。
以图6(b)中的换流网络B中的连通路径B3为例，在确定连通路径B3为换流网络B的最优换流路径后，由于连通路径B3中的各个节点的连接关系为G(2,1)→G(2,0)→G(3,0)→G(3,1)→G(3,2)→G(2,2)→G(1,2)→G(0,2)，分别在节点G(2,1)、G(2,0)、G(3,0)、G(3,1)、G(3,2)、G(2,2)、G(1,2)和G(0,2)上建立线路单元。
在最优换流路径上的各个节点上建立线路单元后，再建立每个线路单元的互联边。示例性地，以节点G(2,1)为例，与该节点互联的节点为G(2,0)，所以节点G(2,1)的互联边为“G(2,1)→G(2,0)”；同理，节点G(2,0)的互联边为“G(2,1)→G(2,0)”和“G(2,0)→G(3,0)”；其它节点以此类推。
步骤S405，利用深度优选搜索模型，在每个换流网络中的目标换流路径上，建立端子路径，以及在端子路径上建立端子节点和互联边。其中，端子节点为端子单元布置在连接图中的节点。
步骤S406，输出电路拓扑的网表上的非空节点和互联边，得到功率模块的衬底的连接图。
深度优先搜索算法(depth first search，DFS)是搜索算法的一种，其原理是沿着树的深度遍历树的节点，尽可能深的搜索树的分支。当节点的所有边都己被探寻过，搜索将回溯到发现节点的那条边的起始节点。这一过程一直进行到已发现从源节点可达的所有节点为止。如果还存在未被发现的节点，则选择其中一个作为源节点并重复以上过程，整个进程反复进行直到所有节点都被访问为止。
仍以图6(a)中的换流网络A中的连通路径A2为例，在连通路径A2的各个节点上建立线路单元后，根据深度优先搜索算法构建的深度优先搜索模型，将每个线路节点的互联边与相邻的线路节点的互联边建立连接，建立实现将各个换流路径建立连接。示例性地，与节点G(1,2)相邻的节点有G(0,2)、G(1,1)和G(2,2)，与节点G(0,2)相邻的节点有G(0,1)和G(1,2)，所以节点G(1,2)与节点G(0,2)互为相邻节点，且节点G(1,2)的互联边为“G(1,2)→G(0,2)”，以及节点G(0,2)的互联边有“G(1,2)→G(0,2)”，因此可以在节点G(1,2)与节点G(0,2)中建立端子单元，并将节点G(1,2)与节点G(0,2)的互联边连接，得到端子单元的互联边；其它节点以此类推。
仍以图6(b)中的换流网络B中的连通路径B3为例，在连通路径B3的各个节点上建立线路单元后，根据深度优先搜索模型，将每个线路节点的互联边与相邻的线路节点的互联边建立连接，建立实现将各个换流路径建立连接。示例性地，与节点G(2,1)相邻的节点有G(2,0)、G(2,2)、G(1,1)和G(3,1)，与节点G(2,0)相邻的节点有G(2,1)、G(1,0)和G(3,0)，所以节点G(2,1)与节点G(2,0)互为相邻节点，且节点G(2,1)的互联边为“G(2,1)→G(2,0)”，以及节点G(2,0)的互联边为“G(2,1)→G(2,0)”，因此可以在节点G(2,1)与节点G(2,0)中建立端子单元，并将节点G(2,1)与节点G(2,0)的互联边连接，得到端子单元的互联边；其它节点以此类推。
将各个换流网络中的最优换流路径连接，得到总的换流路径后，再将各个端子单元的端口所处网表上的一个节点连接到总得换流路径上，得到端子路径，然后在端子路径上建立端子节点和互联边。
本申请中，如果以换流网络A中连通路径A2和换流网络B中连通路径B3作为两个换流网 络的最优换流路径，构建的功率模块的衬底的连接图为如图7(a)所示的连接结构。其中，连接图上包括有开关节点、吸收节点、端子节点和线路节点，开关节点为开关单元布置的连接图上的节点，吸收节点为吸收单元布置的连接图上的节点，端子节点为端子单元布置的连接图上的节点，线路节点为线路单元布置的连接图上的节点。
如图5所示，如果电路拓扑的网表中不包括有吸收单元时，连接图生成模块132构建功率模块的衬底的连接图，具体实现过程如下：
步骤S501，确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度。其中，换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径。具体为：
针对电路拓扑的网表中定义的每个换流网络，是指处在电路拓扑的网表中任意位置上的开关单元和端子单元，利用深度优先搜索算法构建的深度优先搜索模型，获得同一个开关单元的两个端口所处网表上的两个节点、不同两个开关单元的一个端口所处网表上的两个节点、不同两个端子单元的一个端口所处网表上的两个节点、以及开关单元与端子单元的一个端口所处网表上的两个节点之间的所有连通路径，并记录各个连通路径的长度。
步骤S502，构建整数规划模型。
在建立整数规划模型之前，确定优化目标为总的换流网络的路径最小，建立整数规划模型的约束条件定义为：①每个换流网络仅允许有一条路径；②每个网格节点仅容纳一条路径。然后，根据优化目标、约束条件①和约束条件②，对变量为整数的线性规划模型进行训练，得到整数规划模型。
步骤S503，将每个换流网络中的至少一条连通路径和每个连通路径的长度输入到整数规划模型中，得到每个换流网络中的目标换流路径。其中，目标换流路径为每个换流网络中的路径最短的换流路径。
步骤S504，在每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在每个换流网络中的目标换流路径上，建立互联边。其中，线路节点为线路单元布置在连接图中的节点。
步骤S505，输出电路拓扑的网表上的非空节点和互联边，得到功率模块的衬底的连接图。
在连通路径的各个节点上建立线路节点后，根据深度优先搜索算法构建的深度优先搜索模型，将每个线路节点的互联边与相邻的线路节点的互联边建立连接，建立实现将各个换流路径建立连接。
本申请实施例中，通过定义基本布图单元的图论模型，描述基本布图单元的相对位置和连接关系，再通过整数规划模型，在功率模块的衬底设计所需要的电路拓扑上确定出每个换流网络中的最优连通路径，以及建立每个最优连通路径相应的线路单元的节点和互联边，从而构建出连接图，此过程无需人工布图模板的输入，可以不依赖专家经验，实现功率模块的衬底布图自主设计。
本申请实施例中，通过定义基本布图单元的图论模型，描述基本布图单元的相对位置和连接关系，再通过整数规划模型，在功率模块的衬底设计所需要的电路拓扑上确定出每个换流网络中的最优连通路径，以及建立每个最优连通路径相应的线路单元的节点和互联边，从而构建出连接图，此过程无需人工布图模板的输入，可以不依赖专家经验，实现功率模块的衬底布图自主设计。
约束图生成模块133，用于根据设计尺寸约束条件，确定每种基本布图单元的原始尺寸，也即开关单元、吸收单元、端子单元和线路单元的最小尺寸，然后结合每种基本布图单元的 缩放变量，对连接图所在的电路拓扑的网表进行水平方向和垂直方向进行扫描，分别得到水平方向的尺寸约束图和垂直方向的尺寸约束图。其中，尺寸约束图中的节点代表扫描线，尺寸约束图中的边(节点与节点之间区域)代表扫描线间布局单元的尺寸和尺寸约束，且相邻节点之间至少有一条边，每个边的最小值约束w min,n是由其间最大尺寸的布局单元决定。可选地，如果输入参数中规定了衬底外框尺寸的约束条件，则在最外侧两个节点之间增加一条固定边，存储对应的外框尺寸约束w sum。
无论水平方向的尺寸约束图还是垂直方向的尺寸约束图，如果相邻节点间边的数量为n edges，则定义1至nedges-1号边为自由变量，n edges号边为依赖变量。其中，自由变量的取值w n,n∈{1,2,…,n edges-1}，需大于等于对应边的最小值约束，即w n≥w min,n；依赖变量的取值w n，n＝n edges，需要同时满足以下两个条件：①大于等于对应边的最小值约束，即w n≥w min,n；②与自由变量之和等于外框尺寸约束，即∑w n＝w sum,n∈{1,2,…,n edges}。
示例性地，根据图7(a)所示的连接图，生成如图7(b)所示的布图，该布图包括两个开关单元、一个吸收单元和6个线路单元。其中，两个开关单元和一个吸收单元按照如图7(a)中的连接线方式布置，并在其它位置上填充6个线路单元，构成完整的布图，并使得形状为呈长方形。
如图7(c)所示，在水平方向的尺寸约束图中，从左向右分别有节点X 0、节点X 1、节点X 2和节点X 3，在节点X 0与节点X 1之间存在边w 1，节点X 1与节点X 2之间存在边w 2，节点X 2与节点X 3之间存在边w 3。其中，边w 1的宽度与线路单元中的金属层的宽度、开关单元中的金属层的宽度相关联，边w 2与开关单元中的金属层的宽度、吸收单元中的金属层的宽度相关联，边w 3的宽度与吸收单元中的金属层的宽度、线路单元中的金属层的宽度相关联。
在垂直方向的尺寸约束图中，从下向上分别有节点Y 0、节点Y 1、节点Y 2、节点Y 3和节点Y 4，在节点Y 0与节点Y 1之间存在边h 1，在节点Y 1与节点Y 2之间存在边h 2，在节点Y 2与节点Y 3之间存在边h 3，在节点Y 3与节点Y 4之间存在边h 4。其中，边h 1的长度与吸收单元中的金属层的长度、线路单元中的金属层的长度相关联，边h 2的长度与线路单元中的金属层的长度、开关单元中的金属层的长度相关联，边h 3的长度与线路单元中金属层的长度相关联，边h 4的长度与线路单元中的金属层的长度、开关单元中的金属层的长度相关联。
本申请实施例中，通过从水平方向上和垂直方向上对连接图进行扫描，得到连接图的水平方向上的尺寸约束图和垂直方向上的尺寸约束图，可以使用尺寸约束图来描述不同的尺寸，内含有涉及尺寸约束，所以生成的功率模块的衬底模板质量高，无需在后续处理环节进行设计规则检测。
布图生成模块134，用于根据尺寸约束图的边长的取值，获取自身的边界尺寸和位置，并根据定义的缩放变量，调整内部线路尺寸和元件位置，再通过遍历连接图中的互联边，合并互联布图中的金属层线路，生成功率模块的衬底布图。示例性地，再结合图7(b)所示，根据水平方向和垂直方向的尺寸约束图，可以对图7(b)所示的布图的整体尺寸调整、内部线路尺寸调整、元件的位置调整等等，再利用互联边，将各个基本布图单元上的金属层进行电连接，得到功率模块的衬底设计电路图。
可选地，以边w 1的宽度为例，由于边w 1的宽度与线路单元中的金属层的宽度、开关单元中的金属层的宽度相关联，且线路单元中的第七金属层的宽度可以根据线路单元的缩放变量随意缩小和放大，而开关单元中第二金属层和第二金属层的宽度最小值要大于等于1.0mm，且金属层之间的距离要大于0.7mm，所以边w 1的宽度至少在2.2mm以上；其它宽度和长度以此类推，本申请在此不作限定。
本申请中，布图生成模块134还可以根据如图7(c)所示的尺寸约束图，通过镜像对称、平移等方式，获得具有对称结构的布图。示例性地，通过对图7(c)所示的水平方向的尺寸约束图进行镜像对称，而垂直方向的尺寸约束图不作镜像对称处理，得到如图8(a)所示的尺寸约束图。其中，水平方向的尺寸约束图进行镜像对称处理，得到水平方向上的长度w sum为图7(c)所示的水平方向的长度的两倍。
然后，布图生成模块134根据如图8(a)所示的尺寸约束图，对图7(b)所示的布图进行镜像对称处理，得到如图8(b)所示的布图，再对布图的整体尺寸调整、内部线路尺寸调整、元件的位置调整等等，再利用互联边，将各个基本布图单元上的金属层进行电连接，得到功率模块的衬底设计电路图。
本申请实施例中，在构建功率模块的衬底的几何布图过程中，可以通过连接图确定各个基本布图单元的数量和布置的位置，可以通过尺寸约束图限定各个基本布图单元的尺寸，实现构建功率模块的衬底的几何布图，以及构建的功率模块的衬底的几何布图的尺寸最佳。
电感评估模块135，用于利用布图评估工具，计算布图的换流回路的寄生电感、开关单元中的芯片支路的寄生电感、开关单元中芯片的热阻等指标，来判断设计出的几何布图的性能好坏。其中，电感评估具有以下两个特征：一是布图内的换流回路定义为由吸收电容正极电极出发，经过金属层线路和功率半导体芯片组，回到吸收电容负极电极的布图线路；二是开关单元中的芯片支路定义为从属于同一开关单元的功率半导体芯片出发，至吸收电容电极的布图线路。
示例性地，电感评估模块135检测布图生成模块134生成的功率模块的衬底的几何布图的换流回路的寄生电感、开关单元中的芯片支路的寄生电感和开关单元中芯片的热阻中三个指标中的至少一个。如果功率模块的衬底的几何布图的换流回路的寄生电感小于第一阈值、和/或开关单元中的芯片支路的寄生电感小于第二阈值、和/或开关单元中芯片的热阻小于第三阈值时，电感评估模块135输出功率模块的衬底的几何布图；当功率模块的衬底的几何布图的换流回路的寄生电感不小于第一阈值、和/或开关单元中的芯片支路的寄生电感不小于第二阈值、和/或开关单元中芯片的热阻不小于第三阈值时，重新构建功率模块的衬底的几何布图，可以发送指令给连接图生成模块132，重新生成连接图，或可以发送指令给约束图生成模块133，重新生成尺寸约束图，或发送指令给布图生成模块134，重新生成功率模块的衬底的连接图。
本申请实施例中，构建出功率模块的衬底的几何布图后，需要从换流回路的寄生电感、开关单元中的芯片支路的寄生电感、开关单元中芯片的热阻等指标来检测功率模块的衬底的几何布图的好坏，如果换流回路的寄生电感较小，或开关单元中的芯片支路的寄生电感差异较小，或开关单元中芯片的热阻比较小，表明设计出的检测功率模块的衬底的几何布图的性能比较好。如果构建出功率模块的衬底的几何布图中，出现换流回路的寄生电感较大，或开关单元中的芯片支路的寄生电感差异较大，或开关单元中芯片的热阻比较小，表明设计出的检测功率模块的衬底的几何布图的性能比较差，需要重新设计。
本申请中，根据如图6(a)所示的换流网络A与如图6(b)所示的换流网络B，可以组合出不同的布图，设计出的功率模块的衬底的布图，并不仅限于图7(b)和图8(b)两种布图，还可以为其它布图，如图9所示的16种连接图模板，及其相应的布图；以及其它布图，本申请在此不一一列举了。
优化处理模块136用于将尺寸约束图的边的权重作为设计变量、基本布图单元的最小尺寸和衬底外框的尺寸作为设计约束，输入到遗传计算模型中进行优化处理，输出最优的功率模块的衬底的布图。其中，遗传计算模型是指存储有遗传算法的存储单元、电子设备、云服务 器等等。
遗传算法是一种基于自然选择和群体遗传机理的搜索算法，它模拟了自然选择和自然遗传过程中的繁殖、杂交和突变现象。再利用遗传算法求解问题时，问题的每一个可能解都被编码成一个“染色体”，即个体，若干个个体构成了群体(所有可能解)。在遗传算法开始时，总是随机的产生一些个体(即初始解)，根据预定的目标函数对每一个个体进行评估，给出一个适应度值，基于此适应度值，选择一些个体用来产生下一代，选择操作体现了“适者生存”的原理，“好”的个体被用来产生下一代，“坏”的个体则被淘汰，然后选择出来的个体，经过交叉和变异算子进行再组合生成新的一代，这一代的个体由于继承了上一代的一些优良性状,因而在性能上要优于上一代，这样逐步朝着最优解的方向进化。因此，遗传算法可以看成是一个由可行解组成的群体初步进化的过程。
如图10所示，遗传计算单元1343进行迭代寻优，具体实现过程如下：
步骤S1001，系统输入：输入连接图、尺寸约束图、设计尺寸的约束条件(或基本布图单元的信息)，以及遗传算法参数，如种群数量、迭代的代数、交叉/变异率等参数。其中，以连接图的边权重作为设计变量，基本布图单元的最小尺寸和功率模块的衬底外框的尺寸作为设计约束。
步骤S1002，初始种群：根据尺寸约束图，计算随机产生的初代种群的DNA。也即，随机选取多组w 1-w n和h 1-h m的尺寸约束图中的边的长度参数，n表示水平方向的尺寸约束图中边的数量，m表示垂直方向的尺寸约束图中边的数量。
步骤S1003，生成布图：调用布图生成模块134，让布图生成模块134根据步骤S1002中选取的多组w 1-w n和h 1-h m的尺寸约束图中的边的长度参数，生成对应组的生成功率模块的衬底布图。其中，选取的组数与输入的种群数量有关。
步骤S1004，适应度评估：评估换流回路中的寄生电感和评估开关单元中的芯片支路的寄生电感。具体为，调用电感评估模块135，让电感评估模块135对步骤S1003中生成的多组的生成功率模块的衬底布图，进行寄生电感评估，得到换流回路中的寄生电感和评估开关单元中的芯片支路的寄生电感。
步骤S1005，适应度排序：计算帕累托(pareto)等级和拥挤度。具体为，将每组布图对应的换流回路按照寄生电感最小和评估开关单元中的芯片支路的寄生电感差异最小进行排序，将换流回路按照寄生电感最小和评估开关单元中的芯片支路的寄生电感差异最小的前M组布图保留。
步骤S1006，是否达到最大代数：判断是否达到最大代数，如果没有达到最大代数，执行步骤S1007，如果达到最大代数，执行步骤S1009。
步骤S1007，生成子代：根据排序筛选出父代，通过交叉和变异产生子代DNA，生成新种群。具体为，对前M组布图对应的尺寸约束图中的边的长度参数进行修改，生成M组不同数值的尺寸约束图中的边的长度参数。可选地，对尺寸约束图中的边的长度参数的修改，一般是朝着一个方向进行修改，如对M组中的尺寸约束图中的边的长度参数增大，或者对M组中的尺寸约束图中的边的长度参数减小。而且，每次修改，并不一定对每一组中的w 1-w n和h 1-h m都进行修改，也可以修改一部分。
步骤S1008，代数叠加一代，再执行步骤S1003。
步骤S1009，设计输出：输出全局pareto前沿设计集和历代设计集，也即最优的功率模块的衬底布图。
本申请中，输入到遗传算法中的连接图为图9中所示的16种连接图，选取初代种群数量为 30，最大迭代次数为50，然后按照如图10所示的步骤进行迭代寻优，历次迭代结果和最后得到的pareto前沿如图11所示，五种不同的布图对应的换流回路的寄生电感与开关单元中的芯片支路的寄生电感之间的关系。
本申请实施例中，构建出功率模块的衬底的几何布图后，以换流回路的寄生电感最小和开关单元中的芯片支路的寄生电感的差异最小为优化目标，可以将功率模块的衬底的几何布图输入到遗传算法构建的遗传计算模型中进行寻优查找，得到换流回路的寄生电感最小和开关单元中的芯片支路的寄生电感的差异最小两个临界状态下的功率模块的衬底的几何布图，作为最优的几何布图，然后输出该几何布图，得到最佳的功率模块的衬底的几何布图。
结合图12所示的前沿轨迹上不同解的布图和设计参数。其中，前沿解A是根据图9(d)中的布图拓展得到的，其设计参数：芯片间距＝3.4mm，未拓展；设计结果：换流回路中的寄生电感Ls＝4.32nH，开关单元中的芯片支路的寄生电感△Lb＝2.84nH；前沿解B是根据图9(a)中的布图拓展得到的，其设计参数：芯片间距＝2.7mm；设计结果：Ls＝5.03nH，△Lb＝2.75nH，未拓展；前沿解C是根据图9(m)中的布图拓展得到的，其设计参数：芯片间距＝5.7mm；设计结果：Ls＝5.57nH，△Lb＝1.09nH，对称拓展。
为了验证本申请设计的功率模块的衬底设计方案是否具有优化效果，本申请选用了前沿解C进行了仿真验证，开关波形如图13所示。其中，功率模块的设计指标，包括关断过程的电压尖峰，以及开通关断过程的电流均衡性。这里展示了前沿解C的评估结果，其电压尖峰小，电流部分均匀，验证了本申请设计的功率模块的衬底设计方案的有效性。
本申请实施例中，以换流回路的寄生电感最小和开关单元中的芯片支路的寄生电感的差异最小为优化目标，使用遗传算法对功率模块的衬底布图进行优化计算，可实现自动化的衬底布图的设计，且性能比较优异。
图14为本申请实施例中提供的一种功率模块的衬底设计装置的框架示意图。如图14所示的功率模块的衬底设计装置，该装置1400包括收发单元1401和处理单元1402。其中，各个单元执行的功能如下：
在一种实施方式中，收发单元1401用于获取设计功率模块的衬底的输入参数，所述输入参数包括所述功率模块的衬底设计所需要的电路拓扑的信息；处理单元1402用于根据所述电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定所述电路拓扑上的基本布图单元的种类和每种基本布图单元的数量，所述基本布图单元是构成所述功率单元的衬底的几何布图的最小单元；和利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，所述图元素为预先存储的基本布图单元在电路拓扑上构成连接图的节点和互联边，所述连通路径是一个基本布图单元的图元素中的两个节点、或两个基本布图单元的图元素中的一个节点之间的路径。
在一种实施方式中，所述处理单元1402具体用于根据所述电路拓扑的信息，生成所述电路拓扑的网表；根据所述预先存储的每种基本布图单元的结构图，计算出所述电路拓扑的网表上的基本布图单元的种类和每一种基本布图单元的数量，所述基本布图单元的种类包括开关单元、吸收单元、端子单元和线路单元。
在一种实施方式中，所述寻路模型为整数规划模型和深度优选搜索模型中的至少一种。
在一种实施方式中，所述处理单元1402具体用于确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口 所处的两个节点、和/或吸收单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的吸收单元的一个端口所处的两个节点、和/或一个开关单元和一个吸收单元的一个端口所处的两个节点；根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；利用深度优选搜索模型，在所述每个换流网络中的目标换流路径上，建立端子路径，以及在所述端子路径上建立端子节点和互联边，所述端子路径为所述端子单元连接到换流网络的路径，所述端子节点为端子单元布置的节点；和输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
在一种实施方式中，所述处理单元1402具体用于确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的端子单元的一个端口所处的两个节点、和/或一个开关单元和一个端子单元的一个端口所处的两个节点；根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；和输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
在一种实施方式中，所述输入参数还包括基本布图单元的设计尺寸约束条件；所述处理单元1402还用于根据所述设计尺寸约束条件，确定所述每种基本布图单元的原始尺寸；根据每种基本布图单元的原始尺寸和预先存储的每种基本布图单元的缩放变量，对所述功率模块的衬底的连接图进行扫描，得到连接图的尺寸约束图，所述尺寸约束图用于在根据连接图构建几何布图时，限定所述各个基本布图单元的尺寸。
在一种实施方式中，所述处理单元1402具体用于对所述功率模块的衬底的连接图沿第一方向进行扫描，得到连接图的在第一方向上的尺寸约束图；和对所述功率模块的衬底的连接图沿第二方向进行扫描，得到连接图的在第二方向上的尺寸约束图；所述第一方向与所述第二方向为相互垂直的方向。
在一种实施方式中，所述尺寸约束图包括约束节点和约束边，所述约束节点为对所述功率模块的衬底的连接图进行扫描的扫描线，所述约束边为扫描线之间的距离，用于约束所述各个基本布图单元的尺寸。
在一种实施方式中，所述处理单元1402还用于根据所述功率模块的衬底的连接图和所述连接图的尺寸约束图，构建所述功率模块的衬底的几何布图。
在一种实施方式中，所述处理单元1402还用于检测所述功率模块的衬底的几何布图的换流回路的寄生电感、和/或开关单元中的芯片支路的寄生电感、和/或开关单元中芯片的热阻；当所述功率模块的衬底的几何布图的换流回路的寄生电感大小第一阈值、和/或开关单元中的 芯片支路的寄生电感小于第二阈值、和/或开关单元中芯片的热阻小于第三阈值时时，输出所述功率模块的衬底的几何布图。
在一种实施方式中，所述处理单元1402还用于当所述功率模块的衬底的几何布图的换流回路的寄生电感不小于第一阈值、和/或开关单元中的芯片支路的寄生电感不小于第二阈值、和/或开关单元中芯片的热阻不小于第三阈值时，重新构建所述功率模块的衬底的几何布图。
在一种实施方式中，所述处理单元1402还用于将所述功率模块的衬底的几何布图输入到遗传计算模型中，输出目标几何布图，所述目标几何布图为满足设定条件的所述功率模块的衬底的几何布图，所述设定条件为降低所述换流回路的寄生电感数值、和/或减小所述开关单元中的芯片支路的寄生电感差异值、和/或降低开关单元中芯片的热阻达到帕累托优化前沿。
第三方面，本申请实施例提供一种终端设备，包括：至少一个收发器；至少一个存储器；至少一个处理器，所述处理器用于执行存储器中存储的指令，以使得所述终端设备执行如图1-图13和上述对应保护的技术方案，使得该终端设备具有上述保护的技术方案的技术效果。
本申请实施例中还提供了一种计算机可读存储介质，其上存储有计算机程序，当所述计算机程序在计算机中执行时，令计算机执行上述图1-图13和相应描述内容中记载的任一项方法。
本申请实施例中还提供了一种计算机程序产品，所述计算机程序产品存储有指令，所述指令在由计算机执行时，使得所述计算机实施上述图1-图13和相应描述内容中记载的任一项方法。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
此外，本申请实施例的各个方面或特征可以实现成方法、装置或使用标准编程和/或工程技术的制品。本申请中使用的术语“制品”涵盖可从任何计算机可读器件、载体或介质访问的计算机程序。例如，计算机可读介质可以包括，但不限于:磁存储器件(例如，硬盘、软盘或磁带等)，光盘(例如，压缩盘(compact disc，CD)、数字通用盘(digital versatile disc，DVD)等)，智能卡和闪存器件(例如，可擦写可编程只读存储器(erasable programmable read-only memory，EPROM)、卡、棒或钥匙驱动器等)。另外，本文描述的各种存储介质可代表用于存储信息的一个或多个设备和/或其它机器可读介质。术语“机器可读介质”可包括但不限于，无线信道和能够存储、包含和/或承载指令和/或数据的各种其它介质。
在上述实施例中，图14中的功率模块的衬底设计装置1400可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。 所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，高密度数字视频光盘(digital video disc，DVD))、或者半导体介质(例如，固态硬盘(solid state disk，SSD))等。
应当理解的是，在本申请实施例的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者接入网设备等)执行本申请实施例各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请实施例的具体实施方式，但本申请实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请实施例的保护范围之内。

Claims (28)

  1. 一种功率模块的衬底设计方法，其特征在于，包括：
    获取设计功率模块的衬底的输入参数，所述输入参数包括所述功率模块的衬底设计所需要的电路拓扑的信息；
    根据所述电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定所述电路拓扑上的基本布图单元的种类和每种基本布图单元的数量，所述基本布图单元是构成所述功率单元的衬底的几何布图的最小单元；
    利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，所述图元素为预先存储的基本布图单元在电路拓扑上构成连接图的节点和互联边，所述连通路径是一个基本布图单元的图元素中的两个节点、或两个基本布图单元的图元素中的一个节点之间的路径。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定所述电路拓扑上的基本布图单元的种类和每种基本布图单元的数量，具体包括：
    根据所述电路拓扑的信息，生成所述电路拓扑的网表；
    根据所述预先存储的每种基本布图单元的结构图，计算出所述电路拓扑的网表上的基本布图单元的种类和每一种基本布图单元的数量，所述基本布图单元的种类包括开关单元、吸收单元、端子单元和线路单元。
  3. 根据权利要求1或2所述的方法，其特征在于，所述寻路模型为整数规划模型和深度优选搜索模型中的至少一种。
  4. 根据权利要求1-3任意一项所述的方法，其特征在于，所述利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，具体包括：
    确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或吸收单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的吸收单元的一个端口所处的两个节点、和/或一个开关单元和一个吸收单元的一个端口所处的两个节点；
    根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；
    将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；
    在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；
    利用深度优选搜索模型，在所述每个换流网络中的目标换流路径上，建立端子路径，以及在所述端子路径上建立端子节点和互联边，所述端子路径为所述端子单元连接到换流网络的路径，所述端子节点为端子单元布置的节点；
    输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
  5. 根据权利要求1-3任意一项所述的方法，其特征在于，所述利用寻路模型，连接所述电 路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，具体包括：
    确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的端子单元的一个端口所处的两个节点、和/或一个开关单元和一个端子单元的一个端口所处的两个节点；
    根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；
    将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；
    在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；
    输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
  6. 根据权利要求1-5任意一项所述的方法，其特征在于，所述输入参数还包括基本布图单元的设计尺寸约束条件；
    所述方法还包括：
    根据所述设计尺寸约束条件，确定所述每种基本布图单元的原始尺寸；
    根据每种基本布图单元的原始尺寸和预先存储的每种基本布图单元的缩放变量，对所述功率模块的衬底的连接图进行扫描，得到连接图的尺寸约束图，所述尺寸约束图用于在根据连接图构建几何布图时，限定所述各个基本布图单元的尺寸。
  7. 根据权利要求6所述的方法，其特征在于，所述对所述功率模块的衬底的连接图进行扫描，得到连接图的尺寸约束图，具体包括：
    对所述功率模块的衬底的连接图沿第一方向进行扫描，得到连接图的在第一方向上的尺寸约束图；和
    对所述功率模块的衬底的连接图沿第二方向进行扫描，得到连接图的在第二方向上的尺寸约束图；所述第一方向与所述第二方向为相互垂直的方向。
  8. 根据权利要求6或7所述的方法，其特征在于，所述尺寸约束图包括约束节点和约束边，所述约束节点为对所述功率模块的衬底的连接图进行扫描的扫描线，所述约束边为扫描线之间的距离，用于约束所述各个基本布图单元的尺寸。
  9. 根据权利要求1-8任意一项所述的方法，其特征在于，所述方法还包括：
    根据所述功率模块的衬底的连接图和所述连接图的尺寸约束图，构建所述功率模块的衬底的几何布图。
  10. 根据权利要求9所述的方法，其特征在于，所述方法还包括：
    检测所述功率模块的衬底的几何布图的换流回路的寄生电感、和/或开关单元中的芯片支路的寄生电感、和/或开关单元中芯片的热阻；
    当所述功率模块的衬底的几何布图的换流回路的寄生电感小于第一阈值、和/或开关单元中的芯片支路的寄生电感小于第二阈值、和/或开关单元中芯片的热阻小于第三阈值时，输出所述功率模块的衬底的几何布图。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：
    当所述功率模块的衬底的几何布图的换流回路的寄生电感不小于第一阈值、和/或开关单元中的芯片支路的寄生电感不小于第二阈值、和/或开关单元中芯片的热阻不小于第三阈值时，重新构建所述功率模块的衬底的几何布图。
  12. 根据权利要求9-11任意一项所述的方法，其特征在于，还包括：
    将所述功率模块的衬底的几何布图输入到遗传计算模型中，输出目标几何布图，所述目标几何布图为满足设定条件的所述功率模块的衬底的几何布图，所述设定条件为降低所述换流回路的寄生电感数值、和/或减小所述开关单元中的芯片支路的寄生电感差异值、和/或降低开关单元中芯片的热阻达到帕累托优化前沿。
  13. 一种功率模块的衬底设计装置，其特征在于，包括：
    收发单元，用于获取设计功率模块的衬底的输入参数，所述输入参数包括所述功率模块的衬底设计所需要的电路拓扑的信息；
    处理单元，用于根据所述电路拓扑的信息和预先存储的每种基本布图单元的结构图，确定所述电路拓扑上的基本布图单元的种类和每种基本布图单元的数量，所述基本布图单元是构成所述功率单元的衬底的几何布图的最小单元；和
    利用寻路模型，连接所述电路拓扑上各个基本布图单元的图元素的连通路径，得到所述功率模块的衬底的连接图，所述图元素为预先存储的基本布图单元在电路拓扑上构成连接图的节点和互联边，所述连通路径是一个基本布图单元的图元素中的两个节点、或两个基本布图单元的图元素中的一个节点之间的路径。
  14. 根据权利要求13所述的装置，其特征在于，所述处理单元，具体用于
    根据所述电路拓扑的信息，生成所述电路拓扑的网表；
    根据所述预先存储的每种基本布图单元的结构图，计算出所述电路拓扑的网表上的基本布图单元的种类和每一种基本布图单元的数量，所述基本布图单元的种类包括开关单元、吸收单元、端子单元和线路单元。
  15. 根据权利要求13或14所述的装置，其特征在于，所述寻路模型为整数规划模型和深度优选搜索模型中的至少一种。
  16. 根据权利要求13-15任意一项所述的装置，其特征在于，所述处理单元，具体用于
    确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或吸收单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的吸收单元的一个端口所处的两个节点、和/或一个开关单元和一个吸收单元的一个端口所处的两个节点；
    根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；
    将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；
    在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边，所述线路节点为线路单元布置的节点；
    利用深度优选搜索模型，在所述每个换流网络中的目标换流路径上，建立端子路径，以 及在所述端子路径上建立端子节点和互联边，所述端子路径为所述端子单元连接到换流网络的路径，所述端子节点为端子单元布置的节点；和
    输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
  17. 根据权利要求13-15任意一项所述的装置，其特征在于，所述处理单元，具体用于
    确定所述电路拓扑的网表上至少一个换流网络，以及每个换流网络中的至少一条连通路径和每个连通路径的长度，所述换流网络是指所述电路拓扑的网表上的两个节点之间的网络路径，所述两个节点为开关单元的两个端口所处的两个节点、和/或两个不同的开关单元的一个端口所处的两个节点、和/或两个不同的端子单元的一个端口所处的两个节点、和/或一个开关单元和一个端子单元的一个端口所处的两个节点；
    根据优化目标、换流网络的约束条件和换流网络上的节点的约束条件，对线性规划模型进行训练，构建整数规划模型；
    将所述每个换流网络中的至少一条连通路径和所述每个连通路径的长度输入到所述整数规划模型中，得到每个换流网络中的目标换流路径，所述目标换流路径为每个换流网络中的满足设定长度阈值的换流路径；
    在所述每个换流网络中的目标换流路径的每个网络节点上，建立线路节点，以及在所述每个换流网络中的目标换流路径上，建立互联边；和
    输出所述电路拓扑的网表上的非空节点和互联边，得到所述功率模块的衬底的连接图。
  18. 根据权利要求13-17任意一项所述的装置，其特征在于，所述输入参数还包括基本布图单元的设计尺寸约束条件；
    所述处理单元，还用于根据所述设计尺寸约束条件，确定所述每种基本布图单元的原始尺寸；
    根据每种基本布图单元的原始尺寸和预先存储的每种基本布图单元的缩放变量，对所述功率模块的衬底的连接图进行扫描，得到连接图的尺寸约束图，所述尺寸约束图用于在根据连接图构建几何布图时，限定所述各个基本布图单元的尺寸。
  19. 根据权利要求18所述的装置，其特征在于，所述处理单元，具体用于
    对所述功率模块的衬底的连接图沿第一方向进行扫描，得到连接图的在第一方向上的尺寸约束图；和
    对所述功率模块的衬底的连接图沿第二方向进行扫描，得到连接图的在第二方向上的尺寸约束图；所述第一方向与所述第二方向为相互垂直的方向。
  20. 根据权利要求18或19所述的装置，其特征在于，所述尺寸约束图包括约束节点和约束边，所述约束节点为对所述功率模块的衬底的连接图进行扫描的扫描线，所述约束边为扫描线之间的距离，用于约束所述各个基本布图单元的尺寸。
  21. 根据权利要求13-20任意一项所述的装置，其特征在于，所述处理单元，还用于
    根据所述功率模块的衬底的连接图和所述连接图的尺寸约束图，构建所述功率模块的衬底的几何布图。
  22. 根据权利要求21所述的装置，其特征在于，所述处理单元，还用于
    检测所述功率模块的衬底的几何布图的换流回路的寄生电感、和/或开关单元中的芯片支路的寄生电感、和/或开关单元中芯片的热阻；
    当所述功率模块的衬底的几何布图的换流回路的寄生电感大小第一阈值、和/或开关单元中的芯片支路的寄生电感小于第二阈值、和/或开关单元中芯片的热阻小于第三阈值时时，输出所述功率模块的衬底的几何布图。
  23. 根据权利要求22所述的装置，其特征在于，所述处理单元，还用于
    当所述功率模块的衬底的几何布图的换流回路的寄生电感不小于第一阈值、和/或开关单元中的芯片支路的寄生电感不小于第二阈值、和/或开关单元中芯片的热阻不小于第三阈值时，重新构建所述功率模块的衬底的几何布图。
  24. 根据权利要求21-23任意一项所述的装置，其特征在于，所述处理单元，还用于
    将所述功率模块的衬底的几何布图输入到遗传计算模型中，输出目标几何布图，所述目标几何布图为满足设定条件的所述功率模块的衬底的几何布图，所述设定条件为降低所述换流回路的寄生电感数值、和/或减小所述开关单元中的芯片支路的寄生电感差异值、和/或降低开关单元中芯片的热阻达到帕累托优化前沿。
  25. 一种终端设备，其特征在于，包括：
    至少一个收发器；
    至少一个存储器；
    至少一个处理器，所述处理器用于执行存储器中存储的指令，以使得所述终端设备执行如权利要求1-12所述的功率模块的衬底设计方法。
  26. 一种计算设备，其特征在于，包括存储器和处理器，所述存储器用于存储指令，所述处理器用于调用所述存储器中存储的指令，实现如权利要求1-12任一项所述的功率模块的衬底设计方法。
  27. 一种计算机可读存储介质，其上存储有计算机程序，当所述计算机程序在计算机中执行时，令计算机执行权利要求1-12中任一项的所述的方法。
  28. 一种计算机程序产品，其特征在于，所述计算机程序产品存储有指令，所述指令在由计算机执行时，使得所述计算机实施权利要求1-12任意一项所述的方法。
PCT/CN2022/114437 2021-12-27 2022-08-24 一种功率模块的衬底设计方法、装置和终端设备 WO2023124147A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111619868.6 2021-12-27
CN202111619868.6A CN114491881A (zh) 2021-12-27 2021-12-27 一种功率模块的衬底设计方法、装置和终端设备

Publications (1)

Publication Number Publication Date
WO2023124147A1 true WO2023124147A1 (zh) 2023-07-06

Family

ID=81495190

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/114437 WO2023124147A1 (zh) 2021-12-27 2022-08-24 一种功率模块的衬底设计方法、装置和终端设备

Country Status (2)

Country Link
CN (1) CN114491881A (zh)
WO (1) WO2023124147A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116821044A (zh) * 2023-08-17 2023-09-29 飞腾信息技术有限公司 处理系统、访存方法及计算机可读存储介质
CN117574851A (zh) * 2024-01-11 2024-02-20 上海合见工业软件集团有限公司 一种在eda工具中重构电路原理图的方法、设备及存储介质
CN118097087A (zh) * 2024-04-29 2024-05-28 中国石油大学(华东) 工程图纸的构件尺寸标注布局方法、装置、设备及介质

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114491881A (zh) * 2021-12-27 2022-05-13 华为数字能源技术有限公司 一种功率模块的衬底设计方法、装置和终端设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764532A (en) * 1995-07-05 1998-06-09 International Business Machines Corporation Automated method and system for designing an optimized integrated circuit
CN112257376A (zh) * 2020-10-28 2021-01-22 海光信息技术股份有限公司 馈通路径的规划方法及装置、电子设备、存储介质
CN112270148A (zh) * 2020-10-16 2021-01-26 山东云海国创云计算装备产业创新中心有限公司 一种门级网表生成方法及相关装置
CN113065307A (zh) * 2021-03-22 2021-07-02 浙江大学 一种功率半导体模块衬底优化设计方法
CN114491881A (zh) * 2021-12-27 2022-05-13 华为数字能源技术有限公司 一种功率模块的衬底设计方法、装置和终端设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764532A (en) * 1995-07-05 1998-06-09 International Business Machines Corporation Automated method and system for designing an optimized integrated circuit
CN112270148A (zh) * 2020-10-16 2021-01-26 山东云海国创云计算装备产业创新中心有限公司 一种门级网表生成方法及相关装置
CN112257376A (zh) * 2020-10-28 2021-01-22 海光信息技术股份有限公司 馈通路径的规划方法及装置、电子设备、存储介质
CN113065307A (zh) * 2021-03-22 2021-07-02 浙江大学 一种功率半导体模块衬底优化设计方法
CN114491881A (zh) * 2021-12-27 2022-05-13 华为数字能源技术有限公司 一种功率模块的衬底设计方法、装置和终端设备

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116821044A (zh) * 2023-08-17 2023-09-29 飞腾信息技术有限公司 处理系统、访存方法及计算机可读存储介质
CN116821044B (zh) * 2023-08-17 2024-01-09 飞腾信息技术有限公司 处理系统、访存方法及计算机可读存储介质
CN117574851A (zh) * 2024-01-11 2024-02-20 上海合见工业软件集团有限公司 一种在eda工具中重构电路原理图的方法、设备及存储介质
CN117574851B (zh) * 2024-01-11 2024-04-19 上海合见工业软件集团有限公司 一种在eda工具中重构电路原理图的方法、设备及存储介质
CN118097087A (zh) * 2024-04-29 2024-05-28 中国石油大学(华东) 工程图纸的构件尺寸标注布局方法、装置、设备及介质

Also Published As

Publication number Publication date
CN114491881A (zh) 2022-05-13

Similar Documents

Publication Publication Date Title
WO2023124147A1 (zh) 一种功率模块的衬底设计方法、装置和终端设备
Qiu et al. Robustness optimization scheme with multi-population co-evolution for scale-free wireless sensor networks
US9064077B2 (en) 3D floorplanning using 2D and 3D blocks
US6851101B1 (en) Method for computing and using future costing data in signal routing
Eppstein et al. Succinct greedy geometric routing using hyperbolic geometry
WO2000065489A1 (en) Subgrid detailed routing
JP4644586B2 (ja) セラミック集積回路パッケージにおいて電力分配システムを機能強化するための方法及びプログラム
CN115859899B (zh) 一种多驱动能力的集成电路标准单元版图迁移的方法
Ning et al. Review of power module automatic layout optimization methods in electric vehicle applications
US9483598B2 (en) Intellectual property block design with folded blocks and duplicated pins for 3D integrated circuits
CN117422041A (zh) 模拟芯片自动化布线模型训练方法及自动化布线方法
Das et al. Small-world network enabled energy efficient and robust 3D NoC architectures
Alexander et al. An architecture-independent approach to FPGA routing based on multi-weighted graphs.
Radhakrishnan Nair et al. An efficient partitioning and placement based fault TSV detection in 3D-IC using deep learning approach
Ran et al. Via-configurable routing architectures and fast design mappability estimation for regular fabrics
KR20170061911A (ko) 통합 회귀 분석 네트워크 구축 방법 및 이에 의한 통합 분석 시스템
Alpert et al. Minimum buffered routing with bounded capacitive load for slew rate and reliability control
Liu et al. Multilayer pin assignment for macro cell circuits
TWI665932B (zh) 裝置對裝置網路之群組主機選擇方法與選擇群組主機的控制平台
Dai Performance driven layout for thin-film multichip modules
CN117556760B (zh) 一种宏单元和可编程逻辑块分阶段优化的fpga全局布局方法
Rahim et al. The performance study of two genetic algorithm approaches for VLSI macro-cell layout area optimization
CN116227413A (zh) 芯粒布局优化方法、电子设备及存储介质
Hung et al. Dangling-wire avoidance routing for crossbar switch structured ASIC design style
Ravikumar et al. A genetic algorithm approach for global routing of VLSI circuits

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22913430

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022913430

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022913430

Country of ref document: EP

Effective date: 20240618