WO2023123905A1 - Data transmission processing method in chip system and related apparatus - Google Patents

Abstract

Embodiments of the present application provide a data transmission processing method in a chip system and a related apparatus. The method comprises: a first sub-chip receives a first data packet, wherein the first data packet comprises an identifier of a target sub-chip, the first sub-chip and the target sub-chip are sub-chips comprised in the chip system, a plurality of sub-chips in the chip system are arranged in the form of a matrix, and each sub-chip among the plurality of sub-chips is connected to surrounding adjacent sub-chips; and the first sub-chip sends data in the first data packet to the target sub-chip according to a small bandwidth consumption principle on the basis of a direction coordinate system, wherein the small bandwidth consumption principle is a principle that data is sent to the target sub-chip by using a small transmission bandwidth; and the direction coordinate system is constructed by using the first sub-chip as the center. According to the present application, efficient data transmission between sub-chips in a chip system can be achieved, and the processing performance of the chip system is improved.

Description

Data transmission processing method and related device in chip system technical field

The present application relates to the field of communication technologies, and in particular to a data transmission processing method and related devices in a chip system.

This application claims the priority of the Chinese patent application with the application number 202111633357.X and the application name "Data transmission processing method and related device in the chip system" submitted to the China Patent Office on December 28, 2021, the entire content of which is passed References are incorporated in this application.

Background technique

A chip system may include multiple sub-chips, each of which has the function of independently processing data, and the multiple sub-chips are connected in a certain topology to realize mutual communication. Moreover, the multiple sub-chips can cooperatively process a single large-scale computing task in a model-parallel manner, so as to improve the processing efficiency of the task. In the process of cooperatively processing tasks, frequent interactive transmission of data is required among the multiple sub-chips, and the efficiency of the data transmission affects the processing performance of the entire chip system.

technical problem

The embodiment of the present application discloses a data transmission processing method in a chip system and related devices, which can realize efficient data transmission between sub-chips in the chip system and improve the processing performance of the chip system.

In a first aspect, the present application provides a data transmission processing method in a chip system, the method comprising:

The first sub-chip receives the first data packet; wherein, the aforementioned first data packet includes the identification of the target sub-chip; the aforementioned first sub-chip and the aforementioned target sub-chip are sub-chips included in the chip system, and the plurality of sub-chips in the aforementioned chip system Arranged in the form of a matrix, each of the aforementioned multiple sub-chips is connected to surrounding adjacent sub-chips;

The aforementioned first sub-chip sends the data in the aforementioned first data packet to the aforementioned destination sub-chip based on the direction coordinate system with a smaller bandwidth consumption principle, and the aforementioned smaller bandwidth consumption principle is to deliver the aforementioned data to the aforementioned destination with a smaller transmission bandwidth Principles of chiplets;

The aforementioned directional coordinate system is constructed around the aforementioned first sub-chip, and the aforementioned directional coordinate system includes a first directional axis, a second directional axis, a third directional axis, and a fourth directional axis; the row where the aforementioned first sub-chip is located is located in the opposite direction on at least one of the aforementioned first direction axis and the aforementioned second direction axis; the column where the aforementioned first chiplet is located is located on at least one of the aforementioned third direction axis and the aforementioned fourth direction axis in opposite directions .

In this application, the above-mentioned direction coordinate system is constructed centering on the sub-chip that currently needs to send data in the chip system, and then the sub-chip transmits the received data based on the direction coordinate system with the principle of less bandwidth consumption, thereby improving Data transmission efficiency, and then improve the processing performance of the chip system.

In a possible implementation manner, sending the data in the first data packet to the target chiplet by the first chiplet based on the direction coordinate system and the principle of less bandwidth consumption includes: when the target chiplet is on the target direction axis In some cases, the first chiplet sends the data along the direction of the target direction axis; the target direction axis is the first direction axis, the second direction axis, the third direction axis or the fourth direction axis.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned first sub-chip sends the data in the aforementioned first data packet to the aforementioned purpose sub-chip based on the direction coordinate system with the principle of less bandwidth consumption include:

In the case where the aforementioned first target chiplet and the second target chiplet are located in two adjacent areas of the aforementioned first area, second area, third area, and fourth area respectively, the aforementioned first chiplet is The second data packet is sent in the direction of the direction axis; the aforementioned second data packet includes the aforementioned data, the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned common direction axis is the direction axis of the common boundary of the aforementioned two adjacent areas .

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned first sub-chip sends the data in the aforementioned first data packet to the aforementioned purpose sub-chip based on the direction coordinate system with the principle of less bandwidth consumption include:

In the case where the first target chiplet is in the first region and the second target chiplet is in the third region, the first chiplet is along one of the direction axes of the two boundaries of the first region The third data packet is sent in the direction of the third area, and the fourth data packet is sent along the direction of one of the two boundary direction axes of the aforementioned third area; the aforementioned third data packet includes the aforementioned data and the identification of the aforementioned first destination chiplet , the aforementioned fourth data packet includes the aforementioned data and the ID of the aforementioned second destination chiplet.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned first sub-chip sends the data in the aforementioned first data packet to the aforementioned purpose sub-chip based on the direction coordinate system with the principle of less bandwidth consumption include:

In the case where the first target chiplet is in the target area and the second target chiplet is on the direction axis of the boundary of the target area, the first chiplet sends the fifth data along the direction axis of the boundary of the target area package, the aforementioned fifth data packet includes the aforementioned data and the identification of the aforementioned first and second target chiplets; the aforementioned target area is the first area, the second area, the third area or the fourth area.

In the above several possible implementations, the orientation of the target sub-chip relative to the above-mentioned first sub-chip is determined based on the directional coordinate system constructed above, and the direction from the first sub-chip to the target sub-chip is quickly determined based on the determined orientation. The shortest transmission path realizes fast forwarding of data, saves transmission bandwidth resources, and improves transmission efficiency.

In a possible implementation manner, the aforementioned first sub-chip includes a plurality of ports, each of the aforementioned plurality of ports is connected to another sub-chip, each of the aforementioned ports corresponds to a sending buffer, and the aforementioned sending buffer is used for Storing the data to be sent; the aforementioned method also includes: when there are at least two ports to send the aforementioned data, the aforementioned first sub-chip selects the first port to send the aforementioned data; the aforementioned first port is the sending buffer of the aforementioned at least two ports The port with the least amount of data to send.

In this application, data is sent through a port with a small amount to be sent, which can reduce the waiting time for data queuing and improve the efficiency of data sending.

In a possible implementation manner, the aforementioned first data packet includes multiple target chiplet identifiers, and the aforementioned multiple target chiplet identifiers include the aforementioned first chiplet identifier; the aforementioned method further includes:

The aforementioned first sub-chip stores the data in the aforementioned first data packet;

The aforementioned first chiplet repackages the aforementioned data to obtain a sixth data packet;

The aforementioned first sub-chip sends the aforementioned sixth data packet to a destination sub-chip other than the aforementioned first sub-chip.

In this application, the data packet can carry the identifiers of multiple destination sub-chips. Compared with the existing situation where each destination sends a data packet, the number of data packets to be sent can be reduced and the transmission bandwidth can be saved.

In a second aspect, the present application provides a sub-chip, the sub-chip is a first sub-chip, and the aforementioned first sub-chip includes:

The receiving unit is configured to receive the first data packet; wherein, the aforementioned first data packet includes the identification of the target sub-chip; the aforementioned first sub-chip and the aforementioned target sub-chip are sub-chips included in the chip system, and the plurality of sub-chips in the aforementioned chip system The chips are arranged in a matrix, and each sub-chip in the aforementioned plurality of sub-chips is connected to surrounding adjacent sub-chips;

The sending unit is configured to send the data in the aforementioned first data packet to the aforementioned destination sub-chip based on the direction coordinate system with a smaller bandwidth consumption principle, and the aforementioned smaller bandwidth consumption principle is to deliver the aforementioned data to the aforementioned destination with a smaller transmission bandwidth Principles of chiplets;

The aforementioned directional coordinate system is constructed around the aforementioned first sub-chip, and the aforementioned directional coordinate system includes a first directional axis, a second directional axis, a third directional axis, and a fourth directional axis; the row where the aforementioned first sub-chip is located is located in the opposite direction on at least one of the aforementioned first direction axis and the aforementioned second direction axis; the column where the aforementioned first chiplet is located is located on at least one of the aforementioned third direction axis and the aforementioned fourth direction axis in opposite directions .

In a possible implementation manner, the foregoing sending unit is specifically configured to:

In the case that the aforementioned target chiplet is on the target direction axis, send the aforementioned data along the direction of the aforementioned target direction axis; the aforementioned target direction axis is the aforementioned first direction axis, the aforementioned second direction axis, the aforementioned third direction axis or the aforementioned Fourth orientation axis.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned sending unit is specifically used for:

In the case that the first target chiplet and the second target chiplet are located in two adjacent areas of the first area, the second area, the third area, and the fourth area respectively, send along the direction of the common direction axis The second data packet; the aforementioned second data packet includes the aforementioned data, the identification of the first target chiplet and the second target chiplet; the aforementioned common direction axis is the direction axis of the common boundary of the aforementioned two adjacent areas.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned sending unit is specifically used for:

When the aforementioned first target chiplet is in the aforementioned first area and the aforementioned second target chiplet is in the aforementioned third area, send the third data packet, and send the fourth data packet along the direction of one of the two boundary direction axes of the aforementioned third area; the aforementioned third data packet includes the aforementioned data and the identification of the aforementioned first purpose sub-chip, and the aforementioned fourth data The packet includes the aforementioned data and the aforementioned identification of the second target chiplet.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned sending unit is specifically used for:

When the first target chiplet is in the target area and the second target chiplet is on the direction axis of the boundary of the target area, the fifth data packet is sent along the direction of the direction axis of the boundary of the target area, and the fifth The data packet includes the aforementioned data and the identifications of the aforementioned first target chiplet and the second target chiplet; the aforementioned target area is the first area, the second area, the third area or the fourth area.

In a possible implementation manner, the aforementioned first sub-chip includes a plurality of ports, each of the aforementioned plurality of ports is connected to another sub-chip, each of the aforementioned ports corresponds to a sending buffer, and the aforementioned sending buffer is used for Store the data to be sent;

The aforementioned first sub-chip also includes a selection unit for:

When there are at least two ports to send the aforementioned data, select the first port to send the aforementioned data; the aforementioned first port is the port with the least amount of data to be sent in the sending buffer among the aforementioned at least two ports.

In a possible implementation manner, the aforementioned first data packet includes a plurality of target chiplet identifiers, and the identifiers of the aforementioned multiple target chiplets include the identifier of the aforementioned first chiplet; the aforementioned first chiplet further includes:

a storage unit, configured to store the data in the aforementioned first data packet;

An encapsulation unit, configured to re-encapsulate the foregoing data to obtain a sixth data packet;

The aforementioned sending unit is further configured to send the aforementioned sixth data packet to a destination chiplet other than the aforementioned first chiplet.

In a third aspect, the present application provides a sub-chip, which includes a processor, a memory, and a communication port; wherein the aforementioned memory and the communication port are coupled to the aforementioned processor, the aforementioned communication port is used to send and receive data, and the aforementioned memory is used to store computer program, the aforementioned processor is used to call the aforementioned computer program, so that the aforementioned sub-chip executes any one of the aforementioned methods in the first aspect; the aforementioned sub-chip is a sub-chip included in the chip system, and the plurality of sub-chips in the aforementioned chip system are in the form of a matrix Arranged, each sub-chip in the foregoing plurality of sub-chips is connected to surrounding adjacent sub-chips.

In a fourth aspect, the present application provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium. When the aforementioned computer program is executed by a processor, the method described in any one of the first aspect is implemented.

In a fifth aspect, the present application provides a computer program product, the computer program product includes a computer program, and when the computer program is executed by a processor, the method described in any one of the first aspect is implemented.

It can be understood that, the above-mentioned second aspect to the fifth aspect are all corresponding to implementing the method provided by any one of the above-mentioned first aspect. Therefore, the beneficial effects that it can achieve can refer to the beneficial effects in the corresponding method, and will not be repeated here.

Description of drawings

The drawings that need to be used in the embodiments of the present application will be introduced below.

Fig. 1 is a schematic diagram of the chip system provided by the present application;

FIG. 2 is a schematic structural diagram of a chiplet provided by the present application;

3 to 6 are schematic diagrams of the chip system provided by the present application;

FIG. 7 is a schematic diagram of sub-chipset division provided by the present application;

FIG. 8 is a schematic flowchart of a data transmission processing method in the chip system provided by the present application;

FIG. 9 is a schematic diagram of the data packet structure provided by the present application;

Fig. 10 is a schematic diagram of the direction coordinate system provided by the present application;

FIG. 11 is a schematic diagram of a direction coordinate system based on subchip construction provided by the present application;

FIG. 12 is a schematic structural diagram of a virtual device provided by the present application;

FIG. 13 is a schematic structural diagram of a physical device provided by the present application.

Embodiments of the present invention

Embodiments of the present application are described below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a chip system provided by an embodiment of the present application. The chip system 110 includes a plurality of sub-chips (16 sub-chips are exemplarily shown in FIG. 1 ), and the multiple sub-chips are connected according to a preset topology connection relationship. For example, the 16 sub-chips in FIG. 1 can be arranged in a matrix form, Then, a single chiplet is respectively connected to two, three or four surrounding chiplets.

Each sub-chip has its own memory, and FIG. 1 schematically shows the memory of some sub-chips. The memory can be, for example, synchronous dynamic random access memory (synchronous dynamic random access memory, SDRAM) or double rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), DDRSDRAM can be abbreviated as DDR.

Each sub-chip in the chip system 100 has complete processing capability and can perform tasks independently. Of course, multiple sub-chips in the chip system 100 can cooperate with each other to execute large-scale processing tasks.

Referring to FIG. 2 , FIG. 2 exemplarily shows a schematic structural diagram of the chiplets in the above-mentioned chip system 110 . The structure of the sub-chip can be network-on-chip (network-on-chip, Presented in the form of NoC). It can be seen that the chiplet may include a processing module, a routing module, a static memory, a memory controller and four ports (d0, d1, d2 and d3).

The above-mentioned processing module is a control unit (control unit, CU) in the sub-chip, which is responsible for the management of each processing flow in the sub-chip.

The above-mentioned routing module is responsible for data synchronization inside the sub-chip, data synchronization between sub-chips, data broadcasting and data transmission. Wherein, the routing module also includes a control unit, which is used to manage the routing process in the routing module. The routing module also includes a local buffer, which can be used to temporarily store data to be processed. The routing module also includes the port forwarding mapping module (forwarding-port mapper, FPM), the FPM can be a hardware module or a software module, a port forwarding mapping table is stored in the FPM, and the port forwarding mapping table includes the mapping relationship between the destination sub-chip and the sending port, which can be used to forward the data packet Mapped to the corresponding port for sending. The routing module stores the stream input table (stream in table, SIT) and stream output table (stream out table, SOT), the SIT and SOT are used for data transmission between sub-chips, which will be introduced in detail later, and will not be described in detail here.

The above-mentioned static memory may be a static random-access memory (static random-access memory, SRAM), etc., and is used for storing data in the sub-chip.

The above-mentioned memory controller is connected to the memory corresponding to the sub-chip, and the memory controller may be, for example, a DDR controller or the like.

The above four ports ( d0 , d1 , d2 and d3 ) are network interfaces of the sub-chips, which can realize data transmission between the above-mentioned sub-chips. The connection between the above sub-chips and sub-chips is realized through the four ports. Optionally, the sub-chip may also include two such ports, for example, sub-chip 0 , sub-chip 3 , sub-chip 12 and sub-chip 15 in FIG. 1 . Or, optionally, the sub-chip may also include three such ports, such as the sub-chip 4 in FIG. 1 .

The chip system provided by the embodiment of the present application is not limited to the structure shown in FIG. 1 , but may also have other structures, for example, refer to FIG. 3 . FIG. 3 exemplarily shows a chip system 120, which also includes a plurality of sub-chips (8 sub-chips are exemplarily shown in FIG. 2 ), and a plurality of sub-chips of the chip system 120 are arranged and connected in the form of a cuboid, which This connection method can shorten the data transmission path between sub-chips as much as possible. For the structure of the chiplets in the system-on-chip 120, reference may be made to the corresponding description in FIG. 2 above, and details will not be repeated here.

In a possible implementation manner, for ultra-large tasks, more sub-chips are required to process together to improve task processing efficiency, then, the above-mentioned chip system 110 or chip system 120 can be used as a chip subsystem, by A plurality of such subsystems form a larger system-on-a-chip, for example, refer to the system-on-a-chip 130 shown in FIG. 4 .

The system-on-a-chip 130 may include multiple subsystems of the above-mentioned chips. FIG. 4 shows an example including 8 subsystems. Each subsystem of the multiple subsystems may be the above-mentioned system-on-a-chip 110 or system-on-a-chip 120 . Each subsystem can be regarded as a whole, then the multiple subsystems can be connected through a preset topological connection relationship, for example, the connection can be arranged in the form of a cuboid, as shown in FIG. 4 . In order to facilitate understanding of the connection manner of each subsystem in the chip system 130 , as an example, the above-mentioned chip system 110 is used as an example to illustrate the connection structure diagram of each subsystem in the chip system 130 , as shown in FIG. 5 .

As can be seen in FIG. 5 , the chip system 130 includes 8 subsystems, each of the 8 subsystems includes 16 sub-chips, and the 16 sub-chips can be arranged and connected in a matrix. Between two adjacent subsystems, the connection between the two subsystems can be realized by connecting any sub-chip in one subsystem to any sub-chip in the other subsystem. In FIG. 5 , the chiplets arranged at the corners of the matrix in each subsystem are exemplarily used as the chiplets connected to another subsystem. For example, in subsystem 0, the connection between subsystem 0 and subsystem 1 is established through chiplet 3 in subsystem 0 and chiplet 0 in subsystem 1. The connection between the subsystem 0 and the subsystem 2 is established through the chiplet 12 in the subsystem 0 and the chiplet 0 in the subsystem 2 . The connection between subsystem 0 and subsystem 4 is established through chiplet 0 in subsystem 0 and chiplet 0 in subsystem 4 .

In a possible implementation manner, the foregoing subsystems may further include a control bus, for example, refer to the chip system 140 shown in FIG. 6 . The D-type bus shown in the chip system 140 is the control bus. The system-on-a-chip 140 includes a central controller (the central controller may be a sub-chip or a control module in the system-on-a-chip 140 ), and the central controller may manage the task processing flow in the system-on-a-chip 140 . The control bus is connected with the central controller for each subsystem to receive control instructions from the central controller. In a specific implementation, each subsystem may be connected to the control line by a sub-chip, and after receiving the control command, the sub-chip may forward it to the corresponding sub-chip in the same subsystem. Alternatively, each chiplet in each subsystem is connected to the control line for directly receiving control commands. This application does not limit the specific connection of the controller.

In addition to the above-mentioned system-on-a-chip 140, the system-on-a-chip provided in the embodiment of the present application (such as the system-on-a-chip 110, system-on-a-chip 120, and system-on-a-chip 130) also includes a central controller for managing the task processing flow of the entire system-on-a-chip. Similarly, the central controller may be a sub-chip or a control module in the chip system. The central controller can obtain the load conditions and resource usage conditions of all sub-chips in the chip system, so as to assign tasks to each sub-chip based on these conditions. Exemplarily, a task scheduler (scheduler) in the central controller can be used to assign tasks to these sub-chips based on information such as load conditions and resource usage conditions of each sub-chip.

The above-mentioned central controller can also be responsible for data scheduling in the chip system. Specifically, the central controller obtains the data transmission status of each sub-chip through the control bus, and can know the congestion status of each transmission path and/or the port congestion status of each sub-chip by analyzing the data transmission status, so that based on these According to the situation, the data transmission strategy is formulated and sent to each sub-chip in the form of scheduling information. Each sub-chip sends corresponding data based on the scheduling information issued by the controller, thereby reducing the probability of congestion and improving data transmission efficiency.

In the chip system provided in the embodiment of the present application, each sub-chip is capable of processing data independently. But in the case of large data tasks, the processing efficiency of a single sub-chip is low. In order to improve task processing efficiency, the multiple sub-chips included in the above chip system may be divided into multiple sub-chip groups, and each sub-chip group includes at least one sub-chip. In this way, data tasks can be processed with the sub-chipset as a processing unit, thereby improving processing efficiency. In order to facilitate the understanding of the chipset, please refer to Figure 7.

FIG. 7 takes the above chip system 110 as an example, and divides 16 sub-chips in the chip system into 9 sub-chip groups. Refer to the division situation shown in FIG. 7 for details, and each sub-chip group includes at least one sub-chip. In addition, multiple subchips of the same subchipset may be adjacent subchips, such as subchipset 3 , subchipset 4 , subchipset 7 , and subchipset 8 . Alternatively, the sub-chips of the same sub-chipset may be non-adjacent sub-chips, for example, the sub-chipset 2 is composed of non-adjacent sub-chips 1 and 12 .

The chip system provided in the embodiment of the present application may implement data task processing in a manner of data parallelism, model parallelism, or model parallelism plus data parallelism. in:

Data parallelism refers to dividing the data to be processed into several data blocks, and assigning the several data blocks to different sub-chipsets, and each chipset runs the same processing program to process the allocated data. For example, assuming that the data to be processed is divided into 3 data blocks, and the existing 3 sub-chipsets can run the same processing program to process the data blocks, then the first data block of the 3 data blocks can be sent to the 3 The first sub-chipset in the three sub-chipsets processes, the second data block in the three data blocks is sent to the second sub-chipset in the three sub-chipsets for processing, and the third data block in the three data blocks is processed. The data block is sent to the third sub-chipset among the three sub-chipsets for processing.

Model parallelism means that multiple sub-chipsets jointly complete a data processing task, and each sub-chipset in the multiple sub-chipsets only executes a part of the entire data processing task (the part of the steps may be one or more processing steps). For example, assuming that a data processing task requires three steps to be processed, two sub-chipsets can be configured to jointly complete the task. Wherein, the first sub-chipset completes the processing of the first two steps in the three steps, and the second sub-chipset obtains the processed data from the first sub-chipset to complete the processing of the third step. Alternatively, three sub-chipsets can be configured to work together to accomplish this task. Wherein, the first sub-chipset completes the processing of the first step in the three steps, the second sub-chipset obtains the processed data from the first sub-chipset to complete the processing of the second step, and the third sub-chipset completes the processing of the second step from the first sub-chipset. 2. The sub-chipset acquires the processed data to complete the processing in the third step. That is, each chipset may complete one or more steps, which may be specifically determined according to the load and resource usage of the chipset.

The method of model parallelism plus data parallelism combines the above two methods of data parallelism and model parallelism to process data. For example, if a data processing task needs to go through three steps to complete the processing, then three sub-chipsets can be configured to jointly complete the task. Wherein, the first sub-chipset completes the processing of the first step in the three steps, the second sub-chipset obtains the processed data from the first sub-chipset to complete the processing of the second step, and the third sub-chipset completes the processing of the second step from the first sub-chipset. 2. The sub-chipset acquires the processed data to complete the processing in the third step. However, since the processing of the first step is relatively complicated, it takes more time to complete the processing of this step. In order to improve the processing efficiency, one or more sub-chipsets can be configured to jointly execute the processing task of the first step. For example, a fourth sub-chipset may be further configured to perform the processing task of the first step together with the aforementioned first sub-chipset. Specifically, the data for processing in the first step may be divided into two parts, one part is sent to the first sub-chipset for processing, and the other part is sent to the fourth sub-chipset for processing. Then, the processed data of the first sub-chipset and the fourth sub-chipset are sent to the second sub-chipset for processing in the second step.

It should be noted that, in the above method of model parallelism plus data parallelism, each processing step can be processed by data parallel processing, or some processing steps can be processed by data parallel processing, which can be based on specific The implementation is determined, and this application does not limit it.

In a specific implementation, the central controller of the chip system may distribute data processing tasks to each sub-chipset. Using model parallelism or model parallelism plus data parallelism to realize data task processing requires data transmission between sub-chips. Data transmission will generate time delay and reduce processing efficiency. In order to realize efficient data transmission between sub-chips in a chip system and improve the processing performance of the chip system, an embodiment of the present application provides a data transmission processing method in the chip system.

Referring to Figure 8, the data transmission processing method provided by the embodiment of the present application includes but is not limited to the following steps:

S801. The first sub-chip receives a first data packet; wherein, the first data packet includes the identification of the target sub-chip; the first sub-chip and the target sub-chip are sub-chips included in the chip system, and the chip system includes multiple The chiplets are connected in a preset topology.

The chip system may be the chip system 110 , the chip system 120 , the chip system 130 , or the chip system 140 described above. The first sub-chip may be any sub-chip in any one of these chip systems. For the convenience of the following description, the system-on-a-chip where the first sub-chip is located is the first system-on-a-chip. The first sub-chip receives the first data packet from another sub-chip in the first system-on-a-chip.

In a specific implementation, the first data packet may include one or more of information such as packet type (type), task identifier, data stream identifier, destination sub-chip identifier, packet number, and data. item. in:

The packet type is used to indicate a specific type of a packet, and the packet type may include a data packet (DATA), a header packet (Header), or a unblocked packet (unblock, UB) and the like. The packet type of the first data packet is DATA.

The identifier of the task refers to the identifier of the data processing task corresponding to the package. Multiple data processing tasks can be processed simultaneously in the chip system, and each data processing task has its corresponding identifier. The identifier of the task may be, for example, 1 or other identifiers, which is not limited in the present application. The above-mentioned first data packet is a carrier for data in a certain data processing task to be transmitted between chiplets, therefore, the identifier of the task in the first data packet is the identifier of the certain data processing task.

Identification of data flow: Regarding data flow, one sub-chip sends data to another sub-chip, and these data are packaged into multiple data packets, and these data packets are numbered and sent in sequence, and these continuously sent data packets form a data flow. In a possible implementation, each data packet can carry 1kb of data. If the total size of the transmitted data is 64kb, then these data can be split and encapsulated into 64 data packets for transmission, and the 64 data packets can be form a data stream. Each data flow is configured with an identifier, which is the identifier of the data flow. The identifier of the data stream included in the first data packet is the identifier of the data stream where the first data packet is located.

The identification of the destination chiplet is used to indicate the destination to which the packet is destined. The identifiers of the target chiplets in the first data packet may be identifiers of one or more target chiplets. If the data in the first data packet corresponds to one target sub-chip, the identifier of the target sub-chip in the first data packet is the identifier of the one destination sub-chip. If there are multiple target chiplets corresponding to the data in the first data packet, the identifiers of the target chiplets in the first data packet are the identifiers of the multiple target chiplets. For example, if there are two target chiplets of the data packet, which are chiplet 0 and chiplet 9 respectively, then the data packet includes the identifiers of chiplet 0 and chiplet 9 .

The packet number refers to the sequential numbering of a packet within the data stream to which it belongs.

The data is the payload (layout) in the packet, which is the actual transmission content.

In a possible implementation manner, the above-mentioned first data packet may also carry sideband information, and the sideband information may include one or more information of a task identifier, a data flow identifier, or a destination chiplet identifier. The sideband information may not be encapsulated in the first data packet, but sent together with the first data packet. In a specific implementation, the information included in the first data packet can only be kept alive by the routing module of the sub-chip, and other modules such as ports in the sub-chip are not aware of it. Therefore, in order to facilitate fast forwarding of the first data packet, the first data packet may be configured to carry the foregoing sideband information. In order to facilitate understanding of the format of the first data packet and the format of the side information, refer to FIG. 9 by way of example. The format of the first data packet and the corresponding sideband information shown in FIG. 9 are only examples. In a specific implementation, the first data packet may also include other information, and the sideband information may also include more information. The present application There is no restriction on this.

S802. The above-mentioned first sub-chip sends the data in the above-mentioned first data packet to the above-mentioned destination sub-chip based on the direction coordinate system with a smaller bandwidth consumption principle, and the smaller bandwidth consumption principle is to deliver the data with a smaller transmission bandwidth The principle of the target sub-chip: the direction coordinate system is constructed with the first sub-chip as the center.

Firstly, the direction coordinate system constructed with the first sub-chip as the center is introduced. FIG. 10 exemplarily shows a schematic diagram of a direction coordinate system centered on the first chiplet. It can be seen that the directional coordinate system includes four directional axes: a first directional axis, a second directional axis, a third directional axis and a fourth directional axis. The four direction axes all diverge outward from the center of the first sub-chip. Wherein, the first direction axis and the second direction axis are collinear and opposite in direction; the third direction axis and the fourth direction axis are collinear and opposite in direction. The direction coordinate system also includes four regions: a first region, a second region, a third region and a fourth region. Wherein, the first area is bounded by the first direction axis and the third direction axis; the second area is bounded by the second direction axis and the third direction axis; the third area is bounded by the second direction axis and the fourth direction axis as boundaries, and the fourth region is bounded by the first direction axis and the fourth direction axis.

In the chip system, the row of the first sub-chip is located on at least one of the first direction axis and the second direction axis, and the column of the first sub-chip is located on the third direction axis and the second direction axis. on at least one of the four directional axes. An example can be seen in FIG. 11 . Assuming that the sub-chip 5 in the chip system is the first sub-chip, then a direction coordinate system is established with the sub-chip 5 as the center. In the direction coordinate system, the second row of the chiplet 5 is located on the first direction axis and the second direction axis, and the second column of the chiplet 5 is located on the third direction axis and the fourth direction axis . Then, the chiplet 2 and the chiplet 3 are located in the first region of the directional coordinate system. Chiplet 0 is located in the second area of the orientation coordinate system. Chiplet 8 and chiplet 12 are located in the third region of the directional coordinate system. The chiplet 10 , the chiplet 11 , the chiplet 14 and the chiplet 15 are located in the fourth area of the directional coordinate system.

In a possible implementation manner, if the sub-chip 0 is the first sub-chip in the above-mentioned chip system in FIG. 11 , then a direction coordinate system is established centering on the sub-chip 0 . In the directional coordinate system, the first row of the chiplet 0 is located on the first directional axis, and the first column of the chiplet 0 is located on the fourth directional axis. Then, except for the sub-chips in the row and column where the sub-chip 0 is located, all other sub-chips are located in the fourth area of the coordinate system in this direction.

In a possible implementation manner, the sending of the data in the first data packet to the destination chiplet by the first sub-chip based on the direction coordinate system and the principle of less bandwidth consumption includes: the destination sub-chip included in the first data packet When the chip is on the target direction axis, the above-mentioned first sub-chip sends the data of the first data packet along the direction of the target direction axis; the target direction axis is the first direction axis, the second direction axis, the The third directional axis or the fourth directional axis. For ease of understanding, it will be described with reference to the above-mentioned FIG. 11 as an example.

In FIG. 11 , it is assumed that the sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet, and the identifier of the destination sub-chip in the data packet indicates that the destination sub-chip is the sub-chip 7 . If the data packet only includes the identifier of one destination chiplet, then, since the chiplet 7 is located on the first direction axis, the chiplet 5 sends the data packet along the direction of the first direction axis. That is, the sub-chip 5 first sends the data packet to the sub-chip 6 , and then the sub-chip 6 forwards the data packet to the sub-chip 7 . If the data packet includes identifiers of multiple target chiplets, the chiplet 7 as one of the target chiplets is located on the first direction axis. Therefore, the chiplet 5 copies the data in the data packet to generate a new data packet, and sends the new data packet along the direction of the first direction axis. That is, the sub-chip 5 first sends the new data packet to the sub-chip 6 , and then the sub-chip 6 forwards it to the sub-chip 7 . The newly generated data packet includes the identification of the chiplet 7 .

In a possible implementation manner, the first data packet includes identifiers of the first destination chiplet and the second destination chiplet. The first chiplet sending the data in the first data packet to the target chiplet based on the direction coordinate system and the principle of small bandwidth consumption includes: in the direction coordinate system established centering on the first chiplet, in the first In the case where the target chiplet and the second target chiplet are respectively located in two adjacent areas of the first area, the second area, the third area and the fourth area of the coordinate system, the first chiplet is along the common direction A second packet is sent in the direction of the axis. The second data packet includes the data, identifiers of the first destination chiplet and the second destination chiplet. The common direction axis is the direction axis of the common boundary of the two adjacent regions. For ease of understanding, it will be described with reference to the above-mentioned FIG. 11 as an example.

In FIG. 11 , it is assumed that the chiplet 5 is the above-mentioned first chiplet, and it receives a data packet, and the identification of the target chiplet in the data packet indicates that the target chiplets are the chiplet 8 and the chiplet 14 . The sub-chip 8 is located in the third area, and the sub-chip 14 is located in the fourth area, these two areas are adjacent areas, and the common boundary is the fourth direction axis. Therefore, the chiplet 5 sends the data packet along the direction of the fourth directional axis. That is, the sub-chip 5 first sends the data packet to the sub-chip 9 , and then the sub-chip 9 further forwards it. Specifically, the sub-chip 9 can also be regarded as the above-mentioned first sub-chip, and a direction coordinate system is established with the sub-chip 9 as the center, and then data is forwarded based on the above-mentioned principle of smaller bandwidth consumption.

In a possible implementation manner, the first data packet includes identifiers of the first destination chiplet and the second destination chiplet. The first chiplet sending the data in the first data packet to the target chiplet based on the direction coordinate system and the principle of small bandwidth consumption includes: in the direction coordinate system established centering on the first chiplet, in the first In the case where the target chiplet is in the first area of the coordinate system and the second target chiplet is in the third area, the first chiplet is along one of the direction axes of the two boundaries of the first area The third data packet is sent in a direction, and the fourth data packet is sent along the direction of one of the two boundary direction axes of the third area. The third data packet includes the data and the identifier of the first destination chiplet. The fourth data packet includes the data and the identifier of the second destination chiplet. For ease of understanding, it will be described with reference to the above-mentioned FIG. 11 as an example.

In FIG. 11 , it is assumed that the sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet, and the identification of the destination sub-chip in the data packet indicates that the destination sub-chips are the sub-chip 2 and the sub-chip 12 . The chiplet 2 is located in the first area, and the chiplet 12 is located in the third area. Then, the chiplet 5 can regenerate two data packets: data packet A and data packet B based on the data in the received data packet. The data package A includes data and the identification of the sub-chip 2 , and the data package B includes the data and the identification of the sub-chip 12 . Then, the data packet A is sent along the direction of the first direction axis or the third direction axis. For example, the data packet A is sent along the direction of the first direction axis, that is, the data packet A is first sent to the sub-chip 6 , and then the sub-chip 6 forwards the data packet A to the sub-chip 2 . In addition, the chiplet 5 sends the data packet B along the direction of the second direction axis or the fourth direction axis. For example, the data packet B is sent along the direction of the fourth direction axis, that is, the data packet B is first sent to the sub-chip 9 , and then the sub-chip 9 continues to forward it further.

In a possible implementation manner, the first data packet includes identifiers of the first destination chiplet and the second destination chiplet. The first chiplet sending the data in the first data packet to the target chiplet based on the direction coordinate system and the principle of small bandwidth consumption includes: in the direction coordinate system established centering on the first chiplet, in the first When the target chiplet is in the second area of the coordinate system, and the second target chiplet is in the fourth area, the first chiplet is along one of the direction axes of the two boundaries of the second area. The third data packet is sent in the direction, and the fourth data packet is sent along the direction of one of the two boundary direction axes of the fourth area. The third data packet includes the data and the identifier of the first destination chiplet. The fourth data packet includes the data and the identifier of the second destination chiplet. For ease of understanding, it will be described with reference to the above-mentioned FIG. 11 as an example.

In FIG. 11 , it is assumed that chiplet 5 is the above-mentioned first chiplet, and it receives a data packet, and the identification of the target chiplet in the data packet indicates that the target chiplets are chiplet 0 and chiplet 10 . Chiplet 0 is located in the second area, and chiplet 10 is located in the fourth area. Then, the chiplet 5 can regenerate two data packets: data packet C and data packet D based on the data in the received data packet. The data package C includes data and the identification of the sub-chip 0 , and the data package D includes the data and the identification of the sub-chip 10 . Then, the data packet C is sent along the direction of the second direction axis or the third direction axis. For example, the data packet C is sent along the direction of the second direction axis, that is, the data packet C is first sent to the sub-chip 4 , and then the sub-chip 4 forwards the data packet C to the sub-chip 0 . In addition, the chiplet 5 sends the data packet D along the direction of the first direction axis or the fourth direction axis. For example, the data packet D is sent along the direction of the first direction axis, that is, the data packet D is first sent to the sub-chip 6 , and then the sub-chip 6 forwards it to the sub-chip 10 .

In a possible implementation manner, the first data packet includes identifiers of the first destination chiplet and the second destination chiplet. The first chiplet sending the data in the first data packet to the target chiplet based on the direction coordinate system and the principle of small bandwidth consumption includes: in the direction coordinate system established centering on the first chiplet, in the first When the target chiplet is in the target area and the second target chiplet is on the direction axis of the boundary of the target area, the first chiplet sends the fifth data packet along the direction axis of the boundary of the target area. The fifth data packet includes the data and identifications of the first and second destination chiplets. The target area is the first area, the second area, the third area or the fourth area. For ease of understanding, it will be described with reference to the above-mentioned FIG. 11 as an example.

In FIG. 11 , it is assumed that the sub-chip 5 is the above-mentioned first sub-chip, and it receives a data packet, and the identification of the destination sub-chip in the data packet indicates that the destination sub-chips are the sub-chip 14 and the sub-chip 9 . The chiplet 14 is located in the fourth region, and the chiplet 9 is located on the fourth axis. The fourth direction axis is the boundary direction axis of the fourth area, then the chiplet 5 can send the received data packet along the direction of the fourth direction axis, that is, to the chiplet 9 . After the chiplet 9 receives the data packet, it stores the data in the data packet. And make a copy of the data to regenerate a data package. The new data packet includes the identification of the sub-chip 14 , and then the new data packet is sent to the sub-chip 13 or the sub-chip 10 , and then forwarded to the sub-chip 14 by the sub-chip 13 or the sub-chip 10 .

In a possible implementation manner, the above-mentioned first sub-chip may also send the data in the above-mentioned first data packet based on the congestion situation of its own port.

Specifically, based on the above introduction about the chip system, it can be known that each sub-chip includes a plurality of ports for communicating with other sub-chips. Wherein, each port is configured with a corresponding sending buffer, and the sending buffer is used to store data to be sent.

After the first sub-chip receives the first data packet, it parses the first data packet to obtain the identity of the destination sub-chip in the first data packet. If the identification of the target chiplet indicates that the first chiplet is the target chiplet, then the first chiplet extracts the data stored in the first data packet for subsequent processing. Otherwise, the first sub-chip looks up the sending port of the first data packet in its own forwarding mapping table by using the identifier of the destination sub-chip as an index. For the introduction of the forwarding mapping table, reference may be made to the corresponding description in the foregoing description of FIG. 2 , which will not be repeated here. If there are multiple sending ports found, the specific sending port may be determined based on the congestion conditions of the sending buffers of the multiple sending ports. Specifically, in order to improve data transmission efficiency, the port with the least amount of data to be sent among the sending buffers of the multiple sending ports may be selected to send the first data packet.

Optionally, the forwarding mapping table in the first chiplet may be initialized based on the above-mentioned direction coordinate system and the above-mentioned principle of smaller bandwidth consumption. Exemplarily, taking FIG. 11 as an example, assuming that the chiplet 5 is the first chiplet and the chiplet 2 is the target chiplet, then the chiplet 5 can be determined based on the constructed direction coordinate system and the principle of smaller bandwidth consumption: A data packet destined for the sub-chip 2 can be sent through its own port d0 or d1. Therefore, in the forwarding mapping table of the chiplet 5 , the sending port corresponding to the destination chip 2 is port d0 or d1 . For other purpose sub-chips, reference may be made to the description here, and details are not repeated here.

In a possible implementation manner, if the above-mentioned first data packet includes identifications of multiple target chiplets, and the first chiplet is one of the target chiplets, then the first chiplet extracts the first data packet The data in is stored for subsequent processing. In addition, the first chiplet uses the identifiers of the remaining target chiplets as an index to look up the data sending port of the first data packet in its own forwarding mapping table.

If the identification of the above-mentioned remaining target sub-chip is one, then, in the same way, after finding the corresponding sending port, select the port with the least amount of data to be sent in the sending buffer of the sending port to send the first data packet The data. Specifically, the data will be repackaged into a data packet for transmission, and the identification of the target sub-chip in the repackaged data packet no longer includes the identification of the first sub-chip, but only includes the identification of the remaining target sub-chips .

If there are more than one identifiers of the remaining destination sub-chips, then the first sub-chip searches for corresponding sending ports in its own forwarding mapping table. If the found sending ports are the same, then the data included in the first data packet may be copied to regenerate a data packet, and the newly generated data packet includes the identifiers of the remaining destination chiplets. And send this newly generated packet from the same send port found. Similarly, the sending port may be the port with the least amount of data to be sent in the sending buffer among the found sending ports.

Alternatively, if there are more than one identifiers of the remaining target sub-chips, two are taken as an example, assuming that the remaining target sub-chips are sub-chips A and sub-chips B. The above-mentioned first sub-chip looks up the sending port mapped with the identifier of the sub-chip A and the sending port mapped with the identifier of the sub-chip B in its own forwarding mapping table. Assuming that the found sending ports are different, the first sub-chip may regenerate two data packets: data packet A and data packet B. Both data packets include the data included in the above-mentioned first data packet, wherein the identifier of the target sub-chip included in the data packet A is the identifier of the sub-chip A, and the identifier of the target sub-chip included in the data packet B is the identifier of the sub-chip B. Then, the data packet A and the data packet B are sent through the respectively found sending ports. Similarly, the sending port may be the port with the least amount of data to be sent in the sending buffer among the found sending ports.

To sum up, the embodiment of the present application transmits the received data based on the data transmission situation in the chip system, so as to flexibly schedule the data transmission, improve the data transmission efficiency, and further improve the processing performance of the chip system.

The foregoing mainly introduces the data transmission processing method in the chip system provided by the embodiment of the present application. It can be understood that, in order to realize the above corresponding functions, each device includes a corresponding hardware structure and/or software module for performing each function. Combining the units and steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

The embodiments of the present application may divide the device into functional modules according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules. It should be noted that the division of modules in this embodiment of the present application is schematic, and is only a logical function division, and there may be other division methods in actual implementation.

In the case of dividing each functional module corresponding to each function, FIG. 12 shows a specific logical structural diagram of the device, which may be the above-mentioned first sub-chip. The device 1200 includes:

The receiving unit 1201 is configured to receive the first data packet; wherein, the aforementioned first data packet includes the identification of the target sub-chip; the aforementioned device 1200 and the aforementioned target sub-chip are sub-chips included in the chip system, and the multiple sub-chips in the aforementioned chip system Arranged in the form of a matrix, each of the aforementioned multiple sub-chips is connected to surrounding adjacent sub-chips;

The sending unit 1202 is configured to send the data in the aforementioned first data packet to the aforementioned destination chiplet based on the direction coordinate system with a smaller bandwidth consumption principle, and the aforementioned smaller bandwidth consumption principle is to deliver the aforementioned data to the aforementioned The principle of the target chip;

The aforementioned directional coordinate system is constructed around the aforementioned device 1200, and the aforementioned directional coordinate system includes a first directional axis, a second directional axis, a third directional axis, and a fourth directional axis; on at least one of the direction axis and the aforementioned second direction axis; the row in which the device 1200 is located is located on at least one of the aforementioned third direction axis and the aforementioned fourth direction axis in opposite directions.

In a possible implementation manner, the foregoing sending unit 1202 is specifically configured to:

In the case that the aforementioned target chiplet is on the target direction axis, send the aforementioned data along the direction of the aforementioned target direction axis; the aforementioned target direction axis is the aforementioned first direction axis, the aforementioned second direction axis, the aforementioned third direction axis or the aforementioned Fourth orientation axis.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned sending unit 1202 is specifically used for:

In the case that the first target chiplet and the second target chiplet are located in two adjacent areas of the first area, the second area, the third area, and the fourth area respectively, send along the direction of the common direction axis The second data packet; the aforementioned second data packet includes the aforementioned data, the identification of the first target chiplet and the second target chiplet; the aforementioned common direction axis is the direction axis of the common boundary of the aforementioned two adjacent regions.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned sending unit 1202 is specifically used for:

When the aforementioned first target chiplet is in the aforementioned first area and the aforementioned second target chiplet is in the aforementioned third area, send the third data packet, and send the fourth data packet along the direction of one of the two boundary direction axes of the aforementioned third area; the aforementioned third data packet includes the aforementioned data and the identification of the aforementioned first purpose sub-chip, and the aforementioned fourth data The packet includes the aforementioned data and the aforementioned identification of the second target chiplet.

In a possible implementation manner, the aforementioned direction coordinate system further includes a first area, a second area, a third area, and a fourth area; the aforementioned first area is bounded by the aforementioned first direction axis and the aforementioned third direction axis, and the aforementioned The second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, and the fourth area is bounded by the first direction axis and the first direction axis. The four-direction axis is the boundary;

The aforementioned first data packet includes the identification of the first purpose sub-chip and the second purpose sub-chip; the aforementioned sending unit 1202 is specifically used for:

When the first target chiplet is in the target area and the second target chiplet is on the direction axis of the boundary of the target area, the fifth data packet is sent along the direction of the direction axis of the boundary of the target area, and the fifth The data packet includes the aforementioned data and the identifications of the aforementioned first target chiplet and the second target chiplet; the aforementioned target area is the first area, the second area, the third area or the fourth area.

In a possible implementation manner, the aforementioned device 1200 includes a plurality of ports, each of the aforementioned plurality of ports is connected to another sub-chip, each of the aforementioned ports corresponds to a sending buffer, and the aforementioned sending buffer is used to store the data sent;

The aforementioned device 1200 also includes a selection unit for:

When there are at least two ports to send the aforementioned data, select the first port to send the aforementioned data; the aforementioned first port is the port with the least amount of data to be sent in the sending buffer among the aforementioned at least two ports.

In a possible implementation manner, the aforementioned first data packet includes multiple target chiplet identifiers, and the aforementioned multiple target chiplet identifiers include the aforementioned device 1200; the aforementioned device 1200 further includes:

a storage unit, configured to store the data in the aforementioned first data packet;

An encapsulation unit, configured to re-encapsulate the foregoing data to obtain a sixth data packet;

The aforementioned sending unit 1202 is further configured to send the aforementioned sixth data packet to a destination chiplet other than the aforementioned device 1200 .

FIG. 13 is a schematic diagram of a specific hardware structure of the device provided by the present application. The device 1300 may be the above-mentioned first chiplet. The device 1300 includes: a processor 1301 , a memory 1302 and a communication port 1303 . The processor 1301 , the communication port 1303 and the memory 1302 may be connected to each other or through a bus 1304 .

Exemplarily, the memory 1302 is used to store computer programs and data of the device 1300, and the memory 1302 may include but not limited to random storage memory (random access memory, RAM), read-only memory (read-only memory, ROM), erasable programmable read-only memory (erasable programmable read only memory, EPROM) or portable read-only memory (compact disc read-only memory, CD-ROM), etc. Exemplarily, the memory 1302 may be the static memory shown in FIG. 2 above.

The communication port 1303 includes a sending port and a receiving port. The number of the communication port 1303 may be multiple, and is used to support the device 1300 to communicate, for example, to receive or send data or messages. Exemplarily, the communication port 1303 may be the ports d0, d1, d2 and d3 shown in FIG. 2 above.

Exemplarily, the processor 1301 may be a central processing unit, a general processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like. Exemplarily, the processor 1301 may be the processing module shown in FIG. 2 above. The processor 1301 may be used to read the program stored in the above-mentioned memory 1302, so that the device 1300 executes the operations performed by the first chiplet as described above in FIG. 8 and its specific embodiments.

For the specific operations and beneficial effects of each unit in the apparatus 1300 shown in FIG. 13 , refer to the corresponding description in FIG. 8 and its specific method embodiment above, and details are not repeated here.

The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and the computer program is executed by a processor as described in any of the above-mentioned FIG. 8 and its possible method embodiments. Operation performed by the first chiplet.

An embodiment of the present application also provides a computer program product. When the computer program product is read and executed by a computer, the operation performed by the first sub-chip described in any of the above-mentioned FIG. 8 and its possible method embodiments will be realized.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present application. scope.

Claims (10)

1. A data transmission processing method in a chip system, wherein the method includes:

   The first sub-chip receives the first data packet; wherein, the first data packet includes the identification of the target sub-chip; the first sub-chip and the target sub-chip are sub-chips included in the chip system, and in the chip system The multiple sub-chips are arranged in a matrix, and each sub-chip in the multiple sub-chips is connected to surrounding adjacent sub-chips;

   The first sub-chip sends the data in the first data packet to the destination sub-chip based on the direction coordinate system with a smaller bandwidth consumption principle, and the smaller bandwidth consumption principle is to transfer the The principle of data delivery to the target sub-chip;

   The directional coordinate system is constructed around the first sub-chip, and the directional coordinate system includes a first directional axis, a second directional axis, a third directional axis, and a fourth directional axis; where the first sub-chip is located The row is located on at least one of the first direction axis and the second direction axis in opposite directions; the column where the first chiplet is located is located on the third direction axis and the fourth direction axis in opposite directions. on at least one of the orientation axes.
2. The method according to claim 1, wherein the first sub-chip sends the data in the first data packet to the destination sub-chip based on a direction coordinate system with a principle of less bandwidth consumption comprising:

   When the target chiplet is on the target direction axis, the first chiplet sends the data along the direction of the target direction axis; the target direction axis is the first direction axis, the The second direction axis, the third direction axis or the fourth direction axis.
3. The method according to claim 1, wherein the directional coordinate system further comprises a first area, a second area, a third area and a fourth area; three direction axes as boundaries, the second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, the fourth area is bounded by the first orientation axis and the fourth orientation axis;

   The first data packet includes the identification of the first target chiplet and the second target chiplet; the first chiplet sends the first data to the target chiplet based on the direction coordinate system and the principle of less bandwidth consumption The data in the package includes:

   In the case where the first target chiplet and the second target chiplet are located in two adjacent areas of the first area, the second area, the third area and the fourth area respectively, the first chiplet Sending a second data packet along the direction of the common direction axis; the second data packet includes the data, the identification of the first purpose sub-chip and the second purpose sub-chip; the common direction axis is the two adjacent The direction axis of the common boundary of the regions.
4. The method according to claim 1, wherein the directional coordinate system further comprises a first area, a second area, a third area and a fourth area; three direction axes as boundaries, the second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, the fourth area is bounded by the first orientation axis and the fourth orientation axis;

   The first data packet includes the identification of the first target chiplet and the second target chiplet; the first chiplet sends the first data to the target chiplet based on the direction coordinate system and the principle of less bandwidth consumption The data in the package includes:

   When the first target chiplet is in the first area and the second target chiplet is in the third area, the first chiplet is along the direction of the two boundaries of the first area The third data packet is sent in the direction of one of the direction axes in the axis, and the fourth data packet is sent in the direction of one of the two boundary direction axes of the third area; the third data packet includes the data and the identifier of the first destination chiplet, the fourth data packet includes the data and the identifier of the second destination chiplet.
5. The method according to claim 1, wherein the directional coordinate system further comprises a first area, a second area, a third area and a fourth area; three direction axes as boundaries, the second area is bounded by the second direction axis and the third direction axis, the third area is bounded by the second direction axis and the fourth direction axis, the fourth area is bounded by the first orientation axis and the fourth orientation axis;

   The first data packet includes the identification of the first target chiplet and the second target chiplet; the first chiplet sends the first data to the target chiplet based on the direction coordinate system and the principle of less bandwidth consumption The data in the package includes:

   In the case where the first target chiplet is in the target area and the second target chiplet is on the direction axis of the boundary of the target area, the direction axis of the first chiplet along the boundary of the target area Sending a fifth data packet in the direction, the fifth data packet including the data and the identification of the first target chiplet and the second target chiplet; the target area is the first area, the second area, and the third area or the fourth area.
6. The method according to claim 1, wherein the first sub-chip includes a plurality of ports, each port of the plurality of ports is connected to another sub-chip, and each port corresponds to a sending buffer, The sending buffer is used to store data to be sent;

   The method also includes:

   When there are at least two ports to send the data, the first sub-chip selects the first port to send the data; the first port is the amount of data to be sent in the send buffer of the at least two ports Minimal number of ports.
7. The method according to any one of claims 1-6, wherein the first data packet includes a plurality of target chiplet identifiers, and the identifiers of the plurality of target chiplets include the first chiplet the identification of; said method also includes:

   The first chiplet stores data in the first data packet;

   The first chiplet repackages the data to obtain a sixth data packet;

   The first chiplet sends the sixth data packet to a destination chiplet other than the first chiplet.
8. A sub-chip, wherein the sub-chip is a first sub-chip, and the first sub-chip includes:

   A receiving unit, configured to receive a first data packet; wherein, the first data packet includes an identification of a target sub-chip; the first sub-chip and the target sub-chip are sub-chips included in a chip system, and the chip system The plurality of subchips in the matrix are arranged in the form of a matrix, and each subchip in the plurality of subchips is connected to surrounding adjacent subchips;

   A sending unit, configured to send the data in the first data packet to the destination chiplet based on the direction coordinate system with a smaller bandwidth consumption principle, the smaller bandwidth consumption principle is to transmit the data with a smaller transmission bandwidth The principle of delivering the target sub-chip;

   The directional coordinate system is constructed around the first sub-chip, and the directional coordinate system includes a first directional axis, a second directional axis, a third directional axis, and a fourth directional axis; where the first sub-chip is located The row is located on at least one of the first direction axis and the second direction axis in opposite directions; the column where the first chiplet is located is located on the third direction axis and the fourth direction axis in opposite directions. on at least one of the orientation axes.
9. A sub-chip, including a processor, a memory and a communication port; wherein the memory and the communication port are coupled to the processor, the communication port is used to send and receive data, the memory is used to store computer programs, the The processor is used to call the computer program, so that the sub-chip executes the method according to any one of claims 1-7;

   The sub-chips are sub-chips included in a chip system, and a plurality of sub-chips in the chip system are arranged in a matrix, and each sub-chip in the plurality of sub-chips is connected to surrounding adjacent sub-chips.
10. A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1-7 is implemented.