WO2023123011A1 - 一种高数据率的毫米波超再生接收机 - Google Patents

一种高数据率的毫米波超再生接收机 Download PDF

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WO2023123011A1
WO2023123011A1 PCT/CN2021/142318 CN2021142318W WO2023123011A1 WO 2023123011 A1 WO2023123011 A1 WO 2023123011A1 CN 2021142318 W CN2021142318 W CN 2021142318W WO 2023123011 A1 WO2023123011 A1 WO 2023123011A1
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nmos transistor
signal
transistor
nmos
drain
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PCT/CN2021/142318
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English (en)
French (fr)
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丰光银
刘俊宏
涂峻源
吴仪
王彦杰
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华南理工大学
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/12—Neutralising, balancing, or compensation arrangements

Definitions

  • the invention relates to the millimeter wave transceiver technology of the new generation information technology, in particular to a high data rate millimeter wave super regenerative receiver.
  • Receivers working above 200 GHz are limited by the above-mentioned low gain, and have to use the down-converting mixer as the first active circuit in the receiving chain to reduce the operating frequency of the subsequent circuit.
  • This receiver is called It is an IQ two-way mixer Mixer-first receiver [1], [2].
  • this architecture only removes the pre-amplifier circuit with high power consumption and poor gain and noise performance, and the IQ dual mixer Mixer-first receiver is still plagued by large mixer loss. The mixer loss, noise, and gain of the circuit limit the minimum input power of the receiver.
  • Millimeter-wave phased array technology has been widely used. By forming receivers into arrays and beam steering, the gain of the receiver is increased and the SNR is improved, which greatly improves the overall performance of the receiver. But this also means that the chip area and power consumption increase proportionally with the size of the array [3].
  • the goal of the receiver is to receive and amplify the input signal with less power consumption and complexity, restore the information in the signal and reduce the occurrence of errors.
  • the super-regenerative receiver adds a super-regenerative circuit to the signal chain to amplify and process the signal to realize the communication function, and has the characteristics of low power consumption and simple structure. It is a good choice in high data rate mmWave receivers.
  • the super-regenerative amplifier can be realized by an injection-locked oscillator with periodic switching.
  • the oscillator By quenching the signal Quench (or called the switching signal), the oscillator is controlled to start and stop periodically, and the input signal is sampled.
  • the intermittent oscillation of the oscillator is controlled by changing the gate voltage of the tail current source M3.
  • the Super Regenerative Oscillator SILO samples phase and amplitude information during oscillation set-up. The amplitude of the oscillation grows exponentially to its steady-state level and phase information is preserved. The stronger the injected signal, the faster the oscillation will start, and vice versa.
  • the shutdown period of the super regenerative oscillator SILO In order to receive the next symbol, the shutdown period of the super regenerative oscillator SILO must be long enough to allow the oscillation signal to have enough time to decay to a negligible value, otherwise the oscillation signal of the previous period will affect the start-up of the next period, and the super regenerative oscillation
  • the SILO of the super-regenerative oscillator may be locked in the previous symbol, resulting in the degradation of the sensitivity of the super-regenerative oscillator SILO and the increase of the bit error rate.
  • the switch is realized by changing the gate voltage of the tail current source.
  • the working state of the super-regenerative receiver is divided into linear mode and saturation mode.
  • Saturation mode has more gain, but takes longer and slower to start to oscillate.
  • the input signal and the output signal are approximately linear in size, and it is easy to implement complex modulation methods, and its start-up time is short, and it is easy to achieve a higher communication rate.
  • the existing technology has the problem of small dynamic range, because the input signal power is too small, the oscillator cannot establish a sufficiently large oscillation through the signal, and when the received signal power is too large, the oscillator enters a saturated state prematurely, That is, the maximum amplitude is reached.
  • a small dynamic range limits the receiver's ability to detect amplitude information, while reducing the stability and reliability of the communication link.
  • the existing technology is susceptible to inter-symbol interference at high symbol rates, which is caused by two factors.
  • One is that the short oscillator switching time makes the residual problem more serious. This problem is exacerbated by the constraint that the regenerative oscillator SILO decreases with switching time.
  • what limits the data rate of the system to a lower level may be caused by the pre-stage circuit of the super regenerative oscillator SILO. Since the amplifier cannot achieve infinite bandwidth, it will always be affected by the problem of intersymbol interference, and the same performance It is the damped oscillation residue of the previous symbol, which is superimposed on the subsequent symbol to affect demodulation.
  • the existing technology has a small dynamic range, SILO residual problem of the super-regenerative oscillator, and intersymbol interference problem of the pre-stage circuit. These factors limit the increase of the gain and data rate of the super-regenerative receiver. Invention of a complete super-regenerative receiver for high-rate communication scenarios.
  • the purpose of the present invention is to provide a high data rate millimeter-wave super-regenerative receiver to solve the above-mentioned problems in the prior art.
  • a high data rate millimeter-wave super-regenerative receiver includes a low-noise amplifier, a super-regenerative oscillator, an IQ dual-way mixer, and two parallel intermediate frequency amplifiers that are electrically connected in sequence, and also includes a device for controlling all
  • the IQ dual-way mixer provides a quadrature coupler for quadrature local oscillator signals;
  • the input terminal of the low noise amplifier is connected to a radio frequency input signal
  • the super regenerative oscillator adopts a cross-coupled oscillation structure, and a symmetrical MOS tube switch is connected in parallel at the resonant cavity, and the symmetrical MOS tube switch is controlled by a quenching signal;
  • the quenching signal has the same symbol frequency as the input radio frequency signal.
  • the two-phase output ends of the cross-coupled oscillation structure are externally connected to the first tuning voltage through tuning capacitors.
  • the tuning capacitor is a variable capacitor.
  • the low noise amplifier shares a quenching signal with the super regenerative oscillator.
  • the low noise amplifier mainly includes four NMOS transistors, a capacitor, three inductors and an input balun;
  • One plate of the eleventh capacitor is a signal input terminal, and the other plate is connected to the second bias voltage externally through the third inductance and connected to the gate of the eighth NMOS transistor through the fourth inductance;
  • VDD passes through the input stage of the first transformer, the seventh NMOS transistor, the eighth NMOS transistor and the fifth inductor in turn, and then grounds, and the gate of the seventh NMOS transistor is connected to VDD;
  • One end of the output stage of the first transformer is a non-inverting output end, and the other end is an inverting output end, and the output stage is also externally connected with a first bias voltage;
  • the drain of the eighth NMOS transistor and the source of the ninth NMOS transistor are connected to the same point and then connected to the non-inverting output end, the source of the eighth NMOS transistor and the drain of the ninth NMOS transistor are connected to the inverting output end after the common point, and the gate is common After dots connect the quenched signal.
  • the super regenerative oscillator mainly includes six NMOS transistors, two capacitors, two inductors and two PMOS transistors;
  • the gate of the second NMOS transistor is a non-inverting input terminal, and the gate of the sixth NMOS transistor is an inverting input terminal;
  • the drain of the third NMOS transistor is a non-inverting output terminal, and the drain of the fourth NMOS transistor is an inverting output terminal;
  • the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the drain is connected to the non-inverting output terminal, and the gate is connected to VDD;
  • the source of the second NMOS transistor is grounded;
  • the source of the third NMOS transistor is grounded, the drain is connected to VDD through the first inductor, and the gate is connected to the inverting output terminal;
  • the source of the fourth NMOS transistor is grounded, the drain is connected to VDD through the second inductor, and the gate is connected to the non-inverting output terminal;
  • the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the drain is connected to the inverting output terminal, and the gate is connected to VDD;
  • the source of the sixth NMOS transistor is grounded;
  • the source of the first PMOS transistor and the drain of the second PMOS transistor are connected to the inverting output terminal after being common, the drain of the first PMOS transistor is connected to the non-inverting output terminal after the source of the second PMOS transistor is common, and the gate is common Connect the quenching signal after the dot;
  • the non-inverting output end is externally connected to the first tuning voltage through the first capacitor, and the inverting output end is externally connected to the first tuning voltage through the second capacitor.
  • the IQ dual-way mixer mainly includes ten NMOS tubes, four inductors and four resistors;
  • the common point of the drains of the tenth NMOS tube and the twelfth NMOS tube is the inverting output terminal of the I road, which is connected to VDD after passing through the first resistor;
  • the common point of the drains of the eleventh NMOS tube and the thirteenth NMOS tube is the same-phase output terminal of the I road, which is connected to VDD after passing through the second resistor;
  • the common point of the drains of the fourteenth NMOS transistor and the sixteenth NMOS transistor is the inverting output terminal of the Q channel, which is connected to VDD after passing through the third resistor.
  • the common point of the drains of the fifteenth NMOS transistor and the seventeenth NMOS transistor is the non-inverting output terminal of the Q channel, which is connected to VDD after passing through the fourth resistor;
  • the sources of the tenth NMOS transistor, the eleventh NMOS transistor, the fourteenth NMOS transistor and the fifteenth NMOS transistor are at the same point, and then pass through the sixth inductance, the eighteenth NMOS transistor and the eighth inductance, and then grounded;
  • the sources of the twelfth NMOS tube, the thirteenth NMOS tube, the sixteenth NMOS tube and the seventeenth NMOS tube are at the same point and then pass through the seventh inductance, the nineteenth NMOS tube and the ninth inductance and then grounded;
  • the gates of the tenth NMOS transistor and the thirteenth NMOS transistor are connected to the Q-path inverting local oscillator signal output end of the quadrature coupler at a common point;
  • the gates of the eleventh NMOS transistor and the twelfth NMOS transistor are connected to the Q-path in-phase local oscillator signal output end of the quadrature coupler at a common point;
  • the gates of the fourteenth NMOS transistor and the seventeenth NMOS transistor are connected to the I-way inverting local oscillator signal output end of the quadrature coupler at the same point;
  • the gates of the fifteenth NMOS transistor and the sixteenth NMOS transistor are connected to the I-channel in-phase local oscillator signal output end of the quadrature coupler at the same point.
  • the two parallel intermediate frequency amplifiers have the same structure, including two resistors, three PMOS transistors and two NMOS transistors;
  • VDD is grounded after passing through the third PMOS transistor and the twentieth NMOS transistor in sequence
  • VDD is grounded after passing through the fourth PMOS transistor and the twenty-first NMOS transistor in sequence;
  • VDD is grounded after passing through the fifth PMOS transistor and the sixth resistor in turn;
  • the gate of the third PMOS transistor and the gate of the fourth PMOS transistor are connected to the drain of the twentieth NMOS transistor;
  • the gate of the fifth PMOS transistor is connected to the drain of the twenty-first NMOS transistor; the fifth resistor is connected in parallel to both ends of the source and drain of the twenty-first NMOS transistor;
  • the gate of the twentieth NMOS transistor is a non-inverting input terminal, and the gate of the twenty-first NMOS transistor is an inverting input terminal.
  • a width ratio of the third PMOS transistor to the twentieth NMOS transistor and a width ratio of the fourth PMOS transistor to the twenty-first NMOS transistor are both 1.2:1.
  • the quadrature coupler mainly includes four PMOS transistors, four resistors, eight capacitors and an input balun;
  • the input stage of the second transformer is connected in parallel between the local oscillator input signal and the ground, and one end of the output stage is respectively connected to the drain of the sixth PMOS transistor, the upper plate of the third capacitor, the drain of the seventh PMOS transistor, and the upper plate of the fourth capacitor, The other end of the output stage is respectively connected to the drain of the eighth PMOS transistor, the upper plate of the fifth capacitor, the drain of the ninth PMOS transistor, and the upper plate of the sixth capacitor; the output stage is also externally connected to the third bias voltage;
  • the gates of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are connected to the same point, and the second tuning voltage is externally connected;
  • the source of the sixth PMOS tube is divided into three branches: connected to the lower plate of the sixth capacitor, connected to the output terminal of the anti-phase local oscillator signal of the Q channel through the seventh capacitor, and used as the output terminal of the in-phase local oscillator signal of the I channel through the seventh resistor;
  • the source pole of the seventh PMOS tube is divided into three branches: it is connected to the lower plate of the third capacitor, connected to the output terminal of the anti-phase local oscillator signal of the I route through the eighth capacitor, and used as the output terminal of the inverted local oscillator signal of the Q route through the eighth resistor;
  • the source of the eighth PMOS tube is divided into three branches: connected to the lower plate of the fourth capacitor, connected to the Q-path in-phase local oscillator signal output terminal through the ninth capacitor, and used as the I-channel anti-phase local oscillator signal output terminal through the ninth resistor;
  • the source of the ninth PMOS transistor is divided into three branches: it is connected to the lower plate of the fifth capacitor, connected to the I-channel in-phase local oscillator signal output terminal through the tenth capacitor, and used as the Q-channel in-phase local oscillator signal output terminal through the tenth resistor.
  • a kind of high data rate millimeter wave super regenerative receiver of the present invention its advantage is,
  • the super-regenerative oscillator SILO realizes fast start-up and shutdown, which effectively suppresses the thorny residual problems in the prior art invention of the super-regenerative receiver.
  • the low-noise amplifier LNA has low intersymbol interference, and can realize relatively High data rate communication.
  • the low-noise amplifier LNA can realize gain adjustment, and the receiver itself has high sensitivity, and the receiver has a large dynamic range, and is suitable for wider applications.
  • the present invention can realize high-order digital modulation
  • the present invention can prevent the spectrum leakage of the receiver
  • the invention adds a low-noise amplifier LNA before the super regenerative oscillator SILO, which not only amplifies the signal and improves the dynamic range, but also increases the isolation to prevent the oscillation signal of the oscillator from being emitted from the antenna.
  • LNA low-noise amplifier
  • the invention can adjust the frequency and DC bias of the quenching signal Quench according to the input signal, and the circuit can work at different symbol rates, and the circuit has extremely high gain for the case of low symbol rates.
  • FIG. 1 is a schematic structural diagram of a super regenerative oscillator SILO in the prior art.
  • Fig. 2 is the structural representation of a kind of high data rate millimeter wave super regenerative receiver of the present invention
  • Fig. 3 is the structural representation of low noise amplifier LNA of the present invention.
  • Fig. 4 is a structural schematic diagram of the super regenerative oscillator SILO of the present invention.
  • Fig. 5 is the structural representation of the IQ two-way mixer Mixer of the present invention.
  • Fig. 6 is the structural representation of intermediate frequency amplifier described in the present invention.
  • Fig. 7 is a schematic structural diagram of the quadrature coupler Hybrid of the present invention.
  • Fig. 8 is a transient simulation waveform diagram of a high data rate millimeter wave super-regenerative receiver according to the present invention.
  • RFin ⁇ radio frequency input signal LO ⁇ local oscillator input signal, Iout ⁇ I IF output signal, Qout ⁇ Q IF output signal, Quench ⁇ quenching signal, I+ ⁇ I in-phase local oscillator signal, I- ⁇ I inverse Phase local oscillator signal, Q+ ⁇ Q channel in-phase local oscillator signal, Q- ⁇ Q channel anti-phase local oscillator signal;
  • Vtune1 first tuning voltage
  • Vtune2 second tuning voltage
  • Vbias1-Vbias3 the first bias voltage to the third bias voltage.
  • a kind of high data rate millimeter-wave super-regenerative receiver of the present invention comprises low-noise amplifier LNA, super-regenerative oscillator SILO, IQ double-way mixer Mixer, first intermediate frequency amplifier AMP1, the first Two intermediate frequency amplifier AMP2 and quadrature coupler Hybrid.
  • the radio frequency input signal RFin is connected to the signal input terminal of the low noise amplifier LNA.
  • the two-phase output terminals of the low noise amplifier LNA are respectively connected to the two-phase input terminals of the super regenerative oscillator SILO.
  • the quadrature coupler Hybrid couples the local oscillator input signal LO to generate mutually orthogonal IQ local oscillator signals.
  • the IQ two-way mixer Mixer mixes the signal output by the super-regenerative oscillator SILO and the IQ local oscillator signal output by the quadrature coupler Hybrid to obtain an I-channel intermediate frequency signal, which is amplified and output by the first intermediate frequency amplifier AMP1 , and the intermediate frequency signal of channel Q is obtained and amplified and output by the second intermediate frequency amplifier AMP2.
  • the core modules of a high data rate millimeter-wave super-regenerative receiver in the present invention are a low-noise amplifier LNA and a super-regenerative oscillator SILO.
  • the low-pitch amplifier plays a dual role in the receiving chain. On the one hand, it performs low-noise amplification on the received signal, and on the other hand, it prevents the interference caused by the spectrum leakage of the super-regenerative oscillator SILO through its own reverse isolation.
  • the received millimeter-wave signal is amplified by the low-noise amplifier LNA, injected into the super-regenerative oscillator SILO and super-regeneratively amplified through it.
  • the external quenching signal Quench is used to quickly stop the vibration to prepare for receiving the next symbol.
  • the switching frequency of the quenching signal Quench needs to be synchronized with the symbol rate to realize correct demodulation of the received signal.
  • the dynamic range of the receiver detection signal is enhanced: 1) When the power of the received signal is low, use the high gain mode to increase the strength of the injected signal, and realize the injection and signal amplification of the super regenerative oscillator SILO Function; 2) When the power of the received signal is high, use the low gain mode to prevent the super regenerative oscillator SILO from entering the saturation state prematurely due to too high power of the injected signal, that is, reaching the maximum amplitude, resulting in the detection ability of the amplitude information of the received signal degradation. In the case of changes in transmission power or communication distance, the stability and reliability of the communication link can be maintained by adjusting the gain of the low-pitch amplifier.
  • One plate of the eleventh capacitor C11 is a signal input terminal, and the other plate is externally connected to the second bias voltage Vbias2 through the third inductor L3 and connected to the gate of the eighth NMOS transistor N08 through the fourth inductor L4.
  • VDD passes through the input stage of the first transformer B1, the seventh NMOS transistor N07, the eighth NMOS transistor N08 and the fifth inductor L5 in sequence, and then is grounded, and the gate of the seventh NMOS transistor N07 is connected to VDD.
  • One end of the output stage of the first transformer B1 is a non-inverting output end, and the other end is an inverting output end, and the output stage is also externally connected with a first bias voltage Vbias1 .
  • the drain of the eighth NMOS transistor N08 is connected to the same point as the source of the ninth NMOS transistor N09 and then connected to the non-inverting output terminal, and the source of the eighth NMOS transistor N08 and the drain of the ninth NMOS transistor N09 are connected to the same point and then connected to the inverting output terminal , connected to the quenching signal Quench after the gates are co-pointed.
  • the low noise amplifier LNA is a variable gain amplifier with wideband and low intersymbol interference.
  • the present invention adopts the way of load adjustment to realize gain adjustment and reduce intersymbol crosstalk.
  • the low noise amplifier LNA needs to reduce the problem of intersymbol interference.
  • the invention reduces the Q value of the resonant cavity by paralleling the NMOS working in the linear region, and realizes fast transient response. In order not to reduce the gain too much, the present invention reduces the intersymbol interference to a level that does not affect signal demodulation.
  • the NMOS in this linear region is controlled by the quenching signal Quench, so its equivalent resistance changes periodically: in the middle of the symbol, the equivalent resistance is large, and the output signal amplitude of the low noise amplifier LNA is large.
  • the sensitivity of the super regenerative oscillator SILO is relatively high. In the high range, the equivalent resistance is small at the front and back of the symbol, which reduces the signal residue.
  • the low-noise amplifier LNA and the super-regenerative oscillator SILO share the quenching signal Quench. This method further reduces the influence of intersymbol interference without increasing the complexity. By adjusting the DC bias of the NMOS quenching signal Quench in this linear region, the effect of gain adjustment can be realized.
  • the cascode structure can provide higher isolation, which is composed of input matching network, source degeneration inductor, cascode transistor, transformer, and symmetrical NMOS switch.
  • the source degenerate inductance and the input matching network provide broadband impedance matching, and the cascode transistor needs to select a smaller gate finger width and an appropriate current density to reduce noise.
  • the transformer acts as the load for the cascode.
  • the single-ended signal is converted to a differential signal and the bandwidth of the frequency response is improved.
  • the NMOS symmetrical switch connected in parallel to the secondary coil of the transformer plays the role of adjusting the gain and reducing the crosstalk between symbols. Its gate is the control terminal, controlled by the quenching signal Quench, and has a separate bias.
  • the bias of the control terminal When the input signal is small, the bias of the control terminal is small, the equivalent resistance of the NMOS symmetrical switch is large, and the circuit has a large gain. In order to reduce the intersymbol interference, the circuit bias cannot be too small, and its minimum value will decrease as the symbol rate decreases.
  • the bias of the control terminal When the input signal is large, the bias of the control terminal is large, the equivalent resistance of the NMOS symmetrical switch is small, and the circuit gain decreases. Prevent the downstream circuit from being saturated.
  • the equivalent resistance of the NMOS symmetrical switch is time-varying in a symbol period, and the input signal voltage amplitude is relatively large in the middle of the symbol, which reduces the symbol interval of the low-noise amplifier LNA. crosstalk.
  • the super-regenerative oscillator SILO In order to prevent the super regenerative oscillator SILO from entering saturation due to an excessively large input signal, it is necessary to reduce the gain of the low-noise amplifier LNA when the input signal is large, which can increase the upper limit of the input signal power that the receiver can receive and improve the dynamic range of the receiver.
  • the super-regenerative oscillator SILO since the super-regenerative oscillator SILO has greater gain when the Quench frequency of the low-quenching signal is the same as the symbol rate, the super-regenerative receiver is more likely to enter saturation at a low symbol rate, and it is more necessary to improve the dynamic range approach.
  • the dynamic range of the receiver can be improved under different symbol rates, especially in the relatively low working state of the symbol rate.
  • the low noise amplifier LNA gain is realized by adjusting the quenching signal Quench DC bias at the low noise amplifier LNA.
  • the relationship between the bias and the input signal is that when the input signal is small, the quenching signal Quench bias is small, NMOS symmetrical switch, etc.
  • the larger the effective resistance the greater the gain of the circuit.
  • the circuit bias cannot be too small, and its minimum value will decrease as the symbol rate decreases.
  • the quenching signal Quench bias is large, the equivalent resistance of the NMOS symmetrical switch is small, and the circuit gain is reduced to prevent the subsequent stage circuit from being saturated.
  • the gate of the second NMOS transistor N02 is a non-inverting input terminal, and the gate of the sixth NMOS transistor N06 is an inverting input terminal.
  • the drain of the third NMOS transistor N03 is a non-inverting output terminal, and the drain of the fourth NMOS transistor N04 is an inverting output terminal.
  • the source of the first NMOS transistor N01 is connected to the drain of the second NMOS transistor N02 , the drain is connected to the non-inverting output terminal, and the gate is connected to VDD.
  • the source of the second NMOS transistor N02 is grounded.
  • the source of the third NMOS transistor N03 is grounded, the drain is connected to VDD through the first inductor L1 , and the gate is connected to the inverting output terminal.
  • the source of the fourth NMOS transistor N04 is grounded, the drain is connected to VDD through the second inductor L2, and the gate is connected to the non-inverting output terminal.
  • the source of the fifth NMOS transistor N05 is connected to the drain of the sixth NMOS transistor N06 , the drain is connected to the inverting output terminal, and the gate is connected to VDD.
  • the source of the sixth NMOS transistor N06 is grounded.
  • the source of the first PMOS transistor P01 and the drain of the second PMOS transistor P02 are connected to the inverting output terminal, and the drain of the first PMOS transistor P01 and the source of the second PMOS transistor P02 are connected to the non-inverting output terminal. , connected to the quenching signal Quench after the gates are co-pointed.
  • the non-inverting output end is externally connected to the first tuning voltage Vtune1 through the first capacitor C01, and the inverting output end is externally connected to the first tuning voltage Vtune1 through the second capacitor C02.
  • the super-regenerative oscillator SILO is the core of the super-regenerative receiver. Different from the prior art, the super-regenerative oscillator SILO of the present invention adopts a cross-coupling structure and no longer uses tail current control, but is connected in parallel between the oscillator output nodes.
  • the MOS switch composed of symmetrical PMOS controlled by the quenching signal Quench avoids the problem that the parasitic capacitance between the gate of the tail current source transistor and the ground must be charged and discharged every time the super regenerative receiver turns on and off the oscillator . This improvement can increase the super regenerative oscillator SILO start-up and stop speed to reduce the impact of residual phenomena, so that higher switching rates can be achieved.
  • a signal is injected into the resonant cavity by a pair of differential cascode circuits, combined with a MOS switch controlled by the quenching signal Quench, to realize super regenerative amplification.
  • a variable capacitor is connected in parallel between the oscillator output nodes.
  • the common point of the drains of the tenth NMOS transistor N10 and the twelfth NMOS transistor N12 is an I-channel inverting output terminal, which is connected to VDD after passing through the first resistor R01.
  • the common point of the drains of the eleventh NMOS transistor N11 and the thirteenth NMOS transistor N13 is the I non-inverting output terminal, which is connected to VDD after passing through the second resistor R02.
  • the common point of the drains of the fourteenth NMOS transistor N14 and the sixteenth NMOS transistor N16 is the inverting output terminal of the Q channel, which is connected to VDD after passing through the third resistor R03,
  • the common point of the drains of the fifteenth NMOS transistor N15 and the seventeenth NMOS transistor N17 is the non-inverting output terminal of the Q channel, which is connected to VDD after passing through the fourth resistor R04.
  • the sources of the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the fourteenth NMOS transistor N14, and the fifteenth NMOS transistor N15 are at the same point, they pass through the sixth inductance L6, the eighteenth NMOS transistor N18, and the eighth inductance L8 in sequence. back to ground.
  • the sources of the twelfth NMOS transistor N12, the thirteenth NMOS transistor N13, the sixteenth NMOS transistor N16, and the seventeenth NMOS transistor N17 pass through the seventh inductance L7, the nineteenth NMOS transistor N19, and the ninth inductance in sequence. Ground after L9.
  • the gates of the tenth NMOS transistor N10 and the thirteenth NMOS transistor N13 are connected to the Q-path inverting local oscillator signal output end of the quadrature coupler Hybrid at a common point.
  • the gates of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 are connected to the Q-channel in-phase local oscillator signal output end of the quadrature coupler Hybrid at a common point.
  • the gates of the fourteenth NMOS transistor N14 and the seventeenth NMOS transistor N17 are connected at a common point to the I-channel inverting local oscillator signal output end of the quadrature coupler Hybrid.
  • the gates of the fifteenth NMOS transistor N15 and the sixteenth NMOS transistor N16 are connected to the I-channel in-phase local oscillator signal output end of the quadrature coupler Hybrid at a common point.
  • the IQ double-way mixer Mixer is an IQ double-balanced mixer sharing a transconductor, and the gain and linearity are improved by adding a peaking inductance between the transconductor and the switch tube and adding a source degeneration inductance at the source of the two transconductors, In order to realize the demodulation of advanced digital modulation signal.
  • the load of the IQ dual mixer Mixer is a resistive load, which helps to achieve higher linearity and bandwidth at lower supply voltages.
  • the quadrature local oscillator signal of the IQ two-way mixer is generated by the quadrature coupler Hybrid. The frequency of the local oscillator is consistent with the frequency of the RF signal. After mixing with the RF signal amplified by the super regenerative oscillator SILO, a differential zero-IF signal is generated.
  • the structure of the first intermediate frequency amplifier AMP1 and the second intermediate frequency amplifier AMP2 is the same, wherein the structure of any intermediate frequency amplifier is as shown in Figure 6:
  • VDD is grounded after passing through the third PMOS transistor P03 and the twentieth NMOS transistor N20 in sequence.
  • VDD is grounded after passing through the fourth PMOS transistor P04 and the twenty-first NMOS transistor N21 in sequence.
  • VDD is grounded after passing through the fifth PMOS transistor P05 and the sixth resistor R06 in sequence.
  • the gates of the third PMOS transistor P03 and the fourth PMOS transistor P04 are connected to the drain of the twentieth NMOS transistor N20 after being connected to the same point.
  • the gate of the fifth PMOS transistor P05 is connected to the drain of the twenty-first NMOS transistor N21.
  • the fifth resistor R05 is connected in parallel to the source and drain of the twenty-first NMOS transistor N21.
  • the gate of the twentieth NMOS transistor N20 is a non-inverting input terminal, and the gate of the twenty-first NMOS transistor N21 is an inverting input terminal.
  • the IF amplifier converts the differential signal to a single-ended signal using an active current mirror circuit.
  • the input stage of the second transformer B2 is connected in parallel between the local oscillator input signal and the ground, and one end of the output stage is respectively connected to the drain of the sixth PMOS transistor P06, the upper plate of the third capacitor C03, the drain of the seventh PMOS transistor P07, and the fourth capacitor
  • the upper plate of C04, and the other end of the output stage are respectively connected to the drain of the eighth PMOS transistor P08, the upper plate of the fifth capacitor C05, the drain of the ninth PMOS transistor P09, and the upper plate of the sixth capacitor C06.
  • the output stage is also externally connected with a third bias voltage Vbias3.
  • the gates of the sixth PMOS transistor P06 , the seventh PMOS transistor P07 , the eighth PMOS transistor P08 and the ninth PMOS transistor P09 are connected to the same point, and then the second tuning voltage Vtune2 is externally connected.
  • the source of the sixth PMOS transistor P06 is divided into three branches: connected to the lower plate of the sixth capacitor C06, connected to the output terminal of the inverting local oscillator signal of the Q channel through the seventh capacitor C07, and output as the in-phase local oscillator signal of the I channel through the seventh resistor R07 end.
  • the source of the seventh PMOS transistor P07 is divided into three branches: connected to the lower plate of the third capacitor C03, connected to the output terminal of the I-channel inverting local oscillator signal through the eighth capacitor C08, and used as the Q-channel inverting local oscillator signal through the eighth resistor R08 output.
  • the source of the eighth PMOS transistor P08 is divided into three branches: connected to the lower plate of the fourth capacitor C04, connected to the output terminal of the same-phase local oscillator signal of the Q channel through the ninth capacitor C09, and output as an anti-phase local oscillator signal of the I channel through the ninth resistor R09 end.
  • the source of the ninth PMOS transistor P09 is divided into three branches: connected to the lower plate of the fifth capacitor C05, connected to the I-channel in-phase local oscillator signal output terminal through the tenth capacitor C10, and used as the Q-channel in-phase local oscillator signal output terminal through the tenth resistor R10 .
  • the quadrature coupler Hybrid is implemented by a resistor-capacitor polyphase filter, and its equivalent resistance is controlled by the bias of the tail current source M3, thereby adjusting the phase difference of the coupler. Under proper bias, the coupler can generate IQ two-way local oscillator signals with the same frequency as the input local oscillator, close in magnitude and quadrature.
  • the zero-IF quadrature demodulation invention is applied to a super-regenerative receiver, and the simple model of the time-domain relationship of each part of the signal is as follows:
  • ENV(t) and Gain SR represent unit signal envelope and super regenerative gain respectively. It should be noted that Gain SR can replace the circuit gain only when the input signal is small, and the super regenerative circuit works in linear mode at this time.
  • a LO is the amplitude of the local oscillator signal.
  • the signal envelope transformation represented by ENV(t) is slow, and the intermediate frequency signal output by the mixer can be obtained under the quasi-static approximation:
  • V IF_I ENV(t)*Gain SR *Gain mixer *I(t)
  • V IF_Q ENV(t)*Gain SR *Gain mixer *Q(t)
  • Gain mixer is the mixer gain.
  • the above two equations illustrate that the output waveform of the super-regenerative receiver of the present invention is the product of the original IQ signal and the SILO envelope of the super-regenerative oscillator.
  • the transient waveform of the system simulation is shown in Figure 8, where the curves from top to bottom correspond to: RF input signal RFin, low noise amplifier LNA output signal, super regenerative oscillator SILO output signal, local oscillator input signal, I road baseband signal , I-channel IF output signal, Q-channel baseband signal, Q-channel IF output signal.
  • the traditional super regenerative oscillator SILO circuit is shown in Figure 1. It consists of a negative resistance transistor, a direct injection transistor, an inductor and a tail current source M3, which is equivalent to adding a tail current source M3 to control the start-up of the conventional LC oscillator. and stop the oscillation, and inject a signal into the resonator at the signal output port.
  • the signal controlling the tail current source M3 can be a sine wave or other waveforms, which need to be synchronized with the symbol rate.
  • the super regenerative oscillator SILO is a dynamic circuit, the oscillation waveform it establishes is related to the initial state of the circuit, and the phase and amplitude of the injected signal play a key role.
  • the oscillator can work in an injection-locked state, that is, the oscillation frequency is consistent with the frequency of the injected signal.
  • the oscillator output signal maintains a constant phase difference with the input signal, which is a fundamental condition for super-regenerative amplifiers to allow correlated modulation and demodulation.
  • the oscillation amplitude of the oscillator is related to the size of the injected signal.
  • the traditional super-regenerative oscillator SILO is not suitable for super-regenerative receivers with high data rates. The main reason is that it cannot provide a small enough impedance to stop the oscillation quickly, and the time constant is relatively large. If the symbol rate is high, it will be seriously affected by the residual problem, that is, the residual signal of the previous symbol is superimposed on the subsequent symbol, and the IF output shows intersymbol interference, and the circuit cannot work normally.
  • the super regenerative oscillator SILO circuit of the present invention is shown in Figure 4, wherein the first NMOS transistor N01 is combined with the second NMOS transistor N02, and the fifth NMOS transistor N05 is combined with the sixth NMOS transistor N06 to form an injection cascode
  • the transistors, the third NMOS transistor N03 and the fourth NMOS transistor N04 are negative resistance transistors of the oscillator respectively, and the first PMOS transistor P01 and the second PMOS transistor P02 form a PMOS symmetrical switch.
  • the radio frequency signal amplified by the low noise amplifier LNA is connected to the injected cascode, the radio frequency signal is converted into a current signal and injected into the resonant cavity. Compared with common source, cascode further improves isolation and improves gain.
  • the circuit no longer uses the tail current switch to control the start-up and extinguishment of the oscillator, but connects the PMOS symmetrical switch in parallel at the resonant cavity of the cross-coupled oscillator.
  • the quenching signal Quench is at a high voltage, its equivalent resistance is relatively large, and the circuit starts to oscillate to amplify the injected radio frequency signal.
  • the quenching signal Quench is at a low voltage, its equivalent resistance is small, the circuit quickly stops oscillating, the signal attenuates, and it is ready to amplify the next symbol signal.
  • the super regenerative oscillator SILO of the present invention adopts a PMOS symmetrical switch, and the low noise amplifier LNA adopts an NMOS symmetrical switch, so that the high sensitivity range of the super regenerative oscillator SILO will appear when the output swing of the low noise amplifier LNA is relatively large In the range.
  • the use of PMOS symmetrical switches greatly reduces the equivalent parallel impedance of the resonator when the circuit stops oscillating, making the signal attenuate quickly.
  • the super regenerative oscillator SILO can adjust the center frequency of the oscillator by adjusting the control terminal voltages of the first capacitor C01 and the second capacitor C02.
  • the eighteenth NMOS transistor N18 and the nineteenth NMOS transistor N19 are transconductors
  • the tenth NMOS transistor N10 to the seventeenth NMOS transistor N17 are switching transistors
  • the sixth inductance L6 and the seventh inductance L7 is a peaking inductance
  • the eighth inductance L8 and the ninth inductance L9 are source degeneration inductances
  • the first resistor R01 to the fourth resistor R04 are load resistors.
  • the transconductor works in the saturation region and converts the input signal voltage into a current signal.
  • the local oscillator signal modulates the current signal through the switch tube to generate an intermediate frequency current.
  • the load resistor converts the intermediate frequency current into an intermediate frequency voltage.
  • the present invention By sharing the transconductor, the present invention only needs one IQ two-way Mixer to realize the generation of IQ two-way intermediate frequency signals. Compared with using an independent IQ two-way mixer, the present invention reduces power consumption.
  • the introduced peaking inductance can resonate with the parasitic capacitance in the radio frequency band to improve the circuit gain and noise performance, and the introduction of the source degeneration inductance can improve the linearity of the mixer.
  • PMOS is used as the mixer load at a lower power supply voltage
  • a larger transistor can make the mixer work normally, and a larger capacitor will reduce the IF bandwidth.
  • the invention adopts the resistance as the load, avoids the reduction of the bandwidth while realizing the large gain, and improves the reliability of the circuit under the low power supply voltage.
  • the intermediate frequency amplifier is composed of an active current mirror and a PMOS common source amplifier.
  • the active current mirror converts the differential signal into a single-ended signal.
  • no DC blocking capacitor is required to achieve zero-IF signal amplification.
  • the bias of the gate of the PMOS common-source amplifier in the intermediate frequency amplifier is provided by the output of the active current mirror, which requires selecting a suitable PMOS size in the active current mirror circuit.
  • a relatively ideal Ratio The ratio of the width of the P-type transistor to the N-type transistor of the active current mirror is 1.2:1.
  • the third PMOS transistor P03, the fourth PMOS transistor P04, the twentieth NMOS transistor N20 and the twenty-first NMOS transistor N21 together form the active current mirror, and the fifth PMOS transistor P05 is a PMOS common source amplifier.
  • the quadrature coupler Hybrid is shown in Figure 7, which consists of an input balun and a polyphase filter.
  • the local oscillator signal is input from the input terminal of the balun, which is converted into a differential local oscillator signal.
  • the output terminal of the input balun is connected to the input terminal of the polyphase filter, and the polyphase filter is composed of two stages of RC filters, wherein the second stage adopts fixed resistance and capacitance.
  • the first stage uses NMOS working in the linear region to replace the resistor, and uses the characteristics of its equivalent resistance to change with the gate voltage to adjust its resistance value, which plays a role in adjusting the operating frequency of the polyphase filter.
  • the two-stage polyphase filter can reduce the amplitude and phase mismatch of the quadrature local oscillator signal.

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Abstract

本发明公开了一种高数据率的毫米波超再生接收机，涉及新一代信息技术的毫米波收发技术。针对现有技术中存在动态范围小，超再生振荡器SILO残留、前级电路码间串扰等问题提出本方案。采用低噪声放大器直连射频输入信号；超再生振荡器采用交叉耦合振荡结构，且在谐振腔处并联对称MOS管开关，对称MOS管开关由淬灭信号控制实现。优点在于，能够工作在高码元速率的情况；具有较大的动态范围；能够实现高阶数字调制；防止接收机的频谱泄露；相对简单且具有较强的灵活性。

Description

一种高数据率的毫米波超再生接收机 技术领域
本发明涉及新一代信息技术的毫米波收发技术，尤其涉及一种高数据率的毫米波超再生接收机。
背景技术
随着对高数据率无线通信需求的增长，以及毫米波频段宽带电路，如宽带低噪声放大器LNA、PA的发展，人们越来越关注具有中等频谱效率的毫米波频段超高速通信。近年来，有许多CMOS工艺高数据率毫米波接收机被提出。然而，高数据率的实现需要更高的功耗，因为毫米波频段单级放大器的增益十分有限，需要多级放大器级联才能达到足够增益，而宽带毫米波放大器的问题更加严重，因为其为实现超宽带牺牲了部分增益。这些因素也使得设计变得复杂，此外，毫米波频段较大的传播损耗使得这些系统变得低效，实现更高的灵敏度可以一定程度上解决这一问题。
工作在200GHz以上的接收机受限于上述的低增益困扰，不得不将下变频混频器作为接收链路的第一个有源电路，以降低后级电路的工作频率，这种接收机称为IQ双路混频器Mixer-first接收机[1],[2]。然而这种架构只是去掉了功耗较高、增益和噪声性能较差的前级放大电路，IQ双路混频器Mixer-first接收机仍受到较大的混频器损耗的困扰。电路的混频器损耗、噪声，增益限制了接收机的最小输入功率。
毫米波相控阵技术已经被广泛采用，其通过将接收机组成阵列以及波束控制，增大了接收机的增益并改善SNR，较大提高接收机的整体性能。但这也意味着以阵列规模成比例增加的芯片面积与功耗[3]。
接收机的目标是以更小的功耗、复杂度接收与放大输入信号并还原出信号中的信息和减少错误的发生，超再生放大器是一种利用振荡电路起振时的瞬态特性实现放大功能来处理信号的电路。超再生接收机在信号链路中加入超再生电路来放大与处理信号，实现通信功能，具有低功耗、结构简单的特点。在高数据率毫米波接收机中，其不失为一种好的选择。
如图1所示，超再生放大器可采用周期开关的注入锁定振荡器实现，通过淬灭信号Quench(或称为开关信号)，控制振荡器周期起振与关闭，对输入信号进行采样。通过改变尾电流源M3的栅极电压控制振荡器的间歇性振荡。作为动态电路，超再生 振荡器SILO在振荡建立过程中对相位和幅度信息进行采样。振荡幅度以指数形式增长到其稳态水平，并保留相位信息。注入的信号越强，起振越快，反之则越慢。为了接收下一个符号，超再生振荡器SILO的关闭周期必须足够长，以使振荡信号有足够的时间衰减到可以忽略的值，否则前周期的振荡信号影响下一周期的起振，超再生振荡器SILO的可能锁定在前一个码元，从而造成超再生振荡器SILO灵敏度的退化及误码率的提升。图2所示的结构中，开关是通过改变尾电流源的栅极电压来实现的。这种方式带来的问题是，每次打开和关闭振荡器时，尾电流源晶体管的栅极与地之间的寄生电容必须完成充电和放电，此过程所需的时间限制了超再生振荡器SILO的通断速度[4]。
依据超再生电路的输入信号与输出信号是否维持线性特征将超再生接收机的工作状态分为线性模式与饱和模式。饱和模式具有更大的增益，但起振所需时间长，速度较慢。线性模式输入信号与输出信号大小近似为线性关系，易于实现复杂的调制方式，且其起振时间短，易实现更高的通信速率。
现有超再生接收机并不适用于高数据率通信场景。目前的发明多采用检波器检测信号包络，此种结构仅适用于幅度调制，如OOK。虽然这种电路结构简单，但频谱利用效率低，难以实现高数据率通信，常应用于医疗、WSN等低功耗场景[5],[6]。采用超再生振荡器SILO级联可以实现更高灵敏度与更大增益[7]，但依然无法应用于数据通信场景，此电路存在控制信号复杂、难以实现相位还原的问题。此外现有技术存在动态范围(Dynamic Range)小的问题，因为输入信号功率过小时，振荡器无法通过信号建立足够大的振荡，而接收信号功率过大时，振荡器过早的进入饱和状态，即达到最大振幅。较小的动态范围限制了接收机的幅度信息检测能力，同时降低了通信链路的稳定性和可靠性。
此外，现有技术在高码元速率的情况下易受到码间串扰问题的影响，这是由两方面因素带来的，一是振荡器开关时间变短使得残留问题变得更加严重，在超再生振荡器SILO随开关时间减小的限制下，这一问题更加严重。然而，将系统的数据率限制在更低水平的可能是超再生振荡器SILO的前级电路引起的，由于放大器不可能实现无穷大的带宽，其总是会受到码间串扰问题的影响，同样表现为前一码元的减幅振荡残留，叠加在后续码元上影响解调。
综上所述，现有技术存在动态范围小，超再生振荡器SILO残留问题、前级电路码间串扰问题，这些因素限制了超再生接收机增益与数据率的提高，目前缺少适用于 高数据率通信场景的完整超再生接收机发明。
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Figure PCTCN2021142318-appb-000001
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发明内容
本发明目的在于提供一种高数据率的毫米波超再生接收机，以解决上述现有技术存在的问题。
本发明所述一种高数据率的毫米波超再生接收机，包括依次电性连接的低噪声放大器、超再生振荡器、IQ双路混频器和两并行中频放大器，还包括用于对所述IQ双路混频器提供正交本振信号的正交耦合器；
所述低噪声放大器输入端连接射频输入信号；
所述超再生振荡器采用交叉耦合振荡结构，且在谐振腔处并联对称MOS管开关，所述对称MOS管开关由淬灭信号控制；
所述淬灭信号与输入的射频信号码元频率相同。
所述交叉耦合振荡结构的两相输出端分别通过调谐电容外接第一调谐电压。
调谐电容为可变电容。
所述低噪声放大器与所述超再生振荡器共用一淬灭信号。
所述低噪声放大器主要包括四NMOS管、一电容、三电感和一输入巴伦；
第十一电容的一极板为信号输入端，另一极板分别通过第三电感外接第二偏置电压和通过第四电感连接第八NMOS管的栅极；
VDD依次通过第一变压器的输入级、第七NMOS管、第八NMOS管和第五电感后接地，第七NMOS管的栅极连接VDD；
第一变压器的输出级一端为正相输出端，另一端为反相输出端，输出级还外接第一偏置电压；
第八NMOS管的漏极与第九NMOS管的源极共点后连接同相输出端，第八NMOS管的源极与第九NMOS管的漏极共点后连接反相输出端，栅极共点后连接所述淬灭信号。
所述超再生振荡器主要包括六NMOS管、两电容、两电感和两PMOS管；
第二NMOS管的栅极为同相输入端，第六NMOS管的栅极为反相输入端；
第三NMOS管的漏极为同相输出端，第四NMOS管的漏极为反相输出端；
第一NMOS管的源极连接第二NMOS管漏极，漏极连接同相输出端，栅极连接VDD；
第二NMOS管的源极接地；
第三NMOS管的源极接地、漏极经过第一电感连接VDD、栅极连接反相输出端；
第四NMOS管的源极接地、漏极经过第二电感连接VDD、栅极连接同相输出端；
第五NMOS管的源极连接第六NMOS管漏极，漏极连接反相输出端，栅极连接VDD；
第六NMOS管的源极接地；
第一PMOS管的源极和第二PMOS管的漏极共点后连接反相输出端，第一PMOS管的漏极和第二PMOS管的源极共点后连接同相输出端，栅极共点后连接所述淬灭信号；
同相输出端经过第一电容外接第一调谐电压，反相输出端经过第二电容外接第一调谐电压。
所述IQ双路混频器主要包括十NMOS管、四电感和四电阻；
第十NMOS管和第十二NMOS管的漏极共点为I路反相输出端，经过第一电阻后连接VDD；
第十一NMOS管和第十三NMOS管的漏极共点为I路同相输出端，经过第二电阻后连接VDD；
第十四NMOS管和第十六NMOS管的漏极共点为Q路反相输出端，经过第三电阻后连接VDD，
第十五NMOS管和第十七NMOS管的漏极共点为Q路同相输出端，经过第四电阻后连接VDD；
第十NMOS管、第十一NMOS管、第十四NMOS管和第十五NMOS管的源极共点后依次经过第六电感、第十八NMOS管和第八电感后接地；
第十二NMOS管、第十三NMOS管、第十六NMOS管和第十七NMOS管的源极共点后依次经过第七电感、第十九NMOS管和第九电感后接地；
第十NMOS管和第十三NMOS管的栅极共点连接正交耦合器的Q路反相本振信号输出端；
第十一NMOS管和第十二NMOS管的栅极共点连接正交耦合器的Q路同相本振信号输出端；
第十四NMOS管和第十七NMOS管的栅极共点连接正交耦合器的I路反相本振信号输出端；
第十五NMOS管和第十六NMOS管的栅极共点连接正交耦合器的I路同相本振信号输出端。
所述两并行中频放大器结构相同，分别包括两电阻、三PMOS管和两NMOS管；
VDD依次经过第三PMOS管、第二十NMOS管后接地；
VDD依次经过第四PMOS管、第二十一NMOS管后接地；
VDD依次经过第五PMOS管、第六电阻后接地；
第三PMOS管和第四PMOS管栅极共点后连接第二十NMOS管的漏极；
第五PMOS管的栅极连接第二十一NMOS管的漏极；第五电阻并联在第二十一NMOS管的源漏两端；
第二十NMOS管的栅极为同相输入端，第二十一NMOS管的栅极为反相输入端。
第三PMOS管与第二十NMOS管的宽度比例以及第四PMOS管与第二十一NMOS管的宽度比例均为1.2:1。
所述正交耦合器主要包括四PMOS管、四电阻、八电容和一输入巴伦；
第二变压器的输入级并联在本振输入信号与地之间，输出级一端分别连接第六PMOS管漏极、第三电容上极板、第七PMOS管漏极和第四电容上极板，输出级另一端分别连接第八PMOS管漏极、第五电容上极板、第九PMOS管漏极和第六电容上极板；输出级还外接第三偏置电压；
第六PMOS管、第七PMOS管、第八PMOS管和第九PMOS管的栅极共点后外接第二调谐电压；
第六PMOS管源极分三条支路：连接第六电容下极板，经过第七电容连接Q路反相本振信号输出端，经过第七电阻作为I路同相本振信号输出端；
第七PMOS管源极分三条支路：连接第三电容下极板，经过第八电容连接I路反相本振信号输出端，经过第八电阻作为Q路反相本振信号输出端；
第八PMOS管源极分三条支路：连接第四电容下极板，经过第九电容连接Q路同相本振信号输出端，经过第九电阻作为I路反相本振信号输出端；
第九PMOS管源极分三条支路：连接第五电容下极板，经过第十电容连接I路同相本振信号输出端，经过第十电阻作为Q路同相本振信号输出端。
本发明所述一种高数据率的毫米波超再生接收机，其优点在于，
(1)能够工作在高码元速率的情况
所述超再生振荡器SILO实现了快速起振与关闭，有效抑制了超再生接收机已有 技术发明中棘手的残留问题，同时所述低噪声放大器LNA有较低的码间串扰，能够实现较高数据率的通信。
(2)具有较大的动态范围
所述低噪声放大器LNA可实现增益调节，且接收机本身具有较高灵敏度，接收机具有较大的动态范围，适用于更广泛的应用。
(3)本发明能够实现高阶数字调制
可以实现对幅度与相位信息的精确采样，同时具有较高的灵敏度，可实现QPSK、QAM等高阶数字调制，对高阶数字调制的支持也提高了本发明的通信速率。
(4)本发明能够防止接收机的频谱泄露
本发明在超再生振荡器SILO前加入了低噪声放大器LNA，不仅起到放大信号与提高动态范围的作用，还增大了隔离度，防止振荡器的振荡信号从天线发射出去。
(5)本发明结构相对简单且具有较强的灵活性
本发明可根据输入信号对淬灭信号Quench的频率、直流偏置进行调节，电路可以在不同的码元速率下工作，对于低码元速率的情况，电路具有极高增益。
附图说明
图1是现有技术中超再生振荡器SILO的结构示意图。
图2是本发明所述一种高数据率的毫米波超再生接收机的结构示意图；
图3是本发明所述低噪声放大器LNA的结构示意图；
图4是本发明所述超再生振荡器SILO的结构示意图；
图5是本发明所述IQ双路混频器Mixer的结构示意图；
图6是本发明所述中频放大器的结构示意图；
图7是本发明所述正交耦合器Hybrid的结构示意图。
图8是本发明所述一种高数据率的毫米波超再生接收机的瞬态仿真波形图。
附图标记：
RFin～射频输入信号、LO～本振输入信号、Iout～I路中频输出信号、Qout～Q路中频输出信号、Quench～淬灭信号、I+～I路同相本振信号、I-～I路反相本振信号、Q+～Q路同相本振信号、Q-～Q路反相本振信号；
LNA～低噪声放大器、SILO～超再生振荡器、Mixer～IQ双路混频器、Hybrid～正交耦合器、AMP1～第一中频放大器、AMP2～第二中频放大器；
R01-R10～第一电阻至第十电阻；
L1-L9～第一电感至第九电感；
C01-C11～第一电容至第十一电容；
N01-N21～第一NMOS管至第二十一NMOS管；
P01-P09～第一PMOS管至第九PMOS管；
B1～第一变压器、B2、第二变压器；
Vtune1～第一调谐电压、Vtune2～第二调谐电压；
Vbias1-Vbias3～第一偏置电压至第三偏置电压。
具体实施方式
如图2所示，本发明所述一种高数据率的毫米波超再生接收机，包括低噪声放大器LNA、超再生振荡器SILO、IQ双路混频器Mixer、第一中频放大器AMP1、第二中频放大器AMP2和正交耦合器Hybrid。
射频输入信号RFin连接至低噪声放大器LNA的信号输入端。低噪声放大器LNA的两相输出端分别连接至超再生振荡器SILO的两相输入端。所述正交耦合器Hybrid将本振输入信号LO耦合生成互相正交的IQ本振信号。所述的IQ双路混频器Mixer将超再生振荡器SILO输出的信号和正交耦合器Hybrid输出的IQ本振信号进行混频，得到I路中频信号并经第一中频放大器AMP1进行放大输出，以及得到Q路中频信号并经第二中频放大器AMP2进行放大输出。
本发明所述一种高数据率的毫米波超再生接收机核心模块是低噪声放大器LNA和超再生振荡器SILO。其中低啋声放大器在接收链路中发挥双重作用，一方面对接收的信号进行低噪声放大，另一方面通过自身的反向隔离作用防止超再生振荡器SILO频谱泄漏产生干扰。接收的毫米波信号经过低噪声放大器LNA的放大后，注入到超再生振荡器SILO并通过其进行超再生放大。在超再生振荡器SILO达到最大振幅前，通过外部淬灭信号Quench使其快速停振，为接收下一个码元做准备。淬灭信号Quench的开关频率需与码元速率同步，以实现对接收信号的正确解调。通过调节低啋声放大器的增益，增强接收机检测信号的动态范围：1)在接收信号功率较低时，使用高增益模式，提升注入信号的强度，实现超再生振荡器SILO的注入与信号放大功能；2)在接收信号功率较高时，使用低增益模式，避免因注入信号功率太高致使超再生振荡器SILO过早进入饱和状态，即达到最大振幅，导致对接收信号幅度信息检测能力的退化。在发射功率或通信距离发生变化的情况下，通过调节低啋声放大器增益，保持通信链路的稳定性与可靠性。
a、所述的低噪声放大器LNA结构如图3所示：
主要包括四NMOS管、一电容、三电感和一输入巴伦。
第十一电容C11的一极板为信号输入端，另一极板分别通过第三电感L3外接第二偏置电压Vbias2和通过第四电感L4连接第八NMOS管N08的栅极。
VDD依次通过第一变压器B1的输入级、第七NMOS管N07、第八NMOS管N08和第五电感L5后接地，第七NMOS管N07的栅极连接VDD。
第一变压器B1的输出级一端为正相输出端，另一端为反相输出端，输出级还外接第一偏置电压Vbias1。
第八NMOS管N08的漏极与第九NMOS管N09的源极共点后连接同相输出端，第八NMOS管N08的源极与第九NMOS管N09的漏极共点后连接反相输出端，栅极共点后连接所述淬灭信号Quench。
所述低噪声放大器LNA是一种宽带、低码间串扰的可变增益放大器。本发明采用负载调节的方式实现增益调节与降低码间串扰。要让接收机能够实现高码元速率通信，所述低噪声放大器LNA需要减小码间串扰问题。本发明通过并联工作在线性区的NMOS来降低谐振腔Q值，实现快速的瞬态响应。为了不过多降低增益，本发明将码间串扰减小到不影响信号解调的程度。此线性区NMOS由淬灭信号Quench控制，因此其等效电阻是周期变化的：在码元中部，等效电阻大，低噪声放大器LNA输出信号幅度大，此时为超再生振荡器SILO灵敏度较高的区间，在码元前部与后部，等效电阻小，减小了信号残留。低噪声放大器LNA与超再生振荡器SILO共用淬灭信号Quench，此方法在不增加复杂度的情况下进一步降低了码间串扰的影响。通过调节此线性区NMOS淬灭信号Quench的直流偏置，可实现增益调节的效果。
采用共源共栅结构，可提供更高的隔离度，其由输入匹配网络、源退化电感、共源共栅极晶体管、变压器、对称NMOS开关组成。源退化电感与输入匹配网络提供了宽带阻抗匹配，共源共栅极晶体管需要选择较小的栅指宽度和合适的电流密度以减小噪声。变压器作为共源共栅极的负载。同时将单端信号转换为差分信号并提高了频率响应的带宽。并联在变压器次级线圈的NMOS对称开关起到调节增益以及减小码间串扰的作用，其栅极为控制端，由淬灭信号Quench控制，并有单独的偏置。当输入信号较小时，控制端偏置较小，NMOS对称开关等效电阻较大，电路具有较大的增益。为了减小码间串扰，电路偏置不能过小，其最小值将随着码元速率减小而减小。 当输入信号较大时，控制端偏置较大，NMOS对称开关等效电阻较小，电路增益减小。防止后级电路饱和。受到与码元同步的淬灭信号Quench控制，NMOS对称开关等效电阻在一码元周期里是时变的，在码元中部输入信号电压幅度较大，这降低了低噪声放大器LNA的码间串扰。
为了防止输入信号过大导致超再生振荡器SILO进入饱和，需要在输入信号较大时降低低噪声放大器LNA增益，这样可以提高接收机能接收的输入信号功率的上限，提高了接收机的动态范围。此外，由于超再生振荡器SILO在低淬灭信号Quench频率与码元速率相同的情况下具有更大的增益，因此在低码元速率情况下超再生接收机更容易进入饱和，更加需要提高动态范围的办法。在应用上，可在不同码元速率情况下提高接收机动态范围，尤其是在码元速率相对低的工作状态。低噪声放大器LNA增益通过调节低噪声放大器LNA处淬灭信号Quench直流偏置来实现，该偏置与输入信号的关系是当输入信号较小时，淬灭信号Quench偏置较小，NMOS对称开关等效电阻较大，电路具有较大的增益。为了减小码间串扰，电路偏置不能过小，其最小值将随着码元速率减小而减小。当输入信号较大时，淬灭信号Quench偏置较大，NMOS对称开关等效电阻较小，电路增益减小，防止后级电路饱和。
b、所述的超再生振荡器SILO结构如图4所示：
主要包括六NMOS管、两电容、两电感和两PMOS管。
第二NMOS管N02的栅极为同相输入端，第六NMOS管N06的栅极为反相输入端。
第三NMOS管N03的漏极为同相输出端，第四NMOS管N04的漏极为反相输出端。
第一NMOS管N01的源极连接第二NMOS管N02漏极，漏极连接同相输出端，栅极连接VDD。
第二NMOS管N02的源极接地。
第三NMOS管N03的源极接地、漏极经过第一电感L1连接VDD、栅极连接反相输出端。
第四NMOS管N04的源极接地、漏极经过第二电感L2连接VDD、栅极连接同相输出端。
第五NMOS管N05的源极连接第六NMOS管N06漏极，漏极连接反相输出端， 栅极连接VDD。
第六NMOS管N06的源极接地。
第一PMOS管P01的源极和第二PMOS管P02的漏极共点后连接反相输出端，第一PMOS管P01的漏极和第二PMOS管P02的源极共点后连接同相输出端，栅极共点后连接所述淬灭信号Quench。
同相输出端经过第一电容C01外接第一调谐电压Vtune1，反相输出端经过第二电容C02外接第一调谐电压Vtune1。
所述超再生振荡器SILO是超再生接收机的核心，区别于现有技术，本发明的超再生振荡器SILO采用交叉耦合结构，不再采用尾电流控制，而是在振荡器输出节点间并联由淬灭信号Quench控制的对称PMOS组成的MOS开关，避免了超再生接收机每次打开和关闭振荡器时，尾电流源晶体管的栅极与地之间的寄生电容必须完成充电和放电的问题。这一改进可提高超再生振荡器SILO起振与停振速度，以减小残留现象的影响，因而可以实现更高的开关速率。在所述超再生振荡器SILO中，信号由一对差分共源共栅极电路注入谐振腔，结合由淬灭信号Quench控制的MOS开关，实现超再生放大。为了调节振荡器的工作频率，在振荡器输出节点间并联了变容器。
c、所述的IQ双路混频器Mixer结构如图5所示：
主要包括十NMOS管、四电感和四电阻。
第十NMOS管N10和第十二NMOS管N12的漏极共点为I路反相输出端，经过第一电阻R01后连接VDD。
第十一NMOS管N11和第十三NMOS管N13的漏极共点为I路同相输出端，经过第二电阻R02后连接VDD。
第十四NMOS管N14和第十六NMOS管N16的漏极共点为Q路反相输出端，经过第三电阻R03后连接VDD，
第十五NMOS管N15和第十七NMOS管N17的漏极共点为Q路同相输出端，经过第四电阻R04后连接VDD。
第十NMOS管N10、第十一NMOS管N11、第十四NMOS管N14和第十五NMOS管N15的源极共点后依次经过第六电感L6、第十八NMOS管N18和第八电感L8后接地。
第十二NMOS管N12、第十三NMOS管N13、第十六NMOS管N16和第十七 NMOS管N17的源极共点后依次经过第七电感L7、第十九NMOS管N19和第九电感L9后接地。
第十NMOS管N10和第十三NMOS管N13的栅极共点连接正交耦合器Hybrid的Q路反相本振信号输出端。
第十一NMOS管N11和第十二NMOS管N12的栅极共点连接正交耦合器Hybrid的Q路同相本振信号输出端。
第十四NMOS管N14和第十七NMOS管N17的栅极共点连接正交耦合器Hybrid的I路反相本振信号输出端。
第十五NMOS管N15和第十六NMOS管N16的栅极共点连接正交耦合器Hybrid的I路同相本振信号输出端。
所述IQ双路混频器Mixer为共用跨导管的IQ双平衡混频器，通过在跨导管与开关管间加入峰化电感以及在两跨导管源极加入源退化电感提高增益和线性度，以实现高级数字调制信号的解调。IQ双路混频器Mixer的负载为电阻负载，有助于在较低电源电压是实现更高的线性度和带宽。IQ两路混频器的正交本振信号由正交耦合器Hybrid产生，本振频率与射频信号频率一致，与超再生振荡器SILO放大的射频信号混频后，产生差分的零中频信号。
d、所述的第一中频放大器AMP1和第二中频放大器AMP2结构相同，其中任一中频放大器结构如图6所示：
主要包括两电阻、三PMOS管和两NMOS管。
VDD依次经过第三PMOS管P03、第二十NMOS管N20后接地。
VDD依次经过第四PMOS管P04、第二十一NMOS管N21后接地。
VDD依次经过第五PMOS管P05、第六电阻R06后接地。
第三PMOS管P03和第四PMOS管P04栅极共点后连接第二十NMOS管N20的漏极。
第五PMOS管P05的栅极连接第二十一NMOS管N21的漏极。第五电阻R05并联在第二十一NMOS管N21的源漏两端。
第二十NMOS管N20的栅极为同相输入端，第二十一NMOS管N21的栅极为反相输入端。
IQ双路混频器Mixer与中频放大器间的连接无隔直电容，中频放大器的偏置由 混频器的输出提供。中频放大器使用有源电流镜电路将差分信号转换为单端信号。
e、所述的正交耦合器Hybrid结构如图6所示：
主要包括四PMOS管、四电阻、八电容和一输入巴伦。
第二变压器B2的输入级并联在本振输入信号与地之间，输出级一端分别连接第六PMOS管P06漏极、第三电容C03上极板、第七PMOS管P07漏极和第四电容C04上极板，输出级另一端分别连接第八PMOS管P08漏极、第五电容C05上极板、第九PMOS管P09漏极和第六电容C06上极板。输出级还外接第三偏置电压Vbias3。
第六PMOS管P06、第七PMOS管P07、第八PMOS管P08和第九PMOS管P09的栅极共点后外接第二调谐电压Vtune2。
第六PMOS管P06源极分三条支路：连接第六电容C06下极板，经过第七电容C07连接Q路反相本振信号输出端，经过第七电阻R07作为I路同相本振信号输出端。
第七PMOS管P07源极分三条支路：连接第三电容C03下极板，经过第八电容C08连接I路反相本振信号输出端，经过第八电阻R08作为Q路反相本振信号输出端。
第八PMOS管P08源极分三条支路：连接第四电容C04下极板，经过第九电容C09连接Q路同相本振信号输出端，经过第九电阻R09作为I路反相本振信号输出端。
第九PMOS管P09源极分三条支路：连接第五电容C05下极板，经过第十电容C10连接I路同相本振信号输出端，经过第十电阻R10作为Q路同相本振信号输出端。
所述正交耦合器Hybrid通过电阻电容多相位滤波器实现，通过尾电流源M3的偏置来控制其等效电阻，从而调节耦合器的相位差。在合适的偏置下，耦合器能够产生与输入本振频率相同，幅度大小接近且正交的IQ两路本振信号。
本实施例中，将零中频正交解调发明应用于超再生接收机，各部分信号的时域关系的简单模型如下：
射频输入信号RFin：
Figure PCTCN2021142318-appb-000002
其中A(t)与
Figure PCTCN2021142318-appb-000003
分别为其幅度信号与相位信息，这里ω＝60GHz，与超再生振荡器SILO自由振荡频率一致。
淬灭信号Quench：
Figure PCTCN2021142318-appb-000004
其中A q、ω q与
Figure PCTCN2021142318-appb-000005
分别表示淬灭信号Quench的幅度、频率与初始相位。
超再生振荡器SILO输出信号：
Figure PCTCN2021142318-appb-000006
其中ENV(t)、Gain SR分别表示单位信号包络、超再生增益。需要注意Gain SR在输入信号较小时才可以代替电路增益，此时超再生电路工作在线性模式。
将V out表示为正交的两路信号：
Figure PCTCN2021142318-appb-000007
IQ混频器本振信号：
Figure PCTCN2021142318-appb-000008
Figure PCTCN2021142318-appb-000009
其中A LO为本振信号幅度。相比本振信号变换慢，由ENV(t)表示的信号包络变换较慢，在准静态的近似下可得到混频器输出的中频信号:
V IF_I＝ENV(t)*Gain SR*Gain mixer*I(t)
V IF_Q＝ENV(t)*Gain SR*Gain mixer*Q(t)
其中Gain mixer为混频器增益。上述两式说明，本发明超再生接收机的输出波形为原始IQ信号与超再生振荡器SILO包络的乘积。系统仿真瞬态波形如图8所示，其中曲线从上至下分别对应为：射频输入信号RFin、低噪声放大器LNA输出信号、超再生振荡器SILO输出信号、本振输入信号、I路基带信号、I路中频输出信号、Q路基带信号、Q路中频输出信号。
传统超再生振荡器SILO电路如图1所示，由负阻晶体管，直接注入晶体管，电感以及尾电流源M3组成，其相当于在常规LC振荡器的基础上加入尾电流源M3来控制起振与停止振荡，并在信号输出端口向谐振器注入信号。控制尾电流源M3的信号可以是正弦波或其它波形，需与码元速率同步。当尾电流源M3栅极上的电压较大时，通过负阻晶体管的电流较大，其提供的负阻抗也较大，电路起振，对输入信号进行采样；当尾电流源M3栅极上的电压较小时，流过负阻晶体管的电流较小，其提供 的负阻抗也较小，振荡器不能维持振荡，振荡幅度减小。
超再生振荡器SILO作为一种动态电路，其建立的振荡波形与电路初始状态有关，起关键作用的是注入信号的相位与幅度。注入信号与振荡器自由振荡频率接近时，振荡器可以工作在注入锁定的状态下，即振荡频率与注入信号的频率一致。事实上，振荡器输出信号与输入信号维持恒定相位差，这是超再生放大器允许相关调制解调的基础条件。振荡器振荡的幅度与注入信号的大小有关，注入信号越大，振荡器起振越快，在相同的时间内能够达到更大的摆幅。若注入信号过大或振荡开启时间过长，振荡器将达到最大摆幅，此时超再生振荡器SILO工作在饱和模式。传统超再生振荡器SILO不适用于高数据率的超再生接收机，其主要的原因是其不能提供足够小的阻抗使电路快速停止振荡，时间常数较大。若码元速率较大，将受到残留问题的严重影响，即前一码元信号残留叠加在后续码元上，中频输出端表现为码间串扰，电路无法正常工作。
而本发明所述超再生振荡器SILO电路如图4所示，其中第一NMOS管N01结合第二NMOS管N02，以及第五NMOS管N05结合第六NMOS管N06分别组成注入共源共栅极晶体管，第三NMOS管N03和第四NMOS管N04分别为振荡器的负阻晶体管，第一PMOS管P01和第二PMOS管P02组成PMOS对称开关。经过低噪声放大器LNA放大的射频信号连接至注入共源共栅极，将射频信号转换成电流信号并注入谐振腔。相比于共源极，共源共栅极进一步提高了隔离度，并提高了增益。电路不再采用尾电流开关的方式控制振荡器的起振与熄灭，而是在交叉耦合振荡器的谐振腔处并联所述PMOS对称开关。淬灭信号Quench处于高电压时，其等效电阻较大，电路起振，放大注入的射频信号。相反，淬灭信号Quench处于低电压时，其等效电阻较小，电路快速停止振荡，信号衰减，准备放大下一码元信号。
特别提出，本发明超再生振荡器SILO的采用PMOS对称开关，而所述低噪声放大器LNA采用NMOS对称开关，使得超再生振荡器SILO的高灵敏度区间将出现在低噪声放大器LNA输出摆幅较大的范围内。相比于采用尾电流开关控制，使用PMOS对称开关大幅减小了电路停止振荡时谐振器的等效并联阻抗，使得信号快速衰减。所述超再生振荡器SILO可通调节第一电容C01和第二电容C02的控制端电压来调节振荡器的中心频率。
IQ双路混频器Mixer中，第十八NMOS管N18和第十九NMOS管N19为跨导管，第十NMOS管N10至第十七NMOS管N17为开关管，第六电感L6和第七电感L7为峰化电感，第八电感L8和第九电感L9为源退化电感，第一电阻R01至第四电 阻R04为负载电阻。跨导管工作在饱和区，将输入信号电压转换成电流信号，本振信号通过开关管对电流信号进行调制，产生中频电流，负载电阻将中频电流转换为中频电压。通过共用跨导管，本发明只需要一个IQ双路混频器Mixer就可以实现IQ两路中频信号的产生。相比于使用独立的IQ两路混频器，本发明减小了功耗。引入的峰化电感可在射频频带内与寄生电容谐振，提高电路增益与噪声性能，而引入源退化电感可提高混频器的线性度。传统设计中，在较低的电源电压下如采用PMOS作为混频器负载，较大尺寸的晶体管才能使得混频器正常工作，较大的电容将减小中频带宽。本发明采用电阻作为负载，在实现较大增益的同时避免的带宽的减小，并提高了电路在低电源电压下的可靠性。
中频放大器如图6所示，由有源电流镜与PMOS共源放大器组成，其中有源电流镜将差分信号转换成单端信号，有源电流镜输入晶体管的偏置由所述IQ双路混频器Mixer输出提供，不需隔直电容，以实现零中频信号的放大。类似的，中频放大器中PMOS共源极放大器栅极的偏置由有源电流镜输出提供，这需要在有源电流镜电路中选择合适的PMOS尺寸，在本实施例中给出一个较为理想的比值：有源电流镜的P型晶体管与N型晶体管宽度比例为1.2:1。根据公知常识可知，第三PMOS管P03、第四PMOS管P04、第二十NMOS管N20和第二十一NMOS管N21共同组成所述有源电流镜，第五PMOS管P05为PMOS共源极放大器。
正交耦合器Hybrid如图7所示，其由输入巴伦，多相位滤波器组成。本振信号从巴伦的输入端输入，经其转换为差分的本振信号。输入巴伦的输出端与多相位滤波器的输入端连接，所述多相位滤波器由两级RC型滤波器组成，其中第二级采用固定的电阻与电容。而第一级采用工作在线性区的NMOS代替电阻，并利用其等效电阻随栅极电压变化的特点调节其阻值，起到调节多相位滤波器工作频点的作用。此外，相比单级多相位滤波器，采用两级多相位滤波器可以减小正交本振信号的幅度与相位失配。
对于本领域的技术人员来说，可根据以上描述的技术发明以及构思，做出其它各种相应的改变以及形变，而所有的这些改变以及形变都应该属于本发明权利要求的保护范围之内。

Claims (10)

  1. 一种高数据率的毫米波超再生接收机，包括依次电性连接的低噪声放大器、超再生振荡器、IQ双路混频器和两并行中频放大器，还包括用于对所述IQ双路混频器提供正交本振信号的正交耦合器；
    其特征在于，
    所述低噪声放大器输入端连接射频输入信号；
    所述超再生振荡器采用交叉耦合振荡结构，且在谐振腔处并联对称MOS管开关，所述对称MOS管开关由淬灭信号控制；
    所述淬灭信号与输入的射频信号码元频率相同。
  2. 根据权利要求1所述一种高数据率的毫米波超再生接收机，其特征在于，所述交叉耦合振荡结构的两相输出端分别通过调谐电容外接第一调谐电压。
  3. 根据权利要求2所述一种高数据率的毫米波超再生接收机，其特征在于，调谐电容为可变电容。
  4. 根据权利要求1所述一种高数据率的毫米波超再生接收机，其特征在于，所述低噪声放大器与所述超再生振荡器共用一淬灭信号。
  5. 根据权利要求1所述一种高数据率的毫米波超再生接收机，其特征在于，所述低噪声放大器主要包括四NMOS管、一电容、三电感和一输入巴伦；
    第十一电容的一极板为信号输入端，另一极板分别通过第三电感外接第二偏置电压和通过第四电感连接第八NMOS管的栅极；
    VDD依次通过第一变压器的输入级、第七NMOS管、第八NMOS管和第五电感后接地，第七NMOS管的栅极连接VDD；
    第一变压器的输出级一端为正相输出端，另一端为反相输出端，输出级还外接第一偏置电压；
    第八NMOS管的漏极与第九NMOS管的源极共点后连接同相输出端，第八NMOS管的源极与第九NMOS管的漏极共点后连接反相输出端，栅极共点后连接所述淬灭信号。
  6. 根据权利要求1所述一种高数据率的毫米波超再生接收机，其特征在于，所述超再生振荡器主要包括六NMOS管、两电容、两电感和两PMOS管；
    第二NMOS管的栅极为同相输入端，第六NMOS管的栅极为反相输入端；
    第三NMOS管的漏极为同相输出端，第四NMOS管的漏极为反相输出端；
    第一NMOS管的源极连接第二NMOS管漏极，漏极连接同相输出端，栅极连接 VDD；
    第二NMOS管的源极接地；
    第三NMOS管的源极接地、漏极经过第一电感连接VDD、栅极连接反相输出端；
    第四NMOS管的源极接地、漏极经过第二电感连接VDD、栅极连接同相输出端；
    第五NMOS管的源极连接第六NMOS管漏极，漏极连接反相输出端，栅极连接VDD；
    第六NMOS管的源极接地；
    第一PMOS管的源极和第二PMOS管的漏极共点后连接反相输出端，第一PMOS管的漏极和第二PMOS管的源极共点后连接同相输出端，栅极共点后连接所述淬灭信号；
    同相输出端经过第一电容外接第一调谐电压，反相输出端经过第二电容外接第一调谐电压。
  7. 根据权利要求1所述一种高数据率的毫米波超再生接收机，其特征在于，所述IQ双路混频器主要包括十NMOS管、四电感和四电阻；
    第十NMOS管和第十二NMOS管的漏极共点为I路反相输出端，经过第一电阻后连接VDD；
    第十一NMOS管和第十三NMOS管的漏极共点为I路同相输出端，经过第二电阻后连接VDD；
    第十四NMOS管和第十六NMOS管的漏极共点为Q路反相输出端，经过第三电阻后连接VDD，
    第十五NMOS管和第十七NMOS管的漏极共点为Q路同相输出端，经过第四电阻后连接VDD；
    第十NMOS管、第十一NMOS管、第十四NMOS管和第十五NMOS管的源极共点后依次经过第六电感、第十八NMOS管和第八电感后接地；
    第十二NMOS管、第十三NMOS管、第十六NMOS管和第十七NMOS管的源极共点后依次经过第七电感、第十九NMOS管和第九电感后接地；
    第十NMOS管和第十三NMOS管的栅极共点连接正交耦合器的Q路反相本振信号输出端；
    第十一NMOS管和第十二NMOS管的栅极共点连接正交耦合器的Q路同相本振信号输出端；
    第十四NMOS管和第十七NMOS管的栅极共点连接正交耦合器的I路反相本振信号输出端；
    第十五NMOS管和第十六NMOS管的栅极共点连接正交耦合器的I路同相本振信号输出端。
  8. 根据权利要求1所述一种高数据率的毫米波超再生接收机，其特征在于，所述两并行中频放大器结构相同，分别包括两电阻、三PMOS管和两NMOS管；
    VDD依次经过第三PMOS管、第二十NMOS管后接地；
    VDD依次经过第四PMOS管、第二十一NMOS管后接地；
    VDD依次经过第五PMOS管、第六电阻后接地；
    第三PMOS管和第四PMOS管栅极共点后连接第二十NMOS管的漏极；
    第五PMOS管的栅极连接第二十一NMOS管的漏极；第五电阻并联在第二十一NMOS管的源漏两端；
    第二十NMOS管的栅极为同相输入端，第二十一NMOS管的栅极为反相输入端。
  9. 根据权利要求8所述一种高数据率的毫米波超再生接收机，其特征在于，第三PMOS管与第二十NMOS管的宽度比例以及第四PMOS管与第二十一NMOS管的宽度比例均为1.2:1。
  10. 根据权利要求1所述一种高数据率的毫米波超再生接收机，其特征在于，所述正交耦合器主要包括四PMOS管、四电阻、八电容和一输入巴伦；
    第二变压器的输入级并联在本振输入信号与地之间，输出级一端分别连接第六PMOS管漏极、第三电容上极板、第七PMOS管漏极和第四电容上极板，输出级另一端分别连接第八PMOS管漏极、第五电容上极板、第九PMOS管漏极和第六电容上极板；输出级还外接第三偏置电压；
    第六PMOS管、第七PMOS管、第八PMOS管和第九PMOS管的栅极共点后外接第二调谐电压；
    第六PMOS管源极分三条支路：连接第六电容下极板，经过第七电容连接Q路反相本振信号输出端，经过第七电阻作为I路同相本振信号输出端；
    第七PMOS管源极分三条支路：连接第三电容下极板，经过第八电容连接I路反相本振信号输出端，经过第八电阻作为Q路反相本振信号输出端；
    第八PMOS管源极分三条支路：连接第四电容下极板，经过第九电容连接Q路同相本振信号输出端，经过第九电阻作为I路反相本振信号输出端；
    第九PMOS管源极分三条支路：连接第五电容下极板，经过第十电容连接I路同相本振信号输出端，经过第十电阻作为Q路同相本振信号输出端。
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