WO2023122639A1 - Circuit et procédé de correction de facteur de puissance - Google Patents

Circuit et procédé de correction de facteur de puissance Download PDF

Info

Publication number
WO2023122639A1
WO2023122639A1 PCT/US2022/082099 US2022082099W WO2023122639A1 WO 2023122639 A1 WO2023122639 A1 WO 2023122639A1 US 2022082099 W US2022082099 W US 2022082099W WO 2023122639 A1 WO2023122639 A1 WO 2023122639A1
Authority
WO
WIPO (PCT)
Prior art keywords
control loop
current
pfc
voltage
regulator control
Prior art date
Application number
PCT/US2022/082099
Other languages
English (en)
Inventor
Michael J LI
Mikhail Zarkhin
Original Assignee
Vitesco Technologies USA, LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/049,749 external-priority patent/US20230118346A1/en
Application filed by Vitesco Technologies USA, LLC filed Critical Vitesco Technologies USA, LLC
Publication of WO2023122639A1 publication Critical patent/WO2023122639A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
    • H02M1/0035—Control circuits allowing low power mode operation, e.g. in standby mode using burst mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the disclosure relates to a method of power factor correction (PFC) burst mode load measurement and control.
  • PFC power factor correction
  • Regulatory standards such as IEC61000-3 -2 for electromagnetic compatibility (EMC) require devices that draw high power from an alternating current (AC) mains (e.g., power grid) to implement power factor correction (PFC) to reduce harmonic distortion on the input current.
  • PFC is a method of syncing AC line current phase with AC voltage to eliminate inefficiencies associated with reactive current. PFC regulates current draw from the AC mains in proportion to the AC voltage, reducing distortion of the AC sine wave under high load conditions.
  • SMPS Switch Mode Power Supply
  • a typical PFC circuit will convert the input AC mains to a DC output voltage stored in a bank of capacitors, commonly called DC Link. Regulation of the DC output voltage is performed by modulating the AC mains input current amplitude. Because of the requirement that the AC mains current be sinusoidally shaped and proportional to the AC mains voltage, the voltage control loop of the PFC is typically very slow as any rapid changes in the AC mains input current demanded will introduce distortion into the sinusoidal current shape. Typically, voltage regulation control loops have response times in the order of 10 times the AC mains period to reduce Total Harmonic Distortion and maintain high power factor.
  • One aspect of the disclosure provides a power factor correction (PFC) circuit that includes an input for receiving alternating current.
  • the PFC circuit also includes a converter for converting the received alternating current to a direct current.
  • the PFC circuit also includes a direct current link having at least one capacitor and a voltage regulator control loop that operates in burst mode under light load conditions by switching between an ON-state and an OFF-state periodically.
  • the PFC circuit additionally includes a controller that preloads the voltage regulator control loop with an initial value corresponding to initial conditions of the circuit current load under light load conditions when the voltage regulator control loop transitions to an ON-state of the burst mode.
  • Implementations of the disclosure may include one or more of the following optional features.
  • the controller determines, during an OFF- state of the burst mode, the initial value based on a rate of change of the voltage at the direct current link and the capacitance C of the capacitor.
  • the input Im is based on the initial value corresponding to the initial conditions of the circuit current load under the light load.
  • the PFC circuit includes a pulse width modulator and a current regulator control loop that adjusts a duty cycle of the pulse width modulator based on an output current of the voltage regulator control loop.
  • Another aspect of the disclosure provides a method for preloading a voltage regulator control loop of a power factor correction (PFC) circuit with an initial value corresponding to initial conditions of the circuit current load under light load.
  • the method includes receiving alternating current; and converting the received alternating current to a direct current.
  • the method includes preloading the voltage regulator control loop with the initial value corresponding to the initial conditions of the circuit current load under the light load.
  • the method includes determining the initial value based on a rate of change of the voltage at a direct current link and a capacitance of a capacitor of the direct current link.
  • an input of the power factor correction circuit may be based on the initial value corresponding to initial conditions of the circuit current load under light load.
  • the method also includes adjusting, at a current regulator control loop, a duty cycle of a pulse width modulator based on an output current of the voltage regulator control loop.
  • FIG. 1 A is a schematic view of an exemplary on-board charger.
  • FIG. IB is a schematic view of an exemplary power factor correction circuit of FIG. 1A.
  • FIG. 2A is an exemplary graph showing PFC burst mode behavior without the preloading method.
  • FIG. 2B is an exemplary graph showing PFC burst mode behavior with the preloading method.
  • FIG. 3 is an exemplary graph showing the PFC of FIG. 1 operating in burst mode.
  • FIG. 4 is a schematic view of an exemplary arrangement of operations for a method of preloading a voltage regulator control loop of a power factor correction (PFC) circuit with initial values corresponding to initial conditions of the circuit current load under light load conditions.
  • PFC power factor correction
  • an on-board charger (OBC) 10 is used in electrical vehicles or hybrid vehicles to charge a battery of the vehicle.
  • the OBC 10 converts alternating current (AC) input from the main grid to a direct current (DC) output which charges the vehicle battery.
  • the OBC 10 may run a power factor correction (PFC) circuit 100 to transform the input AC voltage into an intermediate DC voltage, referred to as DC Link, which is used by the DC-to-DC stage to generate the charging current at the output.
  • PFC power factor correction
  • the OBC 10 runs the PFC 100 in “burst mode” at light load to convert the inputted AC power from the AC main to DC power. Burst mode is a mode of operation which uses cycle-skipping to reduce switching losses in a switching regulator and increase operation efficiency at low output current levels.
  • FIG. IB shows the PFC 100 of FIG. 1A.
  • the PFC 100 includes controllers and measurement inputs.
  • the PFC 100 receives power from an AC power supply from the grid that provides an input AC voltage.
  • the received AC power supply is then rectified by a rectifier 110 having a diode bridge.
  • Some PFC topologies may not use a rectifier.
  • the PFC 100 also includes a switch mode power supply which is also referred to as boost converter 120.
  • the boost converter 120 includes an inductor 122, a transistor 124, and a diode 126. Other boost converters may also be used.
  • the boost converter 120 boosts the rectified AC voltage to the DC voltage at a DC Link and regulates the AC input current Ln.
  • the boost converter 120 includes two states of operation.
  • a switch of the transistor 124 is closed (i.e., the transistor 124 is ON) and the inductor 122 is charged by the voltage source coming out of the rectifier 110.
  • the switch of the transistor 124 opens (i.e., the transistor 124 is OFF)
  • the energy stored in the inductor 122 during the first state is transferred to the DC Link capacitors 130 through the diode 126, resulting in an increased voltage at an output of the boost converter 120.
  • the injected current from the diode 126 charges the capacitor 130 which maintains the voltage level at the output of the PFC 100 while the inductor 122 recharges. As shown, the capacitor 130 helps smooth an output voltage ripple from the boost converter 120.
  • the PFC 100 includes a first control loop 140 that includes a first error amplifier 142 and a second control loop 150 that includes a second error amplifier 152.
  • Each of the first and second control loops 140, 150 monitors and regulates the PFC 100.
  • the first error amplifier 142 compares the voltage at the DC Link 130 against a desired reference voltage Vref (corresponds to the desired Voui). When the voltage at the DC Link 130 is below the reference voltage Vref, a current output 1142 of the first error amplifier 142 increases; when the voltage at the DC Link 130 is above the reference voltage Vref the current output I142 of the first error amplifier 142 decreases.
  • the output of the first control loop 140 is multiplied at a multiplier 160 with a reference sine wave 170 creating the sinusoidal input current reference ISR for the second control loop 150.
  • the second control loop error amplifier 152 compares the input current lin with the reference current ISR and adjusts the duty cycle of the PWM 180 so that the input current Ln matches the reference current ISR.
  • the amplifiers are described as transconductance amplifiers (voltage input, current output), but may be other types such as those with outputs of voltage or digital count values.
  • the amplitude of the current output 1142 of the first control loop 140 is roughly proportional to the amplitude of the input AC current n, which is in turn roughly proportional to the load current lout at the PFC DC Link output.
  • the current output 1142 of the first control loop is therefore low, and when the current output 1142 falls below a predefined current threshold Lh (I142 ⁇ h), the PFC power stage boost converter 120 is disabled and the PFC 100 enters burst mode.
  • the PFC power stage boost converter 120 is then re-enabled when a DC Link voltage V 'de link (i.e., a voltage of a bank of capacitors of the PFC circuit) falls below a predefined voltage threshold Vth (i.e., Vdcjtnk ⁇ Vth).
  • Vth i.e., Vdcjtnk ⁇ Vth.
  • the PFC 100 will then cycle between enabled and disabled modes and is active only periodically as the DC Link voltage Vdcjtnk falls below the predefined voltage threshold Vth, and turns off again when the first controller amplifier output I142 again falls below the predetermined current threshold h.
  • the first control loop 140 must be disabled during the off part of the burst mode, otherwise the error amplifier 142 of the first control loop 140 continues to integrate the voltage error of the output voltage Vo t with respect to Vref. If the first loop 140 is not disabled during the off burst mode, then when the PFC power stage is re- enabled, the PFC 100 will run at high AC mains input current lin due to accumulated error at the first control loop 140, which will cause the output voltage Vout (i.e., voltage at the DC link) to overshoot until the first control loop 140 can recover and reduce the demand of the input current Im. Conversely, if the first control loop 140 is disabled and reset to too low a value, upon re-enabling of the power stage, in the first control loop 140 there will be a delay to increase demand of the AC mains input current Im to recharge the DC Link voltage Vout.
  • the PFC 100 must not introduce harmonic distortion in the input AC current Ln, the first control loop 140 is very slow.
  • the output 1142 of the first control loop 140 must not change significantly over several AC line periods so that, after being multiplied with the reference sine wave 170, the input ISR to the second control loop 150 remains nearly purely sinusoidal.
  • the bandwidth of the first control loop 140 therefore is typically in the 1 to 10 Hz range.
  • both burst mode restart strategies described in the previous paragraph would result in large deviations in the DC Link voltage VDC jink (overshoot and undershoot, respectively).
  • FIG. 2A shows an example of the over and undershoot showing the DC Link voltage VDC jink which is the PFC DC Link output voltage Vout, the PFC AC input current Im, and the first control loop error amplifier output 1142.
  • the PFC 100 “preloads” the first control loop 140 (with the initial value) so that upon re-enabling of the power stage, the ideal AC mains input current Im is commanded immediately by the PFC 100 and the DC Link 130 begins to recharge at the desired rate.
  • the ideal AC mains input current Im depends on the load demand on the DC Link output Vout. Usually, this information is not available to the PFC controller 102 during the off phase of the burst mode, and would require additional sensing circuitry to implement, which increases cost.
  • the PFC 100 may estimate a circuit load based on a slope of discharge of the DC Link voltage VDC jink at the capacitor 130.
  • the voltage of the DC Link output VDC JM is known and monitored by the PFC controller 102 at all times, including during the burst off phase. Additionally, the capacitance 130 of the DC Link is known, within some tolerance. During the burst off phase, no energy is transferred to the DC Link capacitors 130 from the disabled PFC power stage boost converter 120, so the capacitor 130 is discharged by the load current lout on the DC Link 130.
  • the PFC power stage is active when the DC Link voltage V 'de link drops below a voltage threshold Vth (i.e., V -Ic ink ⁇ Vth) and disabled when the first controller current output I142 falls below a certain threshold (1142 ⁇ Ith).
  • Vth i.e., V -Ic ink ⁇ Vth
  • the PFC controller 102 monitors the DC Link voltage VdcjM so that the rate of discharge dv/dt may be determined.
  • Voc Link shows the voltage at the output of the PFC 100 on the DC Link capacitors 130 charging and discharging during burst on and off phases, respectively.
  • V(PWM) shows the activation of the PFC power stage boost converter 120 during the burst on phase.
  • the first controller amplifier output 1142 is the output of the first controller error amplifier 142, which is zero during the burst off phase, but initialized and preloaded with the initial value 104 corresponding to initial conditions of the circuit current load under light load condition at the start of the burst on phase.
  • the appropriate initial value 104 may be determined by the PFC controller 102.
  • the PFC controller 102 may determine the appropriate initial value 104 either by calculating or by referencing a look up table.
  • the load determined by the discharge rate dv/dt, as well as factors such as AC mains input voltage and DC Link setpoint voltage are used to determine a initial value 104 such that upon re-enabling of the PFC power stage, the DC Link will be recharged at the appropriate lin for the load on DC Link so that there is no additional undershoot or overshoot, and within a target range of charging rate.
  • the initial value 104 must also be above the threshold for entering burst mode, otherwise the PFC 100 will immediately disable the power stage again upon attempting to re-enable.
  • VDC link is the PFC DC Link output voltage
  • Imput is the PFC AC input current
  • 1142 is the first control loop error amplifier 142 output.
  • the DC Link output voltage undershoot and overshoot is eliminated in FIG. 2B, and peak input current is also reduced.
  • FIG. 4 provides an example arrangement of operations for a method 400 of preloading a voltage regulator control loop 140 of a power factor correction (PFC) circuit 100 with an initial value 104 corresponding to initial conditions of the circuit current load under light load conditions using the system of FIGS. 1 A-3.
  • the method 400 includes receiving, at the PFC 100, alternating current Im from an AC power supply supplied by the grid that provides an input AC voltage.
  • the method 400 includes converting, at a converter 120, the received alternating current Im to a direct current.
  • the method 400 may include reducing, at a boost converter 120, the direct current received from the converter 110.
  • the method 400 includes preloading the voltage regulator control loop 140 with the initial value 104, when the voltage regulator control loop 140 transitions to an ON-state of a burst mode.
  • the method 400 further includes determining during an OFF-state of the burst mode, the initial value 104based on a rate of change dv/dt of the voltage at a direct current link DC Link and a capacitance C of a capacitor 130 of the direct current link DC Link.
  • the when the power factor correction is re-enabled an input Im of the PFC circuit is based on the preloaded circuit current load i.
  • the method 400 also includes adjusting, at the current regulator control loop 150, a duty cycle of a pulse width modulator 180 based on an output current of the voltage regulator control loop.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un circuit de correction de facteur de puissance (PFC). Le circuit PFC comprend une entrée permettant de recevoir un courant alternatif et un convertisseur permettant de convertir le courant alternatif reçu en un courant continu. Le circuit PFC comprend également une liaison à courant continu qui comprend au moins un condensateur. De plus, le circuit PFC comprend une boucle de commande de régulateur de tension fonctionnant en mode rafale dans des conditions de charge légère par commutation entre un état MARCHE et un état ARRÊT périodiquement. Le circuit PFC comprend également un dispositif de commande préchargeant la boucle de commande de régulateur de tension sur une valeur initiale correspondant à la charge de courant de circuit dans des conditions légères, lorsque la boucle de commande de régulateur de tension passe à un état MARCHE du mode rafale. La valeur initiale est fondée sur le taux de variation de la tension au niveau de la liaison à courant continu et sur la capacité du condensateur de la liaison à courant continu.
PCT/US2022/082099 2021-12-23 2022-12-21 Circuit et procédé de correction de facteur de puissance WO2023122639A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163293133P 2021-12-23 2021-12-23
US63/293,133 2021-12-23
US18/049,749 US20230118346A1 (en) 2016-02-09 2022-10-26 Method of Power Factor Correction Burst Mode Load Measurement and Control
US18/049,749 2022-10-26

Publications (1)

Publication Number Publication Date
WO2023122639A1 true WO2023122639A1 (fr) 2023-06-29

Family

ID=85174005

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/082099 WO2023122639A1 (fr) 2021-12-23 2022-12-21 Circuit et procédé de correction de facteur de puissance

Country Status (1)

Country Link
WO (1) WO2023122639A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110018507A1 (en) * 2009-07-22 2011-01-27 Mccloy-Stevens Mark Switched power regulator
US7990740B1 (en) * 2004-03-19 2011-08-02 Marvell International Ltd. Method and apparatus for controlling power factor correction

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7990740B1 (en) * 2004-03-19 2011-08-02 Marvell International Ltd. Method and apparatus for controlling power factor correction
US20110018507A1 (en) * 2009-07-22 2011-01-27 Mccloy-Stevens Mark Switched power regulator

Similar Documents

Publication Publication Date Title
US9118239B2 (en) Power supply control method for constant current constant power control
US7038435B2 (en) Method for input current regulation and active-power filter with input voltage feedforward and output load feedforward
US7298119B1 (en) Step-up/step-down (buck/boost) switching regulator control methods
US8723490B2 (en) Controlling a bidirectional DC-to-DC converter
EP2350763B1 (fr) Régulateur de tension commuté
US8929106B2 (en) Monotonic pre-bias start-up of a DC-DC converter
US20090108820A1 (en) Topology for a positive buck-boost switching regulator
US20170338738A1 (en) Control circuit and control method for switching regulator and switching regulator with the same
WO2011109746A2 (fr) Unités de commande de chargeurs de batteries et chargeurs de batteries associés
JP2001514840A (ja) 複合電力コンバータ
WO2006027917A1 (fr) Alimentation electrique
US9490707B2 (en) Control circuit and a method for an energy based pulse skipping mode in a DC/DC converter
US9896048B2 (en) Power supply unit for supplying power to an on-board electrical network of a vehicle
US10948934B1 (en) Voltage regulator with piecewise linear loadlines
US8830701B2 (en) DC-DC converter
Zhao et al. Design of a non-isolated single-switch three-port DC-DC converter for standalone PV-battery power system
US11894779B2 (en) Power supply with active power buffer
US20200195153A1 (en) Simplified hybrid pwm/pfm control method for sllc converter
CN114270683A (zh) 用于直流电压变换器的调节装置、直流电压变换器和用于调节直流电压变换器的方法
US20230118346A1 (en) Method of Power Factor Correction Burst Mode Load Measurement and Control
WO2023163876A1 (fr) Alimentation électrique à tampon de puissance active
WO2023122639A1 (fr) Circuit et procédé de correction de facteur de puissance
US20230170806A1 (en) Method for Actuating a Buck-Boost Converter
US20230216408A1 (en) Method for Regulating a Buck-Boost Converter
US10411594B1 (en) DC-DC converter with regulator having a plurality of parameter sets

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22854443

Country of ref document: EP

Kind code of ref document: A1