WO2023163876A1 - Alimentation électrique à tampon de puissance active - Google Patents

Alimentation électrique à tampon de puissance active Download PDF

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Publication number
WO2023163876A1
WO2023163876A1 PCT/US2023/013062 US2023013062W WO2023163876A1 WO 2023163876 A1 WO2023163876 A1 WO 2023163876A1 US 2023013062 W US2023013062 W US 2023013062W WO 2023163876 A1 WO2023163876 A1 WO 2023163876A1
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WO
WIPO (PCT)
Prior art keywords
converter
control loop
power
voltage
output
Prior art date
Application number
PCT/US2023/013062
Other languages
English (en)
Inventor
Chanwit Prasantanakorn
Bharat K Patel
Yantao Song
Abby CHERIAN
Original Assignee
Apple Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US17/663,143 external-priority patent/US20230275521A1/en
Application filed by Apple Inc. filed Critical Apple Inc.
Publication of WO2023163876A1 publication Critical patent/WO2023163876A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/325—Means for protecting converters other than automatic disconnection with means for allowing continuous operation despite a fault, i.e. fault tolerant converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4258—Arrangements for improving power factor of AC input using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • AC -DC power supplies Many electronic devices require AC -DC power supplies. Personal computers and their associated peripherals are examples of such electronic devices.
  • the size of the electronic device is sufficient that the AC -DC power supply having adequate capacity is sufficiently small that it may be contained within the electronic device’s housing.
  • the AC -DC power supply must be located externally. The external power supply may be incorporated into the power plug for the electronic device, resulting in what is sometimes colloquially known as a “wall wart” power supply.
  • the external power supply may also be a separate unit with a power cord that connects to a wall mains supply and a separate power cord that connects to the electronic device, resulting in what is sometimes colloquially known as a “power brick.”
  • a power brick may be a separate unit with a power cord that connects to a wall mains supply and a separate power cord that connects to the electronic device, resulting in what is sometimes colloquially known as a “power brick.”
  • electronic device power requirements and size constraints have dictated external power supplies when internal power supplies would be preferable.
  • a power converter can include a DC-DC converter stage having an input coupled to an input of the power converter and an output coupled to an output of the converter and an active power buffer coupled to the output of the power converter.
  • the active power buffer can further include an energy storage capacitor and one or more switching devices selectively coupling the energy storage capacitor to the output of the power converter so as to alternately store energy in and discharge energy from the energy storage capacitor.
  • Control circuitry of the power converter can include a first control loop that operates the DC-DC converter stage to regulate an average voltage across the energy storage capacitor of the active power buffer and a second control loop that operates the one or more switching devices of the active power buffer to regulate an output voltage of the power converter.
  • the power converter can be an AC -DC converter, and the DC-DC converter stage can be coupled to the input of the power converter by a rectifier.
  • the DC-DC converter stage can be an isolated converter.
  • the DC-DC converter stage can be a flyback converter.
  • the flyback converter can employ a split magnetics arrangement having two or more flyback transformers with their secondary windings connected in parallel.
  • the two or more flyback transformers can have their primary windings connected in series and driven by a single switching device.
  • the two or more flyback transformers can have their primary windings connected in parallel and driven by respective switching devices for each primary winding.
  • the first control loop can have a bandwidth less than twice the line frequency of an AC input to the converter.
  • the first control loop can employ constant Ton control.
  • the second control loop can have a bandwidth higher than the first control loop.
  • the second control loop can employ duty cycle control.
  • An AC -DC converter can include a rectifier coupled to an AC input of the AC -DC converter, a flyback converter having an input coupled to the rectifier and an output coupled to an output of the AC -DC converter, and an active power buffer coupled to the output of the power converter.
  • the active power buffer can include an energy storage capacitor and one or more switching devices selectively coupling the energy storage capacitor to the output of the power converter so as to alternately store energy in and discharge energy from the energy storage capacitor.
  • the control circuitry can include a first control loop, having a bandwidth less than twice the line frequency of the AC input, that operates the flyback converter to regulate an average voltage across the energy storage capacitor of the active power buffer while providing unity power factor at the AC input of the AC -DC converter and a second faster control loop that operates the one or more switching devices of the active power buffer to regulate an output voltage of the power converter.
  • the flyback converter can employ a split magnetics arrangement having two or more flyback transformers with their secondary windings connected in parallel.
  • the two or more flyback transformers can have their primary windings connected in series and driven by a single switching device.
  • the two or more flyback transformers can have their primary windings connected in parallel and driven by respective switching devices for each primary winding.
  • the active power buffer can further include an inductor coupling the one or more switching devices to output of the power converter, wherein the inductor and one or more switching devices can be operated as a bidirectional buck-boost converter.
  • a method of operating an AC -DC converter having a rectifier, a DC-DC converter, and an active power buffer coupled to an output of the DC-DC converter can include operating the DC- DC converter to maintain an average voltage across an energy storage capacitor of the active power buffer and operating one or more switching devices of the active power buffer to regulate an output voltage of the AC -DC converter.
  • the average voltage can be selected to be approximately halfway between an output voltage of the AC -DC converter and a voltage rating of the energy storage capacitor.
  • Operating the DC-DC converter to maintain an average voltage across an energy storage capacitor of the active power buffer can further include operating the DC-DC converter to present unity power factor at an input of the AC -DC converter.
  • Operating the DC-DC converter to maintain an average voltage across an energy storage capacitor of the active power buffer can include generating PWM signals for one or more switching devices of the DC-DC converter using a constant on time control loop.
  • Operating one or more switching devices of the active power buffer to regulate an output voltage of the AC -DC converter can include generating PWM signals for the one or more switching devices of the active power buffer using a duty cycle control loop.
  • a power converter can include a DC-DC converter having an output with an active power buffer coupled thereto.
  • the active power buffer can include an energy storage capacitor and one or more switching devices selectively coupling the capacitor to the output to alternately store energy in and discharge energy from the capacitor.
  • Control circuitry can include a DC-DC converter control loop that operates the DC-DC converter to regulate an average voltage across the capacitor and an active power buffer control loop that operates the one or more switching devices of the active power buffer to regulate an output voltage of the power converter.
  • the DC- DC converter control loop can include a relatively slower control loop that controls the DC-DC converter during steady state load conditions and at least one relatively faster control loop that controls the DC-DC converter during transient load conditions.
  • the at least one relatively faster control loop can include a first relatively faster control loop that controls the DC-DC converter during transient load conditions resulting from a load increase and a second relatively faster control loop that controls the DC-DC converter during transient load condition resulting from a load decrease.
  • the control circuitry can further include selection circuitry configured to select a reference signal from among the output signals of the relatively slower control loop, the first relatively faster control loop, and the second relatively faster control loop.
  • the selected reference signal can be provided to a current controller and a pulse width modulation signal generator that generate drive signals for a switching device of the DC-DC converter.
  • the relatively slower control loop can be responsive to the voltage across the energy storage capacitor, and the at least one relatively faster control loop can be responsive to the voltage across the energy storage capacitor and a load current of the power converter.
  • the at least one relatively faster control loop can compare the voltage across the energy storage capacitor to a reference voltage that is different than a reference voltage of the relatively slower control loop.
  • the at least one relatively faster control loop can compare an instantaneous value of the load current to an average value of the load current over a time period.
  • the faster control loop compares the instantaneous value of the load current to the average value of the load current over the time period plus an offset.
  • the power converter can be an AC -DC converter, and the DC-DC converter stage can be coupled to the input of the power converter by a rectifier.
  • the DC-DC converter can be a flyback converter employing a split magnetics arrangement having two or more flyback transformers with their secondary windings connected in parallel.
  • the relatively slower control loop can have a bandwidth less than the line frequency of an AC input to the converter.
  • the relatively slower control loop can have a bandwidth less than half the line frequency of the AC input to the converter.
  • An AC -DC converter can include a rectifier coupled to an AC input of the AC -DC converter, a flyback converter having an input coupled to the rectifier and an output coupled to an output of the AC -DC converter, and an active power buffer coupled to the output of the power converter.
  • the active power buffer can further include an energy storage capacitor and one or more switching devices selectively coupling the energy storage capacitor to the output of the power converter to alternately store energy in and discharge energy from the energy storage capacitor and control circuitry including a flyback converter control loop that operates the flyback converter to regulate an average voltage across the energy storage capacitor of the active power buffer while providing unity power factor at the AC input of the AC -DC converter.
  • the flyback converter control loop can include a relatively slower control loop that controls the flyback converter during steady state load conditions and at least one relatively faster control loop that controls the DC-DC converter during transient load conditions.
  • the active power buffer control loop can operate the one or more switching devices of the active power buffer to regulate an output voltage of the power converter.
  • the at least one relatively faster control loop can include a first relatively faster control loop that controls the DC-DC converter during transient load conditions resulting from a load increase and a second relatively faster control loop that controls the DC-DC converter during transient load condition resulting from a load decrease.
  • the control circuitry can further include selection circuitry configured to select a reference signal from among the output signals of the relatively slower control loop, the first relatively faster control loop, and the second relatively faster control loop.
  • the selected reference signal can be provided to a current controller and a pulse width modulation signal generator that generate drive signals for a switching device of the DC-DC converter.
  • the relatively slower control loop can be responsive to the voltage across the energy storage capacitor, and the at least one relatively faster control loop can be responsive to the voltage across the energy storage capacitor and the load current.
  • the at least one relatively faster control loop can compare the voltage across the energy storage capacitor to a reference voltage that is different than a reference voltage of the relatively slower control loop.
  • the at least one relatively faster control loop can compare an instantaneous value of the load current to an average value of the load current over a time period.
  • the faster control loop can compare the instantaneous value of the load current to the average value of the load current over the time period plus an offset.
  • the relatively slower control loop can have a bandwidth less than the line frequency of an AC input to the converter.
  • the relatively slower control loop can have a bandwidth less than half the line frequency of the AC input to the converter.
  • the flyback converter can employ a split magnetics arrangement having two or more flyback transformers with their secondary windings connected in parallel and (a) the two or more flyback transformers can have their primary windings connected in series and driven by a single switching device; or (b) the two or more flyback transformers have their primary windings connected in parallel and driven by respective switching devices for each primary winding.
  • the active power buffer can further include an inductor coupling the one or more switching devices to output of the power converter, wherein the active power buffer control loop operates the inductor and one or more switching devices as a bi-directional buck-boost converter.
  • a method of operating an AC -DC converter having a rectifier, a DC-DC converter, and an active power buffer coupled to an output of the DC-DC converter can include operating one or more switching devices of the active power buffer to regulate an output voltage of the AC -DC converter and operating one or more switching devices of the DC-DC converter to maintain an average voltage across an energy storage capacitor of the active power buffer by controlling switching of the one or more switching devices of the DC-DC converter using a relatively slower control loop that controls the DC-DC converter during steady state load conditions and at least one relatively faster control loop that controls the DC-DC converter during transient load conditions.
  • the average voltage can be selected to be approximately half-way between an output voltage of the AC -DC converter and a voltage rating of the energy storage capacitor.
  • Operating the DC-DC converter to maintain an average voltage across an energy storage capacitor of the active power buffer further comprises operating the DC-DC converter to present unity power factor at an input of the AC -DC converter.
  • a power converter can include a rectifier that receives an AC input voltage and produces a rectified output voltage, a power factor correction (PFC) converter having an input coupled that receives the rectified output voltage of the rectifier and an output that provides an intermediate DC bus voltage, a DC-DC converter having an input that receives the intermediate DC bus voltage and produces a regulated DC output voltage, and control circuitry for the PFC converter stage that includes a relatively slower control loop that controls the PFC converter during steady state load conditions and at least one relatively faster control loop that controls the PFC converter during transient load conditions.
  • PFC power factor correction
  • the at least one relatively faster control loop can include a first relatively faster control loop that controls the PFC converter during transient load conditions resulting from a load increase and a second relatively faster control loop that controls the PFC converter during transient load condition resulting from a load decrease.
  • the control circuitry can further include selection circuitry configured to select a reference signal from among the output signals of the relatively slower control loop, the first relatively faster control loop, and the second relatively faster control loop.
  • the selected reference signal can be provided to a current controller and a pulse width modulation signal generator that generate drive signals for a switching device of the PFC converter.
  • the relatively slower control loop can be responsive to the intermediate DC bus voltage
  • the at least one relatively faster control loop can be responsive to the intermediate DC bus voltage and a load current of the power converter.
  • the at least one relatively faster control loop can compare the intermediate DC bus voltage to a reference voltage that is different than a reference voltage of the relatively slower control loop.
  • the at least one relatively faster control loop can compare an instantaneous value of the load current to an average value of the load current over a time period.
  • the faster control loop can compare the instantaneous value of the load current to the average value of the load current over the time period plus an offset.
  • the PFC converter can be a boost converter or a flyback converter.
  • the relatively slower control loop can have a bandwidth less than half the line frequency of an AC input to the converter.
  • a method of operating an AC -DC converter having a rectifier, a power factor correction (PFC) converter, and a DC-DC converter can include operating one or more switching devices of the DC-DC converter to regulate an output voltage of the AC -DC converter and operating one or more switching devices of the PFC converter to maintain unity power factor at an input of the AC- DC converter and an average voltage across an intermediate bus of the AC -DC converter coupling an output of the PFC converter to an input of the DC-DC converter by controlling switching of the one or more switching devices of the PFC converter using a relatively slower control loop that controls the PFC converter during steady state load conditions and at least one relatively faster control loop that controls the PFC converter during transient load conditions.
  • PFC power factor correction
  • the at least one relatively faster control loop can include a first relatively faster control loop that controls the PFC converter during transient load conditions resulting from a load increase and a second relatively faster control loop that controls the PFC converter during transient load condition resulting from a load decrease.
  • Controlling switching of the one or more switching devices of the PFC converter using a relatively slower control loop that controls the PFC converter during steady state load conditions and at least one relatively faster control loop that controls the PFC converter during transient load conditions can further include selecting a reference signal from among the output signals of the relatively slower control loop, the first relatively faster control loop, and the second relatively faster control loop.
  • the method can further include providing the selected reference signal to a current controller and a pulse width modulation signal generator that generate drive signals for one or more switching devices of the PFC converter.
  • the relatively slower control loop can be responsive to the intermediate DC bus voltage
  • the at least one relatively faster control loop can be responsive to the intermediate DC bus voltage and a load current of the power converter.
  • Controlling switching of the one or more switching devices of the PFC converter using a relatively slower control loop that controls the PFC converter during steady state load conditions and at least one relatively faster control loop that controls the PFC converter during transient load conditions can further include using the at least one relatively faster control loop to compare the intermediate DC bus voltage to a reference voltage that is different than a reference voltage of the relatively slower control loop.
  • Controlling switching of the one or more switching devices of the PFC converter using a relatively slower control loop that controls the PFC converter during steady state load conditions and at least one relatively faster control loop that controls the PFC converter during transient load conditions can further include comparing an instantaneous value of a load current to an average value of the load current over a time period.
  • the relatively slower control loop can have a bandwidth less than the line frequency of an AC input to the converter.
  • the relatively slower control loop can have a bandwidth less than half the line frequency of the AC input to the converter.
  • Figure 1 illustrates a generalized AC -DC converter system and associated waveforms.
  • Figures 2A and 2B illustrate AC-DC converter systems without and with power factor correction.
  • Figure 3 illustrates a schematic of an AC -DC converter with an active power buffer.
  • Figure 4 illustrates an active power buffer and associated current waveforms.
  • Figures 5A and 5B illustrate an AC -DC converter with an active power buffer and associated waveforms.
  • Figure 6 illustrates an AC-DC converter with an active power buffer and an exemplary control system.
  • Figures 7A and 7B illustrate AC-DC converters with active power buffers and split magnetics.
  • Figure 8 illustrates an AC-DC converter with multiple control loops.
  • Figure 9 illustrates a power factor corrected AC-DC converter with multiple control loops.
  • Figure 10A illustrates a boost converter PFC AC-DC converter with multiple control loops.
  • Figure 10B illustrates a flyback converter PFC AC-DC converter with multiple control loops.
  • a given figure may be used to illustrate the features of more than one embodiment, or more than one species of the disclosure, and not all elements in the figure may be required for a given embodiment or species.
  • a reference number when provided in a given drawing, refers to the same element throughout the several drawings, though it may not be repeated in every drawing.
  • the drawings are not to scale unless otherwise indicated, and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure.
  • FIG. 1 illustrates a generalized AC -DC converter system 100 and associated waveforms 103/105/107.
  • AC -DC converter system 100 can include an AC -DC converter 104 that receives an AC input voltage Vin and AC input current from an AC source 102.
  • AC -DC converter 104 could be a power supply for an electronic device such as a computer or associated peripheral.
  • AC source 102 could be an AC mains voltage connection, such as an outlet or receptacle in a home, office, or other installation.
  • AC -DC converter 104 can provide power to a load 106.
  • Load 106 may be any number of devices, for example the above-mentioned electronic device, such as a personal computer or associated peripheral.
  • AC -DC converter 104 converts the AC input power into output power suitable for load 106, e.g., to a specific output voltage Vo.
  • the output power of AC -DC converter 104 is labeled as Pin.
  • the input power to AC -DC converter will be Pin divided by the efficiency of the converter, although for purposes of this discussion, this efficiency is assumed to be 1 or 100% for simplicity.
  • Power Pin may be thought of as being divided between the DC power requirement of load 106, labelled Pdc, and the instantaneous AC power either delivered to or sourced from buffer/output filter capacitor Cb.
  • Pdc the input AC voltage Vin/103a and input AC current Iin/103b are in phase. In other words, the converter operates with unity power factor.
  • Pin is the product of the input AC voltage 103a and the input AC current 103b.
  • AC -DC converter 104 may be designed to operate at unity power factor or may operate with a non-unity power factor, in which case the power is the product of the input AC voltage, input AC current, and the cosine of the phase angle between them (also called the power factor).
  • Waveform 105 plots the instantaneous value of power Pin, which is a sinusoid having twice the frequency of the supplied line frequency. This sinusoidal instantaneous power has a peak value of 2Pdc, a minimum value of zero, and an average value Pdc, corresponding to the power requirement of load 106. Subtracting the constant DC power requirement of load 106 from the instantaneous power produces the AC power waveform 107, which is sourced from or sunk to output filter capacitor Cb.
  • Capacitor Cb thus acts as a (passive) power buffer that makes up the difference between the instantaneous AC input power and the DC output power.
  • an AC -DC converter may be designed with or without power factor correction.
  • Figure 2A illustrates a generalized single-stage AC -DC converter 200a without power factor correction. Such converters are sometimes used in applications in which the power requirement is less than about 75W.
  • Figure 2B illustrates a generalized multi-stage AC -DC converter 200b with power factor correction. Such converters are sometimes used in applications in which the power requirement is more than about 75W. (Various regulatory and other requirements sometimes require power factor correction in AC -DC power supplies/converters above a certain power rating.)
  • the AC input voltage may be applied to a rectifier 210, which converts the AC input voltage Vin into a DC bus voltage Vb.
  • the DC bus may be supported by a DC bus capacitor Cb (which may act as a power buffer in a way analogous to that described above).
  • Rectifier 210 may be a diode bridge, either a full bridge or a half bridge.
  • rectifier 210 could include active/controlled switching devices, such as transistors, thyristors, or other suitable devices.
  • a DC-DC (D2D) converter 212 can receive the DC bus voltage Vb and produce an output DC voltage Vo suitable for the load to be powered.
  • the DC-DC converter may be a switching converter incorporating any of a variety of topologies.
  • LLC resonant converters are often used.
  • any suitable converter topology including flyback converters, buck converters, etc. could also be used as appropriate for a given application.
  • the AC input voltage may range between 90-260Vac, which includes the nominal range of AC line voltages supplied in various countries around the world. Rectification of this voltage may result in a DC bus voltage that ranges between 70-370V, depending on line and load conditions.
  • DC-DC converter 212 can produce an output voltage of 15Vdc. These example voltages are provided here for illustration, but the AC -DC converter may be designed with any suitable operating voltages.
  • the AC input voltage may be applied to a rectifier 210, which converts the AC input voltage Vin into a DC voltage that can be supplied to a power factor correction (PFC) stage 214.
  • rectifier 210 may be a diode bridge, either a full bridge or a half bridge.
  • rectifier 210 could include active/controlled switching devices, such as transistors, thyristors, or other suitable devices.
  • PFC stage 214 may be a switching converter such as a boost converter that draws current from the rectified AC input in phase with the voltage.
  • the output of PFC stage 214 can be a DC bus voltage Vb.
  • the DC bus may be supported by a DC bus capacitor Cb (which may act as a power buffer in a way analogous to that described above).
  • a DC-DC (D2D) converter 212 can receive the DC bus voltage Vb and produce an output DC voltage Vo suitable for the load to be powered.
  • the DC-DC converter may be a switching converter incorporating any of a variety of topologies. For personal computer power supplies (as in the example application mentioned above) LLC resonant converters are often used. However, any suitable converter topology, including flyback converters, buck converters, etc. could also be used as appropriate for a given application.
  • the AC input voltage may again range between 90-260Vac, which includes the nominal range of AC line voltages supplied in various countries around the world. Rectification of this voltage and operation of PFC stage 214 may result in a DC bus voltage of around 400V, due to the boost/PFC operation of PFC stage 214. (The DC bus voltage may be more accurately controlled/regulated in the multi-stage converter case.)
  • DC-DC converter 212 can, as in the preceding example, produce an output voltage of 15Vdc. These example voltages are provided here for illustration, but the AC -DC converter may be designed with any suitable operating voltages.
  • capacitor Cb acts as a power buffer to make up the difference between the instantaneous AC power and the DC power.
  • energy will be stored in the (passive) power buffer during a portion of the AC line cycle (when the input AC voltage and current are relatively high) and drawn from the (passive) power buffer during a portion of the AC line cycle (when the input AC voltage and current are relatively low).
  • the capacitance required may be relatively large. Again using a personal computer power supply as an example, with typical operating voltage and power requirements, the capacitance may range from several tens to hundreds of microfarads (or more). Capacitors used in such applications (e.g., electrolytic capacitors) with the required capacitance and voltage ratings may take up a relatively large volume that makes it difficult to incorporate them within the housing of some small or slim devices.
  • FIG. 3 illustrates a schematic of an AC -DC converter 300 with an active power buffer 318.
  • converter 300 includes a rectifier 210 that rectifies an AC input (e.g., having a range of 90- 264Vac) to a DC voltage.
  • This DC (rectified AC) voltage can then be supplied to the input of a flyback converter 316.
  • the output of flyback converter 316 can produce an output voltage Vo (again 15 V as in the examples discussed above, although other values are also possible).
  • a flyback converter can be advantageously used in AC -DC converter applications because it inherently provides galvanic isolation between the input and output.
  • Other converter topologies could be used in accordance with the teachings herein (such as an LLC or buck converter as discussed above), although such arrangements might require other arrangements for galvanic isolation (e.g., an isolation transformer).
  • Converter 300 may also include an output filter capacitor Co.
  • the most basic flyback converter includes a main switch QI, a flyback transformer T1 having primary winding Np and secondary winding Ns, and an output rectifier SRI.
  • Output rectifier SRI is illustrated as synchronous rectifier switch, although passive rectifier devices could also be used.
  • Flyback transformer T1 may also be thought of as mutually coupled flyback inductors Np and Ns. Additionally, these windings/inductors may have a turns ratio Np/Ns, which can scale the output voltage/current as desired. More complicated flyback converter designs, including various clamp circuits, resonant energy recovery circuits, etc. may also be used to provide for more efficient or otherwise optimized operation.
  • Basic flyback converter operation may be understood as follows: When main switch QI is turned on, a DC voltage is applied across primary winding Np, storing energy in the inductance of the flyback transformer. Because a DC voltage is applied to the primary winding, no current flows in the secondary winding Ns of flyback transformer Tl. When main switch QI is turned off, the energy stored in the inductance of flyback transformer causes the voltage across the primary winding to reverse, inducing current flow out of the secondary winding Ns of flyback transformer Tl. This discharges energy stored in the flyback transformer to the load through synchronous rectifier switch SRI. The cycle repeats when main switch QI is again closed, with the timing of this operation being controlled to provide regulation of the output voltage Vo.
  • Converter 300 does not include a passive power buffer capacitor Cb, such as those described above with reference to Figs. 1, 2A, and 2B. Rather, converter 300 incorporates an active power buffer (APB) 318.
  • Active power buffer 318 can include an energy storage capacitor Ca, switching devices Qal and Qa2, and inductor La. To achieve power buffering functionality, the combination of switches Qal and Qa2 with inductor La may be operated as a bi-directional buck-boost converter. More specifically, when the instantaneous power delivery of flyback converter 316 is greater than the power requirement of a connected load (not shown in Fig.
  • switches Qal, Qa2, and inductor La may operate as a boost converter to store excess energy in capacitor Ca (by charging capacitor Ca to a voltage higher than output voltage Vo).
  • switches Qal, Qa2, and inductor La may operate as a buck converter to discharge energy stored in capacitor Ca to the output bus for delivery to a connected load. Further details of the operation of active power buffer 318 are described in greater detail below.
  • the amount of energy stored in capacitor Ca is proportional to the capacitance of capacitor Ca and the square of the voltage across the capacitor.
  • the physical size of a capacitor of a given type is determined primarily by the energy storage capacity, /. ⁇ ., the rated voltage and the capacitance.
  • a capacitor Ca may be selected to have a physical size, capacitance, and voltage rating that allows for sufficient energy storage to achieve the power buffering functionality described herein.
  • the operating voltage of capacitor Ca can swing between a voltage that is slightly greater than the output DC bus voltage up to the voltage rating of the chosen capacitor or a substantial fraction thereof, which maximizes the capacitor’s energy storage capability.
  • the voltage across capacitor Ca might vary between 16-56V for the exemplary 15V output.
  • the operating voltages take on any values selected as suitable for a given application.
  • FIG. 4 illustrates active power buffer 318 in greater detail with associated current waveforms. More specifically, current 421 is the output current of flyback converter 316.
  • Current 423 is the input/output current of active power buffer 318. Positive current 423 corresponds to energy being stored in capacitor Ca by boost converter operation of switches Qal and Qa2 in conjunction with inductor La. Negative current 423 corresponds to energy being discharged from capacitor Ca by buck converter operation of switches Qal and Qa2 in conjunction with inductor La.
  • Current 425 is the load current supplied to a connected load (not shown in Fig. 4). These three currents sum to zero.
  • the output current of flyback converter 316 is a sinusoidal current ranging between zero and twice the load current Io at twice the line frequency.
  • the active power buffer current is a sinusoidal current ranging between negative Io and positive Io.
  • the load current is a DC current with magnitude Io.
  • the magnitude Io of the output current is the power requirement of a connected load (not shown in Fig. 4) divided by the output voltage Vo. It should be noted that these current waveforms 421, 423, and 425 generally correspond to the power waveforms 105 and 107 discussed above with reference to Fig. 1.
  • FIGs 5 A and 5B illustrate an AC -DC converter 300 with an active power buffer 318 and associated waveforms 503, 505, 521, 523, and 527.
  • Converter 300 is generally as discussed above with reference to Fig. 3, with various additional currents and voltages identified in the schematic of Fig. 5A. Plots of these current and voltage waveforms are plotted in Fig. 5B. More specifically AC input voltage Vin and AC input current lin are identified and plotted in Fig. 5B as waveforms 503a and 503b.
  • the product of the AC input voltage Vin and the AC input current lin is the instantaneous input power Pin, which is plotted in waveform 505, which corresponds to waveform 105 discussed above with respect to Fig. 1.
  • Flyback converter 316 has an output current ID2D/IFlyback (discussed above with reference to Fig. 4 as current 421), which is plotted in Fig. 5B as waveform 521.
  • Active power buffer has an input/output current lAPB/ILa (discussed above with reference to Fig. 4 as current 423), which is plotted in Fig. 5B as waveform 523.
  • storage capacitor Ca has an associated voltage Va and current lea. Voltage Va is plotted in Fig. 5B as waveform 527. Current lea is not plotted in Fig. 5B. [0056] Turning now to Fig. 5B, with reference to plot 503, the input AC voltage Vin/503a and input AC current Iin/503b are in phase.
  • the converter operates with unity power factor.
  • the input power Pin is the product of the input AC voltage 103a and the input AC current 103b Waveform 503 plots the instantaneous value of power Pin, which is a sinusoid having twice the frequency of the supplied line frequency.
  • This sinusoidal instantaneous power has a peak value of 2Pdc, a minimum value of zero, and an average value Pdc, corresponding to the power requirement of a connected load (not shown in Fig. 5 A).
  • the output current of flyback converter 316 (ID2D/IFlyback) is a sinusoidal current ranging between zero and twice the load current Io at twice the line frequency.
  • the active power buffer current IAPB (ILa) is a sinusoidal current ranging between negative Io and positive Io.
  • the voltage Va across capacitor Ca sinusoidally varies between a value slightly greater than the output voltage Vo (e.g., 16V vs. 15 V, as discussed above), with an average value Va avg.
  • This average value Va avg is used by the controller for the converter as described in greater detail below with reference to Fig. 6.
  • FIG. 6 illustrates an AC -DC converter 600 with an active power buffer 318 and an exemplary control system.
  • the control system includes flyback controller 640a and active power buffer 640b.
  • Flyback controller 640a can be operated to control the average voltage Va avg across capacitor Ca. This is distinct from conventional flyback converter controllers, which are controlled to regulate the output voltage of the flyback converter (Vo, in this case).
  • Setpoint Va avg may be selected based on the voltage swing and capacitance values as discussed above. For example, Va_avg may be halfway between the output voltage Vo (or slightly above for safety margin) and the peak voltage rating of capacitor Ca (or slightly below for safety margin).
  • flyback controller 640a may include a “slow” loop controller, such as a proportional, proportional-integral, or proportional-integral-derivative controller 642 that operates with a controller bandwidth that is less than twice the line frequency. This allows control of voltage Va to match the input-output power balance and provide unity power factor operation without being influenced by the twice line frequency ripple associated with the rectified AC input. Controller 642 is illustrated as error amplifier 642, which compares the difference between the instantaneous capacitor voltage Va with the Va avg setpoint.
  • the controller could be implemented using analog, digital, or hybrid analog/digital circuitry as well including using programmable controllers such as microcontrollers, microprocessors, field programmable gate arrays (FPGAs), etc., any or all of which may be integrated into an application specific integrated circuit (ASIC).
  • the controller/error amplifier is located on the secondary side of flyback converter and is coupled to the primary side by an optocoupler 643.
  • the feedback signal Va could be provided to the optocoupler, with the controller/error amplifier residing on the primary side.
  • the output signal of the slow loop regulating the capacitor voltage may be input into a pulse width modulation (PWM) controller 644 that generates drive signals for main switch QI.
  • PWM pulse width modulation
  • PWM controller could also generate corresponding drive signals for other components, such as auxiliary switches associated with a clamp or energy recovery circuit (not shown).
  • the PWM controller may employ constant on time control, in which the on time of main switch QI is modulated to provide the desired voltage Va across capacitor Ca.
  • the PWM controller may be integrated with the controller and may similarly employ any appropriate combination of analog, digital, and/or programmable circuitry.
  • Active power buffer controller 640b is a “fast” loop, which can operate much faster than the slow loop and the line frequency to regulate the output voltage Vo.
  • the fast loop may have a controller bandwidth on the order of kilohertz (kHz), tens of kHz, or even hundreds of kHz.
  • This controller may include a proportional, proportional-integral, or proportional-integral-derivative controller represented by error amplifier 646, which compares the output voltage Vo to output voltage setpoint Vo*.
  • this representation is illustrative, and the controller may be implemented with any appropriate combination of analog, digital, and/or programmable circuitry including various integrated controllers.
  • the resulting error signal can be provided to a PWM controller 648.
  • PWM controller 648 can implement duty cycle control of switches Qal and Qa2 to provide the desired bidirectional buck-boost operation.
  • the PWM controller may be integrated with the remainder of the fast control loop circuitry.
  • the controller may be similar to what would be used to implement a synchronous buck converter that generates a regulated voltage Vo from input voltage Va by operating a half bridge with upper switch Qal and lower switch Qa2 in conjunction with inductor La. Such control will operate upper switch Qal with a duty cycle that produces the desired bucking operation, with lower switch Qa2 having a substantially complementary duty cycle that acts as a synchronous rectifier.
  • substantially complementary means that when Qal is on, Qa2 is off, and vice-versa, except for an intervening “dead time.”
  • This intervening dead time may be a relatively short time (relative to the respective on times) and can be used to prevent shortcircuiting the half bridge.
  • this dead time could also be used (with appropriate additional circuitry) to allow for zero voltage switching of the respective switching devices.
  • flyback converter 316 When the instantaneous power production of flyback converter 316 is less than the power requirements of a connected load (not shown in Fig. 6), the control operation described above will cause active power buffer 318 to act as a buck converter supplying the power deficit to the connected load.
  • the control operation described above When the instantaneous power production of flyback converter 316 is greater than the power requirements of a connected load (not shown in Fig. 6), the control operation described above will cause active power buffer 318 to act as a boost converter supplying the power surplus to capacitor Ca.
  • controller 640b operates switches Qal and Qa2 to maintain voltage regulation of Vo from Va, and current will flow in the required direction to achieve this regulation.
  • control loops may include additional features, including without limitation, current limiting, overcurrent protection, zero voltage and/or zero current switching, and the like.
  • analog control loops based on error amplifiers
  • such circuitry could be implemented using any suitable analog, digital, and/or hybrid circuitry, based on discrete components, integrated circuits, ASICs, programmable processors such as microcontrollers, FPGAs, etc. Any and all such implementations may be configured to provide the functionality described above.
  • FIG. 7A illustrate AC -DC converters with active power buffers and split magnetics.
  • a converter 700a includes a rectifier 210 that receives an AC input voltage and provides a DC (rectified AC) input voltage to a flyback converter 716a that includes a split magnetics arrangement.
  • flyback transformers Tla and Tib which have their primary windings connected in series and their output windings coupled in parallel.
  • a single main switch QI is provided to drive the primary windings as discussed above.
  • Dual output rectifiers SRI a and SRlb are provided for reach respective secondary winding.
  • the combined output is then coupled to the converter output, and an active power buffer 318 is provided, which operates as described above. In this configuration, the operation of the respective transformers is synchronized, meaning that both are in the charge or discharge stage at the same time.
  • FIG. 7B illustrates an alternative converter 700b with a different input configuration. More specifically, the rectified AC input voltage from rectifier 210 is provided to a parallel combination of the primary windings of flyback transformers Tla and Tib. Each primary winding is controlled by a corresponding main switch Qla or Qlb. Thus, more specifically, the parallel combination is a parallel combination of the respective primary windings of the flyback transformers Tla and Tib and their corresponding main switches Qla and Qlb.
  • This configuration allows operation of the respective flyback transformers to be interleaved, meaning that flyback transformer Tla can be charging while Tib is discharging and vice versa.
  • Such an arrangement can use a single controller as described above with respect to Fig. 6, with complementary output PWM signals being supplied to the respective switches Qla and Qlb.
  • the secondary side of converter 700b is as described above with respect to Fig. 7A.
  • the converters above may exhibit undesirable transient behavior.
  • slow control loop 640a has a relatively low bandwidth. Because of this low bandwidth, the slow control loop, and thus the converter, may have a very limited dynamic response. For example, if load current suddenly increases, the input power (from the AC side) may be much lower than the output power (Volo). As a result, the energy stored in capacitor Ca will discharge to power the output, but for a large enough transient this can completely discharge capacitor Ca possibly causing the entire power supply to crash. A sudden load decrease can have the opposite effect. When the load current dramatically decreases, the input power may be much higher than the output power.
  • FIG 8 illustrates an additional or alternative control arrangement that can address these transient issues without unduly increasing the size of the capacitor in the active power buffer.
  • Converter 800 can employ bridge rectifier 210, flyback converter 316, and active power buffer 318 as was described above, for example with reference to Fig. 6. Additionally, can include three control loops 840a, 840b, and 840c that control switching of the main switch QI of flyback converter 316 to regulate the voltage Vb appearing across energy storage capacitor Cb of active power buffer 318.
  • Main control loop 840a can operate as generally described above, being a relatively slow control loop that effectively regulates the average voltage across capacitor Cb.
  • main control loop subtracts the voltage Vb from a reference voltage Vrefl in error amplifier 842a to produce an error signal Verrorl.
  • This error signal may be input into a compensator 845a that may be a proportional, integral, and/or derivative controller that implements a suitable transfer function to achieve desired control responsiveness and stability.
  • Compensator 845a (along with all control circuitry of control loop 840b) may be implemented using any combination of analog, digital, and/or programmable circuitry, as was described above.
  • the output of compensator 845a can be a first current reference signal Irefl that goes through a selection process described in greater detail below with reference to selectors 851b and 851c.
  • the selected current reference signal can be provided to current controller 852, which can provide suitable control signals to PWM generator 644 to regulate the switching of main switch QI of flyback converter 316.
  • Control loop 840b can be a faster control loop that can be active only in response to increasing load transients.
  • the load current can be input into an averaging circuit 847b that generates an average load current signal Iload avgl. This may be summed with an offset value Offset l using summing circuitry 849b and input into the negative/inverting input of a comparator 850b.
  • the instantaneous load current signal may be input into the positive/non-inverting input of comparator 850b.
  • comparator 850b can output an Enable signal that activates compensator 845b only in response to an instantaneous load current that exceeds the average load current by a predetermined offset amount. This current condition would correspond to a significant load increase at the output of converter 800.
  • Fast control loop for load ramp up control loop 840b can therefore operate as generally described above, being a relatively faster control loop that effectively regulates the voltage across capacitor Cb in response to an increasing load. To do so, fast load ramp up control loop 840b subtracts the voltage Vb from a reference voltage Vref2 equal to Vrefl-AV in error amplifier 842b to produce an error signal Verror2. (The reference voltage may be offset by AV to reflect voltage dip associated with an increasing load transient.) Error signal Verror2 may be input into a compensator 845b that may be a proportional, integral, and/or derivative controller that implements a suitable transfer function to achieve desired control responsiveness and stability.
  • Compensator 845b (along with all control circuitry of control loop 840b) may be implemented using any combination of analog, digital, and/or programmable circuitry, as was described above.
  • the output of compensator 845b can be a second current reference signal Iref2 that goes through a selection process described in greater detail below with reference to selectors 851b and 851c.
  • the selected current reference signal can be provided to current controller 852, which can provide suitable control signals to PWM generator 644 to regulate the switching of main switch QI of flyback converter 316.
  • Control loop 840c can be a faster control loop that can be active only in response to decreasing load transients.
  • the load current can be input into an averaging circuit 847c that generates an average load current signal Iload_avg2. This may be summed with an offset value Offset_2 using summing circuitry 849c and input into the positive/non-inverting input of a comparator 850c.
  • the instantaneous load current signal may be input into the negative/inverting input of comparator 850c.
  • comparator 850c can output an Enable signal that activates compensator 845c only in response to an instantaneous load current that is below the average load current by a predetermined offset amount. This current condition would correspond to a significant load decrease at the output of converter 800.
  • Fast control loop for load dump control loop 840c can therefore operate as generally described above, being a relatively faster control loop that effectively regulates the voltage across capacitor Cb in response to a decreasing load. To do so, fast load dump control loop 840c subtracts the voltage Vb from a reference voltage Vref3 equal to Vrefl+AV in error amplifier 842c to produce an error signal Verror3. (The reference voltage may be offset by AV to reflect voltage increase associated with a decreasing load transient.) Error signal Verror3 may be input into a compensator 845c that may be a proportional, integral, and/or derivative controller that implements a suitable transfer function to achieve desired control responsiveness and stability.
  • Compensator 845c (along with all control circuitry of control loop 840c) may be implemented using any combination of analog, digital, and/or programmable circuitry, as was described above.
  • the output of compensator 845c can be a third current reference signal Iref3 that goes through a selection process described in greater detail below with reference to selectors 851b and 851c.
  • the selected current reference signal can be provided to current controller 852, which can provide suitable control signals to PWM generator 644 to regulate the switching of main switch QI of flyback converter 316.
  • the control system can select from the reference signals generated by the respective control loops.
  • a first selector 85 lb can receive the output reference signals Irefl from control loop 840a and Iref2 from control loop 840b.
  • Selector 851b can be a high selector that selects the higher reference signal, /. ⁇ ., the signal commanding the largest current.
  • the reference signal Irefl output from main control loop 840a would be selected, whereas for a load ramp up transient condition, the reference signal Iref2 from control loop 840b.
  • the output of high selector 851b can be provided as a first input to low selector 851c, which can also receive the output reference signal output from control loop 840c.
  • Low selector 851c can be configured to select the lower reference signal, /. ⁇ ., the signal commanding the smallest current.
  • the reference signal from the main control loop 840a (or the load ramp up control loop 840c, as appropriate) would be selected.
  • the reference signal Iref3 from control loop 840c would be selected.
  • power factor corrected converter 900 can include a rectifier 210, power factor correction converter 214, and DC-DC converter 212 that function as described above.
  • PFC converter 214 may be controlled by a control loop responsive to the intermediate bus voltage Vb (coupling the output of PFC converter 214 to the input of DC-DC converter 212).
  • PFC converter control loops may be configured to be relatively slow loops, /. ⁇ ., having a bandwidth less than about half the line frequency of the AC input, to provide the desired power factor and harmonic distortion improvements.
  • Such converters can be susceptible to the same sort of transient stability problems described above with respect to the converter of Fig. 8.
  • a brute force approach to these issues can be to increase the size of capacitor Cb; however, this may not be desirable depending on the physical constraints of a given implementation.
  • the first control target is to maintain stable output voltage to achieve AC input and DC output power balance over a AC line cycle.
  • the second control target is to achieve the sinusoidal input current by either regulating PFC inductor current or directly regulating the turn-on time of the main switch for the PFC converter.
  • the first control target can be realized by a voltage control loop, in which the PFC output voltage Vb is measured, compared with a reference Vref, and their error Verror is amplified by a compensator, with the compensator output A/used as the reference for the current controller that controls switching of the PFC converter switching device.
  • the current controller can be designed to regulate the AC input current so that it is sinusoidal and in line with AC input voltage to achieve the second target, and also to regulate the magnitude of the AC input current to follow the reference A/ from the voltage control loop.
  • Figure 9 also shows key waveforms of an AC -DC power supply with PFC functionality.
  • Waveform 961 /( A and waveform 962// ac are the instantaneous AC input voltage and current.
  • Waveform 963/Pac is the instantaneous input power, which is the product of the instantaneous input voltage and current.
  • the input power can be thought of as including two parts: the first part being constant and equal to the output DC power Pdc/964 (if the power loss is neglected).
  • the second part of the input power is pulsating with a frequency that is twice the AC power source frequency.
  • the pulsating power flows into and out of the bulk capacitor Cb and causes the voltage ripple of twice AC source frequency, as shown in waveform 965/Vb.
  • the compensator in 945a can be designed to limit the bandwidth of the voltage control loop for the PFC converter, for example to under 20Hz, so that the PFC converter has sufficient attenuation to the PFC converter output voltage ripple of the twice AC power source frequency.
  • the relatively low bandwidth of the PFC voltage control loop effectively attenuates the third harmonic current in the input AC current; however, it adversely reduces the load transient performance of PFC converters.
  • the DC output power suddenly increases or decreases, a large output voltage undershoot or overshoot can occur. In extreme cases, such DC load transients may cause the power supply crash.
  • the AC input power of the power supply is less than the DC output power, the energy stored in the bulk capacitor Cb has to be discharged to provide the energy to the DC load, so there will be a undershoot across PFC converter output voltage Vb .
  • the bandwidth of the voltage control loop for the PFC converter is relatively low, it will take a relatively long time (e.g., ⁇ 10ms or more) for the voltage control loop to catch the load change and restore the balance between the AC input power and the DC load power. If the capacitor Cb is not large enough to sustain the energy discharge during the load transient, the Vb will have a large dip and that can crash the power supply.
  • a large capacitor Cb may be used, but as noted above, this may be undesirable for packaging or other reasons.
  • PFC converter topologies such as boost PFC, flyback PFC, etc.
  • current control methods such as average current control, peak current control, hysteresis current control, constant on-time control, etc.
  • the proposed control method consists of two voltage control loops for PFC converters.
  • the compensation network Compensator ! forms the main voltage control loop for the PFC converter, and this main loop of low bandwidth regulates the PFC converter to achieve the balance between the input power and output power and high power factor performance in steady state, same as the existing PFC voltage control method.
  • the measured PFC output voltage Vb is compared with the reference Vrefj in error amplifier 942a, and their error Ve o j is amplified by Compensator ! 945a.
  • the compensation network Compensator ! is used to adjust the bandwidth of the voltage loop.
  • the output signal of Compensator I re fj is used as the reference for the current controller.
  • the bandwidth of the main voltage loop is under 20Hz to meet the requirement of power factor and harmonic distortion.
  • control loop 940b can have a significantly higher bandwidth than the slow main control loop 940a.
  • main control loop 940a can have a bandwidth on the order of a few tens of hertz, e.g., 20-30Hz, while the fast control loop 940b can have a bandwidth on the order of hundreds of hertz or even into the multiple kilohertz range.
  • fast loop 940b can be disabled as described in greater detail below.
  • the output of Compensator_2945b is zero, so that fast loop 940b does not have any impact on steady state operation of the PFC converter 214.
  • Fast loop 940b is only enabled during load transients. In the event of a load ramping up, the fast control loop can quickly respond to the output voltage drop of PFC converter 214. More specifically, the error signal Verrorj that is the difference between Vref and Vb produced by error amplifier 942b can be quickly amplified by Compensator_2, such that the Compensator_2 output Irefj quickly increases and becomes the dominant component of the current reference I re /that is provided to the current controller 952.
  • the current controller 952 can provide suitable control signals to PWM generator 944.
  • the duty cycle of PFC converter 214 can be quickly changed to force the PFC converter input current to track the reference Iref output by summing circuitry 951, ultimately restoring the power balance between AC input and DC output.
  • the AC -DC power supply need not rely on a large capacitor Cb to sustain the load transients.
  • the reference voltages Vrefj and Vrefj for the respective control loops could be the same or different.
  • fast voltage control loop 940b can be enabled by load transient events.
  • One circuit arrangement for detecting load transient events is shown in Fig. 9.
  • the instantaneous DC output load current oad can be measured, and compared with hoad_av g , the averaged load current over a period T ave . If the instantaneous load current is the same as the average load current, then the AC -DC power supply is operating in a steady state, and the fast voltage control loop can be disabled. Conversely, if the measured instantaneous load current is (significantly) different than the averaged load current, then a load transient event, either load ramping up or load ramping down, is occurring.
  • fast control loop 940b is similar in concept and construction to the fast control loops 840b and 840c discussed above. Additionally, they can likewise be constructed using any appropriate combination of analog, digital, and/or programmable circuitry like the various control circuits discussed above.
  • FIG. 10A illustrates one implementation of the proposed control strategy for a converter 1000a that includes a Boost PFC converter 1014a that can operate in a critical conduction mode (CCM).
  • the DC/DC converter 212 can be any topology, such as an LLC resonant converter, a flyback converter, a forward converter, etc.
  • the control strategy can be implemented by one relatively slow main voltage loop 1040a and two fast voltage control loops 1040b and 1040c. Each of these control loops may operate along principles generally similar to those discussed above with respect to Figs. 8 and 9.
  • the main voltage control loop which can have a lower bandwidth on the order of about 20Hz or less
  • the measured PFC output voltage Vb can be compared with the reference ej j, with their error Verror i being amplified by the compensator network Compensator !, which can output a current reference I re f_i.
  • the second control loop 1040b can be a fast voltage loop that only functions as the load power ramps up and is disabled when the power supply operates in steady state.
  • Boost PFC converter output voltage Vb can be measured and compared with the reference Vref_2.
  • the compensator network Compensator_2 processes their voltage error Verrorj and generates a current reference I re f_2.
  • efj and Ay _i can be compared, with the higher one used as the reference I re j2.
  • the main voltage loop is in control, and I re f_i2 and Iref are equal to Irefj.
  • BoostPFC converter 1014a can quickly respond Io Iref 2 to increase the AC input current, quickly restoring the balance between AC input power and DC load power without crashing the power supply.
  • the third control loop 1040c can also be a fast voltage loop that only functions as the load power ramps down and is disabled when the power supply operates in steady state.
  • Boost PFC converter output voltage Vb can be measured and compared with the reference Vrefj.
  • the compensator network Compensator_3 processes their voltage error V error j and generates a current reference Irefj.
  • Iref and Ay j2 can be compared, with the lower one used as the reference ref.
  • the main voltage loop is in control, and Iref_i2 and Iref are equal to Irefj .
  • the second fast control loop 1040c is in control, and Iref is equal to Irefj.
  • Boost PFC converter 1014a can quickly respond to Irefj to decrease the AC input current, quickly restoring the balance between AC input power and DC load power without causing an excessive voltage overshoot, which could potentially damage various power supply components.
  • FIG. 10B illustrates another implementation of the proposed control strategy for a converter 1000b that includes a flyback PFC converter 1014b that can operate using on time control.
  • the DC/DC converter 212 can be any topology, such as an LLC resonant converter, a flyback converter, a forward converter, buck converter, boost converter, buck-boost converter, etc.
  • the control strategy can be implemented by one relatively slow main voltage loop 1040a and two fast voltage control loops 1040b and 1040c. Each of these control loops may operate along principles generally similar to those discussed above with respect to Figs. 8, 9, and 10A.
  • the main voltage control loop which can have a lower bandwidth on the order of about 20Hz or less, the measured PFC output voltage Vb can be compared with the reference Vrefj, with their error Verror j being amplified by the compensator network Compensator !, which can output a current reference Iref .
  • the second control loop 1040b can be a fast voltage loop that only functions as the load power ramps up and is disabled when the power supply operates in steady state.
  • Boost PFC converter output voltage Vb can be measured and compared with the reference Vref
  • the compensator network Compensator_2 processes their voltage error Verror and generates a current reference Irefj.
  • Irefj and Ay _i can be compared, with the higher one used as the reference I re / 72.
  • the main voltage loop is in control, and I re f_i2 and Tre/are equal to Irefj.
  • Boost PFC converter 1014a can quickly respond to Irefj to increase the AC input current, quickly restoring the balance between AC input power and DC load power without crashing the power supply.
  • the third control loop 1040c can also be a fast voltage loop that only functions as the load power ramps down and is disabled when the power supply operates in steady state.
  • Flyback PFC converter output voltage Vb can be measured and compared with the reference Vref .
  • the compensator network Compensator_3 processes their voltage error V error and generates a current reference Iref .
  • Iref and Ay j2 can be compared, with the lower one used as the reference Ire/.
  • Iref_i2 and Iref are equal to Irefj.
  • the second fast control loop 1040c is in control, and Iref is equal to Iref .
  • Flyback PFC converter 1014b can quickly respond to Iref to decrease the AC input current, quickly restoring the balance between AC input power and DC load power without causing an excessive voltage overshoot, which could potentially damage various power supply components.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Un convertisseur de puissance peut comprendre un étage de convertisseur C.C.-C.C. comportant une entrée couplée à une entrée du convertisseur de puissance et une sortie couplée à une sortie du convertisseur et un tampon de puissance active couplé à la sortie du convertisseur de puissance. Le tampon de puissance active peut en outre comprendre un condensateur d'accumulation d'énergie et un ou plusieurs dispositifs de commutation couplant sélectivement le condensateur d'accumulation d'énergie à la sortie du convertisseur de puissance de façon à accumuler alternativement de l'énergie dans le condensateur d'accumulation d'énergie et à décharger l'énergie du condensateur accumulation d'énergie. Un circuit de commande du convertisseur de puissance peut comprendre une première boucle de commande qui actionne l'étage de convertisseur C.C.-C.C. pour réguler une tension moyenne à travers le condensateur d'accumulation d'énergie du tampon de puissance active et une seconde boucle de commande qui actionne le ou les dispositifs de commutation du tampon de puissance active pour réguler une tension de sortie du convertisseur de puissance.
PCT/US2023/013062 2022-02-28 2023-02-14 Alimentation électrique à tampon de puissance active WO2023163876A1 (fr)

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US202263268665P 2022-02-28 2022-02-28
US63/268,665 2022-02-28
US17/663,143 US20230275521A1 (en) 2022-02-28 2022-05-12 Power supply with active power buffer
US17/663,136 US11894779B2 (en) 2022-02-28 2022-05-12 Power supply with active power buffer
US17/663,141 US20230275520A1 (en) 2022-02-28 2022-05-12 Power supply with active power buffer
US17/663,143 2022-05-12
US17/663,136 2022-05-12
US17/663,141 2022-05-12

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