WO2023116245A1 - 发送方法、接收方法、装置、系统、设备及存储介质 - Google Patents

发送方法、接收方法、装置、系统、设备及存储介质 Download PDF

Info

Publication number
WO2023116245A1
WO2023116245A1 PCT/CN2022/130861 CN2022130861W WO2023116245A1 WO 2023116245 A1 WO2023116245 A1 WO 2023116245A1 CN 2022130861 W CN2022130861 W CN 2022130861W WO 2023116245 A1 WO2023116245 A1 WO 2023116245A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
data block
fec
decoding
data blocks
Prior art date
Application number
PCT/CN2022/130861
Other languages
English (en)
French (fr)
Inventor
刘永志
陆玉春
李亮
马林
邱贤文
刘建强
丁力
章成旻
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22909562.5A priority Critical patent/EP4440015A1/en
Publication of WO2023116245A1 publication Critical patent/WO2023116245A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used

Definitions

  • the present application relates to the technical field of communications, and in particular to a sending method, a receiving method, a device, a system, a device, and a storage medium.
  • forward error correction forward error correction
  • Ethernet Ethernet
  • PCIe peripheral component interconnect express
  • the embodiments of the present application provide a sending method, receiving method, device, system, equipment, and storage medium, which can not only retain the error correction capability of high-gain FEC codes, but also reduce the impact of high-gain FEC on The effect of delay.
  • the present application provides a sending method, the method comprising: acquiring multiple data blocks; generating multiple first check digits, multiple first check digits and multiple data blocks according to the multiple data blocks One-to-one correspondence, and generate forward error correction FEC parity bits according to multiple data blocks, so as to obtain encoded data blocks; send encoded data blocks.
  • a corresponding first parity bit is added to each data block to provide a certain error detection capability, so the corresponding data blocks can be respectively checked by multiple first parity bits.
  • An independent check is used to determine whether there is an error in each data block, so that the error prediction in the coded data block can be realized.
  • the embodiment of the present application also adds FEC parity bits to these multiple data blocks (the FEC parity bits can be generated according to the FEC encoding of the above-mentioned multiple data blocks) to provide a certain error correction capability, so the FEC check can be passed.
  • the bits correct errors in the encoded data block (or in other words, the above-mentioned plurality of data blocks in the encoded data block).
  • two different processing granularities can be used for error detection and error correction, and there is an inclusive relationship between the two processing granularities, wherein, error detection takes a data block as the processing granularity, and error correction It is wrong to treat the entire coded data block (or multiple data blocks) as the processing granularity, and the coded data block contains multiple data blocks. Therefore, the decoding method corresponding to the coded data block becomes very flexible, which helps to reduce the influence of delay and power consumption of FEC decoding, and helps to realize FEC with low delay and high gain.
  • generating a plurality of first check digits according to a plurality of data blocks includes: respectively encoding the data of the plurality of data blocks by one or more encoding methods , thereby generating a plurality of first check digits.
  • the first parity bit corresponding to each data block can be generated by performing one or more types of encoding on the data of the data block. Therefore, the design of the first parity bit becomes very flexible, which helps to control the length of the first parity bit, reduces bandwidth occupation, and also makes the design of the length of the data block more flexible, and helps to improve the length of the first parity bit.
  • the reliability of the check digit reduces the probability of false missed detection.
  • the generating the FEC check bits according to the multiple data blocks includes: generating the FEC check bits according to the multiple data blocks and the multiple first check bits.
  • the FEC check bit can not only find and correct errors in the plurality of data blocks in the coded data block, but can also find and correct errors in the first check bit.
  • an embodiment of the present application provides a receiving method, the method including: acquiring a coded data block, wherein the coded data block includes multiple data blocks, multiple first parity bits and FEC parity bits, multiple The first parity bit corresponds to multiple data blocks one by one, and the FEC parity bit corresponds to multiple data blocks; check the corresponding data blocks according to multiple first parity bits and/or FEC parity bits to obtain encoded data The decoding result of the block.
  • the multiple first check digits in the coded data block correspond to multiple data blocks one by one
  • the FEC check digit corresponds to multiple data blocks (or corresponds to the entire coded data block) Therefore, the corresponding data blocks can be checked respectively by using a plurality of first check bits, and the multiple data blocks can also be checked by using the FEC check bits, so as to obtain the decoding result of the coded data block.
  • the decoding method corresponding to this coded data block can be very flexible, which helps to reduce the impact of delay and power consumption of FEC decoding, and helps to realize FEC with low delay and high gain.
  • the verifying the corresponding data block according to a plurality of first check bits and/or FEC check bits to obtain a decoding result of the coded data block includes: The first parity bit respectively checks whether there is an error in the corresponding data block; in the case that multiple data blocks are checked for errors, perform FEC decoding on multiple data blocks according to the FEC parity bit to obtain the decoding of the encoded data block code result.
  • the embodiment of the present application checks the corresponding data blocks according to the plurality of first check digits to respectively determine whether there is an error in each data block. That is to say, the error detection is based on the data block as the processing granularity.
  • Each data block in the data block can be checked independently, so as to realize the prediction of errors in the coded data block.
  • the multiple data blocks can be FEC decoded according to the FEC parity bit, To obtain the decoding result of the coded data block. It can be understood that because FEC decoding needs to be started and FEC decoding delay is introduced only when there is an error, it can reduce the delay impact and power consumption impact of FEC decoding, and help to achieve low delay and High gain FEC.
  • the method further includes: taking the multiple data blocks as decoding results of the coded data block when no error is detected in the multiple data blocks.
  • FEC decoding is performed on multiple data blocks according to the FEC parity bit to obtain a decoding result of the coded data block , including: in the case that the first data block does not check out an error, the first data block is used as the decoding result of the first data block, and the first data block is a data block in a plurality of data blocks; in the second In the case of an error in the data block verification, FEC decoding is performed on multiple data blocks according to the FEC parity bit to obtain FEC decoding data, and the data corresponding to the second data block in the FEC decoding data is used as the second data block For the decoding result, the second data block is a data block in the plurality of data blocks; the decoding results of the plurality of data blocks are used as the decoding results of the coded data block.
  • the multiple data blocks in the coded data block are respectively subjected to error detection according to their corresponding first parity bits.
  • the data block can be directly used as its own decoding result; Perform FEC decoding on the multiple data blocks (or the entire encoded data block) to obtain FEC decoded data.
  • the data corresponding to the data block in the FEC decoded data is after the error of the data block is corrected. The data.
  • error detection is processed at the granularity of data blocks, and the coded data block contains multiple data blocks, so each data block in the coded data block can be checked independently to realize the prediction of errors in the coded data block; and error correction Multiple data blocks are used as the processing granularity, and errors existing in multiple data blocks (including errors existing in each data block) can be corrected at one time. Finally, the decoding results corresponding to the plurality of data blocks are combined as the decoding result of the coded data block.
  • the multiple data blocks have a sequence; the checking whether there is an error in the corresponding data block according to the multiple first check digits includes: according to the multiple first check digits check whether there is an error in the corresponding data block in sequence; the data corresponding to the second data block in the FEC decoding data is used as the decoding result of the second data block, including: the second data block and the second data block after the second data block Data corresponding to other data blocks in the FEC decoded data are respectively used as decoding results of the second data block and other data blocks after the second data block.
  • the check of the multiple data blocks according to the multiple first check digits may be performed sequentially.
  • the data block is directly used as its own decoding result.
  • the verifying the corresponding data block according to a plurality of first check bits and/or FEC check bits to obtain a decoding result of the coded data block includes: The first parity bit respectively checks whether there is an error in the corresponding data block, and performs FEC decoding on multiple data blocks according to the FEC parity bit to obtain FEC decoded data; when multiple data blocks are checked for errors , and obtain a decoding result of the coded data block according to the FEC decoding data.
  • the corresponding data blocks can be checked respectively according to a plurality of first check bits to determine whether there are errors in the multiple data blocks, and FEC is performed on the multiple data blocks according to the FEC check bits.
  • Decode to obtain FEC decoded data That is to say, the error detection is based on the data block as the processing granularity, and the coded data block contains multiple data blocks, so each data block in the coded data block can be checked independently to realize the prediction of errors in the coded data block; Error correction takes multiple data blocks as the processing granularity, and errors of multiple data blocks (including errors existing in each data block) can be corrected at one time.
  • error detection and error correction adopt two different processing granularities, and the two processing granularities have an inclusion relationship, that is, a coded data block includes multiple data blocks.
  • the data corresponding to the data block in the FEC decoding data is the data after the error correction of the data block; if there is no error in a certain data block, then the data block in the FEC decoding The corresponding data in the code data has not undergone error correction, and is the same as the data of the data block itself.
  • the decoding result of the encoded data block can be obtained according to the FEC decoding data.
  • the error detection with data block as the processing granularity and the error correction with multiple data blocks as the processing granularity can be executed in parallel, which is beneficial to reduce the delay impact of FEC decoding.
  • the checking the corresponding data block according to the multiple first check bits and/or FEC check bits to obtain the decoding result of the coded data block further includes: If there is no error detected in the data blocks, multiple data blocks are used as the decoding results of the coded data blocks.
  • the decoding result of the encoded data block is obtained according to the FEC decoding data, including: When an error is detected, the first data block is used as the decoding result of the first data block, and the first data block is a data block in a plurality of data blocks; when an error is detected in the second data block, The data corresponding to the second data block in the FEC decoding data is used as the decoding result of the second data block, and the second data block is a data block in a plurality of data blocks; the decoding results of the plurality of data blocks are used as encoding The decoding result of the data block.
  • the data of the data block is directly used as the decoding result of the data block.
  • a certain data block checks out an error based on its corresponding first parity bit
  • the corresponding data in the data is used as the decoding result of the data block.
  • the decoding results corresponding to the respective data blocks in the encoded data block are combined as the decoding result of the encoded data block.
  • the multiple data blocks have a sequence; the checking whether there is an error in the corresponding data block according to the multiple first check digits includes: according to the multiple first check digits check whether there is an error in the corresponding data block in sequence; the data corresponding to the second data block in the FEC decoding data is used as the decoding result of the second data block, including: the second data block and the second data block after the second data block Data corresponding to other data blocks in the FEC decoded data are respectively used as decoding results of the second data block and other data blocks after the second data block.
  • the multiple data blocks in the coded data block can have a sequence, and the checks on the multiple data blocks according to the multiple first check digits can be performed sequentially, and the data blocks in the first order are prioritized. Perform verification (ie, error detection).
  • the data of the data block is directly used as the decoding result of the data block.
  • the data corresponding to the data block and other subsequent data blocks in the FEC decoding data are respectively used as decoding results of the data block and other subsequent data blocks. Then, the error detection results of other data blocks after this data block can be ignored, or even the error detection of other data blocks after this data block can be stopped, and the decoding results of each data block can be directly integrated as the decoding result of this coded data block. code result. It not only realizes the error correction, ensures the output bit error rate, but also helps to reduce the delay.
  • the embodiment of the present application provides a device, which includes: an acquisition module, configured to acquire multiple data blocks; a processing module, configured to generate multiple first check digits according to the multiple data blocks, multiple A first parity bit is in one-to-one correspondence with a plurality of data blocks, and a forward error correction FEC parity bit is generated according to the plurality of data blocks, thereby obtaining a coded data block; a sending module is used for sending the coded data block.
  • said generating a plurality of first check digits respectively according to a plurality of data blocks includes: respectively encoding the data of a plurality of data blocks by one or more encoding methods to generate a plurality of first check digits. Check Digit.
  • the generating the FEC check bits according to the multiple data blocks includes: generating the FEC check bits according to the multiple data blocks and the multiple first check bits.
  • the embodiment of the present application provides another device, which includes: an acquisition module, configured to acquire a coded data block, wherein the coded data block includes multiple data blocks, multiple first check digits, and FEC parity Check digits, multiple first check digits correspond to multiple data blocks one-to-one, FEC check digits correspond to multiple data blocks; processing module, used for multiple first check digits and/or FEC check digits The corresponding data block is verified to obtain a decoding result of the encoded data block.
  • an acquisition module configured to acquire a coded data block, wherein the coded data block includes multiple data blocks, multiple first check digits, and FEC parity Check digits, multiple first check digits correspond to multiple data blocks one-to-one, FEC check digits correspond to multiple data blocks
  • processing module used for multiple first check digits and/or FEC check digits The corresponding data block is verified to obtain a decoding result of the encoded data block.
  • the verifying the corresponding data block according to the multiple first check bits and/or the FEC check bits to obtain the decoding result of the coded data block includes: according to the multiple first check bits Check whether there is an error in the corresponding data block respectively; in the case that multiple data blocks are checked for errors, perform FEC decoding on the multiple data blocks according to the FEC parity bit to obtain a decoding result of the encoded data block.
  • the method further includes: taking the multiple data blocks as decoding results of the coded data block when no error is detected in the multiple data blocks.
  • performing FEC decoding on multiple data blocks according to the FEC parity bit to obtain a decoding result of the coded data block includes: In the case that a data block does not check out an error, the first data block is used as the decoding result of the first data block, and the first data block is a data block in the plurality of data blocks; In the case of an error, perform FEC decoding on a plurality of data blocks according to the FEC parity bit to obtain FEC decoding data, and use the corresponding data of the second data block in the FEC decoding data as the decoding result of the second data block, The second data block is one of the multiple data blocks; the decoding results of the multiple data blocks are used as the decoding results of the coded data block.
  • the verifying the corresponding data block according to the multiple first check bits and/or the FEC check bits to obtain the decoding result of the coded data block includes: according to the multiple first check bits Check whether there are errors in the corresponding data blocks, and perform FEC decoding on multiple data blocks according to the FEC parity bit to obtain FEC decoded data; The data gets the decoded result of the coded data block.
  • the FEC decoding is performed on the multiple data blocks to obtain the FEC decoding Code data, these two actions are executed in parallel.
  • the verifying the corresponding data block according to the multiple first check bits and/or FEC check bits to obtain the decoding result of the coded data block further includes: If an error is detected, a plurality of data blocks are used as the decoding result of the coded data block.
  • said obtaining the decoding result of the coded data block according to the FEC decoding data in the case where errors are detected in multiple data blocks includes: when no error is detected in the first data block Next, the first data block is used as the decoding result of the first data block, and the first data block is one of the multiple data blocks; when an error is detected in the second data block, the second data block is The data corresponding to the block in the FEC decoding data is used as the decoding result of the second data block, and the second data block is a data block in the multiple data blocks; the decoding results of the multiple data blocks are used as the coded data block decoding result.
  • an embodiment of the present application provides a system, including the device in any one of the embodiments in the third aspect and the device in any one of the embodiments in the fourth aspect.
  • the embodiment of the present application provides a device, including a processor and a memory; the processor and the memory may be connected to each other through a bus, or may be integrated together.
  • the processor is configured to read the program code stored in the memory, so that the device executes the method in any embodiment of the first aspect or the second aspect above.
  • the embodiment of the present application provides a computer-readable storage medium; the computer-readable storage medium is used to store the implementation code of the method in any one of the above-mentioned first aspect or the second aspect.
  • the embodiment of the present application provides a computer program (product), the computer program (product) includes program instructions, and when the computer program product is executed, it is used to perform the above-mentioned first aspect or the second aspect.
  • the embodiment of the present application provides a chip, the chip is used to implement the method in any one of the embodiments in the first aspect or the second aspect.
  • a corresponding first parity bit is generated for multiple data blocks, and a corresponding FEC parity bit is jointly generated for multiple data blocks, so that the receiving end can pass A plurality of first check digits respectively checks whether there is an error in the corresponding data block, realizes the prediction of the error in the encoded data block, and also enables the receiving end to detect the errors in the multiple data blocks through the FEC check digit Make corrections. Therefore, the receiving end can flexibly design the decoding mode of the coded data block, which helps to reduce the delay impact and power consumption impact of FEC decoding, and helps to achieve low delay and high gain.
  • the decoding result of the encoded data block can be obtained according to a plurality of first check bits and/or FEC check bits in the encoded data block, mainly divided into starting FEC on demand.
  • the data of the coded data block is used as the decoding result of the coded data block; if the multiple data blocks are checked for errors (that is, at least one of the multiple data blocks is checked for an error), the FEC function needs to be started, according to The FEC parity bit performs FEC decoding on these multiple data blocks to obtain FEC decoding data. For data blocks that have not been checked out, the data of the data block can be directly used as the decoding result of the data block.
  • the data corresponding to the data block and other data blocks after it in the FEC decoding data are used as the decoding results of this data block and other data blocks after it, so other data blocks after this data block can be ignored
  • the verification result of the coded data block can even stop the verification of other data blocks after the data block in the coded data block. It can be understood that because FEC decoding needs to be started and FEC decoding delay is introduced only when there is an error, it can reduce the delay impact and power consumption impact of FEC decoding, and help to achieve low delay and high gain.
  • the parallel error detection and error correction scheme it is possible to check whether the corresponding data blocks have errors according to multiple data blocks, and perform FEC decoding on multiple data blocks according to the FEC parity bits to obtain FEC decoded data.
  • the actions of error detection and error correction can be performed in parallel.
  • no errors are found in the multiple data blocks, there is no need to wait for/use the above-mentioned FEC decoding data, and directly use the data of the multiple data blocks as the decoding result of the coded data block.
  • the above-mentioned FEC decoding data needs to be used.
  • the data of the data block can be directly used as the decoding result of the data block.
  • the data corresponding to the data block in the FEC decoding data is used as the decoding result of the data block, and finally the decoding results of each data block are comprehensively used as the decoding of the encoded data block result.
  • the order of multiple data blocks can also be considered here, and the verification is performed sequentially.
  • the data block and other subsequent data blocks are included in the FEC decoding data.
  • the corresponding data are respectively used as the decoding results of the data block and other data blocks after it, so the verification results of other data blocks after this data block can be ignored, and even the coded data block after this data block can be stopped. Checksum of other data blocks.
  • FIG. 1 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a sending device provided in an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another sending device provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a receiving device provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another receiving device provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another receiving device provided by an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a sending method provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a processing flow of a sending device provided in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of dividing valid data into data blocks of a set length provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a physical verification unit provided by an embodiment of the present application.
  • Fig. 11 is another schematic diagram of dividing valid data into data blocks of a set length provided by the embodiment of the present application.
  • Fig. 12 is a schematic diagram of a combination of BCH coding and CRC coding provided by the embodiment of the present application.
  • FIG. 13 is a schematic diagram of dividing valid data into fixed-length data blocks provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of using a data block in a physical check unit as an FEC payload provided by an embodiment of the present application;
  • Fig. 15 is a schematic diagram of using both the valid data in the physical check unit and the BCH check bit as the FEC payload provided by the embodiment of the present application;
  • Fig. 16 is a schematic diagram of a physical verification unit provided by an embodiment of the present application.
  • Fig. 17 is a schematic diagram of a data block and an eBCH check bit in a physical check unit provided by an embodiment of the present application as an FEC payload;
  • Fig. 18 is a schematic diagram of using only the data block in the physical check unit as the FEC payload provided by the embodiment of the present application;
  • Fig. 19 is a schematic flowchart of another sending method provided by the embodiment of the present application.
  • FIG. 20 is a schematic diagram of a processing flow of a sending device provided in an embodiment of the present application.
  • Fig. 21 is a schematic flowchart of a receiving method provided by an embodiment of the present application.
  • Fig. 22 is a schematic diagram of parallel execution of an error detection path and an error correction path provided by an embodiment of the present application;
  • Fig. 23 is a schematic diagram of an encoded data block provided by an embodiment of the present application.
  • FIG. 24 is a schematic diagram of a processing flow of another receiving device provided by an embodiment of the present application.
  • Fig. 25 is a schematic flowchart of another receiving method provided by the embodiment of the present application.
  • Fig. 26 is a schematic diagram of starting FEC decoding on demand provided by the embodiment of the present application.
  • Fig. 27 is a flow chart of a sending method provided by an embodiment of the present application.
  • FIG. 28 is a flow chart of a receiving method provided by an embodiment of the present application.
  • Fig. 29 is a schematic structural diagram of a device provided by an embodiment of the present application.
  • Fig. 30 is a schematic structural diagram of another device provided by the embodiment of the present application.
  • Fig. 31 is a schematic structural diagram of a device provided by an embodiment of the present application.
  • Fig. 32 is a schematic structural diagram of another device provided by an embodiment of the present application.
  • FEC is an error control method, which means that the signal is encoded according to a certain algorithm before being sent to the transmission channel, and the redundant code with the characteristics of the signal is added, and the received signal is processed according to the corresponding algorithm at the receiving end.
  • Decoding is a technology to find and correct error codes generated during transmission.
  • the FEC coding gain is an index to measure the error correction capability of the FEC code.
  • the RS code is a forward error correction code, and its parameter representation is usually RS(n, k, t, m), RS(n, k, m) or RS(n, k).
  • n represents the total length of the RS code
  • k represents the length of the payload (payload) in the RS code
  • t represents the error correction capability of the RS code
  • the three parameters of n, k, and t are all in units of symbols
  • m represents the number of bits contained in each symbol.
  • the FEC strategy implemented by using RS codes is also commonly referred to as RS-FEC.
  • FIG. 1 is a schematic diagram of a communication system provided in an embodiment of the present application.
  • the communication system includes a sending device 100 and a receiving device 200.
  • the sending device 100 and the receiving device 200 are connected through a communication link.
  • the communication link may be a PCIe bus or an Ethernet line, etc., which are not specifically limited in this application.
  • the sending device 100 is configured to encode valid data (or data to be FEC coded) to obtain coded data blocks, and then send the coded data blocks to the receiving device 200 .
  • the receiving device 200 is configured to decode the received coded data block to obtain a decoding result of the coded data block (that is, restore the original valid data).
  • the sending device 100 and the receiving device 200 may be processors, accelerators, memories, input/output (I/O) devices, communication chips, network connection devices or computing devices, etc., which are not specifically limited in this application.
  • the communication link in Figure 1 may also include serial-to-parallel conversion devices, modulators, demodulators or photoelectric/electro-optic Replacement of devices, etc. (this part of the device/module is omitted in the figure), so that the coded data block can be converted into a transmission signal suitable for the physical medium. That is to say, the coded data block of the sending device 100 may not be directly transmitted to the receiving device 200, but needs to be converted into a suitable transmission signal before being transmitted. Correspondingly, the receiving device 200 needs to recover the coded data block from the transmission signal, and then decode the coded data block.
  • the sending device 100 and the receiving device 200 are respectively introduced in detail below:
  • the sending device 100 includes a verification unit processing module 101 and an FEC encoding module 102 .
  • the check unit processing module 101 is configured to divide its input data into data blocks of a set length, and generate (or add, insert) a corresponding Pchit check bit for each data block.
  • a data block and its corresponding Pchit check bit constitute a physical check unit (physical check unit, referred to as Pchit), and the Pchit check bit is used to determine whether there is an error in the Pchit.
  • the FEC coding module 102 is configured to perform FEC coding.
  • the verification unit processing module 101 is located before the FEC encoding module 102 , that is, the output of the verification unit processing module 101 serves as the input of the FEC encoding module 102 .
  • valid data is first input into the verification unit processing module 101, and the verification unit processing module 101 performs data block segmentation and Pchit parity bit addition on the valid data, and then inputs it into the FEC encoding module 102; then, the FEC The encoding module 102 performs FEC encoding on the data input by the verification unit processing module 101 to obtain an encoded data block.
  • the verification unit processing module 101 is located after the FEC encoding module 102 , that is, the output of the FEC encoding module 102 serves as the input of the verification unit processing module 101 .
  • the valid data is first input into the FEC encoding module 102, and the FEC encoding module 102 performs FEC encoding on the valid data and then inputs it into the verification unit processing module 101; Segment the data block and add the Pchit check digit to obtain the coded data block.
  • the receiving device 200 includes a buffer module 201 , a verification module 202 , an FEC decoding module 203 and a data selector 204 .
  • the caching module 201 is used for caching data.
  • the verification module 202 is used to verify Pchit to determine whether there is an error in Pchit.
  • the FEC decoding module 203 is used for performing FEC decoding. It should be noted that the cache module 201 and the verification module 202 together constitute an error detection path, while the FEC decoding module 203 constitutes an error correction path, and the data selector 204 is used for the output of the error detection path and the error correction path. Data is selected, and the selected data is used as the output of the data selector 204 (ie, the decoding result).
  • the cache module 201 is located before the verification module 202, that is to say, the cache module 201 first caches the coded data block (or Pchit), and then the verification module 202 Then check each Pchit in the coded data.
  • the cache module 201 is located after the check module 202, that is to say, the check module 202 first checks each Pchit in the coded data block, and every time the check module The verification module 202 completes the verification of a Pchit, and the caching module 201 caches the Pchit again.
  • the coded data blocks are respectively input into the error detection path and the error correction path, so the actions in the error detection path and the error correction path can be executed in parallel.
  • the coded data block is only input into the error detection path at the beginning, but not into the error correction path, and the FEC decoding module 203 in the error correction path may not work temporarily, so The actions of the detection path and the error correction path are not performed in parallel.
  • the FEC decoding module 203 receives the instruction from the verification module 202, it will start to work, and take out corresponding data from the cache module 201 to perform FEC decoding.
  • the caching module 201 in FIG. 6 may also be located after the verification module 202, which will not be described here.
  • the division of various functional modules in the sending device 100 and the receiving device 200 is just an example, and they may also include more or fewer modules.
  • one functional module can be split into multiple modules, multiple functional modules can also be combined into one module, and there can also be other functional modules, which are not specifically limited in this application.
  • FIG. 7 is the first embodiment of the sending method provided by the embodiment of the present application, which is used for the above-mentioned sending device 100, and includes the following steps:
  • the valid data in the embodiment of the present application refers to the data to be FEC encoded, which needs to be correspondingly FEC encoded in the physical layer or the physical coding sublayer (physical coding sublayer, PCS) of Ethernet, To enhance the ability to resist channel interference (so that it has a certain error correction ability).
  • PCS physical coding sublayer
  • the valid data is data after 64/66 encoding and 264/257 encoding in the Ethernet PCS layer, so the valid data can be input into the sending device 100 in units of 257 bits.
  • set length here actually specifies the segmentation granularity of the data block or the size of the data block, which is not specifically limited in this application and can be reasonably selected according to the actual application scenario.
  • the sending device 100 can continuously receive the input of valid data in the last step S701, but if the data volume of the received valid data has not reached the set length, it is not enough to be divided into data blocks (or It is not enough to process as a data block), so the sending device 100 will not execute step S702 yet, and continue to receive input of valid data.
  • the sending device 100 can start to execute step S702, divide the valid data of the set length into a data block, and add a corresponding Pchit checksum to the data block. check position.
  • the verification unit processing module 101 in the sending device 100 is before the FEC encoding module 102 , and the verification unit processing module 101 is responsible for receiving valid data input.
  • the dotted line in the valid data input part in the figure is for the convenience of corresponding to the data blocks that will be divided later, and the valid data at this time has not yet been divided into data blocks.
  • the data blocks in the figure are represented by white bars
  • the FEC check digits are represented by slash-filled long bars
  • the Pchit check digits are represented by small gray squares. The length relationship between them does not constitute a limitation.
  • a data block and its corresponding Pchit parity bit constitute a Pchit.
  • the verification unit processing module 101 receives valid data input, and then executes action 1 to divide the valid data into data blocks of a set length, and the transmission order of each data block in the figure is from right to left.
  • the check unit processing module 101 then executes action 2 to add corresponding Pchit check digits for each data block respectively, wherein each data block and its corresponding Pchit check digit together constitute a Pchit, that is, each Pchit includes a The data block and its corresponding Pchit check digit, the Pchit check digit can be added at the end of the data block.
  • the verification unit processing module 101 inputs Pchit (sequentially) into the FEC encoding module 102 .
  • the verification unit processing module 101 will regard it as a data block (that is, perform action 1) and add a corresponding Pchit check bit to the data block (i.e. perform action 2) to obtain a Pchit, and then send the Pchit to the FEC encoding module 102 .
  • the verification unit processing module 101 When the verification unit processing module 101 receives the valid data of enough set length again, it can be processed as a data block, generates a Pchit parity bit for the data block to obtain a Pchit, and then sends the Pchit to FEC encoding module 102 .
  • the Pchit check digit can be generated by a combination of one or more coding methods.
  • the encoding method can be (Bose-Chaudhuri-Hocquenghem, referred to as BCH) encoding, (extend Bose-Chaudhuri-Hocquenghem, referred to as eBCH) encoding, RS encoding or cyclic redundancy check (cycle redundancy check, CRC) encoding, etc., this application does not Be specific.
  • the transmitting device 100 will divide the valid data of 5200 bits in the figure into 10 data blocks, and use data blocks 0 to 10 in sequence.
  • Data block 9 to represent, each data block is 520bit. It should be noted that the transmission order of the various data blocks in the figure is from top to bottom, that is, from data block 0 to data block 9 in sequence.
  • the sending device 100 adopts the BCH encoding method to add corresponding Pchit check bits to the above-mentioned 10 520-bit data blocks respectively, and the Pchit check bits at this time are BCH check bits.
  • data block 1 the data of data block 1 is encoded with BCH (544,520), which can generate 24-bit BCH check digit 1; then add BCH check digit 1 to the end of data block 1 to obtain 544-bit Pchit 1, Pchit 1 includes both 520-bit data block 1 and 24-bit BCH parity bit 1.
  • the sending device 100 will convert the (10 ⁇ X)bit
  • the valid data of the data block is divided into 10 data blocks, which are sequentially represented as data block 0 to data block 9, and each data block is X-bit.
  • the transmitting device 100 adopts the combination of BCH encoding and CRC encoding to add corresponding Pchit check digits to the 10 X-bit data blocks respectively, and the Pchit check digits at this time include BCH check digits. Check digit and CRC check digit.
  • BCH encoding and CRC encoding are respectively performed on the data of data block 0 to generate Y-bit BCH check bit 0 and Z-bit CRC check bit 0, and then BCH check bit 0 and CRC check digit 0 are added to the end of data block 0, and the order in which the BCH check digit and CRC check digit are added is not limited, and the Pchit 0 of (X+Y+Z)bit is obtained, and X, Y, and Z are all positive integer.
  • Pchit 0 includes X-bit data block 0 and (X+Y)bit Pchit check digit
  • Pchit check digit is composed of Y-bit BCH check digit 0 and Z-bit CRC check Bit 0 collectively constitutes.
  • the length of the Pchit check digit is limited, if a combination of multiple encoding methods is used to generate the Pchit check digit, the length of the check digit obtained by each encoding method can be reasonably designed to satisfy The length requirement of the Pchit check digit reduces the bandwidth occupation of the Pchit check digit, and can also improve the reliability of the Pchit check digit and reduce the probability of false and missed detection.
  • the segmentation granularity of the data block can be matched with the FEC coding method adopted in the sending device 100, so that the length of the payload required by the FEC coding method is an integer multiple of the data block segmentation granularity.
  • the FEC coding method adopted in the sending device 100, so that the length of the payload required by the FEC coding method is an integer multiple of the data block segmentation granularity.
  • two high-gain FEC codewords are defined in the Ethernet standard, namely RS(544,514,15,10) and RS(528,514,7,10). By matching the length of the required payload, the two FEC codes can be directly multiplexed.
  • the FEC encoding method adopted by the sending device 100 is RS(544,514,10)
  • the segmentation granularity of the data block can be designed as X-bit, so that 5140 bits is an integer multiple of X-bit, which realizes the matching between the segmentation granularity of the data block and the FEC encoding method.
  • an integer number of data blocks can be used as the payload of the RS code for FEC encoding, and the Pchit parity bit corresponding to each data block is not used as the FEC payload and does not participate in FEC encoding, so the length of the Pchit parity bit It will not affect the FEC encoding, and the length of the Pchit check digit will be relatively free to choose.
  • the segmentation granularity of the data block can be matched with the 64/66 encoding and 264/257 encoding methods adopted in the Ethernet PCS layer, so that the segmentation granularity of Pchit is an integer multiple of 257bit, It can be compatible with the processing granularity in the Ethernet standard PCS layer.
  • 264/257 encoding is used to compress 264-bit data units into 257-bit data units, so the data to be FEC-encoded (i.e. valid data in the embodiment of this application) The unit is 257bit.
  • the segmentation granularity of the data block can be designed as an integer multiple of 257bit, so each data block contains an integer number of 257bit data units, thus compatible with the processing granularity of the Ethernet PCS layer.
  • the sending device 100 will divide the 5140-bit valid data in the figure into N data blocks, which are respectively represented by data block 0 to data block (N-1), and N is a positive integer.
  • the Pchit parity bit of M-bit is added for each data block respectively, and M is a positive integer, and N Pchits are obtained, represented by Pchit 0 to Pchit(N-1) respectively, each Each Pchit includes a (Q ⁇ 257) bit data block and an M-bit Pchit parity bit.
  • the FEC payload is FEC encoded, and the Pchit check digit is not used as the FEC payload and does not participate in the FEC encoding, so the length of the Pchit check digit will not affect the FEC encoding, so the selection of the length of the Pchit check digit will be more flexible.
  • the segmentation granularity of the data block may be an integer multiple of the symbol granularity in the FEC encoding manner.
  • the adopted FEC encoding mode is RS(544,514,10)
  • the symbol granularity in the FEC encoding mode is 10 bits.
  • the segmentation granularity of the data block is made to be an integer multiple of 10 bits, so that the gearbox (gearbox) logic between the data block and the FEC symbol can be removed or simplified.
  • the data blocks and Pchit parity bits in multiple Pchits are used as FEC payloads for FEC encoding to obtain encoded data blocks.
  • each Pchit includes a 520-bit data block and a 24-bit BCH parity bit (ie, Pchit parity bit).
  • the FEC coding method adopted is RS (576, 544, 10)
  • a 320-bit FEC parity bit is generated, and then the FEC parity bit is added to Pchit9, and the obtained RS codeword is the part selected by the dotted line in Figure 15, and the RS codeword is the coded data block , the FEC parity bit is used to correct errors present in the encoded data block.
  • each Pchit includes a 1285-bit data block and a 35-bit eBCH parity bit.
  • the eBCH check digit here is the Pchit check digit, which is generated by the eBCH (1320, 1285) encoding method. For example, by performing eBCH (1320, 1285) encoding on the 1285bit data block 0, you can Generate 35-bit eBCH parity bit 0.
  • a 280-bit FEC parity bit is generated.
  • the obtained RS codeword is the part selected by the dotted line in Figure 17, and the RS codeword is the coded data block.
  • the FEC parity bit is used to correct errors existing in the encoded data block.
  • the FEC encoding module 102 performs FEC encoding only on data blocks in multiple Pchits as FEC payloads according to the adopted FEC encoding method, to obtain encoded data blocks.
  • each Pchit obtained in the previous step S702 is 538 bits, and each Pchit includes a 514-bit data block and a 24-bit Pchit parity bit.
  • the payload is FEC encoded, that is, the Pchit parity bits in each Pchit are not part of the FEC payload and do not participate in the FEC encoding.
  • a 300-bit FEC parity bit is generated, and the FEC parity bit is inserted into Pchit 9, and the obtained RS codeword is the part selected by the dotted line in Figure 18.
  • the RS codeword only includes the data block part in each Pchit, and does not include the Pchit parity part, and the whole of Figure 18 is regarded as a coded data block (including the RS codeword and the Pchit in these 10 Pchits). Check Digit).
  • the Pchit check bit can be used as a part of the FEC payload to participate in FEC encoding to obtain the FEC check bit, or it can not be used as the FEC payload and not participate in the FEC encoding.
  • the valid data is divided into data blocks of a set length on the sending device 100 side, and the corresponding Pchit parity bit is added to each data block to obtain Pchit, and the Pchit parity bit is used for Verify whether there is an error in the corresponding Pchit, so that Pchit has a certain error detection capability.
  • the appropriate data block segmentation granularity can be selected according to factors such as the FEC encoding method adopted and application scenarios, so that it can match various interconnection standards and can be used for interconnection interfaces such as Ethernet interfaces and PCIe interfaces;
  • a combination of one or more encoding methods is used to generate the Pchit check digit, so that the length adjustment of the Pchit check digit becomes flexible.
  • perform FEC encoding on multiple Pchit according to the adopted FEC encoding method to obtain an encoded data block, so that the encoded data block has a certain error correction capability, and then send the encoded data block to the receiving device 200 .
  • the receiving device 200 can independently check each Pchit in the received coded data block to determine whether there is an error in each Pchit, so as to realize the prediction of errors in the coded data block, and can also perform FEC decoding to correct errors present in encoded data blocks.
  • error detection and error correction adopt two different granularities, error detection is based on Pchit (or data block in Pchit) as the granularity, error correction is based on the entire coded data block (or multiple data blocks) as the granularity, Moreover, there is an inclusion relationship between the two granularities (multiple Pchits can be included in the encoded data block), so the decoding method on the receiving device 200 side becomes very flexible, which helps to reduce the delay impact and power consumption impact of FEC decoding , help to achieve low latency and high gain requirements.
  • FIG. 19 is a second embodiment of the sending method provided by the embodiment of the present application, which is used in the sending device 100, and includes the following steps:
  • step S1901 For the specific content of step S1901, please refer to the aforementioned step S701, which will not be repeated here.
  • the adopted FEC encoding mode perform FEC encoding on the valid data to obtain an FEC codeword.
  • the FEC codeword includes valid data and FEC parity bits, and the FEC parity bits are used to correct errors existing in the FEC codewords.
  • the FEC encoding module 102 in the sending device 100 is before the verification unit processing module 101 , and the FEC encoding module 102 is responsible for receiving valid data input.
  • the dotted line in the valid data input part in the figure is for the convenience of corresponding to the data blocks that will be divided later, and the valid data at this time has not actually been divided into data blocks.
  • the FEC encoding module 102 will perform FEC encoding on the valid data of 5140bit to generate FEC
  • the parity bit is to insert the FEC parity bit into the tail of the 5140bit valid data, so as to obtain the FEC codeword.
  • the dotted line of the effective data part in the FEC codeword in the figure is also for the convenience of corresponding to the subsequent data blocks, and the valid data in the FEC codeword has not been divided into data blocks at this time.
  • the valid data before performing FEC encoding, can be divided into multiple data blocks with a set length; then, according to the FEC encoding method used, FEC encoding is performed on multiple data blocks to obtain An FEC codeword, wherein the FEC codeword includes multiple data blocks and FEC parity bits, and the FEC parity bits are used to correct errors existing in the FEC codeword.
  • the verification unit processing module 101 segments the valid data in the FEC code word to obtain a plurality of fixed-length data blocks, and add corresponding Pchit check digits to each data block to obtain Pchit one by one, and the Pchit check digits are added at the end of each data block in each Pchit.
  • the finally obtained encoded data block is shown in 1 in the figure. It can be seen that the FEC check bit is not processed as a Pchit, and no Pchit check bit is added to it.
  • the valid data in the FEC codeword is divided into multiple data blocks with a set length, a corresponding Pchit check bit is added to each data block, and a Pchit check bit is also added to the FEC check bit. Corresponding Pchit check digits, thereby obtaining the coded data block.
  • the verification unit processing module 101 segments the valid data in the FEC code word to obtain a plurality of Fixed-length data blocks, and add corresponding Pchit check digits to each data block to obtain Pchit one by one, and Pchit check digits are added at the end of each data block.
  • the FEC check bit is also treated as a Pchit, and a corresponding Pchit check bit is added to the FEC check bit.
  • the Pchit check bit corresponding to the FEC check bit can be called the first Two check digits, the final encoded data block is shown in 2 in the figure.
  • the FEC check bit can be regarded as a Pchit, and a corresponding Pchit check bit is added to the FEC check bit, so that the FEC check bit can be judged according to the Pchit check bit corresponding to the FEC check bit. Whether there is an error in the check bit, thereby improving the reliability of the FEC check bit.
  • the FEC check bit may not be processed as Pchit, and the corresponding Pchit check bit may not be added.
  • step S1903 for the generation method of the Pchit check digit and the selection of the granularity of data block segmentation in step S1903, please refer to the related content in step S702, which will not be repeated here.
  • FEC encoding is performed on the effective data according to the adopted FEC encoding method on the side of the sending device 100 to generate an FEC parity bit, and then the FEC parity bit is added to the end of the effective data to obtain the FEC code word, so that the FEC codeword has a certain error correction capability, and the errors existing in the FEC codeword can be corrected according to the FEC parity bit.
  • the sending device 100 divides the valid data in the FEC codeword into data blocks of a set length, and adds a corresponding Pchit parity bit to each data block to obtain each Pchit, and the Pchit parity bit is used to verify the corresponding Pchit whether there is an error, thus getting the encoded data block.
  • an appropriate segmentation granularity of the data block may be selected according to factors such as the adopted FEC coding method and actual application scenarios, and a combination of one or more coding methods may be used to generate the Pchit check digit.
  • the sending device 100 sends the coded data block to the receiving device 200 through a corresponding communication link. Due to the influence of link noise, errors may exist in the coded data block obtained by the receiving device 200 . Therefore, the receiving device 200 can independently check each Pchit in the coded data block to determine whether there is an error in each Pchit, so as to realize the prediction of errors in the coded data block, and can also perform FEC on the received coded data block Decoding to correct errors present in a block of encoded data. Therefore, the decoding method of the coded data block on the side of the receiving apparatus 200 can be very flexible, which helps to reduce the influence of time delay and power consumption of FEC decoding.
  • FIG. 21 is the first embodiment of the receiving method provided by the embodiment of the present application, which is used in the receiving device 200, and includes the following steps:
  • each data block and its corresponding Pchit check bit constitute a Pchit
  • the Pchit check bit is used to check whether there is an error in the corresponding Pchit
  • the FEC check bit is used to find that the coded data block (or multiple data block) and correct the errors.
  • the coded data block originates from the sending device 100, and the coded data block of the sending device 100 is sent to the receiving device 200 through a communication link. Due to the influence of factors such as link noise, there may be errors in the encoded data block obtained by the receiving device 200, so the receiving device 200 needs to perform error detection and/or error correction on the encoded data block to obtain correct data, that is, to restore Raw valid data.
  • the FEC decoded data obtained after the coded data block is decoded by FEC is post-correction data (that is, the errors in the coded data block have been corrected), and multiple data blocks in the coded data block are decoded by FEC respectively. There is corresponding data in the data.
  • the receiving device 200 when the receiving device 200 acquires a Pchit in the coded data block, it can directly start verifying it, and does not need to wait for the complete coded data block before starting the Pchit verification. However, the receiving device 200 needs to receive the entire coded data block before starting FEC decoding, so FEC decoding will introduce a certain frame receiving delay.
  • the above-mentioned “respectively check whether there is an error in the corresponding data block according to a plurality of Pchit parity bits” and the above-mentioned “perform FEC decoding on the encoded data block according to the FEC parity bit to obtain FEC decoded data” can be executed simultaneously/synchronously/parallel.
  • a plurality of data blocks in the coded data block have a sequence; said checking whether there is an error in the corresponding data block according to a plurality of Pchit check digits includes: checking according to a plurality of Pchit check bits Bits in turn check whether there is an error in the corresponding data block.
  • the encoded data block obtained by the receiving device 200 may have two different forms 1 and 2, and the FEC parity bit of the first type does not add corresponding The Pchit check bit, and the FEC check bit of the second type adds the corresponding Pchit check bit.
  • the following texts will take the first type of encoded data block as an example for illustration.
  • the coded data blocks are respectively input into the error detection path and the error correction path, and the actions of the error correction path and the error correction path can be executed in parallel, wherein the error detection path is responsible for correcting each Pchit in the coded data block.
  • the error correction path is responsible for performing FEC decoding on the coded data block to obtain FEC decoded data.
  • the verification module 202 performs verification at the granularity of Pchit (or at the granularity of data blocks), and the FEC decoding module 203 performs FEC at the granularity of encoded data blocks (or at the granularity of multiple data blocks).
  • Decoding, and Pchit verification is generally faster than FEC decoding, so the FEC decoding delay in the error correction path is greater than the Pchit verification delay in the error detection path. Therefore, in order to avoid out-of-order output decoding results, the cache module 201 is used in the figure to cache the coded data blocks.
  • step S2103. Determine whether the target data block has passed the verification. If the target data block passes the verification, proceed to step S2104. If the target data block fails the verification, proceed to step 2105.
  • the target data block is any one of multiple data blocks in the coded data block.
  • the coded data block contains ten 544-bit Pchit and 320-bit FEC check bits, and each Pchit contains a 520-bit data block and a 24-bit Pchit check bit (assuming that BCH The BCH check digit generated by the encoding method).
  • data block 0 is the target data block now, the receiving device 200 starts to check the target data block 0 according to BCH parity bit 0.
  • a specific check scheme may be that the receiving device 200 performs BCH encoding on data block 0 according to the BCH encoding method adopted in the sending device 100 to generate a BCH check bit. Then compare the BCH parity bit generated by receiving device 200 with the BCH parity bit 0 in Pchit0, if the two are consistent, it means that there is no error in data block 0, and the verification of data block 0 is passed; if the two are inconsistent, then It indicates that there is an error in data block 0, and the verification fails.
  • the coded data block contains 10 (X+Y+Z) bit Pchit and 320-bit FEC parity bits, and each Pchit contains an X-bit data block and (Y +Z) bit Pchit check bit, here it is assumed that the Pchit check bit is composed of Y-bit BCH check bit and Z-bit CRC check bit.
  • a specific check scheme may be that, using the same BCH encoding method as that of the sending device 100, BCH encoding is performed on the data block 1 to generate a BCH check bit.
  • the BCH check is performed first, and then the CRC check is performed as needed.
  • the CRC check can also be performed first, and then the BCH check is performed as needed, which is not limited in this application.
  • the probability of finding errors will be higher by combining multiple encoding methods for verification.
  • the generator polynomials of the two codes are different, some error situations may not be detected by BCH, that is, the error detection capability of a single code is limited, but CRC may be detected.
  • the verification methods can achieve complementarity, thereby improving the reliability of the Pchit check digit and reducing the probability of false missed detection.
  • the next target data block can be A data block is updated as the target data block and verified, and the process returns to step S2103.
  • the acquired encoded data block contains 6 Pchits (each Pchit includes a data block and a Pchit parity bit), for the convenience of description, the data blocks of these Pchits in the figure are respectively The serial numbers from 1 to 6 are marked, respectively representing data block 1 to data block 6, corresponding to Pchit 1 to Pchit 6 in turn. It is assumed here that there is an error in Pchit 3 in the coded data block, while the other Pchits have no errors.
  • step S2102 the encoded data block will be respectively input into the error detection path and the error correction path in the receiving device 200 for processing.
  • the FEC decoding module 203 in the error correction path performs FEC decoding on the coded data block, and the speed is relatively slow; while the verification module 202 in the error detection path verifies the target data block in the coded data block, and the speed is relatively slow. faster.
  • the verification module 202 will first obtain the verification result of data block 1, and the FEC decoding module 203 is still performing FEC decoding on the encoded data block, and has not yet obtained the FEC Decode data.
  • the verification result of data block 1 indicates that data block 1 is error-free, so data block 1 is verified, and then the verification module 202 outputs the data of data block 1 to data selector 204, and the control signal Sel of data selector 204 is set to is 0, then the data selector 204 will take the data of the data block 1 input by the verification module 202 as its output, that is, output the decoding result of the data block 1 .
  • the verification module 202 continues to verify the data block 2 and passes the verification, then sends the data block 2 to the data selector 204, and sets Sel to 0, so the data selector 204 also sets the verification module
  • the data block 2 input in 202 is taken as its own output, that is, the decoding result of the data block 2 .
  • the target data block when the FEC decoding is performed on the coded data block in step S2102, the error of the target data block in the coded data block will be corrected. Therefore, the target data block The corresponding data in the obtained FEC decoding data is after error correction. If there is no error in the target data block, then the data corresponding to the target data block in the FEC decoding data has not undergone error correction.
  • multiple data blocks in the coded data block do not need to be verified sequentially, but can be performed simultaneously/in parallel, or in other words, the order of the data blocks is not considered during the verification. Therefore, when the target After the data block is verified, the data corresponding to the target data block in the FEC decoding data can be directly used as the decoding result of the target data block. Afterwards, the decoding results of each data block can be adjusted again so as to conform to the order of the data blocks.
  • multiple data blocks in the coded data block have a sequence, and these multiple data blocks are verified sequentially; the corresponding target data block in the FEC decoding data
  • the data is used as the decoding result of the target data block, including: the data corresponding to the target data block and other data blocks after it in the FEC decoding data are respectively used as the decoding of the target data block and other data blocks after it result.
  • the error detection results of other data blocks after the target data block can be ignored, and even the error detection and verification of other data blocks after the target data block can be directly stopped, so as to save energy consumption.
  • the next step is to verify data block 3, that is, data block 3 becomes the target data piece.
  • the verification result shows that there is an error in the data block 3, so the verification of the data block 3 fails, and the verification module 202 sends an indication message to the FEC decoding module 203 to indicate that there is an error in the data block 3, and the control signal Sel of the data selector 204 is set to is 1, then the data output terminal 204 will wait for the output of the FEC decoding module 203 .
  • the FEC decoding module 203 may not have completed the FEC decoding work of the coded data block when receiving the indication information from the verification module 202 .
  • the FEC decoding data can be obtained, and the data corresponding to the data block 3 in the FEC decoding data is the data after the error of the data block 3 has been corrected.
  • the FEC decoding module 203 inputs the data corresponding to the data block 3 to the data block 6 in the FEC decoding data to the data selector 204 . Because the control signal Sel of the data selector 204 is in the "1" state now, the data selector 204 will take the data input by the FEC decoding module 203 as its own output, and no longer select the data of the verification module 202, so the data block The verification results of data block 4 to data block 6 after 3 will be ignored.
  • the FEC decoding module 203 may also send an instruction to the verification module 202, so that the verification module 202 starts to verify each data block in the next encoded data block in sequence.
  • the decoding result corresponding to the encoded data block finally output by the data selector 204 has a part from the error detection path (data block 1 and data block 2), and another part from the error correction path (data block 3 As for the data block 6, it should be noted that the data block 3 here is the data of the data block 3 after error correction).
  • error detection and error correction are performed separately on the side of the receiving device 200, specifically, they can be executed in parallel, wherein the error detection takes Pchit (or data block) as the processing granularity, and the coded data Each Pchit in the block is checked, and the error correction takes the coded data block (or multiple data blocks) as the processing granularity, and performs FEC decoding on the coded data block.
  • the embodiment of the present application makes full use of the link error distribution law, and by performing independent verification on each data block in the encoded data block, the error distribution in the encoded data block can be quickly known.
  • the decoding results corresponding to the coded data block all come from the error detection path, and there is no need to wait for the FEC decoded data obtained by FEC decoding in the error correction path (equivalent to The FEC decoding module 203) is bypassed, so the time delay of FEC frame receiving and decoding can be omitted, thereby reducing the overall time delay of interface processing, solving the problem that high-gain FEC has a great influence on time delay, and meeting the requirements of low time delay scene requirements.
  • Fig. 25 is the second embodiment of the receiving method provided by the embodiment of the present application, which is used in the receiving device 200, and includes the following steps:
  • step S2501 For the specific content of step S2501, please refer to step S2101, which will not be repeated here.
  • step S2502. Check whether there is an error in the corresponding data block according to a plurality of Pchit check digits, and determine whether the target data block has passed the verification.
  • the target data block is a data block among the plurality of data blocks, and the target data block has passed the verification In the case of , go to step S2503, and in the case of failed verification of the target data block, go to step S2504.
  • the target data block may be any one of multiple data blocks in the coded data block.
  • the specific verification scheme of the target data block please refer to the relevant content in step S2103, which will not be repeated here.
  • the multiple data blocks in the coded data block have a sequence; the checking whether there is an error in the corresponding data block according to the multiple Pchit parity bits respectively includes: respectively according to the multiple Pchit parity bits The bit verification checks whether there is an error in the corresponding data block in turn.
  • the data blocks in the coded data block are verified sequentially, after the current target data block is verified and the data of the target data block is output as its corresponding decoding result, the The next data block of the target data block is updated as the target data block and verified, and returns to step S2502 to determine whether the new target data block passes the verification.
  • the coded data block contains 6 Pchits (each Pchit includes two parts, the data block and the Pchit parity bit), for the convenience of description, the data blocks of these Pchits are respectively marked in the figure
  • the serial numbers from 1 to 6 represent data block 1 to data block 6, corresponding to Pchit 1 to Pchit 6 in turn.
  • Pchit 3 in the coded data block has errors, while other Pchits are error-free.
  • the encoded data block is only input to the error detection path of the receiving device 200 at the beginning, but not to the error correction path, and the FEC decoding module 203 in the error correction path does not work temporarily, which can save energy consumption. The work of the error detection path and the error correction path is not performed in parallel.
  • the check module 202 starts to check. Assuming that data block 1 is the target data block now, since there is no error in Pchit 1, data block 1 will pass the verification, and then the verification module 202 sends the data of data block 1 to the data selector 204, and the data selector 204
  • the control signal Sel is set to 0, so the data selector 204 outputs the data of the data block 1 sent by the verification module 202 as the decoding result of the data block 1 .
  • the data block 2 is set as the target data block, and in the same way, the verification module 202 verifies Pchit 2 and passes the verification, the data of the data block 2 is input to the data selector 204, and Sel is set to 0.
  • the data selector 204 outputs the data of the data block 2 input by the verification module 202 as the decoding result of the data block 1 .
  • the verification failure information of the target data block will be used as a trigger signal for the FEC encoding module 203 to start to perform FEC decoding.
  • the multiple data blocks in the coded data block have a sequence, and the multiple data blocks are checked sequentially; the FEC decoding of the coded data block is performed according to the FEC parity bit Obtaining FEC decoding data, using the data corresponding to the target data block in the FEC decoding data as the decoding result of the target data block, including: performing FEC decoding on the coded data block according to the FEC parity bit to obtain FEC decoding data, The data corresponding to the target data block and other subsequent data blocks in the FEC decoding data are respectively used as decoding results of the target data block and other subsequent data blocks.
  • the error detection results of other data blocks after the target data block can be ignored (that is, the verification of subsequent data blocks can still continue to be executed, but no longer affect the output of the data selector 204), or even directly stop checking the target data block.
  • the error detection checksum of other data blocks after that can be ignored (that is, the verification of subsequent data blocks can still continue to be executed, but no longer affect the output of the data selector 204), or even directly stop checking the target data block.
  • data block 3 becomes the target data block, and the verification module 202 starts to verify it. Due to an error in Pchit 3, data block 3 will fail the verification. Then, the verification module 202 sends instruction information to the FEC decoding module 203 to indicate that there is an error in Pchit 3 and instructs the FEC decoding module 203 to perform FEC decoding on the encoded data block where Pchit3 is located, and the verification module 202 also selects the data
  • the control signal Sel of the device 204 is set to 1, so the data selector 204 will no longer select the data of the error detection path, and the error detection results of the data block 4 to the data block 6 will be ignored, and the output of the data selector 204 will not be affected.
  • the FEC decoding module 203 After the FEC decoding module 203 receives the indication information of the checking module 202, it starts to work, and obtains the coded data block (or the FEC codeword at which the Pchit 3 is located) from the cache module 201 to perform FEC decoding, Get FEC decoded data. Then the FEC decoding module 203 sends data corresponding to data block 3 and other data blocks after it in the FEC decoding data to the data selector 204 according to the indication information. Since the Sel signal is in the "1" state now, the data selector 204 outputs the data input from the FEC decoding module 203 as a decoding result.
  • the FEC decoding module 203 can also send instruction information to the checking module 202, so that the checking module 202 starts to check the Pchit in the next encoded data block in turn, and the FEC decoding module 203 can stop working again to save energy consumption.
  • the decoding result corresponding to the coded data block finally output by the data selector 204 has a part from the error detection path (data block 1 and data block 2), and another part from the error correction path (data block 3
  • data block 3 is the result of error correction of the data in the data block 3, not the original data block 3 with errors). It can be understood that if there is no error in a coded data block, the FEC decoding module 203 will not be activated, and the decoding results of the coded data block output by the data selector 204 all come from the error detection path.
  • the FEC decoding function in the error correction path will be activated to perform FEC decoding on the encoded data block where the target data block is located to obtain FEC decoded data, and then convert the FEC decoded data into The corresponding data is used as the decoding result.
  • the receiving apparatus 200 uses coded data blocks as the error correction granularity, and relatively small Pchit (or data blocks) as the error detection granularity.
  • the embodiment of the present application makes full use of the link error distribution rule, and can quickly know the error distribution in the encoded data block by individually verifying each data block in the encoded data block. When there is no error in each data block in the encoded data block, there is no need to start FEC decoding, and there is no need to wait for FEC decoding data.
  • the decoding results corresponding to the encoded data block come from the error detection path, so saving The delay of FEC frame receiving and decoding is eliminated, thereby reducing the overall delay of interface processing, solving the problem that high-gain FEC has a large impact on delay, meeting the needs of low-latency scenarios, and saving power consumption of FEC decoding .
  • FEC decoding will be started to realize the error correction function to ensure the output bit error rate in the high insertion loss link scenario.
  • the FEC decoding function needs to be enabled only when there is an error, the impact of the FEC frame receiving and decoding delay on the interface delay is reduced, and the fixed FEC decoding delay is changed to a dynamic delay jitter. In the case of an error, the delay is increased, and the disadvantage of the delay of the high-gain FEC code is eliminated. Moreover, there is no power consumption of FEC decoding under the condition of no error, which can reduce the influence of power consumption of FEC decoding.
  • the embodiment of the present application is applicable to all interconnection interfaces that need to introduce the FEC function to improve the link quality, such as Ethernet interface, PCIe interface, small computer system interface (small computer system interface, SCSI), etc., can It is widely applicable to interconnection scenarios such as processors, accelerators, memories, I/O devices, network switching devices, and computing devices.
  • FIG. 27 is a schematic flowchart of another sending method provided by the embodiment of the present application, which is used in the sending device 100, and includes the following steps:
  • the first check digit here is the Pchit check digit mentioned above.
  • Pchit parity bit please refer to the relevant content of the embodiment in FIG. 7 and FIG. 19 , and the introduction will not be repeated here.
  • said generating a plurality of first check digits respectively according to a plurality of data blocks includes: respectively encoding the data of a plurality of data blocks by one or more encoding methods to generate a plurality of first check digits.
  • Check Digit For the specific content of this embodiment, please refer to the relevant part in step S702, which will not be introduced here.
  • the generating the FEC check bits according to the multiple data blocks includes: generating the FEC check bits according to the multiple data blocks and the multiple first check bits.
  • the FEC parity bit please refer to the relevant content in steps S703 and S1902, which will not be introduced here.
  • the sending device 100 executes the above steps S2701 to S2702, it can send the coded data block to the receiving device 200 .
  • the sending device 100 can also convert the coded data block into a suitable transmission signal and then send it to the receiving device 200, for example, the sending device 100 converts the coded data block to After being converted into an optical signal, the optical signal is then transmitted to the receiving device 200 through an optical fiber, which is not specifically limited in this application.
  • a corresponding first parity bit is generated for multiple data blocks, and a corresponding FEC parity bit is jointly generated for multiple data blocks, so that the receiving device
  • the 200 can respectively check whether there is an error in the corresponding data block through a plurality of first check bits, so as to realize the prediction of errors in the encoded data block, and also enable the receiving end to check the data in the multiple data blocks through the FEC check bit. Existing errors are corrected. Therefore, the receiving device 200 can flexibly design the decoding mode of the coded data block, which helps to reduce the influence of time delay and power consumption of FEC decoding, and helps to realize low time delay and high gain.
  • FIG. 28 is a schematic flowchart of another receiving method provided by the embodiment of the present application, which is used in the receiving device 200, and includes the following steps:
  • the first check digit here refers to the Pchit check digit mentioned above.
  • the generation of Pchit check digits, the granularity of data block segmentation, the generation of FEC check digits, etc. please refer to the relevant content of the embodiment in FIG. 7 and FIG. 19 , and the introduction will not be repeated here.
  • the verifying the corresponding data block according to the multiple first check bits and/or the FEC check bits to obtain the decoding result of the coded data block includes: according to the multiple first check bits Check whether there is an error in the corresponding data block respectively; in the case that multiple data blocks are checked for errors, perform FEC decoding on the multiple data blocks according to the FEC parity bit to obtain a decoding result of the encoded data block.
  • the method further includes: taking the multiple data blocks as decoding results of the coded data block when no error is detected in the multiple data blocks.
  • performing FEC decoding on the multiple data blocks according to the FEC parity bit to obtain a decoding result of the coded data block includes: When the first data block does not check out an error, the first data block is used as the decoding result of the first data block, and the first data block is a data block in the plurality of data blocks; When an error is detected, perform FEC decoding on the multiple data blocks according to the FEC parity bit to obtain FEC decoding data, and use the corresponding data of the second data block in the FEC decoding data as the decoding of the second data block As a result, the second data block is one of the plurality of data blocks; the decoding result of the plurality of data blocks is used as the decoding result of the encoded data block.
  • the verifying the corresponding data block according to the multiple first check bits and/or the FEC check bits to obtain the decoding result of the coded data block includes: according to the multiple first check bits Check whether there are errors in the corresponding data blocks, and perform FEC decoding on multiple data blocks according to the FEC parity bit to obtain FEC decoded data; The data gets the decoded result of the coded data block.
  • the plurality of first parity bits it is respectively checked whether the corresponding data blocks have errors, and FEC decoding is performed on the multiple data blocks according to the FEC parity bits to obtain FEC decoded data , are executed in parallel.
  • the verifying the corresponding data block according to the multiple first check bits and/or FEC check bits to obtain the decoding result of the coded data block further includes: If an error is detected, a plurality of data blocks are used as the decoding result of the coded data block.
  • said obtaining the decoding result of the coded data block according to the FEC decoding data in the case where errors are detected in multiple data blocks includes: when no error is detected in the first data block Next, the first data block is used as the decoding result of the first data block, and the first data block is one of the multiple data blocks; when an error is detected in the second data block, the second data block is The data corresponding to the block in the FEC decoding data is used as the decoding result of the second data block, and the second data block is a data block in the multiple data blocks; the decoding results of the multiple data blocks are used as the coded data block decoding result.
  • the decoding result of the encoded data block can be obtained according to multiple first check bits and/or FEC check bits in the encoded data block, which are mainly divided into: Start FEC and error detection and correction parallel schemes on demand.
  • the data of the coded data block is used as the decoding result of the encoded data block; if the multiple data blocks are checked for errors (at least one of the multiple data blocks is checked for errors), the FEC function needs to be activated, and the FEC check bit Perform FEC decoding on these multiple data blocks to obtain FEC decoded data.
  • the data of the data block can be directly used as the decoding result of the data block, and for a data block that has been checked for errors
  • the data corresponding to the data block in the FEC decoded data is used as the decoding result of the data block, and finally the decoding results of each data block are synthesized as the decoding result of the encoded data block.
  • FEC decoding When a certain data block is verified to be faulty, FEC decoding will be started to obtain FEC decoding data, and then , the data corresponding to the data block and other data blocks after it in the FEC decoding data are used as the decoding results of this data block and other data blocks after it, so other data blocks after this data block can be ignored
  • the verification result of the coded data block can even stop the verification of other data blocks after the data block in the coded data block, so as to save energy consumption. It can be understood that because FEC decoding needs to be started and FEC decoding delay is introduced only when there is an error, it can reduce the delay impact and power consumption impact of FEC decoding, and help to achieve low delay and high gain.
  • the parallel error detection and error correction scheme it is possible to check whether the corresponding data blocks have errors according to multiple data blocks, and perform FEC decoding on multiple data blocks according to the FEC parity bits to obtain FEC decoded data.
  • the actions of error detection and error correction can be performed in parallel.
  • no errors are found in the multiple data blocks, there is no need to wait for/use the above-mentioned FEC decoding data, and directly use the data of the multiple data blocks as the decoding result of the coded data block.
  • the above-mentioned FEC decoding data needs to be used.
  • the data of the data block can be directly used as the decoding result of the data block.
  • the data corresponding to the data block in the FEC decoding data is used as the decoding result of the data block, and finally the decoding results of each data block are comprehensively used as the decoding of the encoded data block result.
  • the order of multiple data blocks can also be considered here, and the verification is performed sequentially.
  • the data block and other subsequent data blocks are included in the FEC decoding data.
  • the corresponding data are respectively used as the decoding results of the data block and other data blocks after it, so the verification results of other data blocks after this data block can be ignored, and even the coded data block after this data block can be stopped. Checksum of other data blocks.
  • FIG. 29 is a schematic structural diagram of an apparatus 2900 provided by an embodiment of the present application.
  • the apparatus 2900 includes an acquisition module 2901 , a processing module 2902 and a sending module 2903 .
  • the acquiring module 2901 is configured to: acquire multiple data blocks.
  • the processing module 2902 is configured to: respectively generate a plurality of first check digits according to the plurality of data blocks, the plurality of first check digits are in one-to-one correspondence with the plurality of data blocks, and generate forward error correction (FEC) checksums according to the plurality of data blocks. Check the position to obtain the coded data block.
  • FEC forward error correction
  • the sending module 2903 is configured to: send the coded data block.
  • said generating a plurality of first check digits respectively according to a plurality of data blocks includes: respectively encoding the data of a plurality of data blocks by one or more encoding methods to generate a plurality of first check digits. Check Digit.
  • the generating the FEC check bits according to the multiple data blocks includes: generating the FEC check bits according to the multiple data blocks and the multiple first check bits.
  • the above-mentioned device 2900 may correspond to the sending device 100 in the communication system in FIG. 1 , and is specifically used to implement the embodiment of the sending method in FIG. 7 , FIG. 19 or FIG. 27 . Please refer to the relevant description above, and details will not be repeated here.
  • the device 2900 provided in the embodiment of FIG. 29 is only illustrated by the division of the above-mentioned functional modules/units. In practical applications, the above-mentioned function allocation can be completed by different functional modules/units according to needs. , that is to say, the internal structure of the device 2900 can be divided into other different functional modules/units, so as to complete all or part of the functions described above.
  • FIG. 30 is a schematic structural diagram of an apparatus 3000 provided by an embodiment of the present application.
  • the apparatus 3000 includes an acquisition module 3001 and a processing module 3002 .
  • the obtaining module 3001 is used to: obtain the coded data block, wherein the coded data block includes multiple data blocks, multiple first parity bits and FEC parity bits, and the multiple first parity bits correspond to multiple data blocks one-to-one , the FEC parity bit corresponds to multiple data blocks.
  • the processing module 3002 is configured to: check a corresponding data block according to a plurality of first check bits and/or FEC check bits to obtain a decoding result of the coded data block.
  • checking the corresponding data block according to the multiple first check bits and/or FEC check bits to obtain the decoding result of the coded data block includes: respectively Check whether there is an error in the corresponding data block; in the case that multiple data blocks are checked for errors, perform FEC decoding on the multiple data blocks according to the FEC parity bit to obtain a decoding result of the encoded data block.
  • the processing module 3002 is further configured to: take the multiple data blocks as a decoding result of the coded data block when no error is detected in the multiple data blocks. It should be noted that, in this application, if none of the multiple data blocks has been checked for errors, that is, none of the multiple data blocks has been checked for errors, it indicates that "the Multiple data blocks have not been checked for errors”; if at least one of the multiple data blocks has been checked for errors, it indicates "the multiple data blocks have been checked for errors”.
  • performing FEC decoding on multiple data blocks according to the FEC parity bit to obtain a decoding result of the coded data block includes: In the case that a data block does not check out an error, the first data block is used as the decoding result of the first data block, and the first data block is a data block in a plurality of data blocks; In the case of an error, perform FEC decoding on a plurality of data blocks according to the FEC parity bit to obtain FEC decoding data, and use the data corresponding to the second data block in the FEC decoding data as the decoding result of the second data block, the second data block The second data block is one of the multiple data blocks; the decoding results of the multiple data blocks are used as the decoding results of the coded data block.
  • the above-mentioned multiple data blocks have a sequence; the checking whether there is an error in the corresponding data block according to the multiple first check digits respectively includes: checking in sequence according to the multiple first check digits Whether there is an error in the corresponding data block; said using the data corresponding to the second data block in the FEC decoding data as the decoding result of the second data block includes: using the second data block and other data after the second data block The data corresponding to the block in the FEC decoded data is respectively used as the decoding results of the second data block and other data blocks after the second data block.
  • the verifying the corresponding data block according to the multiple first check bits and/or the FEC check bits to obtain the decoding result of the coded data block includes: according to the multiple first check bits Check whether there are errors in the corresponding data blocks, and perform FEC decoding on multiple data blocks according to the FEC parity bit to obtain FEC decoded data; The data gets the decoded result of the coded data block.
  • the FEC decoding is performed on the multiple data blocks to obtain the FEC decoding Code data is executed in parallel.
  • the processing module 3002 is further configured to: if no error is detected in the plurality of data blocks In some cases, the plurality of data blocks are used as the decoding result of the coded data block.
  • said obtaining the decoding result of the coded data block according to the FEC decoding data in the case where errors are detected in multiple data blocks includes: when no error is detected in the first data block Next, the first data block is used as the decoding result of the first data block, and the first data block is one data block among multiple data blocks; in the case that an error is found in the second data block, the second data block is The corresponding data in the FEC decoding data is used as the decoding result of the second data block, and the second data block is a data block in the plurality of data blocks; the decoding results of the plurality of data blocks are used as the decoding of the encoded data block result.
  • the above-mentioned multiple data blocks have a sequence; the checking whether there is an error in the corresponding data block according to the multiple first check digits respectively includes: checking in sequence according to the multiple first check digits Whether there is an error in the corresponding data block; said using the data corresponding to the second data block in the FEC decoding data as the decoding result of the second data block includes: using the second data block and other data after the second data block The data corresponding to the block in the FEC decoded data is respectively used as the decoding results of the second data block and other data blocks after the second data block.
  • the above device 3000 may correspond to the receiving device 200 in the communication system in FIG. 1 , and is specifically used to implement the embodiment of the receiving method in FIG. 21 , FIG. 25 or FIG. 28 . Please refer to the relevant description above, and details will not be repeated here.
  • the device 3000 provided by the embodiment in Fig. 30 is only illustrated by the division of the above-mentioned functional modules/units. In actual applications, the above-mentioned functions can be assigned to different functional modules/units according to needs. To complete means to divide the internal structure of the device 3000 into other different functional modules/units to complete all or part of the functions described above.
  • FIG. 31 is a schematic structural diagram of a device 3100 provided in an embodiment of the present application.
  • the device 3100 may be devices such as a notebook computer, a tablet computer, and a cloud server, which are not specifically limited in this application.
  • the device 3100 includes a processor 3101, a memory 3102, and a communication interface 3103, and the device 3100 is specifically configured to implement any embodiment of the sending method in FIG. 7 , FIG. 19 or FIG. 17 .
  • the processor 3101, the memory 3102, and the communication interface 3103 may be connected to each other through an internal bus 3104, or communicate through other means such as wireless transmission.
  • the bus 3104 can be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus, an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (unified bus) , Ubus or UB), computer express link (compute express link, CXL) bus, cache coherent interconnect for accelerators (CCIX) bus, etc.
  • PCI peripheral component interconnect standard
  • EISA extended industry standard architecture
  • unified bus unified bus
  • Ubus or UB unified bus
  • CXL compute express link
  • CXL cache coherent interconnect for accelerators
  • the processor 3101 may be composed of at least one general-purpose processor, such as a central processing unit (central processing unit, CPU), or a combination of a CPU and a hardware chip.
  • the aforementioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof.
  • the aforementioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof.
  • the processor 3101 executes various types of digitally stored instructions, such as software or firmware programs stored in the memory 3102, which enable the device 3100 to provide various services.
  • the memory 3102 is used to store program codes, which are executed under the control of the processor 3101 .
  • the memory 3102 may include a volatile memory (volatile memory), such as a random access memory (random access memory, RAM); the memory 3102 may also include a non-volatile memory (non-volatile memory), such as a read-only memory (read-only memory). only memory, ROM), flash memory (flash memory), hard disk (hard disk drive, HDD) or solid-state drive (solid-state drive, SSD); the memory 3102 may also include a combination of the above types.
  • the memory 3102 may store program codes, which may specifically include program codes for executing any embodiment of the sending method in FIG. 7 , FIG. 19 or FIG. 27 , which will not be repeated here.
  • the communication interface 3103 can be a wired interface (such as an Ethernet interface), an internal interface (such as a high-speed serial computer expansion bus (peripheral component interconnect express, PCIe) bus interface), a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or using a wireless LAN interface) for communicating with other devices or modules.
  • a wired interface such as an Ethernet interface
  • an internal interface such as a high-speed serial computer expansion bus (peripheral component interconnect express, PCIe) bus interface
  • a wired interface such as an Ethernet interface
  • a wireless interface such as a cellular network interface or using a wireless LAN interface
  • the foregoing device 3100 may be applied to the communication system architecture shown in FIG. 1 , for example, may be the sending apparatus 100 in FIG. 1 , and is configured to execute the sending method in FIG. 7 , FIG. 19 or FIG. 27 .
  • this embodiment can be implemented by a general physical server, for example, an ARM server or an X86 server, or it can be realized based on a general physical server combined with a virtual machine implemented by NFV technology.
  • a virtual machine refers to a virtual machine simulated by software
  • a complete computer system with complete hardware system functions and running in a completely isolated environment is not specifically limited in this application.
  • the device 3100 shown in FIG. 31 may also be a server cluster composed of at least one server, which is not specifically limited in this application.
  • FIG. 31 is only a possible implementation of the embodiment of the present application.
  • the device 3100 may also include more or fewer components, which is not specifically limited in the present application.
  • the relevant explanations in the embodiment of the sending method in FIG. 7 , FIG. 19 or FIG. 27 are not repeated here.
  • FIG. 32 is a schematic structural diagram of a device 3200 provided in an embodiment of the present application.
  • the device 3200 may be devices such as a notebook computer, a tablet computer, and a cloud server, which are not specifically limited in this application.
  • the device 3200 includes a processor 3201, a memory 3202, and a communication interface 3203, and the device 3200 is specifically configured to implement any embodiment of the receiving method in FIG. 21 , FIG. 25 or FIG. 28 .
  • the processor 3201, the memory 3202, and the communication interface 3203 may be connected to each other through an internal bus 3204, or communicate through other means such as wireless transmission.
  • the bus 3204 can be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus, an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (unified bus) , Ubus or UB), computer express link (compute express link, CXL) bus, cache coherent interconnect for accelerators (CCIX) bus, etc.
  • PCI peripheral component interconnect standard
  • EISA extended industry standard architecture
  • unified bus unified bus
  • Ubus or UB unified bus
  • CXL compute express link
  • CXL cache coherent interconnect for accelerators
  • the bus 3204 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used in FIG. 32 , but it does not mean that there is only one bus or one type of bus.
  • the processor 3201 may be composed of at least one general-purpose processor, such as a central processing unit (central processing unit, CPU), or a combination of a CPU and a hardware chip.
  • the aforementioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof.
  • the aforementioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof.
  • the processor 3201 executes various types of digitally stored instructions, such as software or firmware programs stored in the memory 3202, which enable the device 3200 to provide various services.
  • the memory 3202 is used to store program codes, which are executed under the control of the processor 3201 .
  • the memory 3202 may include a volatile memory (volatile memory), such as a random access memory (random access memory, RAM); the memory 3202 may also include a non-volatile memory (non-volatile memory), such as a read-only memory (read-only memory). only memory (ROM), flash memory (flash memory), hard disk (hard disk drive, HDD) or solid-state drive (solid-state drive, SSD); the memory 3202 may also include a combination of the above types.
  • the memory 3202 may store program codes, which may specifically include program codes for executing any embodiment of the receiving method in FIG. 21 , FIG. 25 or FIG. 28 , which will not be repeated here.
  • the communication interface 3203 can be a wired interface (such as an Ethernet interface), an internal interface (such as a high-speed serial computer expansion bus (peripheral component interconnect express, PCIe) bus interface), a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or using a wireless LAN interface) for communicating with other devices or modules.
  • a wired interface such as an Ethernet interface
  • an internal interface such as a high-speed serial computer expansion bus (peripheral component interconnect express, PCIe) bus interface
  • a wired interface such as an Ethernet interface
  • a wireless interface such as a cellular network interface or using a wireless LAN interface
  • the above-mentioned device 3200 may be applied to the communication system architecture shown in FIG. 1 , for example, it may be the receiving apparatus 200 in FIG. 1 , configured to execute the receiving method in FIG. 21 , FIG. 25 or FIG. 28 .
  • this embodiment can be implemented by a general physical server, for example, an ARM server or an X86 server, or it can be realized based on a general physical server combined with a virtual machine implemented by NFV technology.
  • a virtual machine refers to a virtual machine simulated by software
  • a complete computer system with complete hardware system functions and running in a completely isolated environment is not specifically limited in this application.
  • the device 3200 shown in FIG. 32 may also be a server cluster composed of at least one server, which is not specifically limited in this application.
  • FIG. 32 is only a possible implementation of the embodiment of the present application.
  • the device 3200 may include more or fewer components, which is not specifically limited in the present application.
  • An embodiment of the present application further provides a system, including the device 2900 in any of the above embodiments and the device 3000 in any of the above embodiments.
  • An embodiment of the present application further provides a system, including the device 3100 in any of the foregoing embodiments and the device 3200 in any of the foregoing embodiments.
  • the embodiment of the present application also provides a chip, which is used to execute the method of any embodiment in FIG. 27 or FIG. 28 .
  • the embodiment of the present application also provides a computer-readable storage medium, and instructions are stored in the computer-readable storage medium, and when the instructions are executed on a processor, the method in any one of the embodiments in FIG. 27 or FIG. 28 is realized.
  • the embodiment of the present application also provides a computer program product, and when the computer program product is run on a processor, the method in any one of the embodiments in FIG. 27 or FIG. 28 is implemented.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (read-only memory, ROM) or a random access memory (random access memory, RAM), etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

本申请公开了一种发送方法、接收方法、装置、系统、设备及存储介质，该接收方法包括：获取编码数据块，其中，编码数据块包括多个数据块、多个第一校验位和FEC校验位，多个第一校验位和多个数据块一一对应，FEC校验位和多个数据块对应；然后，根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果。该方法既能够保留高增益FEC码的纠错能力，又能够降低高增益FEC对于时延的影响，可以同时满足低时延和FEC高增益的需求。

Description

发送方法、接收方法、装置、系统、设备及存储介质
本申请要求于2021年12月22日提交中国专利局、申请号为202111578236X、申请名称为“发送方法、接收方法、装置、系统、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种发送方法、接收方法、装置、系统、设备及存储介质。
背景技术
当前各种通信链路的速率迭代非常之快，但链路质量却随着链路速率的提升而逐步劣化。为解决链路质量恶化所带来的误码率增大等问题，前向纠错(forward error correction，FEC)成为了必要的使能技术。
例如，现有的以太网(Ethernet)标准和外围组件快速互联(peripheral component interconnect express，PCIe)6.0中都引入了FEC技术，以提供一定的误码纠错能力，但同时也面临着因FEC译码而带来的时延增加等问题，难以满足计算、存储等应用场景对于时延的要求。
因此，有必要提供一种能够同时满足低时延和高增益的FEC解决方案。
发明内容
为了兼顾低时延和高增益，本申请实施例提供一种发送方法、接收方法、装置、系统、设备及存储介质，既能够保留高增益FEC码的纠错能力，又能够降低高增益FEC对于时延的影响。
第一方面，本申请提供了一种发送方法，该方法包括：获取多个数据块；根据多个数据块分别生成多个第一校验位，多个第一校验位和多个数据块一一对应，并根据多个数据块生成前向纠错FEC校验位，从而得到编码数据块；发送编码数据块。
可以看出，本申请实施例为每个数据块都添加了一个相应的第一校验位，以提供一定的检错能力，于是可以通过多个第一校验位分别对相应的数据块进行独立校验，以确定各数据块中是否存在错误，从而可以实现对编码数据块中的错误的预判。本申请实施例还为这多个数据块添加了FEC校验位(FEC校验位可以根据上述多个数据块进行FEC编码而生成)，以提供一定的纠错能力，于是可以通过FEC校验位对编码数据块(或者说对编码数据块中的上述多个数据块)中的错误进行纠正。
通过本申请实施例的发送方法，使得检错和纠错可以采用两种不同的处理粒度，而且两种处理粒度之间具有包含关系，其中，检错以一个个的数据块为处理粒度，纠错以整个编码数据块(或者说多个数据块)为处理粒度，编码数据块中包含多个数据块。于是，编码数据块对应的解码方式会变得十分灵活，有助于降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益的FEC。
基于第一方面，在可能的实施例中，所述根据多个数据块分别生成多个第一校验位，包 括：通过一种或多种编码方式对这多个数据块的数据分别进行编码，从而生成多个第一校验位。
也就是说，每个数据块所对应的第一校验位，可以通过对该数据块的数据进行一种或多种编码来生成。于是，第一校验位的设计变得十分灵活，有助于控制第一校验位的长度，减少带宽占用，也使得数据块的长度设计变得更为灵活，还有助于提升第一校验位的可靠性，降低错误漏检的概率。
基于第一方面，在可能的实施例中，所述根据多个数据块生成FEC校验位，包括：根据多个数据块和多个第一校验位生成FEC校验位。
也就是说，除了多个数据块，它们所对应的第一校验位也可以作为FEC有效负载的一部分参与到FEC编码当中，从而生成FEC校验位。于是，FEC校验位不仅能发现并纠正编码数据块中的这多个数据块中的错误，还能够发现并纠正第一校验位中的错误。
第二方面，本申请实施例提供了一种接收方法，该方法包括：获取编码数据块，其中，编码数据块包括多个数据块、多个第一校验位和FEC校验位，多个第一校验位和多个数据块一一对应，FEC校验位和多个数据块对应；根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果。
可以看出，编码数据块中的多个第一校验位与多个数据块是一一对应的，而FEC校验位对应的是多个数据块(或者说对应的是整个编码数据块)，因此，可以通过多个第一校验位分别校验对应的数据块，也可以通过FEC校验位校验这多个数据块，从而得到编码数据块的译码结果。显然，这种编码数据块对应的解码方式可以很灵活，有助于降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益的FEC。
基于第二方面，在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误；在多个数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码以得到编码数据块的译码结果。
可以看出，本申请实施例根据多个第一校验位分别校验对应的数据块，以分别确定各数据块是否存在错误，也就是说，检错是以数据块为处理粒度的，编码数据块中的各数据块可以独立校验，以实现编码数据块中错误的预判。在这多个数据块校验出错误的情况下(即多个数据块中至少有一个数据块被校验出错误)，便可以根据FEC校验位对这多个数据块进行FEC译码，以得到编码数据块的译码结果。可以理解的是，因为在有错情况下才需要启动FEC译码、才会引入FEC译码时延，所以能够降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益的FEC。
基于第二方面，在可能的实施例中，该方法还包括：在多个数据块没有校验出错误的情况下，将多个数据块作为编码数据块的译码结果。
也就是说，在这多个数据块均没有校验出错误的情况下，不需要启动FEC译码，可以直接把这多个数据块的数据作为该编码数据块的译码结果，既能够节省功耗，也能够降低FEC译码对时延的影响。
基于第二方面，在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码以得到编码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是多个数据块中的一个数据块；在第二数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码得到FEC译码数据，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译 码结果，第二数据块是多个数据块中的一个数据块；将多个数据块的译码结果作为编码数据块的译码结果。
可以理解的是，编码数据块中的多个数据块是分别根据它们对应的第一校验位进行检错的。在某个数据块没有校验出错误的情况下，可以直接以该数据块作为它自身的译码结果；在某个数据块校验出错误的情况下，就需要启动FEC功能，使用FEC校验位对这多个数据块(或者说整个编码数据块)进行FEC译码得到FEC译码数据，应理解，该数据块在FEC译码数据中对应的数据是该数据块的错误被纠正后的数据。
显然，检错是以数据块为处理粒度的，编码数据块包含多个数据块，所以编码数据块中的各数据块可以独立校验，以实现编码数据块中错误的预判；而纠错是以多个数据块为处理粒度的，可以一次纠正多个数据块中存在的错误(包括各个数据块中存在的错误)。最后，将多个数据块各自对应的译码结果组合起来作为该编码数据块的译码结果。
基于第二方面，在可能的实施例中，多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
也就是说，编码数据块中的多个数据块之间可以有先后顺序，根据多个第一校验位对这多个数据块的校验可以是依次进行的。在某个数据块没有校验出错误的情况下，直接以该数据块作为它自身的译码结果。
当这多个数据块中有任意一个数据块被校验出错误时，就需要启动FEC功能，根据FEC校验位对这多个数据块进行FEC译码得到FEC译码数据，然后，把校验出错误的这个数据块及其之后的其他数据块在FEC译码数据中对应的数据，分别作为该数据块及其之后的其他数据块的译码结果，这时候可以忽略该数据块之后的其他数据块的校验结果(无论该数据块之后的其他数据块是否还会校验出错误)，甚至可以停止该数据块之后的其他数据块的校验，以节省能耗。因为现在各个数据块对应的译码结果已经确定了，所以直接可以把这多个数据块各自的译码结果组合起来作为整个编码数据块的译码结果。
基于第二方面，在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误，并根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据；在多个数据块校验出错误的情况下，根据FEC译码数据得到编码数据块的译码结果。
可以看出，本申请实施例可以根据多个第一校验位分别校验对应的数据块，以确定这多个数据块是否存在错误，并且根据FEC校验位对这多个数据块进行FEC译码以得到FEC译码数据。也就是说，检错是以数据块为处理粒度的，编码数据块包含多个数据块，所以编码数据块中的各数据块可以独立校验，以实现编码数据块中错误的预判；而纠错是以多个数据块为处理粒度的，可以一次纠正多个数据块的错误(包括各个数据块中存在的错误)。显然，检错和纠错采用的是两种不同的处理粒度，而且两种处理粒度具有包含关系，即编码数据块包含多个数据块。
应理解，如果某个数据块存在错误，那么该数据块在FEC译码数据中对应的数据是该数据块经过纠错后的数据；如果某个数据块没有错误，那么该数据块在FEC译码数据中对应的数据是没有经过纠错的，与该数据块本身的数据一样。在这多个数据块校验出错误的情况下(即多个数据块中至少有一个数据块被校验出错误)，便可以根据FEC译码数据得到编码数 据块的译码结果。
可以理解的是，因为在有错情况下才需要使用FEC译码数据、才会引入FEC译码时延，所以能够降低FEC译码的时延影响，有助于实现低时延和高增益。
基于第二方面，在可能的实施例中，所述根据多个第一校验位分别校验对应的数据块是否存在错误，以及，根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据，是并行执行的。
也就是说，以数据块为处理粒度的检错和以多个数据块为处理粒度的纠错可以并行执行，有利于降低FEC译码的时延影响。
基于第二方面，在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，还包括：在多个数据块没有校验出错误的情况下，将多个数据块作为编码数据块的译码结果。
也就是说，在这多个数据块均没有校验出错误的情况下，不需要等待FEC译码得到的FEC译码数据，可以直接把这多个数据块的数据作为编码数据块的译码结果，能够省去无错情况下的FEC译码时延，从而解决高增益FEC对时延影响大的问题，以满足低时延场景的需求。
基于第二方面，在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC译码数据得到编码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是多个数据块中的一个数据块；在第二数据块校验出错误的情况下，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，第二数据块是多个数据块中的一个数据块；将多个数据块的译码结果作为编码数据块的译码结果。
可以看出，在某个数据块根据其对应的第一校验位没有校验出错误的情况下，直接把该数据块的数据作为该数据块的译码结果。在某个数据块根据其对应的第一校验位校验出错误的情况下，则需要使用根据FEC校验位进行FEC译码而得到的FEC译码数据，将该数据块在FEC译码数据中对应的数据作为该数据块的译码结果。最后，将编码数据块中的各个数据块所对应的译码结果组合起来作为该编码数据块的译码结果。
可以理解的是，因为在编码数据块中至少有一个数据块有错的情况下才需要使用FEC译码数据、才会引入FEC译码时延，所以FEC收帧和译码时延对接口时延的影响变小，从固定的FEC译码时延变为了动态时延抖动，能够消除高增益FEC的时延弊端。
基于第二方面，在可能的实施例中，多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
可以看出，编码数据块中的多个数据块之间可以有先后顺序，根据多个第一校验位对这多个数据块的校验可以是依次进行的，顺序靠前的数据块优先进行校验(即检错)。
当某个数据块没有校验出错误时，直接以该数据块的数据作为该数据块的译码结果。
当某个数据块校验出错误的情况下，把该数据块及其之后的其他数据块在FEC译码数据中对应的数据分别作为该数据块及其之后的其他数据块的译码结果。然后，可以忽略该数据块之后的其他数据块的检错结果，甚至可以停止对该数据块之后的其他数据块的检错，直接把各数据块的译码结果综合作为该编码数据块的译码结果。既实现了错误的纠正，保证输出误码率，还有助于降低时延。
第三方面，本申请实施例提供了一种装置，该装置包括：获取模块，用于获取多个数据块；处理模块，用于根据多个数据块分别生成多个第一校验位，多个第一校验位和多个数据块一一对应，并根据多个数据块生成前向纠错FEC校验位，从而得到编码数据块；发送模块，用于发送编码数据块。
在可能的实施例中，所述根据多个数据块分别生成多个第一校验位，包括：通过一种或多种编码方式对多个数据块的数据分别进行编码，生成多个第一校验位。
在可能的实施例中，所述根据多个数据块生成FEC校验位，包括：根据多个数据块和多个第一校验位生成FEC校验位。
第四方面，本申请实施例提供了另一种装置，该装置包括：获取模块，用于获取编码数据块，其中，编码数据块包括多个数据块、多个第一校验位和FEC校验位，多个第一校验位和多个数据块一一对应，FEC校验位和多个数据块对应；处理模块，用于根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果。
在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误；在多个数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码以得到编码数据块的译码结果。
在可能的实施例中，该方法还包括：在多个数据块没有校验出错误的情况下，将多个数据块作为编码数据块的译码结果。
在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码以得到编码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是这多个数据块中的一个数据块；在第二数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码得到FEC译码数据，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，第二数据块是多个数据块中的一个数据块；将这多个数据块的译码结果作为编码数据块的译码结果。
在可能的实施例中，多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误，并根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据；在多个数据块校验出错误的情况下，根据FEC译码数据得到编码数据块的译码结果。
在可能的实施例中，所述根据多个第一校验位分别校验对应的数据块是否存在错误，以及，所述根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据，这两个动作是并行执行的。
在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，还包括：在多个数据块没有校验出错误的情况下，将多个数据块作为编码数据块的译码结果。
在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC译码数据得到编 码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是这多个数据块中的一个数据块；在第二数据块校验出错误的情况下，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，第二数据块是这多个数据块中的一个数据块；将这多个数据块的译码结果作为编码数据块的译码结果。
在可能的实施例中，多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
第五方面，本申请实施例提供了一种系统，包括第三方面中任一实施例的装置和第四方面中任一实施例的装置。
第六方面，本申请实施例提供了一种设备，包括处理器和存储器；处理器和存储器可通过总线相互连接，也可以集成在一起。该处理器用于读取存储器中存储的程序代码，以使得所述设备执行上述第一方面或第二方面中任一实施例的方法。
第七方面，本申请实施例提供一种计算机可读存储介质；该计算机可读存储介质用于存储上述第一方面或第二方面中的任一实施例方法的实现代码。
第八方面，本申请实施例提供了一种计算机程序(产品)，该计算机程序(产品)包括程序指令，当该计算机程序产品被执行时，用于执行上述第一方面或第二方面中的任一实施例的方法。
第九方面，本申请实施例提供了一种芯片，该芯片用于执行上述第一方面或第二方面中的任一实施例的方法。
综上所述，本申请实施例在发送端，为多个数据块分别生成一个对应的第一校验位，并且为多个数据块共同生成一个对应的FEC校验位，使得接收端能够通过多个第一校验位分别校验对应的数据块是否存在错误，实现对编码数据块中的错误的预判，还使得接收端能够通过FEC校验位对这多个数据块中存在的错误进行纠正。于是，接收端可以灵活地设计编码数据块的解码方式，有助于降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益。
相应的，本申请实施例在接收端，可以根据编码数据块中的多个第一校验位和/或FEC校验位来获得该编码数据块的译码结果，主要分为按需启动FEC和检错纠错并行两类方案。
在按需启动FEC的方案中，首先根据多个第一校验位校验对应的数据块是否存在错误，如果这多个数据块均没有校验出错误，就可以直接把这多个数据块的数据作为编码数据块的译码结果；如果这多个数据块校验出错误(也就是说，多个数据块中至少有一个数据块被校验出错误)，就需要启动FEC功能，根据FEC校验位对这多个数据块进行FEC译码得到FEC译码数据，对于没有校验出错误的数据块，可以直接以该数据块的数据作为该数据块的译码结果，而对于校验出错误的数据块，以该数据块在FEC译码数据中对应的数据作为该数据块的译码结果，最后将各个数据块的译码结果综合作为该编码数据块的译码结果。当然，还可以考虑多个数据块之间的先后顺序，按照先后次序校验各个数据块是否有错，当校验到某个数据块有错时，才会启动FEC译码得到FEC译码数据，然后将该数据块及其之后的其他数据块在FEC译码数据中对应的数据分别作为该数据块及其之后的其他数据块的译码结果，于是可以忽略掉该数据块之后的其他数据块的校验结果，甚至可以停止对编码数据块中该数据块之后的其他数据块的校验。可以理解的是，因为在有错情况下才需要启动FEC译码、才会 引入FEC译码时延，所以能够降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益。
在检错纠错并行的方案中，可以根据多个数据块分别校验对应的数据块是否存在错误，并且根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据，上述检错和纠错的动作可以并行执行。在这多个数据块没有校验出错误的情况下，不需要等待/使用上述FEC译码数据，直接把这多个数据块的数据作为编码数据块的译码结果。在这多个数据块校验出错误的情况下，就需要使用上述FEC译码数据，对于没有校验出错误的数据块，可以直接以该数据块的数据作为该数据块的译码结果，而对于校验出错误的数据块，以该数据块在FEC译码数据中对应的数据作为该数据块的译码结果，最后以各个数据块的译码结果综合作为该编码数据块的译码结果。当然，这里也可以考虑多个数据块的先后顺序，依次进行校验，当校验到某个数据块有错的情况下，将该数据块及其之后的其他数据块在FEC译码数据中对应的数据分别作为该数据块及其之后的其他数据块的译码结果，于是可以忽略掉该数据块之后的其他数据块的校验结果，甚至可以停止对编码数据块中该数据块之后的其他数据块的校验。可以理解的是，因为在有错情况下才需要使用FEC译码数据、才会引入FEC译码时延，所以能够降低FEC译码的时延影响，有助于实现低时延和高增益，并且，由于保留了高增益FEC码的纠错能力，有利于控制输出误码率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面对实施例描述中所需要使用的附图作简单地介绍。
图1是本申请实施例提供的一种通信系统的架构示意图；
图2是本申请实施例提供的一种发送装置的结构示意图；
图3是本申请实施例提供的又一种发送装置的结构示意图；
图4是本申请实施例提供的一种接收装置的结构示意图；
图5是本申请实施例提供的又一种接收装置的结构示意图；
图6是本申请实施例提供的又一种接收装置的结构示意图；
图7是本申请实施例提供的一种发送方法的流程示意图；
图8是本申请实施例提供的一种发送装置的处理流程示意图；
图9是本申请实施例提供的一种将有效数据切分为设定长度的数据块的示意图；
图10是本申请实施例提供的一种物理校验单元的示意图；
图11是本申请实施例提供的又一种将有效数据切分为设定长度的数据块的示意图；
图12是本申请实施例提供的一种BCH编码和CRC编码组合的示意图；
图13是本申请实施例提供的一种将有效数据切分为定长的数据块的示意图；
图14是本申请实施例提供的一种将物理校验单元中的数据块作为FEC有效负载的示意图；
图15是本申请实施例提供的一种将物理校验单元中的有效数据以及BCH校验位均作为FEC有效负载的示意图；
图16是本申请实施例提供的一种物理校验单元的示意图；
图17是本申请实施例提供的一种将物理校验单元中的数据块以及eBCH校验位均作为FEC有效负载的示意图；
图18是本申请实施例提供的一种只把物理校验单元中的数据块作为FEC有效负载的示意图；
图19是本申请实施例提供的又一种发送方法的流程示意图；
图20是本申请实施例提供的一种发送装置的处理流程示意图；
图21是本申请实施例提供的一种接收方法的流程示意图；
图22是本申请实施例提供的一种检错路径和纠错路径并行执行的示意图；
图23是本申请实施例提供的一种编码数据块的示意图；
图24是本申请实施例提供的又一种接收装置的处理流程示意图；
图25是本申请实施例提供的又一种接收方法的流程示意图；
图26是本申请实施例提供的一种按需启动FEC译码的示意图；
图27是本申请实施例提供的一种发送方法的流程图；
图28是本申请实施例提供的一种接收方法的流程图；
图29是本申请实施例提供的一种装置的结构示意图；
图30是本申请实施例提供的又一种装置的结构示意图；
图31是本申请实施例提供的一种设备的结构示意图；
图32是本申请实施例提供的又一种设备的结构示意图。
具体实施方式
为了便于理解本申请实施例中的技术方案，下面对本申请实施例中涉及的部分术语及概念进行简单说明。
1、前向纠错(forward error correction，FEC)：
FEC是一种差错控制方式，它是指信号在被送入传输信道之前按照一定的算法进行编码处理，加入带有信号本身特征的冗余码，在接收端依照相应算法对接收到的信号进行解码，从而找出在传输过程中产生的错误码并将其纠正的技术。FEC编码增益，则是衡量FEC码的纠错能力的指标。
2、里德-所罗门(Reed-Solomon，简称RS)码：
RS码是一种前向纠错码，其参数表示方式通常为RS(n，k，t，m)、RS(n，k，m)或RS(n，k)。其中，n表示该RS码的总长度，k表示该RS码中的有效负载(payload)的长度，t表示该RS码的纠错能力，n、k、t这三个参数均以符号为单元，m则表示每个符号中所包含的比特(bit)数。利用RS码所实现的FEC策略，通常也称为RS-FEC。
下面介绍本申请实施例中涉及的通信系统。
请参见图1，图1是本申请实施例中提供的一种通信系统的架构示意图，该通信系统包括发送装置100和接收装置200，发送装置100与接收装置200通过通信链路进行连接。通信链路可以是PCIe总线或者以太网线等等，本申请不做具体限定。
发送装置100用于对有效数据(或者说待FEC编码的数据)进行编码，以得到编码数据块，然后将编码数据块发送给接收装置200。
接收装置200用于对接收到的编码数据块进行译码，以得到该编码数据块的译码结果(即恢复出原始的有效数据)。
发送装置100和接收装置200分别可以是处理器、加速器、存储器、输入/输出(input/output， I/O)设备、通讯芯片、网络连接设备或者计算设备等等，本申请不做具体限定。
需要说明的是，图1中的通信链路除了有相应的物理介质，比如光纤、双绞线或者同轴电缆等等，可能还包括串并转换器件、调制器、解调器或者光电/电光装换器件等等(图中省略了这部分器件/模块)，以便编码数据块能够转化为适合该物理介质的传输信号。也就是说，发送装置100的编码数据块可能不是直接传输给接收装置200的，还需要转化成合适的传输信号后再传输过去。相应的，接收装置200需要从传输信号中恢复出编码数据块，再对该编码数据块进行译码。
下面分别对发送装置100和接收装置200进行具体介绍：
(1)在一具体实施例中，如图2所示，发送装置100包括校验单元处理模块101和FEC编码模块102。
校验单元处理模块101，用于将其输入数据切分为设定长度的数据块，为每个数据块生成(或者说添加、插入)相应的Pchit校验位。其中，一个数据块及其相应的Pchit校验位构成一个物理校验单元(physical check unit，简称为Pchit)，Pchit校验位则用于判断该Pchit中是否存在错误。
FEC编码模块102，用于执行FEC编码。
在一种可能的实施例中，如图2所示，校验单元处理模块101位于FEC编码模块102之前，即校验单元处理模块101的输出作为FEC编码模块102的输入。具体来说，有效数据首先输入校验单元处理模块101，校验单元处理模块101对有效数据进行数据块的切分以及Pchit校验位的添加后，输入到FEC编码模块102中；接着，FEC编码模块102对校验单元处理模块101输入的数据进行FEC编码，得到编码数据块。
在又一种可能的实施例中，如图3所示，校验单元处理模块101位于FEC编码模块102之后，即FEC编码模块102的输出作为校验单元处理模块101的输入。具体来说，有效数据首先输入FEC编码模块102，FEC编码模块102对有效数据进行FEC编码后输入到校验单元处理模块101中；接着，校验单元处理模块101对FEC编码模块102输入的数据进行数据块的切分以及Pchit校验位的添加，从而得到编码数据块。
(2)在一具体实施例中，如图4所示，接收装置200包括缓存模块201、校验模块202、FEC译码模块203和数据选择器204。
其中，缓存模块201用于缓存数据。校验模块202用于对Pchit进行校验，以确定Pchit是否存在错误。FEC译码模块203用于执行FEC译码。需要说明的是，缓存模块201和校验模块202一起构成检错路径，而FEC译码模块203构成纠错路径，数据选择器204则用于在检错路径和纠错路径这两路的输出数据之间进行选择，以选择的数据作为数据选择器204的输出(即译码结果)。
在一种可能的实施例中，如图4所示，缓存模块201位于校验模块202之前，也就是说，缓存模块201先对编码数据块(或者是Pchit)进行缓存，然后校验模块202再对编码数据中的各个Pchit进行校验。
在又一种可能的实施例中，如图5所示，缓存模块201位于校验模块202之后，也就是说，校验模块202先对编码数据块中的各个Pchit进行校验，每当校验模块202完成一个Pchit的校验，缓存模块201再把该Pchit缓存起来。
上述两种实施例表明，Pchit的校验可以在写入缓存之后，也可以在写入缓存之前。若无特别说明，下文皆以写入缓存在前、Pchit校验在后的方案为例进行描述。
在一些可能的实施例中，如图4所示，编码数据块分别输入到了检错路径和纠错路径中， 于是检错路径和纠错路径中的动作可以并行执行。
在又一些可能的实施例中，如图6所示，编码数据块一开始只输入了检错路径，而没有输入纠错路径，纠错路径中的FEC译码模块203暂时可以不工作，所以检测路径和纠错路径的动作不是并行执行的。当FEC译码模块203收到校验模块202的指示时，它才会开始工作，从缓存模块201中取出相应的数据进行FEC译码。应理解，图6中的缓存模块201也可以位于校验模块202之后，这里不过多介绍。
需要说明的是，上述发送装置100和接收装置200中的各种功能模块的划分只是示例，它们还可以包括更多或者更少的模块。比如，一个功能模块可以拆分为多个模块，多个功能模块也可以组合为一个模块，还可以有其他功能模块，本申请不做具体限定。
基于上述发送装置100和接收装置200，下面分别介绍本申请中的发送方法以及接收方法的实施例。
请参见图7，图7是本申请实施例提供的发送方法的第一实施例，用于上述发送装置100，包括以下步骤：
S701、获取有效数据。
需要说明的是，本申请实施例中的有效数据指的是待FEC编码的数据，其需要在物理层或者说以太网的物理编码子层(physical coding sublayer，PCS)中进行相应的FEC编码，以增强抵抗信道干扰的能力(使其具有一定的纠错能力)。
在可能的实施例中，有效数据是以太网PCS层中经过了64/66编码和264/257编码后的数据，所以，有效数据可以以257bit为单位输入到发送装置100中。
S702、将有效数据切分为设定长度的数据块，分别为每个数据块添加Pchit校验位得到相应的Pchit，Pchit校验位用于校验相应的Pchit是否存在错误。
需要说明的是，这里的“设定长度”其实规定的是数据块的切分粒度或者说数据块的大小，本申请不做具体限定，可以根据实际应用场景进行合理选择。
还需要说明的是，发送装置100在上一个步骤S701中可以连续接收有效数据的输入，但如果接收到的有效数据的数据量还未达到设定长度，就不足以切分为数据块(或者说还不足以作为一个数据块进行处理)，所以，发送装置100还不会执行步骤S702，继续接收有效数据的输入。当接收到的有效数据的数据量达到设定长度时，发送装置100就可以开始执行步骤S702，将设定长度的有效数据划分为一个数据块，并为该数据块添加上一个相应的Pchit校验位。
举例来说，如图8所示，发送装置100中的校验单元处理模块101在FEC编码模块102之前，校验单元处理模块101负责接收有效数据输入。
需要说明的是，图中的有效数据输入部分的虚线，是为了便于和后面切分的数据块作对应，此时的有效数据还没有做数据块的切分。还需要说明的是，图中的数据块用白色长条表示，FEC校验位用斜线填充的长条表示，Pchit校验位用灰色小方块表示，它们之间的长度关系不构成限定，一个数据块及其相应的Pchit校验位则构成一个Pchit。
如图8所示，校验单元处理模块101接收有效数据输入，然后执行动作①，把有效数据切分为设定长度的数据块，图中的各个数据块之间的传输顺序是从右到左的。校验单元处理模块101接着执行动作②，分别为各个数据块添加相应的Pchit校验位，其中，每个数据块及其相应的Pchit校验位共同构成一个Pchit，即每个Pchit中包括一个数据块及其相应的Pchit校验位，Pchit校验位可以添加在数据块的尾部。然后，校验单元处理模块101将Pchit(依次) 输入到FEC编码模块102中。
需要说明的是，为了便于和FEC编码模块102执行FEC编码后得到的编码数据块对应，图中的动作①和动作②部分分别绘制了多个数据块和多个Pchit。实际上，只要接收到的有效数据的数据量达到了设定长度，校验单元处理模块101就会将其作为一个数据块(即执行动作①)，为该数据块添加相应的Pchit校验位(即执行动作②)得到一个Pchit，然后把该Pchit送至FEC编码模块102中。当校验单元处理模块101又接收够设定长度的有效数据时，又可以将其作为一个数据块进行处理，为该数据块生成一个Pchit校验位从而得到一个Pchit，再把该Pchit发送给FEC编码模块102。
在可能的实施例中，Pchit校验位可以通过一种或多种编码方式的组合来生成。编码方式可以是(Bose-Chaudhuri-Hocquenghem，简称BCH)编码、(extendBose-Chaudhuri-Hocquenghem，简称eBCH)编码、RS编码或者循环冗余校验(cycle redundancy check，CRC)编码等等，本申请不做具体限定。
以BCH编码方式为例，如图9所示，假设数据块的切分粒度为520bit，所以发送装置100会将图中这5200bit的有效数据切分为10个数据块，依次用数据块0至数据块9来表示，每个数据块都是520bit。需要说明的是，图中的各个数据块之间的传输顺序是从上到下的，也就是从数据块0依次到数据块9。
然后，如图10所示，发送装置100采用BCH编码方式，分别为上述10个520bit的数据块添加相应的Pchit校验位，此时的Pchit校验位就是BCH校验位。以数据块1为例，对数据块1的数据采用BCH(544,520)编码，可以生成24bit的BCH校验位1；然后将BCH校验位1添加到数据块1的尾部得到544bit的Pchit 1，Pchit 1既包括520bit的数据块1，也包括24bit的BCH校验位1。
再以BCH编码和CRC编码组合的方式为例，如图11所示，假设数据块的切分粒度为X-bit，X为正整数，所以发送装置100会将图中(10×X)bit的有效数据切分为10个数据块，依次表示为数据块0至数据块9，每个数据块均为X-bit。
然后，如图12所示，发送装置100采用BCH编码和CRC编码组合的方式，分别为这10个X-bit的数据块添加相应的Pchit校验位，此时的Pchit校验位包括BCH校验位和CRC校验位这两部分。以数据块0为例，对数据块0的数据分别进行BCH编码和CRC编码，生成了Y-bit的BCH校验位0和Z-bit的CRC校验位0，然后将BCH校验位0和CRC校验位0添加到数据块0的尾部，BCH校验位和CRC校验位添加的先后顺序没有限定，得到(X+Y+Z)bit的Pchit 0，X、Y、Z均为正整数。也就是说，Pchit 0包括X-bit的数据块0以及(X+Y)bit的Pchit校验位，Pchit校验位是由Y-bit的BCH校验位0和Z-bit的CRC校验位0共同构成的。
可以理解的是，相对于只采用一种编码方式来生成Pchit校验位的情况，如果采用多种编码方式的组合来生成Pchit校验位，那么Pchit校验位的长度调节会更灵活，于是数据块的切分粒度的选择也会变得更为灵活。尤其是在Pchit校验位的长度受限的情况下，如果采用多种编码方式的组合来生成Pchit校验位，通过合理设计每种编码方式各自所得到的校验位的长度，就能够满足Pchit校验位的长度要求，减少Pchit校验位的带宽占用，还能够提升Pchit校验位的可靠性，降低错误漏检的概率。
在一种可能的实施例中，数据块的切分粒度可以和发送装置100中采用的FEC编码方式做匹配，使FEC编码方式所要求的有效负载的长度为数据块切分粒度的整数倍。比如，以太网标准中定义了两种高增益FEC码字，分别为RS(544,514,15,10)和RS(528,514,7,10)， 只要让数据块的切分粒度与这两种码字所要求的有效负载的长度匹配，就能够直接复用这两种FEC码。
具体举例来说，假设发送装置100采用的FEC编码方式为RS(544,514,10)，该RS码所要求的有效负载的长度是514个符号，并且每个符号包含10个bit，因此，该RS码要求的有效负载为514×10bit＝5140bit。可以将数据块的切分粒度设计为X-bit，使得5140bit为X-bit的整数倍，也就实现了数据块的切分粒度和FEC编码方式的匹配。于是，可以使用整数个数据块作为该RS码的有效负载进行FEC编码，并且，每个数据块所对应的Pchit校验位不作为FEC有效负载、不参与FEC编码，所以Pchit校验位的长度不会影响FEC编码，Pchit校验位的长度选择会比较自由。
在又一种可能的实施例中，数据块的切分粒度可以和以太网PCS层中采用的64/66编码和264/257编码方式进行匹配，使Pchit的切分粒度为257bit的整数倍，就能够兼容以太网标准PCS层中的处理粒度。具体来说，以太网PCS层中在执行FEC编码之前，采用了264/257编码将264bit的数据单元压缩为257bit的数据单元，所以待FEC编码的数据(即本申请实施例中的有效数据)是以257bit为单位的。为了兼容以太网标准，可以将数据块的切分粒度设计为257bit的整数倍，于是每个数据块包含整数个257bit的数据单元，从而兼容了以太网PCS层的处理粒度。
例如，如图13所示，假设数据块的切分粒度为(Q×257)bit，Q为正整数，则能够兼容以太网标准PCS层中的处理粒度，每个数据块都会包含Q个257bit的数据单元。根据此切分粒度，发送装置100会将图中5140bit的有效数据切分为N个数据块，分别用数据块0至数据块(N-1)来表示，N为正整数。然后，如图14所示，分别为每一个数据块添加M-bit的Pchit校验位，M为正整数，得到N个Pchit，分别用Pchit 0至Pchit(N-1)来表示，每个Pchit中均包含一个(Q×257)bit的数据块以及一个M-bit的Pchit校验位。
假设发送装置100采用的FEC编码方式为RS(544,514,10)，并且N×Q×257＝5140，于是只需要把上述N个Pchit中的数据块(即图中虚线所框选的部分)作为FEC有效负载进行FEC编码，Pchit校验位不作为FEC有效负载、不参与到FEC编码中，所以Pchit校验位的长度不会影响FEC编码，因而Pchit校验位的长度选择会比较灵活。
在又一种可能的实施例中，数据块的切分粒度可以是FEC编码方式中的符号粒度的整数倍。
比如，假设采用的FEC编码方式为RS(544,514,10)，该FEC编码方式中的符号粒度为10bit。令数据块的切分粒度为10bit的整数倍，于是可以去除或简化数据块与FEC符号之间的变速箱(gearbox)逻辑。
S703、根据采用的FEC编码方式，对多个Pchit进行FEC编码得到编码数据块。
在一种可能的实施例中，根据采用的FEC编码方式，将多个Pchit中的数据块以及Pchit校验位均作为FEC有效负载进行FEC编码，得到编码数据块。
例如，请参见图10，假设上一步骤S702中得到的Pchit均为544bit，每个Pchit都包括一个520bit的数据块和24bit的BCH校验位(即Pchit校验位)。
再参见图15，假设采用的FEC编码方式为RS(576，544，10)，该RS码字所要求的有效负载为544×10bit＝5440bit，所以需要将10个544bit的Pchit作为FEC有效负载进行FEC编码。也就是说，各Pchit中的BCH校验位也作为了FEC有效负载的一部分、参与到了FEC编码当中。FEC编码完成后生成一个320bit的FEC校验位，然后将FEC校验位添加到Pchit9之后，得到的RS码字即为图15中虚线所框选的部分，该RS码字即为编码数据块，该FEC 校验位用于纠正编码数据块中存在的错误。
再如，请参见图16，假设上一步骤S702中得到的Pchit均为1320bit，每个Pchit都包括一个1285bit的数据块和一个35bit的eBCH校验位。需要说明的是，这里的eBCH校验位即Pchit校验位，是通过eBCH(1320,1285)编码方式来生成的，比如，通过对1285bit的数据块0进行eBCH(1320,1285)编码，可以生成35bit的eBCH校验位0。
再参见图17，假设采用的FEC编码方式为RS(952，924，10)，该RS码字所要求的有效负载为924×10bit＝9240bit，所以需要将7个1320bit的Pchit作为FEC有效负载进行FEC编码，也就是说，需要用到图16中的Pchit0至Pchit6共7个Pchit作为FEC有效负载，各Pchit中的eBCH校验位也作为了FEC有效负载的一部分、参与到了FEC编码当中。FEC编码完成后生成一个280bit的FEC校验位，将FEC校验位添加到Pchit 6之后，得到的RS码字即为图17中虚线所框选的部分，该RS码字即为编码数据块，该FEC校验位用于纠正编码数据块中存在的错误。
在又一种可能的实施例中，FEC编码模块102根据采用的FEC编码方式，只把多个Pchit中的数据块作为FEC有效负载进行FEC编码，得到编码数据块。
例如，假设上一步骤S702中得到的每个Pchit都为538bit，每个Pchit均包括一个514bit的数据块和24bit的Pchit校验位。
如图18所示，假设采用的FEC编码方式为RS(544，514，10)，该RS码字所要求的有效负载为514×10bit＝5140bit，所以需要将10个Pchit中的数据块作为FEC有效负载进行FEC编码，也就是说，各Pchit中的Pchit校验位不作为FEC有效负载的一部分、不参与到FEC编码当中。FEC编码完成后生成一个300bit的FEC校验位，将FEC校验位插入到Pchit 9之后，得到的RS码字即为图18中虚线所框选的部分。
可以看出，该RS码字中仅包括各Pchit中的数据块部分，而不包括Pchit校验位部分，将图18整体作为一个编码数据块(包括RS码字以及这10个Pchit中的Pchit校验位)。
上述两种实施例表明，Pchit校验位既可以作为FEC有效负载的一部分参与FEC编码而得到FEC校验位，也可以不作为FEC有效负载、不参与到FEC编码中。
综上所述，本申请实施例通过在发送装置100侧，将有效数据切分为设定长度的数据块，并且为每一个数据块添加对应Pchit校验位得到Pchit，Pchit校验位用于校验对应的Pchit是否存在错误，使得Pchit具有一定的检错能力。具体的，可以根据采用的FEC编码方式、应用场景等因素选择合适的数据块切分粒度，因而能够匹配各种互连标准，可用于诸如以太接口、PCIe接口等互连接口；也可以采用一种或多种编码方式的组合来生成Pchit校验位，使得Pchit校验位的长度调节变得灵活。然后，根据采用的FEC编码方式对多个Pchit进行FEC编码得到编码数据块，使得编码数据块具有一定的纠错能力，再将编码数据块发送给接收装置200。
于是，接收装置200既能够对接收到的编码数据块中的各个Pchit进行独立校验，以分别确定各个Pchit是否存在错误，从而实现编码数据块中错误的预判，还能对编码数据块进行FEC译码，以纠正编码数据块中存在的错误。也就是说，检错和纠错采用两种不同的粒度，检错以Pchit(或者说Pchit中的数据块)为粒度，纠错以整个编码数据块(或者是多个数据块)为粒度，而且两种粒度之间具有包含关系(编码数据块中可以包含多个Pchit)，于是接收装置200侧的译码方式变得很灵活，有助于降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益的需求。
请参见图19，图19是本申请实施例提供的发送方法的第二实施例，用于发送装置100，包括以下步骤：
S1901、获取有效数据。
步骤S1901的具体内容请参见前述步骤S701，这里不重复。
S1902、根据采用的FEC编码方式，对有效数据进行FEC编码得到FEC码字，FEC码字中包括有效数据和FEC校验位，FEC校验位用于纠正FEC码字中存在的错误。
例如，如图20所示，发送装置100中的FEC编码模块102在校验单元处理模块101之前，FEC编码模块102负责接收有效数据输入。这里需要说明的是，图中的有效数据输入部分的虚线，是为了便于和后面切分的数据块作对应，此时的有效数据实际上还没有做数据块切分。
假设FEC编码模块102中采用的FEC编码方式为RS(544,514,10)，该编码方式所要求的FEC有效负载的长度为5140bit，所以，FEC编码模块102会对5140bit的有效数据进行FEC编码生成FEC校验位，将FEC校验位插入到这5140bit有效数据的尾部，从而得到FEC码字。
需要说明的是，图中的FEC码字中的有效数据部分的虚线也是为了方便和后面切分的数据块作对应，此时FEC码字中的有效数据还未做数据块的切分。
在一种可能的实施例中，可以在进行FEC编码之前，将有效数据切分为多个设定长度的数据块；然后，根据采用的FEC编码方式，对多个数据块进行FEC编码从而得到FEC码字，其中，FEC码字包括多个数据块和FEC校验位，FEC校验位用于纠正该FEC码字中存在的错误。
S1903、将FEC码字中的有效数据切分为设定长度的数据块，分别为每个数据块添加Pchit校验位得到相应的Pchit，Pchit校验位用于校验相应的Pchit是否存在错误，从而得到编码数据块。
例如，如图20所示，FEC编码模块102将得到的FEC码字输入到校验单元处理模块101后，校验单元处理模块101对FEC码字中的有效数据进行切分，得到多个设定长度的数据块，并且为每一个数据块添加相应的Pchit校验位，得到一个个的Pchit，Pchit校验位添加在每个Pchit中的数据块的尾部。
最终得到的编码数据块如图中的①所示，可以看出，FEC校验位并没有作为一个Pchit进行处理，没有为其添加Pchit校验位。
在一种可能的实施例中，将FEC码字中的有效数据切分为多个设定长度的数据块，分别为每一个数据块添加相应的Pchit校验位，为FEC校验位也添加相应的Pchit校验位，从而得到编码数据块。
例如，如图20所示，FEC编码模块102将得到的FEC码字输入到校验单元处理模块101后，校验单元处理模块101对FEC码字中的有效数据进行切分，得到多个设定长度的数据块，并且为每一个数据块添加相应的Pchit校验位，得到一个个的Pchit，Pchit校验位添加在每个数据块的尾部。并且，把FEC校验位也看作一个Pchit进行处理，为FEC校验位添加了一个相应的Pchit校验位，为了便于描述，FEC校验位所对应的这个Pchit校验位可以称为第二校验位，最终得到的编码数据块如图中的②所示。
上述两种实施例表明，FEC校验位可以看作一个Pchit，为FEC校验位也添加上一个相应的Pchit校验位，以便根据FEC校验位对应的Pchit校验位，判断该FEC校验位是否存在错误，从而提升FEC校验位的可靠性。FEC校验位也可以不作为Pchit进行处理、不添加相应的Pchit校验位。
需要说明的是，步骤S1903中的Pchit校验位的生成方法以及数据块切分粒度的选择，请参见步骤S702中的相关内容，这里不重复介绍。
可以理解的是，图7和图19的发送方法的本质区别在于：Pchit校验位的添加和FEC编码的先后顺序。Pchit校验位的添加可以在执行FEC编码之前，也可以在执行FEC编码之后，当然，这两个动作也可以同时执行。
综上所述，本申请实施例通过在发送装置100侧，根据采用的FEC编码方式对有效数据进行FEC编码生成FEC校验位，再将FEC校验位添加到有效数据的尾部而得到FEC码字，使得FEC码字具有一定的纠错能力，可以根据FEC校验位纠正FEC码字中存在的错误。然后，发送装置100将FEC码字中的有效数据切分为设定长度的数据块，并且为每一个数据块添加相应的Pchit校验位得到一个个Pchit，Pchit校验位用于校验相应的Pchit是否存在错误，从而得到编码数据块。具体的，可以根据采用的FEC编码方式、实际应用场景等因素选择合适的数据块的切分粒度，还可以采用一种或多种编码方式的组合来生成Pchit校验位。
发送装置100将编码数据块通过相应的通信链路发送给接收装置200，由于链路噪声的影响，接收装置200获得的编码数据块中可能会存在错误。于是，接收装置200既能够对编码数据块中的各个Pchit进行独立校验，以确定各个Pchit是否存在错误，从而实现编码数据块中错误的预判，还能够对接收到的编码数据块进行FEC译码，以纠正编码数据块中存在的错误。所以说，接收装置200侧对编码数据块的译码方式可以很灵活，有助于降低FEC译码的时延影响和功耗影响。
请参见图21，图21是本申请实施例提供的接收方法的第一实施例，用于接收装置200，包括以下步骤：
S2101、获取编码数据块，编码数据块包括多个数据块、多个Pchit校验位以及FEC校验位，多个数据块和多个Pchit校验位一一对应。
其中，每个数据块及其对应的Pchit校验位构成一个Pchit，Pchit校验位用于校验相应的Pchit是否存在错误；FEC校验位用于发现该编码数据块(或者是多个数据块)中存在的错误并纠正。
根据前文的描述可知，编码数据块源自发送装置100，发送装置100的编码数据块是经过通信链路发送到接收装置200的。由于存在链路噪声等因素的影响，接收装置200获得的编码数据块中可能会存在错误，所以接收装置200需要对编码数据块进行检错和/或纠错，以获得正确的数据，即恢复原始的有效数据。
关于编码数据块的具体形式、Pchit校验位的生成方法等等，请参见图7和图19的实施例中的相关描述，这里不重复介绍。
S2102、根据多个Pchit校验位分别校验对应的数据块是否存在错误，并根据FEC校验位对编码数据块进行FEC译码以得到FEC译码数据。
需要说明的是，编码数据块经过FEC译码后得到的FEC译码数据为纠后数据(即编码数据块里面的错误已经被纠正)，编码数据块中的多个数据块分别在FEC译码数据中有对应的数据。
还需要说明的是，接收装置200在获取到编码数据块中的一个Pchit时，就可以直接开始对其进行校验，不需要等待接收到完整的编码数据块后才开始Pchit的校验。而接收装置200需要接收到整个编码数据块之后，才能开始FEC译码，所以说FEC译码会引入一定的收帧时延。
在可能的实施例中，上述“根据多个Pchit校验位分别校验对应的数据块是否存在错误”和上述“根据FEC校验位对编码数据块进行FEC译码以得到FEC译码数据”，这两个动作可以是同时/同步/并行执行的。
在可能的实施例中，编码数据块中的多个数据块之间具有先后顺序；所述根据多个Pchit校验位分别校验对应的数据块是否存在错误，包括：根据多个Pchit校验位依次校验对应的数据块是否存在错误。
例如，如图22所示，由前文对发送装置100侧动作的描述可知，接收装置200获得的编码数据块可能有①和②两种不同的形式，第①种的FEC校验位没有添加相应的Pchit校验位，而第②种的FEC校验位添加了相应的Pchit校验位。为了便于描述，后文皆以第①种编码数据块为例进行说明。
如图22所示，编码数据块分别输入到了检错路径和纠错路径中，纠错路径和纠错路径的动作可以并行执行，其中，检错路径负责对编码数据块中的各个Pchit进行校验，而纠错路径负责对编码数据块进行FEC译码以得到FEC译码数据。
可以看出，校验模块202是以Pchit为粒度(或者说以数据块为粒度)进行校验的，FEC译码模块203是以编码数据块(或者说以多个数据块)为粒度进行FEC译码的，而Pchit的校验相对于FEC译码来说一般会更快，所以纠错路径中的FEC译码时延要大于检错路径中的Pchit校验时延。因此，为了避免输出的译码结果出现乱序，图中采用了缓存模块201对编码数据块进行缓存。
S2103、判断目标数据块是否校验通过，在目标数据块校验通过的情况下，转入步骤S2104，在目标数据块校验失败的情况下，转入步骤2105。
其中，目标数据块是编码数据块中的多个数据块中的任意一个。
例如，如图15所示，假设编码数据块中包含10个544bit的Pchit以及320bit的FEC校验位，每个Pchit都包含一个520bit的数据块以及一个24bit的Pchit校验位(假设是用BCH编码方式生成的BCH校验位)。假设现在数据块0是目标数据块，接收装置200根据BCH校验位0开始对目标数据块0进行校验。
具体的校验方案可以是，接收装置200根据发送装置100中采用的BCH编码方式，对数据块0进行BCH编码生成一个BCH校验位。然后将接收装置200生成的BCH校验位和Pchit0中的BCH校验位0进行比较，如果二者一致，就说明数据块0不存在错误，数据块0校验通过；如果二者不一致，就说明数据块0存在错误，校验失败。
再如，如图23所示，假设编码数据块中包含10个(X+Y+Z)bit的Pchit以及320bit的FEC校验位，每个Pchit都包含一个X-bit的数据块以及(Y+Z)bit的Pchit校验位，这里假设Pchit校验位是由Y-bit的BCH校验位和Z-bit的CRC校验位共同构成的。
假设现在数据块1是目标数据块，接收装置200根据数据块1对应的Pchit校验位开始对数据块1进行校验。具体的校验方案可以是，与发送装置100采用同样的BCH编码方式，对数据块1进行BCH编码生成BCH校验位。将接收装置200生成的BCH校验位与Pchit 1中的BCH校验位进行比较，若二者不一致，则说明数据块1存在错误，校验失败；若二者一致，则继续采用和发送装置100同样的CRC编码方式，对数据块1进行CRC编码生成CRC校验位，然后将接收装置200生成的CRC校验位与Pchit 1中的CRC校验位进行比较，若二者不一致，则说明数据块1存在错误，数据块1校验失败，若二者一致，则说明数据块1不存在错误，校验通过。
需要说明的是，上述例子是先进行BCH校验，根据需要再进行CRC校验的，实际上也 可以先进行CRC校验，再根据需要进行BCH校验，本申请不做限定。
可以理解的是，通过多种编码方式组合校验，发现错误的概率会更高。像是BCH和CRC组合校验的方式，因为两种编码的生成多项式是不一样的，有些错误情况BCH可能检测不了，即单一编码检错能力有限，而CRC却有可能检测出来，两种校验方式可以实现互补，从而提升Pchit校验位的可靠性，降低错误漏检的概率。
S2104、将目标数据块的数据作为该目标数据块的译码结果。
需要说明的是，如果编码数据块中的各数据块是依次进行校验的，在当前的目标数据块校验通过并作为该目标数据块的译码结果输出之后，可以将目标数据块的下一个数据块更新为目标数据块并对其进行校验，返回步骤S2103。
例如，如图24所示，假设获取的编码数据块中包含6个Pchit(每个Pchit中均包括一个数据块和一个Pchit校验位)，为了方便描述，图中这些Pchit的数据块中分别标注了1至6的序号，分别表示数据块1至数据块6，依次对应Pchit 1至Pchit 6。这里假设编码数据块中的Pchit 3存在错误，而其他Pchit均没有错误。
由步骤S2102可知，该编码数据块会分别输入接收装置200中的检错路径和纠错路径进行处理。其中，纠错路径中的FEC译码模块203对该编码数据块进行FEC译码，速度较慢；而检错路径中的校验模块202对编码数据块中的目标数据块进行校验，速度较快。假设现在的目标数据块是数据块1，于是校验模块202会先获得数据块1的校验结果，而FEC译码模块203仍在对该编码数据块进行FEC译码，还未得出FEC译码数据。
数据块1的校验结果表示数据块1无错，因此数据块1校验通过，然后校验模块202向数据选择器204输出数据块1的数据，并且将数据选择器204的控制信号Sel设置为0，于是数据选择器204会将校验模块202输入的数据块1的数据作为自身的输出，即输出数据块1的译码结果。
同理，校验模块202继续对数据块2进行校验并且校验通过，然后将数据块2发送给数据选择器204，并且将Sel设置为0，于是数据选择器204也会把校验模块202输入的数据块2作为自身的输出，即为数据块2的译码结果。
S2105、将目标数据块在FEC译码数据中对应的数据作为该目标数据块的译码结果。
需要说明的是，如果目标数据块是存在错误的，那么在步骤S2102中对编码数据块进行FEC译码时，就会对编码数据块中的目标数据块的错误进行纠正，所以，目标数据块在得到的FEC译码数据中所对应的数据是经过纠错之后的。如果目标数据块不存在错误，那么目标数据块在FEC译码数据中对应的数据是没有经过纠错的。
在一种可能的实施例中，编码数据块中的多个数据块之间不需要依次进行校验，可以同时/并行进行，或者说校验时不考虑数据块的先后顺序，所以，当目标数据块校验通过后，就可以直接将目标数据块在FEC译码数据中对应的数据作为该目标数据块的译码结果。之后可以对各个数据块的译码结果再进行调整，使其符合数据块之间的先后顺序。
在一种可能的实施例中，编码数据块中的多个数据块之间具有先后顺序，这多个数据块是依次进行校验的；所述将目标数据块在FEC译码数据中对应的数据作为该目标数据块的译码结果，包括：将目标数据块及其之后的其他数据块在FEC译码数据中对应的数据，分别作为该目标数据块及其之后的其他数据块的译码结果。这时候，就可以忽略目标数据块之后的其他数据块的检错结果，甚至可以直接停止对目标数据块之后的其他数据块的检错校验，以节省能耗。
承接上例，假设编码数据块中的各个数据块是依次校验的，现在数据块1和数据块2都 已经检验完毕，下面开始对数据块3进行校验，即数据块3成为了目标数据块。校验结果表示数据块3存在错误，因此数据块3校验失败，校验模块202向FEC译码模块203发送指示信息以表明数据块3存在错误，并且将数据选择器204的控制信号Sel设为1，于是数据输出端204会等待FEC译码模块203的输出。
可以理解的是，由于FEC译码速度相对较慢，FEC译码模块203在收到校验模块202的指示信息时，可能还没有完成该编码数据块的FEC译码工作。当FEC译码模块203完成FEC译码后，可以得到FEC译码数据，数据块3在FEC译码数据中对应的数据是数据块3的错误被纠正后的数据。
根据指示信息，FEC译码模块203将数据块3至数据块6在FEC译码数据中对应的数据输入到数据选择器204。因为数据选择器204的控制信号Sel现在处于“1”状态，所以数据选择器204会把FEC译码模块203输入的数据作为自身的输出，而不再选择校验模块202的数据，于是数据块3之后的数据块4至数据块6的校验结果会被忽略掉。
然后，FEC译码模块203还可以向校验模块202发送指示，使得校验模块202开始对下一个编码数据块中的各数据块依次进行校验。
如图24所示，数据选择器204最终输出的该编码数据块所对应的译码结果，有一部分来自检错路径(数据块1和数据块2)，另一部分来自纠错路径(数据块3至数据块6，需要注意的是，这里的数据块3是经过纠错之后的数据块3的数据)。
综上所述，本申请实施例在接收装置200侧将检错和纠错分开执行，具体可以是并行执行，其中，检错以Pchit(或者说以数据块)为处理粒度，分别对编码数据块中的各个Pchit进行校验，而纠错以编码数据块(或者说以多个数据块)为处理粒度，对编码数据块进行FEC译码。
本申请实施例充分利用了链路误码分布规律，通过对编码数据块中的各个数据块进行独立校验，能够快速获知编码数据块中的错误分布情况。在编码数据块中的各个Pchit均不存在错误的情况下，该编码数据块对应的译码结果均来自检错路径，不必等待纠错路径中通过FEC译码得到的FEC译码数据(相当于旁路了FEC译码模块203)，于是可以省去FEC收帧和译码的时延，从而降低接口处理的总体时延，解决高增益FEC对时延影响大的问题，能够满足低时延场景的需求。在编码数据块中的某个Pchit检验出错误的情况下，就需要使用纠错路径中得到的FEC译码数据，以FEC译码数据中的相应数据作为译码结果，能够保证高插损链路场景下的输出误码率不会过高。
可以理解的是，由于只在有错情况下才需要使用FEC译码数据、才会引入FEC译码时延，所以FEC收帧和译码时延对接口时延的影响变小，从固定的FEC译码时延变为了动态时延抖动，消除了高增益FEC码的时延弊端。一般来说，高增益FEC码的译码时延往往会更高，而本申请实施例能够将FEC码长(对应收帧时延)和纠错能力(对应译码时延)与物理层的静态时延解耦，拓展了高增益FEC码在低时延领域的应用前景，能够同时满足低时延和高增益的需求。
请参见图25，图25是本申请实施例提供的接收方法的第二实施例，用于接收装置200，包括以下步骤：
S2501、获取编码数据块，编码数据块包括多个数据块、多个Pchit校验位以及FEC校验位，多个数据块和多个Pchit校验位一一对应。
步骤S2501的具体内容请参见步骤S2101，这里不重复介绍。
S2502、根据多个Pchit校验位分别校验对应的数据块是否存在错误，判读目标数据块是否校验通过，目标数据块是多个数据块中的一个数据块，在目标数据块校验通过的情况下，转到步骤S2503，在目标数据块校验失败的情况下，转到步骤S2504。
需要说明的是，目标数据块可以是编码数据块中的多个数据块中的任意一个数据块，关于目标数据块的具体校验方案，请参见步骤S2103中的相关内容，这里不重复。
在可能的实施例中，编码数据块中的多个数据块之间具有先后顺序；所述根据多个Pchit校验位分别校验对应的数据块是否存在错误，包括：分别根据多个Pchit校验位依次校验对应的数据块是否存在错误。
S2503、将目标数据块的数据作为该目标数据块的译码结果。
需要说明的是，如果编码数据块中的各数据块是依次进行校验的，在当前的目标数据块校验通过，并且该目标数据块的数据作为它对应的译码结果输出之后，可以将目标数据块的下一个数据块更新为目标数据块并进行校验，返回步骤S2502去判断新的目标数据块是否校验通过。
例如，如图26所示，假设编码数据块中包含6个Pchit(每个Pchit都包括数据块和Pchit校验位两部分)，为了便于描述，图中在这些Pchit的数据块中分别标注了1至6的序号，表示数据块1至数据块6，依次对应Pchit 1至Pchit 6。假设编码数据块中的Pchit 3存在错误，而其他Pchit无错。如图26所示，编码数据块一开始只输入到了接收装置200的检错路径，而没有输入纠错路径，纠错路径中的FEC译码模块203暂时不工作，可以节省能耗，这时候检错路径和纠错路径的工作不是并行执行的。
在检错路径中，缓存模块201先将这个编码数据块缓存后(或者只是完成Pchit的缓存后)，校验模块202才开始校验。假设现在数据块1是目标数据块，由于Pchit 1不存在错误，数据块1会校验通过，然后校验模块202将数据块1的数据发送给数据选择器204，并且将数据选择器204的控制信号Sel设为0，于是数据选择器204会将校验模块202发送的数据块1的数据作为数据块1的译码结果而输出。
接着，数据块2被设为了目标数据块，同理，校验模块202对Pchit 2进行校验并且校验通过，将数据块2的数据输入到数据选择器204，并且将Sel设置为0。接着，数据选择器204将校验模块202输入的数据块2的数据作为数据块1的译码结果而输出。
S2504、根据FEC校验位对编码数据块进行FEC译码得到FEC译码数据，将目标数据块在FEC译码数据中对应的数据作为该目标数据块的译码结果。
也就是说，目标数据块的校验失败信息，将作为FEC编码模块203的触发信号，进而开始执行FEC译码。
在一种可能的实施例中，编码数据块中的多个数据块之间具有先后顺序，多个数据块是依次进行校验的；所述根据FEC校验位对编码数据块进行FEC译码得到FEC译码数据，将目标数据块在FEC译码数据中对应的数据作为该目标数据块的译码结果，包括：根据FEC校验位对编码数据块进行FEC译码得到FEC译码数据，将目标数据块及其之后的其他数据块在FEC译码数据中对应的数据分别作为目标数据块及其之后的其他数据块的译码结果。这时候，可以忽略目标数据块之后的其他数据块的检错结果(即后续数据块的校验依然可以继续执行，但不再影响数据选择器204的输出)，甚至可以直接停止对目标数据块之后的其他数据块的检错校验。
承接上例，如图26所示，依次完成数据块1和数据块2的校验后，数据块3成为了目标数据块，校验模块202开始对其进行校验。由于Pchit 3中存在错误，所以数据块3会校验失 败。然后，校验模块202向FEC译码模块203发送指示信息，以表明Pchit 3存在错误并指示FEC译码模块203对Pchit3所在的编码数据块进行FEC译码，校验模块202还会把数据选择器204的控制信号Sel设置为1，于是数据选择器204不会再选择检错路径的数据，数据块4至数据块6的检错结果会被忽略掉，不影响数据选择器204的输出。
FEC译码模块203收到校验模块202的指示信息之后，便开始工作，从缓存模块201中获取Pchit 3所在的编码数据块(或者说是Pchit 3所在的FEC码字)进行FEC译码，得到FEC译码数据。然后FEC译码模块203根据指示信息，将数据块3及其之后的其他数据块在FEC译码数据中对应的数据发送给数据选择器204。由于Sel信号现在处于“1”状态，所以数据选择器204会将FEC译码模块203输入过来的这些数据作为译码结果而输出。然后，FEC译码模块203还可以向校验模块202发送指示信息，使得校验模块202开始对下一个编码数据块中的Pchit依次进行校验，FEC译码模块203又可以停止工作，以节省能耗。
如图26所示，数据选择器204最终输出的该编码数据块所对应的译码结果，有一部分来自检错路径(数据块1和数据块2)，另一部分来自纠错路径(数据块3至数据块6，需要注意的是，这里的数据块3是经过数据块3中的数据经过纠错后的结果，并非原来存在错误的数据块3)。可以理解的是，如果某个编码数据块中不存在错误，那么FEC译码模块203就不会被启动，数据选择器204输出的该编码数据块的译码结果均来自检错路径。
综上所述，本申请实施例中在接收装置200侧，通过对编码数据块中的各个数据块进行独立校验，能够对编码数据块中的错误进行预判。在目标数据块校验通过的情况下，将目标数据块的数据作为该目标数据块的译码结果而输出。在目标数据块校验失败的情况下，才会启动纠错路径中的FEC译码功能，对目标数据块所在的编码数据块进行FEC译码得到FEC译码数据，然后将FEC译码数据中的相应数据作为译码结果。
可以看出，接收装置200以编码数据块作为纠错粒度，以相对较小的Pchit(或者说是数据块)作为检错粒度。本申请实施例充分利用了链路误码分布规律，通过对编码数据块中的各个数据块的单独校验，能够快速获知编码数据块中的错误分布情况。在编码数据块中的各个数据块均不存在错误的情况下，就不需要启动FEC译码、不需要等待FEC译码数据，该编码数据块对应的译码结果均来自检错路径，因此省去了FEC收帧和译码的时延，从而降低接口处理的总体时延，解决高增益FEC对时延影响大的问题，能够满足低时延场景的需求，还能够节省FEC译码功耗。在编码数据块中的某数据块检验出错误的情况下，才会启动FEC译码，实现纠错功能，以保证高插损链路场景下的输出误码率。
由于只在有错情况下才需要启动FEC译码功能，所以FEC收帧和译码时延对接口时延的影响变小，从固定的FEC译码时延变为了动态时延抖动，仅在出错的情况下带来时延的增加，消除了高增益FEC码的时延弊端。而且，无错情况下不会存在FEC译码功耗，能够降低FEC译码的功耗影响。
需要说明的是，本申请实施例适用于所有需要引入FEC功能来提升链路质量的互连接口，比如以太网接口、PCIe接口、小型计算机系统接口(small computer system interface，SCSI)等等，可以广泛适用于处理器、加速器、存储器、I/O设备、网络交换设备、计算设备等互连场景。
请参见图27，图27是本申请实施例提供的又一种发送方法的流程示意图，用于发送装置100，包括以下步骤：
S2701、获取多个数据块。
关于数据块的获取以及数据块的切分粒度等等，请参见步骤S701、S702和S1903中的相关内容，这里不重复。
S2702、根据多个数据块分别生成多个第一校验位，多个第一校验位和多个数据块一一对应，并根据多个数据块生成前向纠错FEC校验位，从而得到编码数据块。
需要说明的是，这里的第一校验位就是前文中所述的Pchit校验位。关于Pchit校验位，请参见图7和图19的实施例的相关内容，这里不重复介绍。
在可能的实施例中，所述根据多个数据块分别生成多个第一校验位，包括：通过一种或多种编码方式对多个数据块的数据分别进行编码，生成多个第一校验位。此实施例的具体内容，请参见步骤S702中的相关部分，这里不过多介绍。
在可能的实施例中，所述根据多个数据块生成FEC校验位，包括：根据多个数据块和多个第一校验位生成FEC校验位。关于FEC校验位的生成，请参见步骤S703和S1902中的相关内容，这里不过多介绍。
S2703、发送编码数据块。
具体来说，发送装置100执行完上述步骤S2701至S2702后，便可以将编码数据块发送给接收装置200。当然，根据发送装置100和接收装置200之间的实际传输介质，发送装置100还可以把编码数据块转换为合适的传输信号后再发送给接收装置200，比如，发送装置100将编码数据块转换为光信号后，再通过光纤将此光信号传输给接收装置200，本申请不做具体限定。
综上所述，本申请实施例在发送装置100侧，为多个数据块分别生成一个对应的第一校验位，并且为多个数据块共同生成一个对应的FEC校验位，使得接收装置200能够通过多个第一校验位分别校验对应的数据块是否存在错误，实现对编码数据块中的错误的预判，还使得接收端能够通过FEC校验位对这多个数据块中存在的错误进行纠正。于是，接收装置200可以灵活地设计编码数据块的解码方式，有助于降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益。
请参见图28，图28是本申请实施例提供的又一种接收方法的流程示意图，用于接收装置200，包括以下步骤：
S2801、获取编码数据块，其中，编码数据块包括多个数据块、多个第一校验位和FEC校验位，多个第一校验位和多个数据块一一对应，FEC校验位和多个数据块对应。
需要说明的是，这里的第一校验位指的就是前文中所述的Pchit校验位。关于Pchit校验位的生成、数据块的切分粒度、FEC校验位的生成等等，请参见图7和图19的实施例的相关内容，这里不重复介绍。
S2802、根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果。
在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误；在多个数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码以得到编码数据块的译码结果。
在可能的实施例中，该方法还包括：在多个数据块没有校验出错误的情况下，将多个数据块作为编码数据块的译码结果。
在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC校验位对这多个 数据块进行FEC译码以得到编码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是这多个数据块中的一个数据块；在第二数据块校验出错误的情况下，根据FEC校验位对这多个数据块进行FEC译码得到FEC译码数据，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，第二数据块是多个数据块中的一个数据块；将多个数据块的译码结果作为编码数据块的译码结果。
在可能的实施例中，多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
上述四个实施例的具体内容，请参见前述步骤S2502至S2504的相关部分，这里不过多介绍。
在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误，并根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据；在多个数据块校验出错误的情况下，根据FEC译码数据得到编码数据块的译码结果。
在可能的实施例中，所述根据多个第一校验位分别校验对应的数据块是否存在错误，以及，根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据，是并行执行的。
在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，还包括：在多个数据块没有校验出错误的情况下，将多个数据块作为编码数据块的译码结果。
在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC译码数据得到编码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是这多个数据块中的一个数据块；在第二数据块校验出错误的情况下，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，第二数据块是这多个数据块中的一个数据块；将这多个数据块的译码结果作为编码数据块的译码结果。
在可能的实施例中，多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
上述五个实施例的具体内容，请参见前述步骤S2102至S2105的相关部分，这里也不过多介绍。
综上所述，本申请实施例在接收装置200侧，可以根据编码数据块中的多个第一校验位和/或FEC校验位来获得该编码数据块的译码结果，主要分为按需启动FEC和检错纠错并行两类方案。
在按需启动FEC的方案中，首先根据多个第一校验位校验对应的数据块是否存在错误，如果这多个数据块均没有校验出错误，就可以直接把这多个数据块的数据作为编码数据块的译码结果；如果这多个数据块校验出错误(多个数据块中至少有一个数据块被校验出错误)， 就需要启动FEC功能，根据FEC校验位对这多个数据块进行FEC译码得到FEC译码数据，对于没有校验出错误的数据块，可以直接以该数据块的数据作为该数据块的译码结果，而对于校验出错误的数据块，以该数据块在FEC译码数据中对应的数据作为该数据块的译码结果，最后将各个数据块的译码结果综合作为该编码数据块的译码结果。当然，还可以考虑多个数据块之间的先后顺序，按照次序校验各个数据块是否有错，当校验到某个数据块有错时，才会启动FEC译码得到FEC译码数据，然后，将该数据块及其之后的其他数据块在FEC译码数据中对应的数据分别作为该数据块及其之后的其他数据块的译码结果，于是可以忽略掉该数据块之后的其他数据块的校验结果，甚至可以停止对编码数据块中该数据块之后的其他数据块的校验，以节省能耗。可以理解的是，因为在有错情况下才需要启动FEC译码、才会引入FEC译码时延，所以能够降低FEC译码的时延影响和功耗影响，有助于实现低时延和高增益。
在检错纠错并行的方案中，可以根据多个数据块分别校验对应的数据块是否存在错误，并且根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据，上述检错和纠错的动作可以并行执行。在这多个数据块没有校验出错误的情况下，不需要等待/使用上述FEC译码数据，直接把这多个数据块的数据作为编码数据块的译码结果。在这多个数据块校验出错误的情况下，就需要使用上述FEC译码数据，对于没有校验出错误的数据块，可以直接以该数据块的数据作为该数据块的译码结果，而对于校验出错误的数据块，以该数据块在FEC译码数据中对应的数据作为该数据块的译码结果，最后以各个数据块的译码结果综合作为该编码数据块的译码结果。当然，这里也可以考虑多个数据块的先后顺序，依次进行校验，当校验到某个数据块有错的情况下，将该数据块及其之后的其他数据块在FEC译码数据中对应的数据分别作为该数据块及其之后的其他数据块的译码结果，于是可以忽略掉该数据块之后的其他数据块的校验结果，甚至可以停止对编码数据块中该数据块之后的其他数据块的校验。可以理解的是，因为在有错情况下才需要使用FEC译码数据、才会引入FEC译码时延，所以能够降低FEC译码的时延影响，有助于实现低时延和高增益，并且，由于保留了高增益FEC码的纠错能力，有利于控制输出误码率。
请参见图29，图29是本申请实施例提供的一种装置2900的结构示意图，装置2900包括获取模块2901、处理模块2902和发送模块2903。
获取模块2901用于：获取多个数据块。
处理模块2902用于：根据多个数据块分别生成多个第一校验位，多个第一校验位和多个数据块一一对应，并根据多个数据块生成前向纠错FEC校验位，从而得到编码数据块。
发送模块2903用于：发送编码数据块。
在可能的实施例中，所述根据多个数据块分别生成多个第一校验位，包括：通过一种或多种编码方式对多个数据块的数据分别进行编码，生成多个第一校验位。
在可能的实施例中，所述根据多个数据块生成FEC校验位，包括：根据多个数据块和多个第一校验位生成FEC校验位。
上述装置2900可以对应于图1的通信系统中的发送装置100，具体用于实现图7、图19或图27中的发送方法的实施例，请参见上文相关描述，这里不赘述。
需要说明的是，图29的实施例提供的装置2900，仅以上述各功能模块/单元的划分进行举例说明，在实际应用中，可以根据需要而将上述功能分配由不同的功能模块/单元完成，也就是说，可以将装置2900的内部结构划分成其他不同的功能模块/单元，以完成以上描述的 全部或者部分功能。
请参见图30，图30是本申请实施例提供的一种装置3000的结构示意图，装置3000包括获取模块3001和处理模块3002。
获取模块3001用于：获取编码数据块，其中，编码数据块包括多个数据块、多个第一校验位和FEC校验位，多个第一校验位和多个数据块一一对应，FEC校验位和多个数据块对应。
处理模块3002用于：根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果。
在可能的实施例中，上述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误；在多个数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码以得到编码数据块的译码结果。
在可能的实施例中，处理模块3002还用于：在所述多个数据块没有校验出错误的情况下，将所述多个数据块作为所述编码数据块的译码结果。需要说明的是，在本申请中，如果在所述多个数据块中没有任何一个数据块被校验出错误，即所述多个数据块都没有被校验出错误，则表明“所述多个数据块没有校验出错误”；如果在所述多个数据块中有至少一个数据块被校验出错误，则表明“所述多个数据块校验出错误”。
在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码以得到编码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是多个数据块中的一个数据块；在第二数据块校验出错误的情况下，根据FEC校验位对多个数据块进行FEC译码得到FEC译码数据，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，第二数据块是多个数据块中的一个数据块；将多个数据块的译码结果作为编码数据块的译码结果。
在可能的实施例中，上述多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；所述将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
在可能的实施例中，所述根据多个第一校验位和/或FEC校验位校验对应的数据块以得到编码数据块的译码结果，包括：根据多个第一校验位分别校验对应的数据块是否存在错误，并根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据；在多个数据块校验出错误的情况下，根据FEC译码数据得到编码数据块的译码结果。
在可能的实施例中，所述根据多个第一校验位分别校验对应的数据块是否存在错误，以及，所述根据FEC校验位对多个数据块进行FEC译码以得到FEC译码数据，是并行执行的。
在可能的实施例中，在所述根据多个第一校验位分别校验对应的数据块是否存在错误之后，处理模块3002还用于：在所述多个数据块没有校验出错误的情况下，将所述多个数据块作为所述编码数据块的译码结果。
在可能的实施例中，所述在多个数据块校验出错误的情况下，根据FEC译码数据得到编码数据块的译码结果，包括：在第一数据块没有校验出错误的情况下，将第一数据块作为第一数据块的译码结果，第一数据块是多个数据块中的一个数据块；在第二数据块校验出错误的情况下，将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，第二数 据块是多个数据块中的一个数据块；将多个数据块的译码结果作为编码数据块的译码结果。
在可能的实施例中，上述多个数据块具有先后顺序；所述根据多个第一校验位分别校验对应的数据块是否存在错误，包括：根据多个第一校验位依次校验对应的数据块是否存在错误；所述将第二数据块在FEC译码数据中对应的数据作为第二数据块的译码结果，包括：将第二数据块和第二数据块之后的其他数据块在FEC译码数据中对应的数据，分别作为第二数据块和第二数据块之后的其他数据块的译码结果。
上述装置3000可以对应于图1的通信系统中的接收装置200，具体用于实现图21、图25或图28中的接收方法的实施例，请参见上文相关描述，这里不赘述。
需要说明的是，图30的实施例提供的装置3000，仅以上述各功能模块/单元的划分进行举例说明，在实际的应用中，可以根据需要而将上述功能分配由不同的功能模块/单元完成，即将装置3000的内部结构划分成其他不同的功能模块/单元，以完成以上描述的全部或者部分功能。
图31是本申请实施例提供的一种设备3100的结构示意图。设备3100可以是笔记本电脑、平板电脑以及云端服务器等设备，本申请不做具体限定。
设备3100包括处理器3101、存储器3102以及通信接口3103，所述设备3100具体用于实现图7、图19或图17的发送方法中的任一实施例。其中，处理器3101、存储器3102以及通信接口3103可以通过内部总线3104相互连接，也可通过无线传输等其他手段实现通信。本申请实施例以通过总线3104连接为例，总线3104可以是外设部件互连标准(peripheral component interconnect,PCI)总线、扩展工业标准结构(extended industry standard architecture,EISA)总线、统一总线(unified bus，Ubus或UB)、计算机快速链接(compute express link，CXL)总线、缓存一致互联协议(cache coherent interconnect for accelerators，CCIX)总线等。总线3104可以分为地址总线、数据总线、控制总线等。为便于表示，图31中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
处理器3101可以由至少一个通用处理器构成，例如中央处理器(central processing unit,CPU)，或者CPU和硬件芯片的组合。上述硬件芯片可以是专用集成电路(application-specific integrated circuit,ASIC)、可编程逻辑器件(programmable logic device,PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device,CPLD)、现场可编程逻辑门阵列(field-programmable gate array,FPGA)、通用阵列逻辑(generic array logic,GAL)或其任意组合。处理器3101执行各种类型的数字存储指令，例如存储在存储器3102中的软件或者固件程序，它能使设备3100提供多种服务。
存储器3102用于存储程序代码，并由处理器3101来控制执行。存储器3102可以包括易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)；存储器3102也可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)、快闪存储器(flash memory)、硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器3102还可以包括上述种类的组合。存储器3102可以存储有程序代码，具体可以包括用于执行图7、图19或图27中的发送方法的任一实施例的程序代码，这里不再进行赘述。
通信接口3103可以为有线接口(例如以太网接口)，可以为内部接口(例如高速串行计算机扩展总线(peripheral component interconnect express,PCIe)总线接口)、有线接口(例如以太网接口)或无线接口(例如蜂窝网络接口或使用无线局域网接口)，用于与与其他设备或 模块进行通信。
上述设备3100可以应用于图1所示的通信系统架构中，例如，可以是图1中的发送装置100，用于执行图7、图19或图27的发送方法。
需要说明的是，本实施例可以是通用的物理服务器实现的，例如，ARM服务器或者X86服务器，也可以是基于通用的物理服务器结合NFV技术实现的虚拟机实现的，虚拟机指通过软件模拟的具有完整硬件系统功能的、运行在一个完全隔离环境中的完整计算机系统，本申请不作具体限定。应理解，图31所示的设备3100还可以是至少一个服务器构成的服务器集群，本申请不作具体限定。
还需要说明的，图31仅仅是本申请实施例的一种可能的实现方式，在实际的应用中，设备3100还可以包括更多或更少的部件，本申请不作具体限制。关于本申请实施例中未出示或未描述的内容，可参见前述图7、图19或图27的发送方法的实施例中的相关阐述，这里不再赘述。
图32是本申请实施例提供的一种设备3200的结构示意图。设备3200可以是笔记本电脑、平板电脑以及云端服务器等设备，本申请不做具体限定。
设备3200包括处理器3201、存储器3202以及通信接口3203，所述设备3200具体用于实现图21、图25或图28的接收方法中的任一实施例。其中，处理器3201、存储器3202以及通信接口3203可以通过内部总线3204相互连接，也可通过无线传输等其他手段实现通信。本申请实施例以通过总线3204连接为例，总线3204可以是外设部件互连标准(peripheral component interconnect,PCI)总线、扩展工业标准结构(extended industry standard architecture,EISA)总线、统一总线(unified bus，Ubus或UB)、计算机快速链接(compute express link，CXL)总线、缓存一致互联协议(cache coherent interconnect for accelerators，CCIX)总线等。总线3204可以分为地址总线、数据总线、控制总线等。为便于表示，图32中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
处理器3201可以由至少一个通用处理器构成，例如中央处理器(central processing unit,CPU)，或者CPU和硬件芯片的组合。上述硬件芯片可以是专用集成电路(application-specific integrated circuit,ASIC)、可编程逻辑器件(programmable logic device,PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device,CPLD)、现场可编程逻辑门阵列(field-programmable gate array,FPGA)、通用阵列逻辑(generic array logic,GAL)或其任意组合。处理器3201执行各种类型的数字存储指令，例如存储在存储器3202中的软件或者固件程序，它能使设备3200提供多种服务。
存储器3202用于存储程序代码，并由处理器3201来控制执行。存储器3202可以包括易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)；存储器3202也可以包括非易失性存储器(non-volatile memory)，例如只读存储器(read-only memory，ROM)、快闪存储器(flash memory)、硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)；存储器3202还可以包括上述种类的组合。存储器3202可以存储有程序代码，具体可以包括用于执行图21、图25或图28中的接收方法的任一实施例的程序代码，这里不再进行赘述。
通信接口3203可以为有线接口(例如以太网接口)，可以为内部接口(例如高速串行计算机扩展总线(peripheral component interconnect express,PCIe)总线接口)、有线接口(例如以太网接口)或无线接口(例如蜂窝网络接口或使用无线局域网接口)，用于与与其他设备或 模块进行通信。
上述设备3200可以应用于图1所示的通信系统架构中，例如，可以是图1中的接收装置200，用于执行图21、图25或图28的接收方法。
需要说明的是，本实施例可以是通用的物理服务器实现的，例如，ARM服务器或者X86服务器，也可以是基于通用的物理服务器结合NFV技术实现的虚拟机实现的，虚拟机指通过软件模拟的具有完整硬件系统功能的、运行在一个完全隔离环境中的完整计算机系统，本申请不作具体限定。应理解，图32所示的设备3200还可以是至少一个服务器构成的服务器集群，本申请不作具体限定。
还需要说明的，图32仅仅是本申请实施例的一种可能的实现方式，在实际的应用中，设备3200还可以包括更多或更少的部件，本申请不作具体限制。关于本申请实施例中未出示或未描述的内容，可参见前述图21、图25或图28的发送方法的实施例中的相关阐述，这里不再赘述。
本申请实施例还提供一种系统，包括上述任一实施例的装置2900和上述任一实施例的装置3000。
本申请实施例还提供一种系统，包括上述任一实施例的设备3100和上述任一实施例的设备3200。
本申请实施例还提供一种芯片，该芯片用于执行图27或图28的任一实施例的方法。
本申请实施例还提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当其在处理器上运行时，图27或图28的任一实施例的方法得以实现。
本申请实施例还提供一种计算机程序产品，当计算机程序产品在处理器上运行时，图27或图28中的任一实施例的方法得以实现。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(read-only memory，ROM)或随机存储记忆体(random access memory，RAM)等。
需要说明的是，以上所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
还需要说明的是，在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指包含一个或多个相关联的列出项目的任意或所有可能组合。

Claims (29)

  1. 一种发送方法，其特征在于，所述方法包括：
    获取多个数据块；
    根据所述多个数据块分别生成多个第一校验位，所述多个第一校验位和所述多个数据块一一对应，并根据所述多个数据块生成前向纠错FEC校验位，从而得到编码数据块；
    发送所述编码数据块。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述多个数据块分别生成多个第一校验位，包括：
    通过一种或多种编码方式对所述多个数据块的数据分别进行编码，生成所述多个第一校验位。
  3. 根据权利要求1或2所述的方法，其特征在于，所述根据所述多个数据块生成FEC校验位，包括：
    根据所述多个数据块和所述多个第一校验位生成所述FEC校验位。
  4. 一种接收方法，其特征在于，所述方法包括：
    获取编码数据块，其中，所述编码数据块包括多个数据块、多个第一校验位和FEC校验位，所述多个第一校验位和所述多个数据块一一对应，所述FEC校验位和所述多个数据块对应；
    根据所述多个第一校验位和/或所述FEC校验位校验对应的数据块以得到所述编码数据块的译码结果。
  5. 根据权利要求4所述的方法，其特征在于，所述根据所述多个第一校验位和/或所述FEC校验位校验对应的数据块以得到所述编码数据块的译码结果，包括：
    根据所述多个第一校验位分别校验对应的数据块是否存在错误；
    在所述多个数据块校验出错误的情况下，根据所述FEC校验位对所述多个数据块进行FEC译码以得到所述编码数据块的译码结果。
  6. 根据权利要求5所述的方法，其特征在于，所述方法还包括：
    在所述多个数据块没有校验出错误的情况下，将所述多个数据块作为所述编码数据块的译码结果。
  7. 根据权利要求5或6所述的方法，其特征在于，所述在所述多个数据块校验出错误的情况下，根据所述FEC校验位对所述多个数据块进行FEC译码以得到所述编码数据块的译码结果，包括：
    在第一数据块没有校验出错误的情况下，将所述第一数据块作为所述第一数据块的译码结果，所述第一数据块是所述多个数据块中的一个数据块；
    在第二数据块校验出错误的情况下，根据所述FEC校验位对所述多个数据块进行FEC译码得到FEC译码数据，将所述第二数据块在所述FEC译码数据中对应的数据作为所述第 二数据块的译码结果，所述第二数据块是所述多个数据块中的一个数据块；
    将所述多个数据块的译码结果作为所述编码数据块的译码结果。
  8. 根据权利要求7所述的方法，其特征在于，所述多个数据块具有先后顺序；
    所述根据所述多个第一校验位分别校验对应的数据块是否存在错误，包括：根据所述多个第一校验位依次校验对应的数据块是否存在错误；
    所述将所述第二数据块在所述FEC译码数据中对应的数据作为所述第二数据块的译码结果，包括：将所述第二数据块和所述第二数据块之后的其他数据块在所述FEC译码数据中对应的数据，分别作为所述第二数据块和所述第二数据块之后的其他数据块的译码结果。
  9. 根据权利要求4所述的方法，其特征在于，所述根据所述多个第一校验位和/或所述FEC校验位校验对应的数据块以得到所述编码数据块的译码结果，包括：
    根据所述多个第一校验位分别校验对应的数据块是否存在错误，并根据所述FEC校验位对所述多个数据块进行FEC译码以得到FEC译码数据；
    在所述多个数据块校验出错误的情况下，根据所述FEC译码数据得到所述编码数据块的译码结果。
  10. 根据权利要求9所述的方法，其特征在于，所述根据所述多个第一校验位分别校验对应的数据块是否存在错误，以及，所述根据所述FEC校验位对所述多个数据块进行FEC译码以得到FEC译码数据，是并行执行的。
  11. 根据权利要求9或10所述的方法，其特征在于，所述方法还包括：
    在所述多个数据块没有校验出错误的情况下，将所述多个数据块作为所述编码数据块的译码结果。
  12. 根据权利要求9至11中任一项所述的方法，其特征在于，所述在所述多个数据块校验出错误的情况下，根据所述FEC译码数据得到所述编码数据块的译码结果，包括：
    在第一数据块没有校验出错误的情况下，将所述第一数据块作为所述第一数据块的译码结果，所述第一数据块是所述多个数据块中的一个数据块；
    在第二数据块校验出错误的情况下，将所述第二数据块在所述FEC译码数据中对应的数据作为所述第二数据块的译码结果，所述第二数据块是所述多个数据块中的一个数据块；
    将所述多个数据块的译码结果作为所述编码数据块的译码结果。
  13. 根据权利要求12所述的方法，其特征在于，所述多个数据块具有先后顺序；
    所述根据所述多个第一校验位分别校验对应的数据块是否存在错误，包括：根据所述多个第一校验位依次校验对应的数据块是否存在错误；
    所述将所述第二数据块在所述FEC译码数据中对应的数据作为所述第二数据块的译码结果，包括：将所述第二数据块和所述第二数据块之后的其他数据块在所述FEC译码数据中对应的数据，分别作为所述第二数据块和所述第二数据块之后的其他数据块的译码结果。
  14. 一种装置，其特征在于，所述装置包括：
    获取模块，用于获取多个数据块；
    处理模块，用于根据所述多个数据块分别生成多个第一校验位，所述多个第一校验位和所述多个数据块一一对应，并根据所述多个数据块生成前向纠错FEC校验位，从而得到编码数据块；
    发送模块，用于发送所述编码数据块。
  15. 根据权利要求14所述的装置，其特征在于，所述根据所述多个数据块分别生成多个第一校验位，包括：
    通过一种或多种编码方式对所述多个数据块的数据分别进行编码，生成所述多个第一校验位。
  16. 根据权利要求14或15所述的装置，其特征在于，所述根据所述多个数据块生成FEC校验位，包括：
    根据所述多个数据块和所述多个第一校验位生成所述FEC校验位。
  17. 一种装置，其特征在于，所述装置包括：
    获取模块，用于获取编码数据块，其中，所述编码数据块包括多个数据块、多个第一校验位和FEC校验位，所述多个第一校验位和所述多个数据块一一对应，所述FEC校验位和所述多个数据块对应；
    处理模块，用于根据所述多个第一校验位和/或所述FEC校验位校验对应的数据块以得到所述编码数据块的译码结果。
  18. 根据权利要求17所述的装置，其特征在于，所述根据所述多个第一校验位和/或所述FEC校验位校验对应的数据块以得到所述编码数据块的译码结果，包括：
    根据所述多个第一校验位分别校验对应的数据块是否存在错误；
    在所述多个数据块校验出错误的情况下，根据所述FEC校验位对所述多个数据块进行FEC译码以得到所述编码数据块的译码结果。
  19. 根据权利要求18所述的装置，其特征在于，所述处理模块还用于：在所述多个数据块没有校验出错误的情况下，将所述多个数据块作为所述编码数据块的译码结果。
  20. 根据权利要求18或19所述的装置，其特征在于，所述在所述多个数据块校验出错误的情况下，根据所述FEC校验位对所述多个数据块进行FEC译码以得到所述编码数据块的译码结果，包括：
    在第一数据块没有校验出错误的情况下，将所述第一数据块作为所述第一数据块的译码结果，所述第一数据块是所述多个数据块中的一个数据块；
    在第二数据块校验出错误的情况下，根据所述FEC校验位对所述多个数据块进行FEC译码得到FEC译码数据，将所述第二数据块在所述FEC译码数据中对应的数据作为所述第二数据块的译码结果，所述第二数据块是所述多个数据块中的一个数据块；
    将所述多个数据块的译码结果作为所述编码数据块的译码结果。
  21. 根据权利要求20所述的装置，其特征在于，所述多个数据块具有先后顺序；
    所述根据所述多个第一校验位分别校验对应的数据块是否存在错误，包括：根据所述多个第一校验位依次校验对应的数据块是否存在错误；
    所述将所述第二数据块在所述FEC译码数据中对应的数据作为所述第二数据块的译码结果，包括：将所述第二数据块和所述第二数据块之后的其他数据块在所述FEC译码数据中对应的数据，分别作为所述第二数据块和所述第二数据块之后的其他数据块的译码结果。
  22. 根据权利要求17所述的装置，其特征在于，所述根据所述多个第一校验位和/或所述FEC校验位校验对应的数据块以得到所述编码数据块的译码结果，包括：
    根据所述多个第一校验位分别校验对应的数据块是否存在错误，并根据所述FEC校验位对所述多个数据块进行FEC译码以得到FEC译码数据；
    在所述多个数据块校验出错误的情况下，根据所述FEC译码数据得到所述编码数据块的译码结果。
  23. 根据权利要求22所述的装置，其特征在于，所述根据所述多个第一校验位分别校验对应的数据块是否存在错误，以及，所述根据所述FEC校验位对所述多个数据块进行FEC译码以得到FEC译码数据，是并行执行的。
  24. 根据权利要求22或23所述的装置，其特征在于，所述处理模块还用于：在所述多个数据块没有校验出错误的情况下，将所述多个数据块作为所述编码数据块的译码结果。
  25. 根据权利要求22至24中任一项所述的装置，其特征在于，所述在所述多个数据块校验出错误的情况下，根据所述FEC译码数据得到所述编码数据块的译码结果，包括：
    在第一数据块没有校验出错误的情况下，将所述第一数据块作为所述第一数据块的译码结果，所述第一数据块是所述多个数据块中的一个数据块；
    在第二数据块校验出错误的情况下，将所述第二数据块在所述FEC译码数据中对应的数据作为所述第二数据块的译码结果，所述第二数据块是所述多个数据块中的一个数据块；
    将所述多个数据块的译码结果作为所述编码数据块的译码结果。
  26. 根据权利要求25所述的装置，其特征在于，所述多个数据块具有先后顺序；
    所述根据所述多个第一校验位分别校验对应的数据块是否存在错误，包括：根据所述多个第一校验位依次校验对应的数据块是否存在错误；
    所述将所述第二数据块在所述FEC译码数据中对应的数据作为所述第二数据块的译码结果，包括：将所述第二数据块和所述第二数据块之后的其他数据块在所述FEC译码数据中对应的数据，分别作为所述第二数据块和所述第二数据块之后的其他数据块的译码结果。
  27. 一种系统，其特征在于，包括权利要求14-16中任一项所述的装置和权利要求17-26中任一项所述的装置。
  28. 一种设备，其特征在于，包括处理器和存储器；
    所述存储器，用于存储计算机程序；
    所述处理器，用于执行所述存储器中存储的计算机程序，以使得所述设备执行如权利要求1-3或4-13中任一项所述的方法。
  29. 一种计算机可读存储介质，其特征在于，包括程序或指令，当所述程序或指令在处理器上运行时，如权利要求1-3或4-13中任意一项所述的方法被执行。
PCT/CN2022/130861 2021-12-22 2022-11-09 发送方法、接收方法、装置、系统、设备及存储介质 WO2023116245A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP22909562.5A EP4440015A1 (en) 2021-12-22 2022-11-09 Sending method and apparatus, receiving method and apparatus, system, device, and storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111578236.X 2021-12-22
CN202111578236.XA CN116346278A (zh) 2021-12-22 2021-12-22 发送方法、接收方法、装置、系统、设备及存储介质

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/750,192 Continuation US20240364455A1 (en) 2021-12-22 2024-06-21 Sending method, receiving method, apparatus, system, device, and storage medium

Publications (1)

Publication Number Publication Date
WO2023116245A1 true WO2023116245A1 (zh) 2023-06-29

Family

ID=86879226

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/130861 WO2023116245A1 (zh) 2021-12-22 2022-11-09 发送方法、接收方法、装置、系统、设备及存储介质

Country Status (3)

Country Link
EP (1) EP4440015A1 (zh)
CN (1) CN116346278A (zh)
WO (1) WO2023116245A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116882429B (zh) * 2023-09-08 2024-02-02 紫光同芯微电子有限公司 用于智能卡芯片的数据传输方法及装置、智能卡
CN118300865A (zh) * 2024-01-22 2024-07-05 北京天空卫士网络安全技术有限公司 一种基于互联网的数据传输安全监测系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101610139A (zh) * 2009-07-20 2009-12-23 中国船舶重工集团公司第七一五研究所 一种水声modem混合自动重传方法
CN102025448A (zh) * 2010-11-18 2011-04-20 华为技术有限公司 通用公共无线接口业务发送、接收方法及装置
CN102427398A (zh) * 2011-12-31 2012-04-25 兆讯恒达微电子技术(北京)有限公司 一种基于双向奇偶校验的纠检错方法和系统及装置
CN102687445A (zh) * 2011-12-30 2012-09-19 华为技术有限公司 前向纠错编、解码方法、装置及系统
CN105634504A (zh) * 2014-11-07 2016-06-01 中兴通讯股份有限公司 数据校验方法及装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106817192B (zh) * 2015-11-30 2020-08-14 华为技术有限公司 一种错误估计的方法、基站及终端
CN111628780B (zh) * 2020-05-07 2023-04-25 中国科学院微电子研究所 数据编码、解码方法及数据处理系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101610139A (zh) * 2009-07-20 2009-12-23 中国船舶重工集团公司第七一五研究所 一种水声modem混合自动重传方法
CN102025448A (zh) * 2010-11-18 2011-04-20 华为技术有限公司 通用公共无线接口业务发送、接收方法及装置
CN102687445A (zh) * 2011-12-30 2012-09-19 华为技术有限公司 前向纠错编、解码方法、装置及系统
CN102427398A (zh) * 2011-12-31 2012-04-25 兆讯恒达微电子技术(北京)有限公司 一种基于双向奇偶校验的纠检错方法和系统及装置
CN105634504A (zh) * 2014-11-07 2016-06-01 中兴通讯股份有限公司 数据校验方法及装置

Also Published As

Publication number Publication date
EP4440015A1 (en) 2024-10-02
CN116346278A (zh) 2023-06-27

Similar Documents

Publication Publication Date Title
WO2023116245A1 (zh) 发送方法、接收方法、装置、系统、设备及存储介质
US10044372B2 (en) Sliding window list decoder for error correcting codes
WO2020228126A1 (zh) 数据传输、编码、解码方法、装置、设备及存储介质
CN101662335B (zh) 前向纠错编码方法、前向纠错译码方法及其装置
US8271850B2 (en) Fast low-density parity-check code encoder
US20100262887A1 (en) High Integrity Data Network System and Method
US11528094B2 (en) Data sending and receiving method and device
US20180091332A1 (en) Hybrid forward error correction and replay technique for low latency
EP1605621A2 (en) Data transmission with improved error correction capability
CN112104412B (zh) 一种适用于低轨卫星宽带通信的加速器
US20240364455A1 (en) Sending method, receiving method, apparatus, system, device, and storage medium
WO2022199529A1 (zh) 一种数据编码处理方法、装置、存储介质及电子装置
CN116722954B (zh) 一种编解码验证系统、方法、设备以及存储介质
CN117650870B (zh) 一种基于纵向编码纠错的通信方法、系统、设备及介质
CN111600613B (zh) 一种校验方法、装置、译码器、接收机及计算机存储介质
CN109787717B (zh) 一种基于fpga的qr31码译码方法
WO2023015863A1 (zh) 数据传输的方法、装置、设备、系统及可读存储介质
CN117811590A (zh) 数据编码纠错方法、装置及相关设备
CN115883012A (zh) 一种编码方法及装置
WO2023236838A1 (zh) 编码传输方法、解码方法和通信装置
CN116820832B (zh) 一种用于高速数据传输的错误校验方法、介质及装置
EP4170914A1 (en) On-demand decoding method and device
CN112803955B (zh) 通用Turbo码编码器结构、编码器、方法、装置、设备及介质
WO2023071309A1 (zh) 数据传输的方法、装置、设备、系统及可读存储介质
US20210391875A1 (en) Decoding circuit and decoding method based on Viterbi algorithm

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22909562

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022909562

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022909562

Country of ref document: EP

Effective date: 20240625

NENP Non-entry into the national phase

Ref country code: DE