WO2023116046A1

WO2023116046A1 - Memory and preparation method therefor

Info

Publication number: WO2023116046A1
Application number: PCT/CN2022/116774
Authority: WO
Inventors: 于志猛; 申力杰; 杨丹丹; 何世坤
Original assignee: 浙江驰拓科技有限公司
Priority date: 2021-12-22
Filing date: 2022-09-02
Publication date: 2023-06-29
Also published as: CN116367552A

Abstract

A memory and a preparation method therefor. The memory comprises: a bottom circuit layer (1); a bottom electrode (2) provided on the upper surface of the bottom circuit layer (1); an oxide layer (3) provided around the bottom electrode (2); a memory cell layer (4) and a metal hard mask layer (5) which are arranged on the upper surface of the bottom electrode (2) and are stacked from bottom to top; and a top circuit layer (6) provided on the upper surface of the metal hard mask layer (5). In the memory of the present application, the oxide layer is provided around the bottom electrode, that is, the sidewall of the bottom electrode is fully oxidized, so that occurrence of a short circuit caused by anti-sputtering is reduced in the etching process of the memory cell layer, and the performance and yield of the memory are improved; moreover, since the bottom electrode has a large critical dimension, nesting precision control is looser, and the implementation difficulty of a patterning process of the bottom electrode is remarkably reduced; the thickness of the oxide layer is controllable, and can be adjusted according to the dimension of the memory cell layer to be compatible with memory cells of different dimensions.

Description

A kind of memory and its preparation method

This application claims the priority of the Chinese patent application with the application number 202111583992.1 and the title of the invention "a memory and its preparation method" submitted to the China Patent Office on December 22, 2021, the entire contents of which are incorporated by reference in this application .

technical field

The present application relates to the field of semiconductors, in particular to a memory and a manufacturing method thereof.

Background technique

Magnetic random access memory (MRAM for short) is a non-volatile magnetic random access memory, which has the characteristics of high-speed reading and writing and high integration.

In the manufacturing process of MRAM, ion beam etching is used to etch MRAM memory cells. Vertical etching can effectively remove etching backsplash, thereby reducing the proportion of short-circuit failures and improving device performance and yield. Efficient vertical etching requires that the bottom electrode is not exposed during overetching to avoid backsplash sources. Based on the above limitations, as the size of the memory cell shrinks, the bottom electrode needs to be synchronized with the shrinking of the memory cell, and the size is smaller than the memory cell, the manufacturing process is limited, and the nesting precision control requirements are more stringent.

Therefore, how to solve the above technical problems should be the focus of those skilled in the art.

Contents of the invention

The purpose of the present application is to provide a memory and a manufacturing method thereof, so as to simplify the process while improving device performance and yield.

In order to solve the above technical problems, the present application provides a memory, including:

bottom circuit layer;

a bottom electrode disposed on the upper surface of the bottom circuit layer;

an oxide layer disposed around the bottom electrode;

The memory cell layer and the metal hard mask layer are arranged on the upper surface of the bottom electrode, stacked from bottom to top;

The top circuit layer is arranged on the upper surface of the metal hard mask layer.

Optionally, when the connection between the bottom circuit layer and the bottom electrode is a copper conductor, the upper surface of the copper conductor is located within the projection area of the lower surface of the bottom electrode on the horizontal plane.

Optionally, when the connection between the bottom circuit layer and the bottom electrode is a non-copper conductor, the lower surface of the bottom electrode is located within the region of the upper surface of the non-copper conductor.

Optionally, also include:

An insulating protection layer arranged around the storage unit layer and the metal hard mask layer.

The present application also provides a memory preparation method, including:

forming a bottom electrode on the upper surface of the bottom circuit layer;

performing oxidation treatment on the surface of the bottom electrode to form an oxide layer on the surface of the bottom electrode;

removing the oxide layer located on the upper surface of the bottom circuit layer, so that the oxide layer remains around the bottom electrode;

forming a memory cell layer and a metal hard mask layer stacked from bottom to top on the upper surface of the bottom electrode;

etching the memory cell layer and introducing overetching;

A top circuit layer is formed on the upper surface of the metal hard mask layer.

Optionally, the oxidizing the surface of the bottom electrode includes:

The surface of the bottom electrode is oxidized using a peroxide solution.

Optionally, the oxidizing the surface of the bottom electrode includes:

The gas is ionized into the plasma in the etching chamber, and the surface of the bottom electrode is oxidized with the plasma, wherein the gas is oxygen or a mixed gas of oxygen and inert gas.

Optionally, the oxidizing the surface of the bottom electrode includes:

In a high-temperature environment, the gas is ionized out of the plasma in the degumming machine, and the surface of the bottom electrode is oxidized with the plasma, wherein the gas is oxygen, or a combination of oxygen and an inert gas mixed composition.

Optionally, the removing the oxide layer on the upper surface of the bottom circuit layer includes:

forming a dielectric layer on the upper surface of the bottom circuit layer not covered by the bottom electrode and the oxide layer to obtain a pretreatment structure;

Thinning the pretreatment structure and the oxide layer on the upper surface of the bottom electrode to expose the bottom electrode and form a conductive path.

Optionally, after the over-etching of the memory cell layer, further comprising:

An insulating protection layer is formed around the memory cell layer and the metal hard mask layer.

A memory provided by the present application includes a bottom circuit layer; a bottom electrode arranged on the upper surface of the bottom circuit layer; an oxide layer arranged around the bottom electrode; Stacked storage unit layer, metal hard mask layer; top circuit layer arranged on the upper surface of the metal hard mask layer.

It can be seen that the memory in this application is provided with an oxide layer around the bottom electrode, that is, the side walls of the bottom electrode are completely oxidized, which reduces the occurrence of short circuits due to reverse sputtering during the etching process, and improves the performance and yield of the memory. , at the same time, the existence of the oxide layer can make the critical dimension of the bottom electrode larger, the nesting precision control is more relaxed than that without the oxide layer, and greatly reduces the difficulty of process realization; the thickness of the oxide layer is controllable, and can be stored according to the The size of the unit layer is adjusted to be compatible with storage units of different sizes.

In addition, the present application also provides a preparation method with the above advantages.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are only For some embodiments of the present application, those of ordinary skill in the art can also obtain other drawings based on these drawings without creative effort.

FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of another memory provided by the embodiment of the present application;

FIG. 3 is a schematic structural diagram of another memory provided by an embodiment of the present application;

FIG. 4 is a flow chart of a manufacturing method of a memory provided in an embodiment of the present application;

FIG. 5 to FIG. 11 are process flow charts of a memory provided by an embodiment of the present application;

FIG. 12 to FIG. 19 are process flow charts of another memory provided by the embodiments of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the drawings and specific implementation methods. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

As mentioned in the background section, the bottom electrode is required not to be exposed during over-etching to avoid backsplash sources. However, as the size of the memory cell shrinks, the bottom electrode is synchronized with the shrinking of the memory cell, and the size is smaller than the memory cell, the manufacturing process is limited, and the nesting precision control requirements are more stringent.

In view of this, this application provides a memory, please refer to Figure 1, including:

Bottom circuit layer 1;

a bottom electrode 2 disposed on the upper surface of the bottom circuit layer 1;

an oxide layer 3 disposed around the bottom electrode 2;

The memory cell layer 4 and the metal hard mask layer 5 are arranged on the upper surface of the bottom electrode 2, stacked from bottom to top;

The top circuit layer 6 disposed on the upper surface of the metal hard mask layer 5 .

It should be pointed out that the memory also includes a dielectric layer filled between the bottom circuit layer 1 and the top circuit layer 6 .

The material of the bottom electrode 2 includes but not limited to Ta (tantalum), TaN (tantalum nitride), Ti (titanium), TiN (titanium nitride) and other metals or metal compounds with good conductivity.

It should be pointed out that the storage unit layer 4 is not limited in this application, it depends on the type of the storage. When the memory is a magnetic random access memory, the storage unit layer 4 is a magnetic random access memory film layer, including a pinned layer, a coupling layer, a reference layer, a barrier layer, a free layer and other specific structures that can refer to existing related technologies, and will not be repeated here. To repeat in detail; when the memory is a phase-change memory, the storage unit layer 4 is a phase-change layer.

In this application, the material of the metal hard mask layer 5 is not specifically limited, and can be set by itself. For example, the material of the metal hard mask layer 5 can be titanium, aluminum and so on.

The material of the dielectric layer includes but not limited to SiO ₂ , SiN, SiON.

The bottom circuit layer 1 is provided with through holes for providing conductive contact (the through holes are filled with conductive materials). The shapes of the bottom electrodes 2 will be introduced below according to the different filling materials in the through holes.

When the connection between the bottom circuit layer 1 and the bottom electrode 2 is a copper conductor 7, the upper surface of the copper conductor 7 is located within the projection area of the lower surface of the bottom electrode 2 on the horizontal plane, as shown in the figure 1 to avoid exposure of copper conductors. Wherein, the bottom electrode 2 can be in the shape of an inverted T, but the application does not specifically limit the shape of the bottom electrode 2, and can also be set into other shapes, as long as the upper surface of the copper conductor 7 is guaranteed to be located on the lower surface of the bottom electrode 2 within the projection area of the horizontal plane.

When the connection between the bottom circuit layer 1 and the bottom electrode 2 is a non-copper conductor 8, the lower surface of the bottom electrode 2 can be located within the area of the upper surface of the non-copper conductor 8, as shown in FIG. 2, there is no risk of metal contamination in the non-copper conductor 8 at this time. The cross-section of the bottom electrode 2 may be a regular rectangle or trapezoid. However, the present application does not specifically limit this, and in other embodiments of the present application, the lower surface of the bottom electrode 2 may also be located outside the range of the upper surface of the non-copper conductor 8 .

The memory in the present application is provided with an oxide layer 3 around the bottom electrode 2, that is, the side walls of the bottom electrode 2 are completely oxidized, which reduces the occurrence of short circuits due to reverse sputtering during the etching process, and improves the performance and good performance of the memory. At the same time, the existence of the oxide layer can make the critical dimension of the bottom electrode larger, and the nesting precision control is more relaxed than that without the oxide layer 3, and greatly reduces the difficulty of process realization; the thickness of the oxide layer 3 is controllable, It can be adjusted according to the size of the storage unit layer 4 and is compatible with storage units of different sizes.

In addition, when the memory is a phase change random access memory (PCRAM), the existence of the oxide layer 3 can also be used to make the bottom electrode 2 smaller, reducing the effective contact area between the bottom electrode 2 and the phase change layer, thereby reducing the PCRAM operating power consumption.

Please refer to FIG. 3, on the basis of any of the above embodiments, in one embodiment of the present application, the memory further includes:

The insulating protective layer 9 provided around the memory cell layer 4 and the metal hard mask layer 5 is to prevent oxidation when exposed to air after leaving the etching chamber, causing irreversible damage to the device and yield .

It should be noted that, in this application, the material of the insulating protection layer 9 is not specifically limited, and can be set by itself. For example, the material of the insulating protection layer 9 may be SiN or SiO ₂ .

The present application also provides a memory preparation method, please refer to Figure 4, the method includes:

Step S101: forming a bottom electrode on the upper surface of the bottom circuit layer.

Depositing a bottom electrode material layer and a photoresist layer on the upper surface of the bottom circuit layer, and performing photolithographic patterning to form a bottom electrode.

Preferably, in one embodiment of the present application, a dielectric hard mask layer can also be deposited on the upper surface of the bottom electrode material layer as a mask for etching the bottom electrode material, so as to facilitate the patterning of the bottom electrode material layer. The dielectric hard mask layer is removed when the bottom electrode is thinned.

The material of the dielectric hard mask layer includes but not limited to SiO ₂ , SiN, SiON, SOC (spin of coating, spin coating), ACL (amorphous carbon layer, amorphous carbon layer).

Step S102: performing oxidation treatment on the surface of the bottom electrode to form an oxide layer on the surface of the bottom electrode.

In this step, an oxide layer is formed on the surrounding sides and the upper surface of the bottom electrode.

It should be noted that, in this application, the oxidation method of the bottom electrode is not limited, and can be selected by oneself.

As a specific implementation manner, the oxidizing the surface of the bottom electrode includes: using a peroxide solution to oxidize the surface of the bottom electrode. The peroxide solution may be hydrogen peroxide.

As another specific implementation manner, the oxidizing the surface of the bottom electrode includes: ionizing the gas out of the plasma in the etching chamber, and using the plasma to oxidize the surface of the bottom electrode, Wherein, the gas is oxygen, or a mixed gas of oxygen and inert gas.

As another specific implementation manner, the oxidizing treatment on the surface of the bottom electrode includes: ionizing the gas into the plasma in the glue remover under high temperature environment, and using the plasma to treat the bottom electrode. The surface of the electrode is oxidized, wherein the gas is oxygen, or a mixed gas of oxygen and inert gas.

Step S103: removing the oxide layer located on the upper surface of the bottom circuit layer, so that the oxide layer remains around the bottom electrode.

As an implementation manner, removing the oxide layer located on the upper surface of the bottom circuit layer includes:

Step S1031: forming a dielectric layer on the upper surface of the bottom circuit layer not covered by the bottom electrode and the oxide layer to obtain a pre-treated structure;

Step S1032 : Thinning the pretreatment structure and the oxide layer on the upper surface of the bottom electrode to expose the bottom electrode and form a conductive path.

Wherein, the material of the dielectric layer includes but not limited to SiO ₂ , SiN, SiON.

In this application, the method of thinning is not limited, and it depends on the situation. Optionally, a chemical mechanical planarization technique is used to planarize the pretreatment structure to expose the bottom electrode. Alternatively, the preprocessed structure is thinned using chemical mechanical planarization and etching techniques.

Step S104: forming a memory cell layer and a metal hard mask layer stacked from bottom to top on the upper surface of the bottom electrode.

First, form a storage unit layer, a metal hard mask layer and a dielectric hard mask layer on the upper surface of the pretreatment structure after thinning, and then etch the storage unit layer and the metal hard mask layer, so that the storage unit layer and the metal The hard mask layer corresponds to the bottom electrode. Preferably, a dielectric hard mask layer can also be deposited on the upper surface of the metal hard mask layer as a mask for etching memory cells to facilitate patterning, and will be removed naturally during the process of etching memory cells.

The etching method can be reactive ion etching (Reactive Ion Etching, RIE), or ion beam etching (Ion beam etching, IBE), or a mixed etching of both RIE and IBE.

Step S105: Etching the memory cell layer and introducing over-etching.

Step S106: forming a top circuit layer on the upper surface of the metal hard mask layer.

The formation process of the top circuit layer includes:

Step S1061: backfilling the dielectric layer on the upper surface of the dielectric layer, and making the backfilled dielectric layer flush with the upper surface of the metal hard mask layer;

It should be noted that the upper surface of the metal hard mask layer is exposed to create back-end conductive contacts.

After backfilling the dielectric layer, the method of exposing the metal hard mask layer is not specifically limited in this application, and can be selected by oneself. For example, chemical mechanical polishing can be used to grind and polish the backfilled dielectric layer, or first planarize the backfilled dielectric layer, and then etch the entire dielectric layer, or pattern the dielectric layer after planarization Top circuit structure (Damascus process).

Step S1062: forming a top circuit layer on the upper surface of the metal hard mask layer and the backfilled dielectric layer.

In this step, a double damascene process is generally used to generate logic vias and upper circuit traces.

In the memory preparation method in this application, an oxide layer is provided around the bottom electrode, that is, the side walls of the bottom electrode are completely oxidized, and the short circuit caused by reverse sputtering is reduced during the etching process, and the performance and yield of the memory are improved. , at the same time, the existence of the oxide layer can make the critical dimension of the bottom electrode larger, reducing the difficulty of process realization, and the nesting accuracy control is more relaxed than that without the oxide layer; the thickness of the oxide layer is controllable, and can be controlled according to the memory cell Size is adjustable for compatibility with different sized storage units.

In the preparation method of the memory in this application, an oxide layer is formed around the bottom electrode, that is, the side walls of the bottom electrode are completely oxidized, and the short circuit caused by reverse sputtering is reduced during the etching process, and the performance and goodness of the memory are improved. At the same time, due to the reduction of anti-sputtering, the nesting accuracy control is more relaxed than that without oxide layer, which is beneficial to improve the lithography alignment window; the thickness of the oxide layer is controllable and can be adjusted according to the size of the memory cell layer , Compatible with memory cells of different sizes; the existence of the oxide layer can increase the critical size of the bottom electrode, reduce the process requirements for patterning the bottom electrode, and thus reduce the difficulty of process implementation. In addition, when the memory is a phase change random access memory (PCRAM), the existence of the oxide layer can also be used to make the bottom electrode smaller, reducing the effective contact area between the bottom electrode and the phase change layer, thereby reducing the operating power of the PCRAM. consumption.

On the basis of any of the above embodiments, in one embodiment of the present application, after over-etching the memory cell layer, the memory preparation method further includes:

It should be noted that the insulating protection layer is also located on the surface of the dielectric layer formed before backfilling the dielectric layer.

Forming methods of the insulating protective layer include but are not limited to chemical vapor deposition and plasma enhanced chemical vapor deposition.

In this embodiment, an insulating protective layer is deposited on the upper surface of the dielectric layer to prevent oxidation when exposed to air after leaving the etching chamber, causing irreversible damage to the device and yield.

The above preparation methods will be described respectively below with different MRAM structures.

Embodiment 1: When the connection between the bottom circuit layer and the bottom electrode is a copper conductor

Step 1, depositing a bottom electrode material layer 2' and a photoresist layer 10 on the bottom circuit layer 1, and etching the bottom electrode material layer 2' to form a bottom electrode 2, and removing the photoresist layer 10, cleaning, such as Figure 5 and Figure 6 show. In order to avoid pollution of the copper conductor 7, the upper surface of the copper conductor 7 needs to be located within the lower surface area of the bottom electrode 2. When forming the bottom electrode 2 by photolithography, care should be taken not to cut off the bottom electrode material layer 2' completely.

Step 2, performing oxidation treatment on the bottom electrode to form an oxide layer 3, as shown in FIG. 7 .

Step 3, filling the dielectric material 11, as shown in FIG. 8 .

Step 4, self-aligning etch the dielectric material 11 and the uncut bottom electrode material 2 to form a structure in which the upper surface of the copper conductor is located within the projected area of the lower surface of the bottom electrode on the horizontal plane, and backfill the dielectric 11 again .

Step 5, exposing the bottom electrode by chemical mechanical planarization; depositing a memory cell layer 4, a metal hard mask layer 5, a dielectric hard mask layer and a photoresist layer, performing etching and patterning, and over-etching the memory cell Layer 4, as shown in Figure 9.

Step 6, backfill the dielectric layer 11 and expose the metal hard mask layer, as shown in FIG. 10 .

Step 7, forming the top circuit layer 6, as shown in FIG. 11 . Generally, it is a double damascene process, which produces logic vias and upper circuit traces.

Embodiment 2: When the connection between the bottom circuit layer and the bottom electrode is a non-copper conductor

Step 1, depositing a bottom electrode material layer 2' and a photoresist layer 10 on the bottom circuit layer 1, and etching the bottom electrode material layer 2' to form a bottom electrode 2, and removing the photoresist layer 10, cleaning, such as As shown in FIG. 12 and FIG. 13 , the lower surface of the bottom electrode 2 may be located within the range of the upper surface of the non-copper conductor 8 .

Step 2, performing oxidation treatment on the bottom electrode 2 to form an oxide layer 3 as shown in FIG. 14 .

Step 3, filling the dielectric material 11, as shown in FIG. 15 .

Step 4, exposing the bottom electrode through chemical mechanical planarization, as shown in FIG. 16 .

Step 5, depositing the memory cell layer 4, the metal hard mask layer 5, and the dielectric hard mask layer, performing etching and patterning; over-etching the memory cell layer 4, and backfilling the dielectric layer 11, as shown in FIG. 17 .

Step 6, exposing the metal hard mask layer 5, as shown in FIG. 18 .

Step 7, forming the top circuit layer 6, as shown in FIG. 19 . Generally, it is a double damascene process, which produces logic vias and upper circuit traces.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and for the related part, please refer to the description of the method part.

The memory provided by the present application and the preparation method thereof have been introduced in detail above. In this paper, specific examples are used to illustrate the principles and implementation methods of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. It should be pointed out that those skilled in the art can make several improvements and modifications to the application without departing from the principles of the application, and these improvements and modifications also fall within the protection scope of the claims of the application.

Claims

A memory, characterized in that, comprising:

bottom circuit layer;

a bottom electrode disposed on the upper surface of the bottom circuit layer;

an oxide layer disposed around the bottom electrode;

The memory cell layer and the metal hard mask layer are arranged on the upper surface of the bottom electrode, stacked from bottom to top;

The top circuit layer is arranged on the upper surface of the metal hard mask layer.
The memory device according to claim 1, wherein when the connection between the bottom circuit layer and the bottom electrode is a copper conductor, the upper surface of the copper conductor is located at the level of the lower surface of the bottom electrode within the projection area.
The memory device according to claim 1, wherein when the connection between the bottom circuit layer and the bottom electrode is a non-copper conductor, the lower surface of the bottom electrode is located on the upper surface of the non-copper conductor within the region.
The memory according to any one of claims 1 to 3, further comprising:

An insulating protection layer arranged around the storage unit layer and the metal hard mask layer.
A memory preparation method, characterized in that, comprising:

forming a bottom electrode on the upper surface of the bottom circuit layer;

performing oxidation treatment on the surface of the bottom electrode to form an oxide layer on the surface of the bottom electrode;

removing the oxide layer located on the upper surface of the bottom circuit layer, so that the oxide layer remains around the bottom electrode;

forming a memory cell layer and a metal hard mask layer stacked from bottom to top on the upper surface of the bottom electrode;

etching the memory cell layer and introducing overetching;

A top circuit layer is formed on the upper surface of the metal hard mask layer.
The memory manufacturing method according to claim 5, wherein the oxidizing the surface of the bottom electrode comprises:

The surface of the bottom electrode is oxidized using a peroxide solution.
The memory manufacturing method according to claim 5, wherein the oxidizing the surface of the bottom electrode comprises:

The gas is ionized into the plasma in the etching chamber, and the surface of the bottom electrode is oxidized with the plasma, wherein the gas is oxygen, or a mixed gas of oxygen and inert gas.
The memory manufacturing method according to claim 5, wherein the oxidizing the surface of the bottom electrode comprises:

In a high-temperature environment, the gas is ionized out of the plasma in the degumming machine, and the surface of the bottom electrode is oxidized with the plasma, wherein the gas is oxygen, or a combination of oxygen and an inert gas mixed composition.
The memory manufacturing method according to claim 5, wherein the removing the oxide layer on the upper surface of the bottom circuit layer comprises:

forming a dielectric layer on the upper surface of the bottom circuit layer not covered by the bottom electrode and the oxide layer to obtain a pretreatment structure;

Thinning the pretreatment structure and the oxide layer on the upper surface of the bottom electrode to expose the bottom electrode and form a conductive path.
The memory manufacturing method according to any one of claims 5 to 9, characterized in that, after the over-etching of the memory cell layer, further comprising:

An insulating protection layer is formed around the memory cell layer and the metal hard mask layer.