WO2023115270A1 - 一种基于互补晶体管的push-push二倍频器 - Google Patents

一种基于互补晶体管的push-push二倍频器 Download PDF

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WO2023115270A1
WO2023115270A1 PCT/CN2021/139748 CN2021139748W WO2023115270A1 WO 2023115270 A1 WO2023115270 A1 WO 2023115270A1 CN 2021139748 W CN2021139748 W CN 2021139748W WO 2023115270 A1 WO2023115270 A1 WO 2023115270A1
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transistor
signal
output
frequency
push
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PCT/CN2021/139748
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English (en)
French (fr)
Inventor
吴亮
吴小平
王义晖
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香港中文大学（深圳）
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Priority to CN202180010460.0A priority Critical patent/CN115088187A/zh
Priority to PCT/CN2021/139748 priority patent/WO2023115270A1/zh
Priority to US17/891,249 priority patent/US11632090B1/en
Publication of WO2023115270A1 publication Critical patent/WO2023115270A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
    • H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/534—Transformer coupled at the input of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

  • the invention relates to the field of radio frequency technology, in particular to a push-push frequency doubler based on complementary transistors.
  • one of the main challenges in realizing the signal transceiving system in the millimeter wave band is: how to solve the performance degradation of passive components as the frequency increases, among which, the generation of high-quality local oscillator (LO) is particularly important.
  • One solution to generate a high-frequency local oscillator (LO) is to use a frequency doubler, and the signal generated by the frequency doubler is used as the local oscillator.
  • the conversion gain of the frequency doubler with the traditional structure is low, and the single-ended output is difficult to drive High performance mixer.
  • the invention discloses a push-push frequency doubler based on complementary transistors with higher conversion gain and capable of differential output.
  • An embodiment provides a push-push frequency doubler based on complementary transistors, including a first differential amplifier circuit, a second differential amplifier circuit and an output load circuit;
  • the first differential amplifier circuit is configured to receive a differential input signal with an initial frequency, and amplify the amplitude of the second harmonic of the differential input signal with an initial frequency to obtain a first signal;
  • the second differential amplifier circuit is configured to receive the differential input signal with the initial frequency, and amplify the amplitude of the second harmonic of the differential input signal with the initial frequency to obtain a second signal; wherein, the The first signal and the second signal are a set of differential signals having the same amplitude and a phase difference of 180°;
  • the output load circuit is used to extract the second harmonic signal in the first signal and the second signal respectively to obtain a differential output signal with a first output frequency, and output the differential output signal with a first output frequency ; Wherein, the first output frequency is twice the initial frequency.
  • a voltage supply terminal VDD is also included, and both the first differential amplifier circuit and the second differential amplifier circuit include a plurality of transistors;
  • the voltage supply terminal VDD is used to provide driving currents to multiple transistors in the first differential amplifier circuit and the second differential amplifier circuit.
  • the types of the multiple transistors in the first differential amplifier circuit are the same; the types of the multiple transistors in the second differential amplifier circuit are the same; the types of the multiple transistors in the first differential amplifier circuit are the same as The types of the plurality of transistors in the second differential amplifier circuit are different.
  • the first differential amplifier circuit includes a transistor MN1, a transistor MN2, a capacitor CN1, a capacitor CN2, a resistor RN1 and a resistor RN2;
  • the control pole of the transistor MN1 receives the signal VBN through the resistor RN1, the second pole of the transistor MN1 is grounded, the first pole of the transistor MN1 is connected to the first pole of the transistor M2, and the control pole of the transistor MN1 is also connected to one end of the capacitor CN1, The other end of the capacitor CN1 is used to receive one signal in the differential input signal with the initial frequency; the control electrode of the transistor M2 receives the signal VBN through the resistor RN2, the second electrode of the transistor M2 is grounded, and the control electrode of the transistor M2 is also connected to the ground.
  • the capacitor CN2 It is connected to one end of the capacitor CN2, and the other end of the capacitor CN2 is used to receive another signal in the differential input signal with the initial frequency; the first pole of the transistor MN1 is also connected to the output load circuit, which is used to output the first a signal.
  • both the transistor MN1 and the transistor MN2 are NMOS transistors.
  • the second differential amplifier circuit includes a transistor MP1, a transistor MP2, a capacitor CP1, a capacitor CP2, a resistor RP1, and a resistor RP2;
  • the control electrode of the transistor MP1 receives the signal VBP through the resistor RP1, the first electrode of the transistor MP1 is connected to the voltage supply terminal VDD, the second electrode of the transistor MP1 is connected to the second electrode of the transistor MP2, and the control electrode of the transistor MP1 is also connected to the capacitor CP1.
  • One end is connected, and the other end of the capacitor CP1 is used to receive one signal in the differential input signal with the initial frequency;
  • the control pole of the transistor MP2 is connected to the signal VBP through the resistor RP2, and the first pole of the transistor MP2 is connected to the first pole of the transistor MP1 , the second pole of the transistor MP2 is connected to the output load circuit, which is used to output the second signal, the control pole of the transistor MP2 is also connected to one end of the capacitor CP2, and the other end of the capacitor CP2 is used to receive a differential input signal with an initial frequency Another signal in .
  • both the transistor MP1 and the transistor MP2 are PMOS transistors.
  • the first output frequency is 58-66.5GHz.
  • the width of the transistor MN1 and the transistor MN2 is 16 ⁇ m, and the length is 60 nm; the width of the transistor MP1 and the transistor MP2 is 48 ⁇ m, and the length is 60 nm.
  • the output load circuit includes an inductor L4, one end of the inductor L4 is used to receive the first signal, and the other end of the inductor L4 is used to receive the second signal.
  • the output load circuit includes a transformer T2 and a common source amplifier CS;
  • the transformer T2 is used to balance the first signal output by the first differential amplifier circuit and the second signal output by the second differential amplifier circuit, and output them to the common source amplifier CS respectively;
  • the common-source amplifier CS is used to amplify the phase-balanced first signal and the second signal output by the transformer T2 and output them respectively.
  • the common source amplifier CS includes: a transistor MN3 and a transistor MN4, the control electrode of the transistor MN3 is used to receive a signal output by the transformer T2, and the control electrode of the transistor MN3 is also connected to the first pole, the second pole of the transistor MN3 is grounded; the control pole of the transistor MN4 is used to receive another signal output by the transformer T2, the control pole of the transistor MN4 is also connected to the first pole of the transistor MN3 through the capacitor CN4, the first pole of the transistor MN3 and The first pole of the transistor MN4 is respectively connected to the two ends of the inductor L7, and the two ends of the inductor L7 are used to output the differential output signal.
  • it also includes an input balun circuit and an output balun circuit;
  • the input balun circuit is used to convert the received single-ended input signal into the differential input signal
  • the output balun circuit is used to convert the differential output signal output by the output load circuit into a single-ended output signal, and output the single-ended output signal.
  • the input balun circuit includes a transformer T1, the primary coil of the transformer T1 is an inductor L1, the secondary coil is an inductor L2, and the inductor L1 and the inductor L2 are coupled; one end of the inductor L1 It is used to receive a single-ended input signal, and the other end of the inductor L1 is grounded; the two ends of the inductor L2 are respectively used to output two signals in the differential input signal.
  • the output balun circuit includes a transformer T3, the primary coil of the transformer T3 is an inductor L5, the secondary coil is an inductor L6, and the inductor L5 and the inductor L6 are coupled; the two inductors of the inductor L5 One end of the inductor L6 is connected to the output load circuit 30 for receiving differential output signals; one end of the inductor L6 is used for outputting a single-ended output signal, and the other end of the inductor L6 is grounded.
  • the first differential amplifier circuit receives the differential input signal with the initial frequency, and amplifies the amplitude of the second harmonic of the differential input signal to obtain the first signal ;
  • the second differential amplifier circuit receives a differential input signal with an initial frequency, and amplifies the amplitude of the second harmonic of the differential input signal to obtain a second signal; wherein, the first signal and the second signal have the same amplitude and phase A set of differential signals with a phase difference of 180°;
  • the output load circuit extracts the second harmonic signal in the first signal and the second signal respectively to obtain a differential output signal with the first output frequency, and outputs a differential output with the first output frequency signal; wherein, the first output frequency is twice the initial frequency; thus, the same frequency multiplier is realized to output a differential signal, and the two signals in the output differential signal have the same amplitude, and the two signals can be greatly increased after the amplitude superposition Boost the conversion gain of the frequency multiplier.
  • Figure 1 is a circuit schematic diagram of an existing NMOS Push-Push frequency multiplier
  • Fig. 2 is the circuit schematic diagram of existing PMOS Push-Push frequency multiplier
  • FIG. 3 is a schematic structural diagram of a push-push frequency doubler based on complementary transistors in an embodiment
  • Fig. 4 is the circuit principle diagram of frequency multiplier shown in Fig. 3;
  • Fig. 5 is a schematic diagram of an output load model of an embodiment
  • FIG. 6 is a schematic structural diagram of a push-push frequency doubler based on complementary transistors in another embodiment
  • Fig. 7 is a schematic circuit diagram of the frequency multiplier shown in Fig. 6;
  • Fig. 8 is a schematic circuit diagram of a common source amplifier of an embodiment
  • FIG. 9 is a schematic diagram of the layout of the transformer T3;
  • Fig. 10 is a simulation schematic diagram of the relationship between the bias voltage and the output power of the frequency multiplier
  • Fig. 11 is a simulation schematic diagram of the influence of different transistor widths on the conversion gain of the frequency multiplier
  • Figure 12 is a schematic diagram of a frequency multiplier chip for testing
  • Fig. 13 is the structural representation of test platform
  • Figure 14 is a schematic diagram of the simulation of the fundamental wave suppression effect of the frequency multiplier under different input powers
  • Fig. 15 is a simulation schematic diagram of the second harmonic conversion gain and output frequency of the frequency multiplier
  • Fig. 16 is a schematic diagram of spectrum simulation of the output signal of the frequency multiplier
  • Fig. 17 is the simulation schematic diagram of the second harmonic power and DC power consumption and input power relation of frequency multiplier
  • FIG. 18 is a simulation schematic diagram of the input phase noise and the output phase noise of the frequency multiplier.
  • connection and “connection” mentioned in this application all include direct and indirect connection (connection) unless otherwise specified.
  • the transistors involved in the circuits of the embodiments of the present invention may be transistors of any structure, such as bipolar transistors (BJTs) or field effect transistors (FETs), unless otherwise specified.
  • BJTs bipolar transistors
  • FETs field effect transistors
  • the transistor is a bipolar transistor
  • its control pole refers to the gate of the bipolar transistor
  • the first pole can be the collector or emitter of the bipolar transistor
  • the corresponding second pole can be the gate of the bipolar transistor.
  • Emitter or collector in the actual application process, “emitter” and “collector” can be interchanged according to the signal flow direction; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first One pole can be the drain or source of the field effect transistor, and the corresponding second pole can be the source or drain of the field effect transistor.
  • the "source” and “drain” can be based on the signal flow direction And swap.
  • Document 3 A 90nm CMOS Low Power 60GHz Transceiver with Integrated Baseband Circuit (C.Marcu, D.Chowdhury, C.Thakkar, L.-K.Kong, M.Tabesh, J.-D.Park, Y. .Wang, B.Afshar, A.Gupta, A.Arbabian, S.Gambini, R.Zamahi, A.M.Niknejad, and E.Alon, "A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitry," in IEEE Int) ;
  • Document 5 A performance analysis technique in multi-gigabit millimeter-wave communication with LO noise floor limitation (J.Chen, Z.S.He, D.Kuylenstierna, T.Eriksson, M.H ⁇ orberg, T.Emanuelsson, T.Swahn, and H. Zirath, "Does LO Noise Floor Limit Performance in Multi-Gigabit Millimeter-Wave Communication?” IEEE Microwave and Wireless Components Letters, vol.27, no.8, pp.769-771, Aug.2017);
  • Literature 8 A new transformer balun based on 0.13-_m SiGe technology and a K-band frequency doubler with 35-dB fundamental suppression (S.Chakraborty, L.E.Milher, X.Zhu, L.T.Hall, O.Sevimli, and M.C.Heimlich, "A K-Band Frequency Doubler with 35-dB Fundamental Rejection Based on Novel Transformer Balun in 0.13-_m SiGe Technology," IEEE Electron Device Letters, vol.37, no.11, pp.1375-1378, Nov. 2016);
  • Document 12 A 100Gb/s ultra-high-speed SiGe bipolar IC design (M.Moller, "Challenges in the cell-based design of very-high-speed SiGe-bipolar ICs at 100Gb/s," IEEE J.Solid-State Circuits, vol.43, no.9, pp.1877-1888, Sep.2008);
  • Literature 15 A highly efficient 138-170GHz SiGe HBT frequency multiplier for power-constrained applications (C.Coen, S.Zeinolabedinzadeh, M.Kaynak, B.Tillack and J.D.Cressler, "A highly-efficient 138-170GHz SiGe HBT frequency doubler for power-constrained applications," 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016, pp.23-26);
  • Document 17 A technology for designing an ultra-compact low-power 60GHz frequency doubler in 22nm FD-SOI (M.Cui, C.Carta and F.Ellinger, "Design of an Ultra Compact Low Power 60GHz Frequency Doubler in 22nm FD -SOI," 2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2020, pp.40-42);
  • Literature 19 A Compact V-band Frequency Doubler with True Balanced Differential Output (S.Yuan and H.Schumacher, "Compact V band frequency doubler with true balanced differential output,” 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting( BCTM), 2013, pp.191-194);
  • documents 1-3 provide the CMOS transceiver design based on the 60GHz millimeter-wave frequency band, but the premise of designing this CMOS transceiver is that it is necessary to generate a high-frequency local oscillator (LO) for frequency mixing; document 4 shows However, to generate a high-frequency LO, a voltage-controlled oscillator (VCO) consumes considerable power and exhibits relatively poor performance.
  • LO local oscillator
  • VCO voltage-controlled oscillator
  • the circuit structure of frequency multiplier is divided into four types, namely: frequency multiplier with single-stage amplifier structure (document 10), frequency multiplier with Gilbert unit (document 6) , push-push (PP) frequency multiplier (Documents 8 and 11) and injection-locked frequency multiplier technology (Document 9).
  • the frequency multiplier of the Gilbert unit can achieve high conversion gain and wide frequency band, but its power consumption is usually large and is easily affected by DC offset.
  • the frequency multiplier injected with locked frequency multiplication technology can increase the output amplitude and achieve lower power consumption.
  • the design of high-frequency VCO is more difficult.
  • only injection of locked frequency multiplication technology will show Very narrow bandwidth.
  • the frequency multiplier of the push-push structure takes advantage of the nonlinear characteristics of the device, has good fundamental wave suppression ability and is easy to implement, but the conversion gain of the frequency multiplier of the traditional push-push structure is low and the single-ended output is difficult to drive High performance mixer.
  • Document 12 shows that at high frequencies, the existence of differential signals is very necessary, which can avoid accurate simulation of the current return path in the design.
  • Documents 13-15 show some performance improvements to the push-push multiplier, where Document 13 shows that an inductor-based phase shifter and two push-push multiplier cores can achieve greater balance differential output. However, this method will double the power consumption and the occupied area of the phase shifter is very large, which is difficult to be applied to a highly integrated system.
  • literature 14 introduced a silicon-based phase shifter to create two differential inputs with opposite phases and push-push two frequency multiplication cores and reduce the chip area, the operation efficiency of this frequency multiplier is still very low, and Differential input signals are subject to the insertion loss and phase shift errors of the phase shifter.
  • Reference 15 shows that for power-constrained applications, high-efficiency frequency multipliers using compound semiconductor devices and carrying output amplifiers and multipliers have emerged in recent years, but unbalanced output, cost, and system integration are still a problem.
  • FIG. 1 and FIG. 2 are structural schematic diagrams of an existing push-push structure frequency multiplier (hereinafter referred to as a PP frequency multiplier), wherein FIG. 1 shows an NMOS PP frequency multiplier, It includes two identical NMOS transistors, and Figure 2 shows a PMOS PP frequency multiplier, which includes two identical PMOS transistors.
  • the PP frequency multiplier pushes the generated current into the inductive load. Since the peak impedance of the inductive load is designed at the second harmonic frequency of the input signal, and the fundamental wave is suppressed by the load characteristics of the inductive load, the PP frequency multiplier The frequency of the output signal is twice the frequency of the input signal.
  • the output current is regarded as a general nonlinear system. If the NMOS PP frequency doubler is regarded as a general nonlinear system, the current at the common-mode node retains only even harmonics. For each NMOS transistor in the PP doubler, the output current is
  • V B1 is the bias voltage of the transistor
  • V THN is the threshold voltage of the transistor.
  • the bias voltage V B1 should be close to the threshold voltage V THN of the transistor. Since both inputs are converted to currents only during half a cycle, the output voltage of the NMOS PP frequency multiplier
  • R Ln represents the resonant load resistance at the inductor L1 in the NMOS PP frequency doubler
  • k n represents the transconductance of the NMOS transistor. It can be seen that the output of the NMOS PP frequency multiplier produces a second harmonic signal.
  • R Lp is the resonant load resistance at the inductor L2 in the PMOS PP frequency doubler
  • k p represents the transconductance of the PMOS transistor.
  • the phase difference of the output voltage of the NMOS PP frequency multiplier and the PMOS PP frequency multiplier is 180°, and the amplitude of the output voltage is the same.
  • the frequency multiplier provided by the embodiment of the present invention combines the NMOS PP frequency multiplier and the PMOS PP frequency multiplier to increase the amplitude of the output signal and improve The conversion gain of the frequency multiplier is improved, and the differential signal can be output, which is convenient for driving a high-performance mixer in the later stage.
  • FIG. 3 is a schematic structural diagram of a push-push frequency doubler based on complementary transistors according to an embodiment of the present invention.
  • the two differential amplifier circuits 20 and the output load circuit 30 will be described in detail below.
  • the first differential amplifier circuit 10 is used for receiving the differential input signal with the initial frequency, and amplifying the amplitude of the second harmonic of the differential input signal with the initial frequency to obtain the first signal.
  • the first differential amplifier circuit 10 has two input terminals, and the differential input signal is two signals, and the two signals are respectively input into the first differential amplifier circuit 10 through the two input terminals, and the first differential amplifier circuit 10 passes the internal parameter Set to amplify the magnitude of the second harmonic of the differential input signal.
  • the second differential amplifier circuit 20 is used for receiving the differential input signal with the initial frequency, and amplifying the amplitude of the second harmonic of the differential input signal with the initial frequency to obtain the second signal.
  • the input terminal of the second differential amplifier circuit 20 is connected to the input terminal of the first differential amplifier circuit 10, that is, the second differential amplifier circuit 20 has the same input as the first differential amplifier circuit 10, and the second differential amplifier circuit 20 has the same input on the input terminal.
  • the differential amplifier circuit 20 has the same structure as the first differential amplifier circuit 10, and it also has two input terminals, and the two signals in the differential input signal are respectively input to the second differential amplifier circuit 20 through the two input terminals, and the second differential amplifier circuit
  • the circuit 20 amplifies the amplitude of the second harmonic of the differential input signal by setting internal parameters.
  • the first signal output by the first differential amplifier circuit 10 and the second signal output by the second differential amplifier circuit 20 have the same amplitude, but the phase difference between the first signal and the second signal is 180°, so that the second signal The first signal and the second signal form a set of differential signals.
  • the output load circuit 30 is used to extract the second harmonic signal in the first signal and the second signal respectively to obtain a differential output signal with the first output frequency, and output the differential output signal with the first output frequency to make the frequency multiplication
  • the device can realize the output of high frequency differential signal.
  • the output load circuit 30 has an inductive load characteristic, which can suppress the fundamental signal in the first signal and the second signal, and extract the second harmonic signal, and obtain the first output signal and the second output signal It is a group of differential signals with a first output frequency, and the first output frequency is twice the initial frequency, that is, the frequency of the differential output signal output by the output load circuit 30 is twice the initial frequency, realizing the difference of the frequency multiplier output.
  • the amplitudes of the first output signal and the second output signal are both amplified and identical, a higher conversion gain of the frequency multiplier is realized.
  • both the first differential amplifier circuit 10 and the second differential amplifier circuit 20 are transistor-structured circuits, which include a plurality of transistors.
  • the first differential amplifier circuit 10 and the second differential amplifier circuit All the transistors in 20 are driven by a driving voltage source. Compared with the existing PP frequency multiplier, there is no need to add a new driving voltage source, the chip area will not be increased too much, and the power consumption is low.
  • the amplitude of the second harmonic signal in the differential input signal can be amplified, for example: adjusting the bias voltage of the transistor to make it equal to or infinitely close to the threshold of the transistor Voltage, the threshold voltage of the transistor is the turn-on voltage of the transistor, which varies according to the model and type of the transistor.
  • the frequency multiplier provided by the embodiment of the present invention can be applied to a communication device based on a millimeter wave frequency band.
  • a signal transceiver device in a millimeter wave frequency band needs a high-frequency local
  • the frequency of the oscillator output signal cannot reach the millimeter-wave frequency band, so a frequency multiplier is required to double the frequency of the voltage-controlled oscillator output signal as a high-frequency local oscillator, for example: the frequency multiplier based on complementary transistors provided in this embodiment
  • the output frequency is 58-66.5GHz differential signal as a high-frequency local oscillator, which can be used to excite mixers in signal transceiver equipment in the 58-66.5GHz frequency band.
  • the first differential amplifier circuit 10 has two input terminals, which are respectively used to receive two signals Vinn and Vinp of the differential input signal, and the first differential amplifier circuit 10 passes the bias voltage of its internal transistor The adjustment, so that the transistors are biased at their threshold voltage, in order to maximize the output amplitude of the second harmonic.
  • the first differential amplifier circuit 10 includes a transistor MN1, a transistor MN2, a capacitor CN1, a capacitor CN2, a resistor RN1 and a resistor RN2.
  • the control pole of the transistor MN1 receives the signal VBN through the resistor RN1, the second pole of the transistor MN1 is grounded, the first pole of the transistor MN1 is connected to the first pole of the transistor M2, the control pole of the transistor MN1 is also connected to one end of the capacitor CN1, and the capacitor CN1
  • the other end of the transistor M2 is used to receive one of the differential input signals with the initial frequency;
  • the control pole of the transistor M2 receives the signal VBN through the resistor RN2, the second pole of the transistor M2 is grounded, and the control pole of the transistor M2 is also connected to one end of the capacitor CN2 , the other end of the capacitor CN2 is used to receive another signal in the differential input signal with the initial frequency;
  • the transistor MN1 and the transistor MN2 are the same two NMOS transistors, the capacitor CN1 and the capacitor CN2 have the same parameters, and the resistor RN1 and the resistor RN2 have the same parameters.
  • the bias voltages of the transistor MN1 and the transistor MN2 are provided by the voltage signal VBN, therefore, the bias voltages of the transistor MN1 and the transistor MN2 can be adjusted by adjusting the magnitude of the voltage signal VBN, so that the bias voltage is consistent with the transistor same threshold voltage.
  • the second differential amplifying circuit 20 is the same as the first differential amplifying circuit 10, and it has two input ends, which are respectively used to receive two-way signals V inn and V inp of the differential input signal, and the second differential amplifying circuit 20 passes through its internal
  • the bias voltage of the transistors is adjusted so that the transistors are all biased at their threshold voltages to maximize the output amplitude of the second harmonic.
  • the second differential amplifier circuit includes a transistor MP1, a transistor MP2, a capacitor CP1, a capacitor CP2, a resistor RP1 and a resistor RP2.
  • the control pole of the transistor MP1 receives the signal VBP through the resistor RP1, the first pole of the transistor MP1 is connected to a voltage supply terminal VDD, the second pole of the transistor MP1 is connected to the second pole of the transistor MP2, and the control pole of the transistor MP1 is also connected to one end of the capacitor CP1 Connection, the other end of the capacitor CP1 is used to receive one of the differential input signals with the initial frequency; the control pole of the transistor MP2 is connected to the signal VBP through the resistor RP2, the first pole of the transistor MP2 is connected to the first pole of the transistor MP1, and the transistor MP2 The second pole of the transistor MP2 is connected to the output load circuit 30, which is used to output the second signal to the output load circuit 30.
  • the control pole of the transistor MP2 is also connected to one end of the capacitor CP2, and the other end of the capacitor CP2 is used to receive the signal with the initial frequency. The other signal of the differential input signal.
  • the transistor MP1 and the transistor MP2 are the same two PMOS transistors, the capacitor CP1 and the capacitor CP2 have the same parameters, and the resistor RP1 and the resistor RP2 have the same parameter.
  • the bias voltages of the transistor MP1 and the transistor MP2 are provided by the voltage signal VBP, therefore, the bias voltages of the transistor MP1 and the transistor MP2 can be adjusted by adjusting the magnitude of the voltage signal VBP, so that the bias voltage is consistent with the transistor same threshold voltage.
  • the first differential amplifier circuit 10 and the second differential amplifier circuit 20 constitute the core module of the frequency multiplier. From the description of the above-mentioned first differential amplifier circuit 10 and the second differential amplifier circuit 20, it can be seen that the drive currents are provided by the same voltage terminal VDD, thus, compared with the existing PP frequency multiplier, the core module in the frequency multiplier provided by the embodiment of the present invention does not add a new driving voltage source, therefore, the core module of the frequency multiplier Compared with the chip area of the core module of the existing PP frequency multiplier, the chip area of the chip has not increased much, and the chip area is kept small while realizing the differential output.
  • the output load circuit 30 is used to extract the second harmonic signal in the first signal output by the first differential amplifier circuit 10 and the second signal output by the second differential amplifier circuit 20.
  • the output load circuit 30 has an inductive load characteristic, which can suppress Fundamental signal, get the second harmonic signal.
  • the output load circuit 30 includes an inductor L4, and the inductor L4 is connected between the first differential amplifier circuit 10 and the second differential amplifier circuit 20, that is, the two ends of the inductor L4 are respectively the first differential amplifier The output terminal of the circuit 10 and the second differential amplifier circuit 20 .
  • the parasitic capacitance in the inductance L4 and the transistor can resonate at the frequency of the second harmonic, so that the inductance L4 can extract the second harmonic signal and then output it, so as to Enables the frequency doubler to output a doubled differential output signal.
  • the signal cycle includes two time slots t1 and t2. Assume first that transistor MN1, transistor MN2, transistor MP1, and transistor MP2 are all biased at their respective threshold voltages. At this time, transistor MN1, transistor MN2, transistor MP1, and transistor MP2 maximize the amplitude of the second harmonic signal in the signal, and the differential The input signals are Vinp and Vinn .
  • V inp is higher than the threshold voltage V THN of the transistor MN1 and the transistor MN2, and Vin is lower than V THN ; in the time slot t2, Vin is higher than The threshold voltages V THN of the transistors MN1 and MN2 , while V inp is lower than V THN ; under the above bias strategy, V inp will be amplified in time slot t1 , and Vin will be amplified in time slot t2 . Therefore, the output signal phase of node B is opposite to V inp in time slot t1, and the signal phase of node B is opposite to Vin in time slot t2.
  • the voltage of node A is similar to that of node B, and eventually the frequency multiplier forms differential output signals V outp and V outn .
  • the second harmonic signal is finally extracted by making the inductance L4 and the parasitic capacitance resonate in the corresponding frequency range.
  • this structure makes full use of the input signal for frequency multiplication conversion, In the case of constant DC current and supply voltage, there will be no increase in core chip area and power consumption. Additionally, differential outputs are created to help drive high-performance mixers.
  • the output load model of the entire frequency multiplier is analyzed by taking the output end of the first differential amplifier circuit 10 as an example.
  • FIG. 5 is a schematic diagram of an output load model of an embodiment, taking small signal input as an example.
  • the output impedance Rpn of the output load model seen from the output terminal of the first differential amplifier circuit 10 can be expressed as:
  • the output impedance R pp of the output load model seen from the output terminal of the second differential amplifier circuit 20 can be expressed as:
  • r o1 is the output resistance of transistor MN1 (transistor MN2)
  • r o2 is the output resistance of transistor MP1 (transistor MP2)
  • C gd1 is the parasitic capacitance of transistor MN1 (transistor MN2)
  • C gd2 is the transistor MP1
  • L 4 is the inductance value of the inductor L4.
  • the inductance value of the inductor L4 can be set appropriately, so that the inductor L4 Resonates with the parasitic capacitance at the second harmonic frequency to amplify the amplitude of the second harmonic signal.
  • the magnitude V pd of the differential output signal of the frequency multiplier shown in Figure 4 can be expressed as:
  • ⁇ p is the channel length modulation coefficient of the PMOS transistor
  • ⁇ n is the channel length modulation coefficient of the NMOS transistor
  • K p is the transconductance of the PMOS transistor
  • K n is the transconductance of the NMOS transistor
  • V dsp is the transconductance of the PMOS transistor Drain voltage
  • V dsn is the drain voltage of the NMOS transistor
  • V DD is the driving voltage
  • V p is the amplitude of the differential input signal.
  • the output load circuit 30 includes a transformer T2 and a common source amplifier CS.
  • the transformer T2 is used to perform phase balance on the first signal output by the first differential amplifier circuit 10 and the second signal output by the second differential amplifier circuit 20, and then output them to the common source amplifier CS respectively; the common source amplifier CS is used to output the signal to the transformer T2
  • the phase-balanced first signal and the second signal are amplified and output respectively.
  • the primary coil of the transformer T2 is an inductance L4, the secondary coil is an inductance L3, the inductance L4 and the inductance L3 are coupled, the coupling coefficient is k2, the inductance L4 is connected between the first differential amplifier circuit 10 and the second differential amplifier circuit 20, the inductance One end of L3 is connected to the positive input pin of the common source amplifier CS, and the other end is connected to the negative input pin of the common source amplifier CS.
  • the inductor L3 also has a bias end for connecting the working voltage.
  • the primary coil of the transformer T2 is an inductive load, and through the coupling of the secondary coil and the primary coil, the unbalanced first signal and the second signal can be balanced, and then the amplitude is amplified through the common source amplifier CS, so that the output of the first The first output signal and the second output signal have larger amplitudes, which improves the overall conversion gain of the frequency multiplier.
  • the input and output of frequency multipliers require single-ended signals.
  • single-pin interfaces are often used for input and output of single-ended signals.
  • the push-push frequency doubler based on complementary transistors (frequency doubler for short) provided in this embodiment further includes: an input balun circuit 40 and an output balun circuit 50 .
  • the input balun circuit 40 is used to convert the received single-ended input signal into a differential input signal.
  • the input balun circuit 40 includes a three-port device capable of converting a single-ended input signal to a differential input signal.
  • the input balun circuit 40 includes a wide RF transmission line transformer, which can convert single-ended input signals into differential input signals to realize the connection between the balanced transmission line circuit and the unbalanced transmission line circuit.
  • the output balun circuit 50 is used for converting the differential output signal output by the output load circuit into a single-ended output signal, and outputting the single-ended output signal.
  • the output balun circuit 50 is similar in principle to the input balun circuit 40 and includes a wide radio frequency transmission line transformer capable of converting a differential output signal to a single-ended output signal.
  • the input balun circuit 40 includes a transformer T1, the primary coil of the transformer T1 is an inductor L1, the secondary coil is an inductor L2, and the coupling between the inductor L1 and the inductor L2 is k1;
  • One end of the inductor L1 is used to receive a single-ended input signal, the other end of the inductor L1 is grounded, and the two ends of the inductor L2 are respectively used to output two signals of the differential input signal.
  • the inductor L2 also has a bias end for grounding.
  • the output balun circuit 50 includes a transformer T3, the primary coil of the transformer T3 is an inductance L5, the secondary coil is an inductance L6, the inductance L5 and the inductance L6 are coupled, and the coupling coefficient is k3; both ends of the inductance L5 are connected to the output load circuit 30 , for receiving differential output signals, one end of the inductor L6 is used for outputting single-ended output signals, and the other end of the inductor L6 is grounded.
  • the inductor L5 also has a position end for connecting the working voltage.
  • FIG. 8 shows a schematic diagram of a common source amplifier CS in an embodiment
  • the common source amplifier CS includes a transistor MN3 and a transistor MN4, the control electrode of the transistor MN3 is used to receive the positive input signal V in+ , and the transistor MN3
  • the control electrode of the transistor MN4 is connected to the first electrode of the transistor MN4 through the capacitor CN3, the second electrode of the transistor MN3 is grounded, the control electrode of the transistor MN4 is used to receive the negative input signal V in- , the control electrode of the transistor MN4 is also connected to the transistor MN3 through the capacitor CN4
  • the first pole, the first pole of the transistor MN3 and the first pole of the transistor MN4 are respectively connected to the two ends of the inductor L7, and the two ends of the inductor L7 are respectively used for outputting V out+ and V out ⁇ .
  • V in+ is the signal received by the positive input terminal of the common source amplifier CS
  • V in- is the signal received by the
  • Capacitor CN1 , capacitor CN2 , capacitor CP1 and capacitor CP2 are 617fF MoM capacitors. Under 0-dBm single-ended input signal, the simulated gate voltage amplitude of transistor MP1 (MP2) and transistor MN1 (MN2) is 310mV.
  • the transformer diagram is used for the load of the core frequency doubler, and the balanced differential output signal output by the transformer T2 is finally amplified by the common source amplifier CS and converted into After the single-ended output signal is output.
  • the width of the transistor MN1 is selected to be 16 ⁇ m and the length is 60 nm.
  • Figure 9 is a schematic diagram of the layout of the transformer T2.
  • the inductance design values of the two-turn inductor L3 and the one-turn inductor L4 are 360pH and 110pH respectively at 60GHz, and the line width is designed to be 2.05 ⁇ m to reduce the skin effect.
  • the spacing is designed to be 2 ⁇ m to achieve tight coupling.
  • the simulation results show that the coupling coefficient k 2 of the inductor L3 and the inductor L4 is 0.85, and the operating voltage is selected as 1V, where M7, M8, and M9 represent the number of layers of metal wires, which are the seventh layer and the first layer respectively. Eighth floor, ninth floor.
  • Transistor MN1 MN2
  • transistor MP1 MP2
  • Transistor MN1 MN2
  • MP2 transistor Both MP1
  • V dsp and V dsn are determined by W 2 .
  • the value of W2 is also related to the optimal conversion gain of the frequency multiplier, when W2 is small enough, the bias current and Vdsn will become small together, assuming the amplitude of the differential output voltage Vpd at L4 is Apd and the transistor MN1 (MN2) still works in the saturation region (V dsn is slightly greater than V dsatn ) under large signal input, then the amplitude A pd of the differential output signal will be limited, so that:
  • V dsn increases and V dsp decreases, and the upper limit of A pd is also limited:
  • W increases from 8 ⁇ m to 32 ⁇ m, the conversion gain increases, but the gain peak frequency decreases.
  • the frequency multiplier of the present invention can be manufactured using a 65nm CMOS process, the input signal and the output signal are single-ended signals, the input signal and the output signal pass through two GSG pads, and the bare chip of the test chip is shown in Figure 12
  • the total area of the chip is 0.43mm ⁇ 0.08mm, the area of the core module in the chip is 0.15mm ⁇ 0.08mm, the chip is glued on the PCB for testing, the input signal and output signal are provided by the probe, the driving power and the bias signal Provided by bonding wires, wherein the core module includes a first differential amplifier circuit and a second differential amplifier circuit, and the driver includes an output load circuit and an output balun circuit.
  • the core module includes a first differential amplifier circuit and a second differential amplifier circuit
  • the driver includes an output load circuit and an output balun circuit.
  • FIG. 13 shows the schematic diagram of building the test platform, wherein (a) is set to test the output power of the frequency multiplier with a V-band harmonic mixer, and (b) is set to test the output power of the fundamental wave , and combine the data measured in (a) to calculate the effect of fundamental wave suppression (FR).
  • FR fundamental wave suppression
  • the spectrum analyzer only shows a -60dBm noise floor during the test in Figure 10(b). This indicates that the fundamental power from the output driver is less than -60dBm and is swamped by the analyzer's noise floor. Therefore, the fundamental frequency suppression results of the core frequency multiplier and the frequency multiplier with driver are provided by the simulation results shown in Fig. 14. It can be seen that the simulated fundamental wave of the core frequency multiplier and frequency multiplier with driver Rejection is better than 43.6dBc and 61dBc respectively.
  • Figure 15 shows the second harmonic conversion gain of the frequency doubler versus output frequency measured at 30GHz equivalent 0dBm and -4dBm input power.
  • the output power of the frequency multiplier is 0dBm
  • the conversion gain is 0dB (the line loss of the output test is not considered).
  • the frequency doubler output power is -5.7dBm
  • the conversion gain is -1.7dB.
  • the -3-dB bandwidth ranges from 58GHz to 66.5GHz (13.7%).
  • Figure 16 shows the measured spectrum of the 60GHz output of the frequency doubler with a 0-dBm input at 30GHz.
  • Figure 17 shows the measured output second harmonic power and DC power consumption (including drive) of the doubler versus input power.
  • the input power is 0dBm
  • the overall DC power consumption is 21.5mW
  • the core power is only 2.5mW.
  • the tested input and output phase noise of the doubler is shown in Figure 18.
  • the frequency doubler is driven by a signal source with high spectral purity (Keysight PSG E8257D), the output phase noise is 6dB higher than the input phase noise (this is the theoretically expected minimum value of frequency multiplied by 2), and the test frequency offset ranges from 100Hz to 200MHz .
  • P out, 2nd (mW) represents the power of the output signal
  • P in, 1st (mW) represents the power of the input signal
  • P dc (mW) represents the power consumption of the driving voltage source.
  • Table 1 lists the performance data and performance comparison of frequency multipliers. It can be seen from Table 1 that the core module of the frequency multiplier provided by the present invention shows a good conversion gain of -0.1dB at 0-dBm input, its core power consumption is only 2.5mW, and the corresponding efficiency can reach 27.9%. In addition, the 0.012 core area makes the multiplier easy to integrate into modern transceiver systems. Even considering the output driver, the efficiency of this multiplier is still higher than other multipliers, and it achieves 0-dBm input. Up to 1.5dB maximum conversion gain.
  • the embodiment of the present invention utilizes the phase difference of the output signals in the basic NMOS and PMOS PP frequency multipliers, combined with the driving current multiplexing technology, increases the output power of the frequency multiplier and reduces DC power consumption, and improves the conversion gain of the frequency multiplier , and using the transformer to output balanced differential signals, it is easier to drive a high-performance mixer.
  • the frequency multiplier provided by the embodiment of the present invention only adds a small area of transistors, capacitors and Resistors, so there is almost no increase in chip area, and it can show great potential in the integration of high-performance transceiver systems.
  • the term “comprises” and any other variants thereof are non-exclusive, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also elements not expressly listed or not part of the process. , method, system, article or other element of a device.
  • the term “coupled” and any other variations thereof, as used herein refers to a physical connection, an electrical connection, a magnetic connection, an optical connection, a communicative connection, a functional connection, and/or any other connection.

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Abstract

一种基于互补晶体管的push-push二倍频器，包括第一差分放大电路(10)、第二差分放大电路(20)和输出负载电路(30)；第一差分放大电路(10)对差分输入信号的二次谐波的幅度进行放大，得到第一信号；第二差分放大电路(20)对差分输入信号的二次谐波的幅度进行放大，得到第二信号；其中，第一信号和第二信号为具有相同幅度、相位相差180°的一组差分信号；输出负载电路(30)分别提取第一信号和第二信号中的二次谐波信号，以得到具有第一输出频率的差分输出信号，输出具有第一输出频率的差分输出信号；其中，第一输出频率为初始频率的二倍；由此，实现了同一倍频器输出差分信号，且输出差分信号中的两路信号具有相同幅度，两路信号经过幅度叠加后可大大提升倍频器的转换增益。

Description

一种基于互补晶体管的push-push二倍频器 技术领域
本发明涉及射频技术领域，具体涉及一种基于互补晶体管的push-push二倍频器。
背景技术
在雷达通信中，实现毫米波频段的信号收发系统的一个主要挑战是：如何解决无源元件的性能会随着频率的增加而退化，其中，高质量本振(LO)的生成尤为重要。产生高频本振(LO)的一种解决方案是利用倍频器，将倍频器产生的信号作为本振，然而，传统结构的倍频器的转换增益较低，且单端输出难以驱动高性能混频器。
综上，丞需一种具有较高转换增益、且能够差分输出的倍频器。
发明内容
本发明公开了一种具有较高转换增益、且能够差分输出的基于互补晶体管的push-push二倍频器。
一种实施例中提供一种基于互补晶体管的push-push二倍频器，包括第一差分放大电路、第二差分放大电路和输出负载电路；
所述第一差分放大电路用于接收具有初始频率的差分输入信号，并对所述具有初始频率的差分输入信号的二次谐波的幅度进行放大，得到第一信号；
所述第二差分放大电路用于接收所述具有初始频率的差分输入信号，并对所述具有初始频率的差分输入信号的二次谐波的幅度进行放大，得到第二信号；其中，所述第一信号和第二信号为具有相同幅度、相位相差180°的一组差分信号；
所述输出负载电路用于分别提取所述第一信号和第二信号中的二次谐波信号，以得到具有第一输出频率的差分输出信号，输出所述具有第一输出频率的差分输出信号；其中，所述第一输出频率为所述初始频率的二倍。
在一实施例中，还包括电压提供端VDD，所述第一差分放大电路和第二差分放大电路均包括多个晶体管；
所述电压提供端VDD用于给第一差分放大电路和第二差分放大电路中的多个晶体管提供驱动电流。
在一实施例中，所述第一差分放大电路中多个晶体管的类型相同；所述第二差分放大电路中多个晶体管的类型相同；所述第一差分放大电路中多个晶体管的类型与第二差分放大电路中多个晶体管的类型不同。
在一实施例中，所述第一差分放大电路包括晶体管MN1、晶体管MN2、电容CN1、电容CN2、电阻RN1和电阻RN2；
所述晶体管MN1的控制极通过电阻RN1接收信号VBN，晶体管MN1 的第二极接地，晶体管MN1的第一极与晶体管M2的第一极连接，晶体管MN1的控制极还与电容CN1的一端连接，电容CN1的另一端用于接收具有初始频率的差分输入信号中的一路信号；所述晶体管M2的控制极通过电阻RN2接收信号VBN，晶体管M2的第二极接地，所述晶体管M2的控制极还与电容CN2的一端连接，电容CN2的另一端用于接收具有初始频率的差分输入信号中的另一路信号；晶体管MN1的第一极还与所述输出负载电路连接，其用于输出所述第一信号。
在一实施例中，所述晶体管MN1和晶体管MN2均为NMOS晶体管。
在一实施例中，所述第二差分放大电路包括晶体管MP1、晶体管MP2、电容CP1、电容CP2、电阻RP1和电阻RP2；
所述晶体管MP1的控制极通过电阻RP1接收信号VBP，晶体管MP1的第一极连接电压提供端VDD，晶体管MP1的第二极连接晶体管MP2的第二极，晶体管MP1的控制极还与电容CP1的一端连接，电容CP1的另一端用于接收具有初始频率的差分输入信号中的一路信号；所述晶体管MP2的控制极通过电阻RP2连接信号VBP，晶体管MP2的第一极连接晶体管MP1的第一极，晶体管MP2的第二极连接所述输出负载电路，其用于输出第二信号，晶体管MP2的控制极还与电容CP2的一端连接，电容CP2的另一端用于接收具有初始频率的差分输入信号中的另一路信号。
在一实施例中，所述晶体管MP1和晶体管MP2均为PMOS晶体管。
在一实施例中，所述第一输出频率为58-66.5GHz。
在一实施例中，所述晶体管MN1和晶体管MN2的宽度为16μm，长度为60nm；所述晶体管MP1和晶体管MP2的宽度为48μm，长度为60nm。
在一实施例中，所述输出负载电路包括电感L4，所述电感L4的一端用于接收所述第一信号，电感L4的另一端用于接收所述第二信号。
在一实施例中，所述输出负载电路包括变压器T2和共源放大器CS；
所述变压器T2用于对第一差分放大电路输出的第一信号和第二差分放大电路输出的第二信号进行平衡后分别输出至共源放大器CS；
所述共源放大器CS用于对变压器T2输出的相位平衡后的第一信号和第二信号进行放大后分别进行输出。
在一实施例中，所述共源放大器CS包括：晶体管MN3和晶体管MN4，晶体管MN3的控制极用于接收变压器T2输出的一路信号，晶体管MN3的控制极还通过电容CN3连接晶体管MN4的第一极，晶体管MN3的第二极接地；晶体管MN4的控制极用于接收变压器T2输出的另一信号，晶体管MN4的控制极还通过电容CN4连接晶体管MN3的第一极，晶体管MN3的第一极和晶体管MN4的第一极与电感L7的两端分别连接，电感L7的两端用于输出所述差分输出信号。
在一实施例中，还包括输入巴伦电路和输出巴伦电路；
所述输入巴伦电路用于将接收的单端输入信号转换为所述差分输入信号；
所述输出巴伦电路用于将所述输出负载电路输出的差分输出信号 转换为单端输出信号，并输出所述单端输出信号。
在一实施例中，所述输入巴伦电路包括变压器T1，变压器T1的初级线圈为电感L1，次级线圈为电感L2，所述电感L1和电感L2之间相耦合；所述电感L1的一端用于接收单端输入信号，电感L1的另一端接地；所述电感L2的两端分别用于输出差分输入信号中的两路信号。
在一实施例中，所述输出巴伦电路包括变压器T3，变压器T3的初级线圈为电感L5，次级线圈为电感L6，所述电感L5和电感L6之间相耦合；所述电感L5的两端与输出负载电路30连接，用于接收差分输出信号；所述电感L6的一端用于输出单端输出信号，电感L6的另一端接地。
依据上述实施例的基于互补晶体管的push-push二倍频器，第一差分放大电路接收具有初始频率的差分输入信号，并对差分输入信号的二次谐波的幅度进行放大，得到第一信号；第二差分放大电路接收具有初始频率的差分输入信号，并对差分输入信号的二次谐波的幅度进行放大，得到第二信号；其中，第一信号和第二信号为具有相同幅度、相位相差180°的一组差分信号；输出负载电路分别提取第一信号和第二信号中的二次谐波信号，以得到具有第一输出频率的差分输出信号，输出具有第一输出频率的差分输出信号；其中，第一输出频率为初始频率的二倍；由此，实现了同一倍频器输出差分信号，且输出差分信号中的两路信号具有相同幅度，两路信号经过幅度叠加后可大大提升倍频器的转换增益。
附图说明
图1为现有NMOS Push-Push倍频器的电路原理图；
图2为现有PMOS Push-Push倍频器的电路原理图；
图3为一种实施例的基于互补晶体管的push-push二倍频器的结构示意图；
图4为图3所示倍频器的电路原理图；
图5为一种实施例的输出负载模型示意图；
图6为另一种实施例的基于互补晶体管的push-push二倍频器的结构示意图；
图7为图6所示倍频器的电路原理图；
图8为一种实施例的共源放大器的电路原理图；
图9为电压器T3的版图示意图；
图10为倍频器偏置电压与输出功率关系的仿真示意图；
图11为不同晶体管的宽度对倍频器转换增益影响的仿真示意图；
图12为用于测试的倍频器芯片示意图；
图13为测试平台的结构示意图；
图14为不同输入功率下倍频器的基波抑制效果仿真示意图；
图15为倍频器的二次谐波转换增益与输出频率的仿真示意图；
图16为倍频器的输出信号的频谱仿真示意图；
图17为倍频器的二次谐波功率和直流功耗与输入功率关系的仿真 示意图；
图18为倍频器的输入相位噪声和输出相位噪声的仿真示意图。
具体实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。其中不同实施方式中类似元件采用了相关联的类似的元件标号。在以下的实施方式中，很多细节描述是为了使得本申请能被更好的理解。然而，本领域技术人员可以毫不费力的认识到，其中部分特征在不同情况下是可以省略的，或者可以由其他元件、材料、方法所替代。在某些情况下，本申请相关的一些操作并没有在说明书中显示或者描述，这是为了避免本申请的核心部分被过多的描述所淹没，而对于本领域技术人员而言，详细描述这些相关操作并不是必要的，他们根据说明书中的描述以及本领域的一般技术知识即可完整了解相关操作。
另外，说明书中所描述的特点、操作或者特征可以以任意适当的方式结合形成各种实施方式。同时，方法描述中的各步骤或者动作也可以按照本领域技术人员所能显而易见的方式进行顺序调换或调整。因此，说明书和附图中的各种顺序只是为了清楚描述某一个实施例，并不意味着是必须的顺序，除非另有说明其中某个顺序是必须遵循的。
本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接(联接)。
本发明实施例的电路中所涉及的晶体管，在没有特别限定的情况下，可以是任何结构的晶体管，比如双极型晶体管(BJT)或者场效应晶体管(FET)。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的栅极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极，在实际应用过程中，“发射极”和“集电极”可以依据信号流向而互换；当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极，在实际应用过程中，“源极”和“漏极”可以依据信号流向而互换。
下面为本发明实施例所涉及的文献：
文献1：一种60GHz CMOS前端接收器(B.Razavi，“A 60-GHz CMOS receiver front-end，”IEEE J.Solid-State Circuits，vol.41，no.1，pp.17-22，Jan.2006)；
文献2：一种用于硅片宽带通信的60GHz接收器和发射器芯片组(B.Floyd，S.Reynolds，U.Pfeiffer，T.Beukema，J.Grzyb，and C.Haymes，“A 60GHz receiver and transmitter chipset for broadband communications in silicon，”in IEEE Int.Solid-State Circuits Conf.Dig.Tech.Papers，Feb.2006，pp.184-185)；
文献3：一种具有集成基带电路的90nm CMOS低功耗60GHz收 发器(C.Marcu，D.Chowdhury，C.Thakkar，L.-K.Kong，M.Tabesh，J.-D.Park，Y.Wang，B.Afshar，A.Gupta，A.Arbabian，S.Gambini，R.Zamahi，A.M.Niknejad，and E.Alon，“A 90nm CMOS low-power 60GHz transceiver with integrated baseband circuitry，”in IEEE Int)；
文献4：一种65nm SOI CMOS中90GHz静态CML分频器的性能可变性分析技术(D.Lim，J.-O.Plouchart，C.Choongyeun，D.Kim，R.Trzcinski，and D.Boning，“Performance variability of a 90GHz static CML frequency divider in 65nm SOI CMOS”in IEEE Int.Solid-State Circuits Conf.Dig.Tech.Papers，Feb.2007，pp.542-543)；
文献5：一种LO本底噪声限制多千兆毫米波通信中的性能分析技术(J.Chen，Z.S.He，D.Kuylenstierna，T.Eriksson，M.H¨orberg，T.Emanuelsson，T.Swahn，and H.Zirath，“Does LO Noise Floor Limit Performance in Multi-Gigabit Millimeter-Wave Communication？”IEEE Microwave and Wireless Components Letters，vol.27，no.8，pp.769-771，Aug.2017)；
文献6：一种采用SiGe BiCMOS的36-80GHz高增益毫米波双平衡有源倍频器(A.Y.-K.Chen，Y.Baeyens，Y.-K.Chen，and J.Lin，“A 36-80GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS”IEEE Microwave and Wireless Components Letters，vol.19，no.9，pp.572-574，Sep.2009)；
文献7：一种60-80GHz倍频器的工作性能分析技术(G.Liu，A.C.Ulusoy，A.Trasser，and H.Schumacher，“60-80GHz Frequency Doubler Operating Close to fmax”in Proc.of Asia-Pacific Microwave Conference，Dec.2010，pp.770-773)；
文献8：一种基于0.13-_m SiGe技术的新型变压器巴伦以及具有35-dB基波抑制的K波段倍频器(S.Chakraborty，L.E.Milher，X.Zhu，L.T.Hall，O.Sevimli，and M.C.Heimlich，“A K-Band Frequency Doubler with 35-dB Fundamental Rejection Based on Novel Transformer Balun in 0.13-_m SiGe Technology，”IEEE Electron Device Letters，vol.37，no.11，pp.1375-1378，Nov.2016)；
文献9：一种用于μ-波和毫米波应用的注入锁定CMOS倍频器(E.Monaco，M.Pozzoni，F.Svelto and A.Mazzanti，″Injection-Locked CMOS Frequency Doublers for μ-Wave and mm-Wave Applicatiohs，″in IEEE Journal of Solid-State Circuits，vol.45，no.8，pp.1565-1574，Aug.2010)；
文献10：一种用于26.5-28.5GHz低功耗应用的超紧凑型SOI CMOS倍频器(F.Ellinger and H.Jackel，“Ultracompact SOI CMOS frequency doubler for low power applicatiohs at 26.5-28.5GHz，”IEEE Microwave and Wireless Components Letters，vol.14，no.2，pp.53-55，Feb 2004)；
文献11：一种130nm SiGe BiCMOS中60GHz全差分倍频器的分 析与设计(V.Rieβ，P.V.Testa，C.Carta，and F.Ellinger，“Analysis and Design of a 60GHz Fully-Differential Frequency Doubler in 130nm SiGe BiCMOS，”in 2018 IEEE International Symposium on Circuits and Systems (ISCAS)，May 2018，pp.1-5)；
文献12：一种100Gb/s超高速SiGe双极IC设计(M.Moller，“Challenges in the cell-based design of very-high-speed SiGe-bipolar ICs at 100Gb/s，”IEEE J.Solid-State Circuits，vol.43，no.9，pp.1877-1888，Sep.2008)；
文献13：一种平衡的K波段push-push倍频器(S.Vehring and G.Boeck，″Truly Balanced K-Band Push-Push Frequency Doubler，″2018 IEEE Radio Frequency Integrated Circuits Symposium(RFIC)，2018，pp.348-351)；
文献14：一种采用130nm SiGe BiCMOS技术的具有差分输出的60GHz倍频器(V.Rieβ，C.Carta and F.Ellinger，“A 60GHz Frequency Doubler with Differential Output in 130nm SiGe BiCMOS Technology，”2018 Asia-Pacific Microwave Conference(APMC)，2018，pp.279-281)；
文献15：一种适用于功率受限应用的高效138-170GHz SiGe HBT倍频器(C.Coen，S.Zeinolabedinzadeh，M.Kaynak，B.Tillack and J.D.Cressler，“A highly-efficient 138-170GHz SiGe HBT frequency doubler for power-constrained applications，”2016 IEEE Radio Frequency Integrated Circuits Symposium(RFIC)，2016，pp.23-26)；
文献16：一种使用具有16％PAE的电容交叉耦合中和的60GHz CMOS功率放大器(H.Asada，K.Matsushita，K.Bunsen，K.Okada and A.Matsuzawa，″A 60GHz CMOS power amplifier using capacitive cross-coupling neutralization with 16％PAE，″2011 6th European Microwave Integrated Circuit Conference，2011，pp.554-557)；
文献17：一种在22nm FD-SOI中设计超紧凑低功耗60GHz倍频器的技术(M.Cui，C.Carta and F.Ellinger，“Design of an Ultra Compact Low Power 60GHz Frequency Doubler in 22nm FD-SOI，”2020 IEEE International Symposium on Radio-Frequency Integration Technology(RFIT)，2020，pp.40-42)；
文献18：一种基于90nm CMOS的50-70GHz倍频器(J.Chen，P.Yan and W.Hong：“A 50-70GHz Frequency Doubler in 90nm CMOS”，IEEE MTT-S Int.Microw.Workshop Series on Millim.Wave Wirel.Tech.and Appl.(IMWS)，(2012))；
文献19：一种具有真正平衡差分输出的紧凑型V波段倍频器(S.Yuan and H.Schumacher，″Compact V band frequency doubler with true balanced differential output，″2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting(BCTM)，2013，pp.191-194)；
文献20：一种具有90nm CMOS谐波抑制功能的宽带倍频器(B.Y.Chen，Y.H.Hsiao and H.Wang，“A broadband doubler with harmonic rejection in 90nm CMOS，”2015 IEEE International Symposium on Radio-Frequency Integration Technology(RFIT)，Sendai，2015，pp.25-27)；
文献21：一种通过电流操作实现差分输出的非平衡变压器倍频器(C.Li and W.Wu，“A Balunless Frequency Multiplier with Differential Output by Current Flow Manipulation，”in IEEE Transactions on Very Large Scale Integration(VLSI)Systems，vol.26，no.7，pp.1391-1402，July 2018)。
发明人研究了这些文献，文献1-3提供了基于60GHz毫米波频段的CMOS收发机设计，然而设计该CMOS收发机的前提是需要生成高频的本振(LO)进行混频；文献4示出了采用高频的频率综合器产生高频本振(LO)，然而若要产生高频本振(LO)，压控振荡器(VCO)会消耗相当大的功率并表现出相对较差的频谱纯度、相位噪声和有限的调谐范围，并且锁相环(PLL)的预分频器需要大的输入电压摆幅，最终会使压控振荡器(VCO)本身消耗更多的功率；文献5-8示出了产生高频LO的另一种解决方案是利用倍频，尽管在N倍频之后信号的相位噪声会比输入信号的高出20log10N dB，但压控振荡器(VCO)谐振腔在较低频率下具有更高的品质因数，除此之外，用于低功耗收发器设计的VCO的功率要求也有所放宽相位噪声、调谐范围、功耗和电路复杂性之间依然会进行折衷与权衡，这取决于需要设计的系统的具体要求。文献9示出了倍频技术的综述，倍频器的电路结构分为四种，分别为：单级放大器结构的倍频器(文献10)、吉尔伯特单元的倍频器(文献6)、push-push(PP)结构的倍频器(文献8和11)和注入锁定倍频技术的倍频器(文献9)。其中，吉尔伯特单元的倍频器可以实现高转换增益和宽频带，但其功耗通常会很大，并容易受到直流偏移的影响。注入锁定倍频技术的倍频器能提高输出幅度和实现较低功耗，然而，一方面高频VCO的设计显得更加困难，另一方面如果不增加调谐技术，只注入锁定倍频技术会展现非常窄的带宽。Push-push结构的倍频器利用了器件非线性的特点，具有良好的基波抑制能力且易于实现，但传统结构的push-push结构的倍频器的转换增益较低且单端输出难以驱动高性能混频器。文献12示出了在高频下，差分信号的存在是非常有必要的，其可以避免在设计中对电流返回路径进行精确模拟。文献13-15示出了对push-push倍频器的一些性能上的改进，其中，文献13示出了基于电感的移相器和两个push-push倍频核心可以实现更大幅度的平衡式差分输出。然而该方法会使功耗翻倍并且移相器的占用面积非常大，难以应用于高集成系统。尽管文献14引入了基于硅的移相器来创建两个具有相反相位的差分输入和push-push两个倍频核心并减小了芯片面积，但该倍频器的工作效率仍然很低，并且差分输入信号会遭受移相器的插入损耗和相移误差。文献15示出了针对功率受限的应用，近年来出现了利用化合物半导体器件和载有输出放大器和的高效率倍频器，然而不平衡的输出、成本以及 系统集成仍然是一个问题。
请参考图1和图2，图1和图2分别为现有push-push结构的倍频器(以下简称PP倍频器)的结构示意图，其中，图1所示为NMOS PP倍频器，其包括两个相同的NMOS晶体管，图2所示为PMOS PP倍频器，其包括两个相同的PMOS晶体管。该PP倍频器将产生的电流推入电感负载，由于电感负载的的峰值阻抗设计在输入信号的二次谐波频率处，同时基波被电感负载的负载特性所抑制，因此PP倍频器的输出信号的频率为输入信号的频率的二倍。本实施例以NMOS PP倍频器为例进行说明，输入信号V inp表示为V inp＝V psin(ωt)。在晶体管M1的栅极处的差分输入信号可表示为V inp＝V psin(ωt)+V B1，V inn＝-V psin(ωt)+V B1。
若将NMOS PP倍频器视为一般的非线性系统，共模节点处的电流仅保留偶次谐波。对于PP倍频器中的每个NMOS晶体管，输出电流为
Figure PCTCN2021139748-appb-000001
其中，V B1为晶体管的偏置电压，V THN为晶体管的阈值电压，为了使晶体管输出电流的二次谐波最大化，偏置电压V B1应接近晶体管的阈值电压V THN。由于两个输入只有在半个周期内被转换为电流，则NMOS PP倍频器的输出电压
Figure PCTCN2021139748-appb-000002
其中R Ln表示NMOS PP倍频器中电感L1处的谐振负载电阻，k n表示NMOS晶体管的跨导。由此可见，NMOS PP倍频器的输出产生了二次谐波信号。
同理，在PMOS PP倍频器中，输出电压
Figure PCTCN2021139748-appb-000003
其中，R Lp是PMOS PP倍频器中电感L2处的谐振负载电阻，k p表示PMOS晶体管的跨导。
由于在相同输入信号下，NMOS PP倍频器和PMOS PP倍频器输出电压的相位差180°，且输出电压的幅度相同。基于NMOS PP倍频器和PMOS PP倍频器输出电压的特性，本发明实施例提供的倍频器将NMOS PP倍频器和PMOS PP倍频器结合在一起，增加了输出信号的幅度，提升了倍频器的转换增益，且能够输出差分信号，便于后期驱动高性能的混频器。
请参考图3，图3为本发明一种实施例的基于互补晶体管的push-push二倍频器的结构示意图，以下简称倍频器，倍频器可以包括：第一差分放大电路10、第二差分放大电路20和输出负载电路30，下面具体说明。
第一差分放大电路10用于接收具有初始频率的差分输入信号，并对具有初始频率的差分输入信号的二次谐波的幅度进行放大，得到第一信号。第一差分放大电路10具有两个输入端，差分输入信号为两路信号，该两路信号分别通过两个输入端输入至第一差分放大电路10中，第一差 分放大电路10通过内部参数的设置，使其对差分输入信号的二次谐波的幅度进行放大。
第二差分放大电路20用于接收具有初始频率的差分输入信号，并对具有初始频率的差分输入信号的二次谐波的幅度进行放大，得到第二信号。第二差分放大电路20的输入端与第一差分放大电路10的输入端连接，也就是，第二差分放大电路20与第一差分放大电路10具有相同的输入，并且，在输入端上第二差分放大电路20与第一差分放大电路10结构相同，其同样具有两个输入端，差分输入信号中的两路信号分别通过两个输入端输入至第二差分放大电路20中，第二差分放大电路20通过内部参数的设置，使其对差分输入信号的二次谐波的幅度进行放大。
在本实施例中，第一差分放大电路10输出的第一信号和第二差分放大电路20输出的第二信号具有相同的幅度，但第一信号和第二信号的相位相差180°，使得第一信号和第二信号组成一组差分信号。
输出负载电路30用于分别提取第一信号和第二信号中的二次谐波信号，以得到具有第一输出频率的差分输出信号，输出具有第一输出频率的差分输出信号，以使倍频器能够实现高频差分信号的输出。在本实施例中，输出负载电路30呈感性负载特性，其能够抑制第一信号和第二信号中的基波信号，并提取二次谐波信号，得到的第一输出信号和第二输出信号为一组具有第一输出频率的差分信号，且第一输出频率为初始频率的二倍，即输出负载电路30输出的差分输出信号的频率为初始频率的二倍，实现了倍频器的差分输出。并且，由于第一输出信号和第二输出信号的幅度均经过放大且相同，因此实现了倍频器较高的转换增益。
在一实施例中，第一差分放大电路10和第二差分放大电路20均为晶体管结构的电路，其包括多个晶体管，在本实施例中，第一差分放大电路10和第二差分放大电路20中的所有晶体管均通过一驱动电压源进行驱动，相比于现有的PP倍频器，无需增加新的驱动电压源，不会增加太多芯片面积，且功耗较低。本实施例中，通过调整晶体管的偏置电压的值，可实现对差分输入信号中的二次谐波信号的幅度进行放大，例如：调整晶体管的偏置电压使其等于或无限接近晶体管的阈值电压，晶体管的阈值电压为晶体管的开启电压，其根据晶体管的型号、类型不同而不同。
在一些实施例中，可以将本发明实施例提供的倍频器应用于基于毫米波频段的通信设备中，例如，毫米波频段的信号收发设备需要高频本振来进行混频，但压控振荡器输出信号的频率无法达到毫米波频段，因此需要倍频器将压控振荡器输出信号的频率进行倍频后作为高频本振，例如：本实施例提供的基于互补晶体管的倍频器经过二倍频后输出频率为58-66.5GHz的差分信号作为高频本振，可用于58-66.5GHz频段的信号收发设备中混频器的激发。
下面对倍频器中各个电路、模块进行详细说明。
请参考图4，第一差分放大电路10具有两个输入端，其分别用于接 收差分输入信号的两路信号V inn和V inp，第一差分放大电路10通过对其内部晶体管的偏置电压的调整，使晶体管均偏置在其阈值电压处，以最大化二次谐波的输出幅度。
一些实施例中，第一差分放大电路10包括晶体管MN1、晶体管MN2、电容CN1、电容CN2、电阻RN1和电阻RN2。
晶体管MN1的控制极通过电阻RN1接收信号VBN，晶体管MN1的第二极接地，晶体管MN1的第一极与晶体管M2的第一极连接，晶体管MN1的控制极还与电容CN1的一端连接，电容CN1的另一端用于接收具有初始频率的差分输入信号中的一路信号；晶体管M2的控制极通过电阻RN2接收信号VBN，晶体管M2的第二极接地，晶体管M2的控制极还与电容CN2的一端连接，电容CN2的另一端用于接收具有初始频率的差分输入信号中的另一路信号；晶体管MN1的第一极还与输出负载电路30连接，其用于输出第一信号至输出负载电路30。
其中，晶体管MN1和晶体管MN2为相同的两个NMOS晶体管，电容CN1和电容CN2具有相同的参数，电阻RN1和电阻RN2具有相同的参数。
本实施例中晶体管MN1和晶体管MN2的偏置电压由电压信号VBN提供，因此，可通过调整电压信号VBN的大小，对晶体管MN1和晶体管MN2的偏置电压进行调整，以使偏置电压与晶体管的阈值电压相同。
第二差分放大电路20与第一差分放大电路10相同，其具有两个输入端，其分别用于接收差分输入信号的两路信号V inn和V inp，第二差分放大电路20通过对其内部晶体管的偏置电压的调整，使晶体管均偏置在其阈值电压处，以最大化二次谐波的输出幅度。
在一些实施例中，第二差分放大电路包括晶体管MP1、晶体管MP2、电容CP1、电容CP2、电阻RP1和电阻RP2。
晶体管MP1的控制极通过电阻RP1接收信号VBP，晶体管MP1的第一极连接一电压提供端VDD，晶体管MP1的第二极连接晶体管MP2的第二极，晶体管MP1的控制极还与电容CP1的一端连接，电容CP1的另一端用于接收具有初始频率的差分输入信号中的一路信号；晶体管MP2的控制极通过电阻RP2连接信号VBP，晶体管MP2的第一极连接晶体管MP1的第一极，晶体管MP2的第二极连接所述输出负载电路30，其用于输出第二信号至输出负载电路30，晶体管MP2的控制极还与电容CP2的一端连接，电容CP2的另一端用于接收具有初始频率的差分输入信号中的另一路信号。
其中，晶体管MP1和晶体管MP2为相同的两个PMOS晶体管，电容CP1和电容CP2具有相同的参数，电阻RP1和电阻RP2具有相同的参数。
本实施例中晶体管MP1和晶体管MP2的偏置电压由电压信号VBP提供，因此，可通过调整电压信号VBP的大小，对晶体管MP1和晶体管MP2的偏置电压进行调整，以使偏置电压与晶体管的阈值电压相同。
第一差分放大电路10和第二差分放大电路20组成了倍频器的核心模块，从上述第一差分放大电路10和第二差分放大电路20的描述可知， 其驱动电流均通过相同的电压提供端VDD进行提供，由此，相比与现有的PP倍频器，本发明实施例提供的倍频器中的核心模块并没有额外增加新的驱动电压源，因此，倍频器的核心模块的芯片面积相比于现有PP倍频器的核心模块的芯片面积并没有增加太多，在实现差分输出的同时，保持了较小的芯片面积。
输出负载电路30用于提取第一差分放大电路10输出的第一信号和第二差分放大电路20输出的第二信号中的二次谐波信号，输出负载电路30呈感性负载特性，其可以抑制基波信号，获取二次谐波信号。
一些实施例中，输出负载电路30包括电感L4，电感L4连接于所述第一差分放大电路10和第二差分放大电路20之间，也即是，电感L4的两端分别为第一差分放大电路10和第二差分放大电路20的输出端。
本实施例可通过设置合适参数的电感L4，以使电感L4和晶体管中的寄生电容能够在二次谐波所在频率处发生谐振，以使电感L4能够提取二次谐波信号后进行输出，以使倍频器能够输出二倍频的差分输出信号。
下面对图4所示倍频器的输入信号和输出信号进行分析。
以一个信号周期为例进行分析，该信号周期包括两个时隙t1和t2。先假设晶体管MN1、晶体管MN2、晶体管MP1和晶体管MP2均偏置在其各自的阈值电压处，此时晶体管MN1、晶体管MN2、晶体管MP1和晶体管MP2最大化信号中二次谐波信号的幅度，差分输入信号为V inp和V inn。以第一放大电路10为例进行分析，在时隙t1中，V inp高于晶体管MN1、晶体管MN2的阈值电压V THN，而V inn低于V THN；在时隙t2中，V inn高于晶体管MN1、晶体管MN2的阈值电压V THN，而V inp低于V THN；在上述偏置策略下，V inp将在时隙t1中放大，V inn将在时隙t2中放大。因此，节点B的输出信号相位在时隙t1中与V inp相反，在时隙t2中节点B的信号相位与V inn相反。节点A的电压与节点B的原理类似，最终使倍频器形成差分输出信号V outp和V outn。本发明实施例通过使电感L4和寄生电容在相应频率范围内谐振，最终提取出二次谐波信号，与现有的PP倍频器相比，这种结构充分利用输入信号进行倍频转换，在直流电流和电源电压保持不变的情况下，不会增加核心芯片面积和功耗。此外，差分输出的建立有助于驱动高性能混频器。
下面基于倍频器的负载模型，对其输出的差分输出信号的幅度进行分析。
本实施例以第一差分放大电路10的输出端为例分析整个倍频器的输出负载模型，请参考图5，图5为一种实施例的输出负载模型的示意图，以小信号输入为例，从第一差分放大电路10输出端看到的输出负载模型的输出阻抗R pn可表示为：
Figure PCTCN2021139748-appb-000004
同理，从第二差分放大电路20输出端看到的输出负载模型的输出阻抗R pp可表示为：
Figure PCTCN2021139748-appb-000005
其中，s＝jω，r o1是晶体管MN1(晶体管MN2)的输出电阻，r o2是晶体管MP1(晶体管MP2)的输出电阻，C gd1是晶体管MN1(晶体管MN2)的寄生电容，C gd2是晶体管MP1(晶体管MP2)的寄生电容，L 4为电感L4的电感值。
从输出阻抗R pn和R nn可知，倍频器的谐振频率主要受电感L4和晶体管的寄生电容的影响，因此，基于晶体管寄生电容的大小，可设置合适的电感L4的电感值，使得电感L4与寄生电容在二次谐波频率处发生谐振，以放大二次谐波信号的幅度。
根据输出阻抗R pn和R pp，图4所示倍频器差分输出信号的幅度V pd可被表示为：
Figure PCTCN2021139748-appb-000006
其中，λ p是PMOS晶体管的沟道长度调制系数，λ n是NMOS晶体管的沟道长度调制系数，K p是PMOS晶体管的跨导，K n是NMOS晶体管的跨导，V dsp为PMOS晶体管的漏极电压，V dsn为NMOS晶体管的漏极电压，V DD为驱动电压，V p为差分输入信号的幅度。
另一些实施例中，输出负载电路30包括变压器T2和共源放大器CS。
变压器T2用于对第一差分放大电路10输出的第一信号和第二差分放大电路20输出的第二信号进行相位平衡后分别输出至共源放大器CS；共源放大器CS用于对变压器T2输出的相位平衡后的第一信号和第二信号进行放大后分别进行输出。
变压器T2的初级线圈为电感L4，次级线圈为电感L3，电感L4和电感L3相耦合，耦合系数为k2，电感L4连接于第一差分放大电路10和第二差分放大电路20之间，电感L3的一端连接共源放大器CS的正输入引脚，另一端连接共源放大器CS的负输入引脚。其中，电感L3除了两端外，还具有一个偏置端，用于接工作电压。
变压器T2的初级线圈呈感性负载，并通过次级线圈和初级线圈的耦合，可对不平衡的第一信号和第二信号进行平衡，再通过共源放大器CS进行幅度放大，以使输出的第一输出信号和第二输出信号具有较大的幅度，提升了倍频器整体的转换增益。
在一些应用环境中，倍频器的输入和输出需要单端信号，例如：在仿真时，为了方便输入信号以及采集输出信号，常常采用单针的接口进行单端信号的输入和输出，由此，在一些实施例中，请参考图6，本实 施例提供的基于互补晶体管的push-push二倍频器(简称倍频器)还包括：输入巴伦电路40和输出巴伦电路50。
输入巴伦电路40用于将接收的单端输入信号转换为差分输入信号。输入巴伦电路40包括一三端口器件，其能够将单端输入信号转换为差分输入信号。或者说，输入巴伦电路40包括一宽度射频传输线变压器，该变压器能够将单端输入信号转换为差分输入信号而实现平衡传输线电路与不平衡传输线电路之间的连接。
输出巴伦电路50用于将输出负载电路输出的差分输出信号转换为单端输出信号，并输出该单端输出信号。输出巴伦电路50与输入巴伦电路40在原理上类似，包括一宽度射频传输线变压器，该变压器能够将差分输出信号转换为单端输出信号。
请参考图7，在一实施例中，输入巴伦电路40包括变压器T1，变压器T1的初级线圈为电感L1，次级线圈为电感L2，电感L1和电感L2之间耦合，耦合系数为k1；电感L1的一端用于接收单端输入信号，电感L1的另一端接地，电感L2的两端分别用于输出差分输入信号中的两路信号。其中，电感L2除了两端外，还具有一个偏置端，用于接地。
输出巴伦电路50包括变压器T3，变压器T3的初级线圈为电感L5，次级线圈为电感L6，电感L5和电感L6之间耦合，耦合系数为k3；电感L5的两端与输出负载电路30连接，用于接收差分输出信号，电感L6的一端用于输出单端输出信号，电感L6的另一端接地。其中，电感L5除了两端外，还具有一个位置端，用于接工作电压。
请参考图8，图8示出了一种实施例的共源放大器CS的原理图，共源放大器CS包括晶体管MN3和晶体管MN4，晶体管MN3的控制极用于接收正输入信号V in+，晶体管MN3的控制极通过电容CN3连接晶体管MN4的第一极，晶体管MN3的第二极接地，晶体管MN4的控制极用于接收负输入信号V in-，晶体管MN4的控制极还通过电容CN4连接晶体管MN3的第一极，晶体管MN3的第一极和晶体管MN4的第一极与电感L7的两端分别连接，电感L7的两端分别用于输出V out+、V out-。其中，V in+为共源放大器CS正输入端接收的信号，V in-为共源放大器CS负输入端接收的信号，V out+、V out-为共源放大器CS的输出信号。
下面通过仿真实验对图7所示倍频器的效果进行验证。
使用HFSS软件在30GHz下进行仿真，其中变压器T1中电感L1的电感值为104pH，电感L2的电感值为297pH，耦合系数k 1为0.8；电阻RN1、电阻RN2、电阻RP1和电阻RP2的电阻值设计为7.9kΩ，以防止信号泄漏到偏置电源。电容CN1、电容CN2、电容CP1和电容CP2 为617fF的MoM电容。在0-dBm单端输入信号下，仿真得到的晶体管MP1(MP2)和晶体管MN1(MN2)的栅极电压振幅为310mV。为了将电感L4处的不平衡差分输出信号转换为平衡差分输出信号，变压器图用于核心倍频器的负载，变压器T2输出的平衡差分输出信号最终由共源放大器CS放大并通过变压器T3转成单端输出信号后输出。
在本发明实施例对倍频器的电路功耗、寄生效应和电流放大能力的综合考虑的前提下，晶体管MN1(MN2)的宽度选择为16μm，长度为60nm。如图9所示，图9是变压器T2的版图示意图，两圈电感L3和一圈电感L4的电感设计值在60GHz时分别为360pH和110pH，线宽设计为2.05μm以减少趋肤效应，线间距设计为2μm以实现紧耦合，仿真得到电感L3和电感L4的耦合系数k 2为0.85，工作电压选择为1V，其中M7、M8、M9表示金属线的层数，分别为第七层、第八层、第九层。
为了验证将晶体管的栅极偏置电压调整至阈值电压的偏置策略对倍频器产生最大的二倍频输出功率并借此找到晶体管MP1(MP2)和晶体管MN1(MN2)的最佳栅极偏置电压，优化过程可以先固定信号VBP来找到最优的信号VBN。找出最优信号VBN后，记为V BNOP，再通过设置VBN＝V BNOP来优化信号VBP。在图6中，假设设置晶体管MN1(MN2)的宽度W 1＝16μm和晶体管MP1(MP2)的宽度W 2＝48μm，管长均为60nm，图10中的(a)显示了在66GHz输出频率下VBP＝0.7V时，倍频器的仿真输出功率，图10中的(b)显示了在66GHz输出频率下VBN＝0.4V时，倍频器的仿真输出功率。其中晶体管MN1(MN2)和晶体管MP1(MP2)在室温下的平均阈值电压分别为0.38V和0.32V，从图8中的(a)可以观察到，在多个不同的输入功率下，在分别实行输出功率优化时，最大输出功率均在VBN＝0.42V和VBP＝0.65V附近达到，同时验证了将晶体管的栅极偏置电压调整至阈值电压的偏置策略的正确性。
基于上述偏置条件下，且已知以下条件：(1)晶体管MN1(MN2)和晶体管MP1(MP2)都处于饱和区，保证了良好的电流放大能力；(2)晶体管MN1(MN2)和晶体管MP1(MP2)均处于偏置电压等于阈值电压的偏置策略状态下并共享相同的偏置电流I D。如果同时也考虑沟道长度调制效应(系数分别为λ n和λ p)，则有：
Figure PCTCN2021139748-appb-000007
如果偏置电流较小且电感L的压降可以忽略，则此处有近似关系V dsp+V dsn＝V DD。在上述偏置策略状态下，上式中平方项近似相等，因此上式又可以改写成：
(1+λ pV dsp)K′ pW 2＝[1+λ n(V DD-V dsp)]K′ nW 1
由于K′ p、K′ n、λ n、λ p均为常数，如果我们指定W 1和V DD，那么V dsp和V dsn便由W 2决定。W 2的值也与倍频器的最佳转换增益相关，当W 2足够小时，偏置电流和V dsn会一起变小，假设L 4处差分输出电压V pd的幅值为A pd且晶体管MN1(MN2)在大信号输入下仍工作在饱和区(V dsn略大于V dsatn)，则差分输出信号的幅度A pd会被限制，使得：
A pd≤V dsn-V dsatn
当W 2过大，V dsn增加而V dsp减小，A pd的上限同样会被限制：
A pd≤V DD-V dsatp-V dsn
图11示出了在输出频率为66GHz下，不同晶体管MP1(MP2)的宽度W 2的值对仿真的转换增益的影响(仿真条件：0dBm输入，W 1＝16μm)。当W 2从8μm增加到32μm时，转换增益增加，但增益峰值频率降低。当W 2＝128μm时，第一差分放大电路的输出信号V outn和第二差分放大电路的输出信号V outp的仿真振幅分别为300mV和40mV。V outp的幅值小的原因主要是由于晶体管MP1(MP2)的输出电阻R pp比NMOS晶体管的输出电阻R pn小，导致并联的R pp小。另一方面，从R pn来看，电感L4(包括MP1(MP2)的输出电阻)的等效品质因数逐渐增加。因此，总谐振并联输出电阻R pn和V outn增加。进一步增加W 2的值，如196μm，将开始限制差分输出信号的幅度A pd的大小并引入较大的寄生参数。此外，对于固定的W 1和驱动电源电压，较大的W 2会导致更多的功耗。因此，在仿真设计中，为了给倍频器留下足够的寄生裕量，晶体管MP1(MP2)的宽度W 2的值设计为32μm，仿真得到的V dsn为0.48V。
以上为本发明一些实施例中倍频器的说明。
一些实施例中，本发明的倍频器可以采用65nm CMOS工艺制造，输入信号和输出信号均为单端信号，输入信号和输出信号通过两个GSG焊盘，测试芯片的裸片如图12所示，芯片总面积为0.43mm×0.08mm，芯片中核心模块的面积为0.15mm×0.08mm，芯片被粘在PCB上进行测试，输入信号和输出信号通过探针提供，驱动电源和偏置信号通过键合线提供，其中，核心模块包括第一差分放大电路和第二差分放大电路，驱动器包括输出负载电路和输出巴伦电路。图13示出了测试平台的搭建示意图，其中(a)的设置是用V-波段谐波混频器来测试倍频器的输出 功率，(b)的设置是用于测试基波的输出功率，并结合(a)中测得的数据来计算基波抑制(FR)的效果。根据测试用线缆的数据表，1-m 67GHz电缆的典型损耗在30GHz时为4dB，在60GHz时为6dB，而0.2-m110GHz电缆在60GHz时的损耗为1.5dB。因此，0-dBm的倍频器输入功率相当于对应信号发生器处产生的4-dBm信号。然而，当倍频器输入功率为等效的0-dBm时，在图10(b)的测试过程中，频谱分析仪仅显示了-60dBm的本底噪声。这表明来自输出驱动的基波功率小于-60dBm，并被淹没在分析仪的底噪下。因此，核心倍频器和带驱动器的倍频器的基波抑制结果由图14所示仿真结果提供，可以看出在33GHz输入时，核心倍频器和带驱动器的倍频器的仿真基波抑制分别优于43.6dBc和61dBc。
图15示出了在30GHz等效0dBm和-4dBm输入功率下测量的倍频器二次谐波转换增益与输出频率的关系。在30GHz，0-dBm输入下，倍频器输出功率为0dBm，转换增益为0dB(未考虑输出测试的线损)。在30GHz和-4-dBm输入下，倍频器输出功率为-5.7dBm，转换增益为-1.7dB。-3-dB带宽范围为58GHz到66.5GHz(13.7％)。图16示出了30GHz、0-dBm输入时倍频器60GHz输出的测量频谱。在30GHz输入下，图17示出了测得的倍频器输出二次谐波功率和直流功耗(包括驱动)与输入功率的关系。在1-V电源电压下，输入功率为0dBm时，整体DC功耗为21.5mW，核心功率仅为2.5mW。
倍频器经过测试得到的输入和输出相位噪声如图18所示。倍频器由高频谱纯度的信号源(Keysight PSG E8257D)驱动，输出相位噪声比输入相位噪声高6dB(这是频率乘以2的理论预期的最小值)，测试频率偏移范围从100Hz到200MHz。
本发明实施例提供的倍频器的性能与其它一些倍频器进行了比较。在指标中发明人还加入了功率效率η，计算方式由下式给出：
Figure PCTCN2021139748-appb-000008
其中，P out，2nd(mW)表示输出信号的功率，P in，1st(mW)表示输入信号的功率，P dc(mW)表示驱动电压源的功耗。
表1列出了倍频器的性能数据和性能对比。从表1可见，本发明实施提供的倍频器的核心模块在0-dBm输入表现出良好的-0.1dB的转换增益，其核心功耗仅为2.5mW，相应的效率可达27.9％。此外，0.012的核心面积使倍频器易于集成到现代的收发器系统中，既使考虑了输出驱动器，该倍频器的效率仍然高于其它倍频器，并且在0-dBm输入时实现了高达1.5dB的最大转换增益。
表1
Figure PCTCN2021139748-appb-000009
本发明实施例利用基本的NMOS和PMOS PP倍频器中输出信号的相位差，结合驱动电流复用技术，增加了倍频器的输出功率并减少直流功耗，提升了倍频器的转换增益，并且利用变压器输出平衡差分信号，更容易驱动高性能混频器，本发明实施例提供的倍频器相比于现有的PP倍频器，由于只增加了面积很小的晶体管、电容和电阻，因此几乎没有增加芯片面积，在高性能收发系统集成方面能展现巨大的潜力。
本文参照了各种示范实施例进行说明。然而，本领域的技术人员将认识到，在不脱离本文范围的情况下，可以对示范性实施例做出改变和修正。例如，各种操作步骤以及用于执行操作步骤的组件，可以根据特定的应用或考虑与系统的操作相关联的任何数量的成本函数以不同的方式实现(例如一个或多个步骤可以被删除、修改或结合到其他步骤中)。
虽然在各种实施例中已经示出了本文的原理，但是许多特别适用于特定环境和操作要求的结构、布置、比例、元件、材料和部件的修改可以在不脱离本披露的原则和范围内使用。以上修改和其他改变或修正将被包含在本文的范围之内。
前述具体说明已参照各种实施例进行了描述。然而，本领域技术人员将认识到，可以在不脱离本披露的范围的情况下进行各种修正和改变。因此，对于本披露的考虑将是说明性的而非限制性的意义上的，并且所有这些修改都将被包含在其范围内。同样，有关于各种实施例的优点、其他优点和问题的解决方案已如上所述。然而，益处、优点、问题的解决方案以及任何能产生这些的要素，或使其变得更明确的解决方案都不应被解释为关键的、必需的或必要的。本文中所用的术语“包括”和其任何其他变体，皆属于非排他性包含，这样包括要素列表的过程、方法、文章或设备不仅包括这些要素，还包括未明确列出的或不属于该过程、方法、系统、文章或设备的其他要素。此外，本文中所使用的术语“耦合”和其任何其他变体都是指物理连接、电连接、磁连接、光连接、通信连接、功能连接和/或任何其他连接。
具有本领域技术的人将认识到，在不脱离本发明的基本原理的情况下，可以对上述实施例的细节进行许多改变。
具有本领域技术的人将认识到，在不脱离本发明的基本原理的情况下，可以对上述实施例的细节进行许多改变。因此，本发明的范围应根据以下权利要求确定。

Claims (15)

  1. 一种基于互补晶体管的push-push二倍频器，其特征在于，包括第一差分放大电路、第二差分放大电路和输出负载电路；
    所述第一差分放大电路用于接收具有初始频率的差分输入信号，并对所述具有初始频率的差分输入信号的二次谐波的幅度进行放大，得到第一信号；
    所述第二差分放大电路用于接收所述具有初始频率的差分输入信号，并对所述具有初始频率的差分输入信号的二次谐波的幅度进行放大，得到第二信号；其中，所述第一信号和第二信号为具有相同幅度、相位相差180°的一组差分信号；
    所述输出负载电路用于分别提取所述第一信号和第二信号中的二次谐波信号，以得到具有第一输出频率的差分输出信号，输出所述具有第一输出频率的差分输出信号；其中，所述第一输出频率为所述初始频率的二倍。
  2. 如权利要求1所述的push-push二倍频器，其特征在于，还包括电压提供端VDD，所述第一差分放大电路和第二差分放大电路均包括多个晶体管；
    所述电压提供端VDD用于给第一差分放大电路和第二差分放大电路中的多个晶体管提供驱动电流。
  3. 如权利要求2所述的push-push二倍频器，其特征在于，所述第一差分放大电路中多个晶体管的类型相同；所述第二差分放大电路中多个晶体管的类型相同；所述第一差分放大电路中多个晶体管的类型与第二差分放大电路中多个晶体管的类型不同。
  4. 如权利要求2所述的push-push二倍频器，其特征在于，所述第一差分放大电路包括晶体管MN1、晶体管MN2、电容CN1、电容CN2、电阻RN1和电阻RN2；
    所述晶体管MN1的控制极通过电阻RN1接收信号VBN，晶体管MN1的第二极接地，晶体管MN1的第一极与晶体管M2的第一极连接，晶体管MN1的控制极还与电容CN1的一端连接，电容CN1的另一端用于接收具有初始频率的差分输入信号中的一路信号；所述晶体管M2的控制极通过电阻RN2接收信号VBN，晶体管M2的第二极接地，所述晶体管M2的控制极还与电容CN2的一端连接，电容CN2的另一端用于接收具有初始频率的差分输入信号中的另一路信号；晶体管MN1的第一极还与所述输出负载电路连接，其用于输出所述第一信号。
  5. 如权利要求4所述的push-push二倍频器，其特征在于，所述晶体管MN1和晶体管MN2均为NMOS晶体管。
  6. 如权利要求4所述的push-push二倍频器，其特征在于，所述第二差分放大电路包括晶体管MP1、晶体管MP2、电容CP1、电容CP2、电阻RP1和电阻RP2；
    所述晶体管MP1的控制极通过电阻RP1接收信号VBP，晶体管MP1的第一极连接电压提供端VDD，晶体管MP1的第二极连接晶体管MP2的第二极，晶体管MP1的控制极还与电容CP1的一端连接，电容CP1的另一端用于接收具有初始频率的差分输入信号中的一路信号；所述晶体管MP2的控制极通过电阻RP2连接信号VBP，晶体管MP2的第一极连接晶体管MP1的第一极，晶体管MP2的第二极连接所述输出负载电路，其用于输出第二信号，晶体管MP2的控制极还与电容CP2的一端连接，电容CP2的另一端用于接收具有初始频率的差分输入信号中的另一路信号。
  7. 如权利要求6所述的push-push二倍频器，其特征在于，所述晶体管MP1和晶体管MP2均为PM0S晶体管。
  8. 如权利要求6所述的push-push二倍频器，其特征在于，所述第一输出频率为58-66.5GHz。
  9. 如权利要求8所述的倍频器，其特征在于，所述晶体管MN1和晶体管MN2的宽度为16μm，长度为60nm；所述晶体管MP1和晶体管MP2的宽度为48μm，长度为60nm。
  10. 如权利要求1所述的push-push二倍频器，其特征在于，所述输出负载电路包括电感L4，所述电感L4的一端用于接收所述第一信号，电感L4的另一端用于接收所述第二信号。
  11. 如权利要求1所述的push-push二倍频器，其特征在于，所述输出负载电路包括变压器T2和共源放大器CS；
    所述变压器T2用于对第一差分放大电路输出的第一信号和第二差分放大电路输出的第二信号进行平衡后分别输出至共源放大器CS；
    所述共源放大器CS用于对变压器T2输出的相位平衡后的第一信号和第二信号进行放大后分别进行输出。
  12. 如权利要求11所述的push-push二倍频器，其特征在于，所述共源放大器CS包括：晶体管MN3和晶体管MN4，晶体管MN3的控制极用于接收变压器T2输出的一路信号，晶体管MN3的控制极还通过电容CN3连接晶体管MN4的第一极，晶体管MN3的第二极接地；晶体管MN4的控制极用于接收变压器T2输出的另一信号，晶体管MN4的控制极还通过电容CN4连接晶体管MN3的第一极，晶体管MN3的第一极和晶体管MN4的第一极与电感L7的两端分别连接，电感L7的两端用于输出所述差分输出信号。
  13. 如权利要求1所述的push-push二倍频器，其特征在于，还包括输入巴伦电路和输出巴伦电路；
    所述输入巴伦电路用于将接收的单端输入信号转换为所述差分输入信号；
    所述输出巴伦电路用于将所述输出负载电路输出的差分输出信号转换为单端输出信号，并输出所述单端输出信号。
  14. 如权利要求13所述的push-push二倍频器，其特征在于，所述输入巴伦电路包括变压器T1，变压器T1的初级线圈为电感L1，次级 线圈为电感L2，所述电感L1和电感L2之间相耦合；所述电感L1的一端用于接收单端输入信号，电感L1的另一端接地；所述电感L2的两端分别用于输出差分输入信号中的两路信号。
  15. 如权利要求13所述的push-push二倍频器，其特征在于，所述输出巴伦电路包括变压器T3，变压器T3的初级线圈为电感L5，次级线圈为电感L6，所述电感L5和电感L6之间相耦合；所述电感L5的两端与输出负载电路30连接，用于接收差分输出信号；所述电感L6的一端用于输出单端输出信号，电感L6的另一端接地。
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