WO2023109645A1 - 光互连装置及其制造方法、计算装置 - Google Patents

光互连装置及其制造方法、计算装置 Download PDF

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Publication number
WO2023109645A1
WO2023109645A1 PCT/CN2022/137593 CN2022137593W WO2023109645A1 WO 2023109645 A1 WO2023109645 A1 WO 2023109645A1 CN 2022137593 W CN2022137593 W CN 2022137593W WO 2023109645 A1 WO2023109645 A1 WO 2023109645A1
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Prior art keywords
optical
electronic chip
conversion unit
analog
chip
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PCT/CN2022/137593
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English (en)
French (fr)
Inventor
徐叶龙
孟怀宇
沈亦晨
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上海曦智科技有限公司
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Publication of WO2023109645A1 publication Critical patent/WO2023109645A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements

Definitions

  • the present application relates to the field of chip technology, and more specifically, to an optical interconnection device, a manufacturing method thereof, and a computing device.
  • VLSI technology has become a pillar supporting the development and evolution of an information society. All kinds of chips widely used in information systems usually rely on the upgrading of the process of electronic chips to achieve performance improvement and power consumption optimization.
  • the development of digital electronic chips pursues more advanced manufacturing processes, emphasizing the ratio of computing speed to cost.
  • the analog electronic chip emphasizes high signal-to-noise ratio, low distortion, low power consumption, high reliability and stability, and the shrinkage of the manufacturing process may lead to a decrease in the performance of the analog circuit.
  • the development cycle of analog electronic chips is generally longer than that of digital electronic chips. In the same more advanced process, optimizing digital and analog circuits at the same time will limit product iteration cycles and waste R&D and production costs.
  • the embodiment of the present application provides an optical interconnection device, its manufacturing method, and a computing device, which can not only solve the problem of optimizing the respective performances of digital electronic chips and analog electronic chips in different processes, but also solve the problem of slow iteration cycle of analog electronic chip products.
  • Problem, using optical interconnection instead of electrical interconnection, optical interconnection has large bandwidth, low delay, low power consumption, high integration density and strong anti-electromagnetic interference ability.
  • an embodiment of the present application provides an optical interconnection device, the optical interconnection device includes: a plurality of digital electronic chips, including a first digital electronic chip and a second digital electronic chip; a plurality of analog electronic chips, It includes a first analog electrical chip and a second analog electrical chip; and an optical interconnect including a photonic integrated circuit including a plurality of optical waveguides; wherein the first digital electrical chip is connected to the second digital electrical chip.
  • An analog electronic chip is communicatively connected, the second digital electronic chip is communicatively connected to the second analog electronic chip, and the first analog electronic chip and the second analog electronic chip are communicatively connected through the optical interconnect ;
  • the information transmission path from the first digital electronic chip to the second digital electronic chip includes information successively passing through the first digital electronic chip, the first analog electronic chip, and the optical interconnection waveguide, the second analog electrical chip, and the second digital electrical chip.
  • the optical interconnection device further includes a carrier substrate; the optical interconnection is arranged on the carrier substrate; the plurality of analog electronic chips are arranged on the optical interconnection, the A plurality of digital electronic chips are disposed around the optical interconnect.
  • the plurality of digital electrical chips are closer to the carrier substrate than the plurality of analog electrical chips.
  • the electrical connection path from the first digital electronic chip to the first analog electronic chip passes through the conductive wiring structure of the carrier substrate and the conductive wiring structure in the optical interconnect successively.
  • the photonic integrated circuit of the optical interconnect further includes: a first electrical-to-optical conversion unit, which is electrically connected to the first analog electronic chip, and is used to connect the analog electrical chip of the first analog electronic chip to The information carried by the signal is carried in the first optical signal, and the first optical signal is transmitted in the optical waveguide of the optical interconnect; the first photoelectric conversion unit, which is electrically connected with the second analog electrical chip, uses for converting the received first optical signal into an analog electrical signal transmitted to the second analog electrical chip.
  • the photonic integrated circuit of the optical interconnect further includes: a second electro-optical conversion unit, which is electrically connected to the second analog electronic chip, and is used to convert the analog of the second analog electronic chip to the information carried by the electrical signal is carried into the second optical signal, and the second optical signal is transmitted in the optical waveguide of the optical interconnection; the second photoelectric conversion unit is electrically connected to the first analog electrical chip, It is used for converting the received second optical signal into an analog electrical signal transmitted to the first analog electrical chip.
  • a second electro-optical conversion unit which is electrically connected to the second analog electronic chip, and is used to convert the analog of the second analog electronic chip to the information carried by the electrical signal is carried into the second optical signal, and the second optical signal is transmitted in the optical waveguide of the optical interconnection
  • the second photoelectric conversion unit is electrically connected to the first analog electrical chip, It is used for converting the received second optical signal into an analog electrical signal transmitted to the first analog electrical chip.
  • the first electro-optical conversion unit and the second electro-optic conversion unit each include a plurality of modulators, which are used to modulate the information carried by the electrical signal onto optical signals of different wavelengths and perform wavelength division multiplexing
  • the first photoelectric conversion unit and the second photoelectric conversion unit each include a plurality of photodetectors, which perform wave division multiplexing on the received optical signal and convert it into an electrical signal.
  • the modulator comprises a microring modulator; and/or the detector comprises a microring filtered detector.
  • the photonic integrated circuit of the optical interconnect further includes: a dielectric layer, a plurality of conductive wiring units; the dielectric layer covers the plurality of optical waveguides, the first electro-optic conversion unit, The first photoelectric conversion unit, the second electro-optical conversion unit, the second photoelectric conversion unit; the plurality of conductive wiring units configured to connect the first photoelectric conversion unit, the first photoelectric conversion unit , the second electro-optical conversion unit, the second photoelectric conversion unit is electrically connected to the corresponding analog electrical chip; the plurality of conductive wiring units include a plurality of electrical connection structures, each of the plurality of electrical connection structures One each passes through at least part of the dielectric layer.
  • the plurality of electrical chips includes one or more chiplets.
  • the first digital electronic chip and the second digital electronic chip further include ultra-short-range serial-parallel interfaces for communicating with the first analog electronic chip and the second analog electronic chip respectively.
  • a computing device that includes an optical interconnect.
  • a method for manufacturing an optical interconnection device including: providing a wafer; forming a plurality of photonic integrated circuits on the wafer; wherein each of the plurality of photonic integrated circuits Including a plurality of optical waveguides, electro-optical conversion units, and photoelectric conversion units; installing at least one analog electrical chip required on each of the plurality of photonic integrated circuits; dividing the wafer to obtain a plurality of independent an optical interconnect; installing the optical interconnect on a carrier substrate; installing a digital electronic chip on the carrier substrate.
  • the optical interconnection device, its manufacturing method, and computing device of the embodiments of the present invention use chiplet technology, which can break through the physical bottleneck of the chip area, and is an important way to realize higher performance chips. As the area of each die becomes smaller, the number of dies that can be placed on a single wafer increases, which can improve yield and reduce cost.
  • the present invention can flexibly only upgrade some modules when improving the system performance, so the iterative cycle of system upgrading can be accelerated.
  • a series of analog electronic chips are integrated on the optical interconnect, and the analog electronic chips and a series of digital electronic chips around the optical interconnect are connected through ultra-short-distance serial-to-parallel conversion interfaces.
  • Load the information on different analog electronic chips on the optical signal and then let the optical signal shuttle through the optical interconnect at high speed to complete the information interconnection between different analog electronic chips, and then use the ultra-short-distance serial connection on the digital electronic chip
  • the conversion interface converts high-speed analog electrical signals into low-speed parallel signals processed by digital chips, so that digital electrical chips form an organic whole through photoelectric interconnection.
  • optical interconnection Compared with electrical interconnection, optical interconnection has large bandwidth, low delay, low power consumption, high integration density and strong anti-electromagnetic interference ability. Moreover, the on-chip or inter-chip optical interconnection transmission information is not sensitive to distance, allowing more data to be transmitted over longer distances, making the design of computer architecture more flexible.
  • the modulator array adopts a high-efficiency and small-area microring modulator array
  • the detector array adopts a microring filter detector with wave division multiplexing function.
  • optical interconnection device can integrate more computing units and storage units, and the use of optical interconnection can ensure organic information interconnection between them, thereby providing a higher system energy efficiency ratio.
  • FIG. 1 is a schematic top view of an optical interconnection device according to an exemplary embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an optical waveguide arrangement, an electro-optical conversion unit, and a photoelectric conversion unit arrangement of an optical interconnection in an optical interconnection device according to an exemplary embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view of an optical interconnection device
  • FIG. 4 is a schematic structural diagram of an electro-optical conversion unit including multiple modulators in an embodiment of the present invention
  • Fig. 5 is a schematic structural diagram of a photoelectric conversion unit including multiple detectors in an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view of a related structure when manufacturing a photonic integrated circuit according to an embodiment of the present application.
  • FIG. 7 is a schematic cross-sectional view of a related structure when manufacturing a photonic integrated circuit according to an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of a related structure when manufacturing a photonic integrated circuit according to an embodiment of the present application.
  • connection herein includes any direct and indirect means of connection. Therefore, if it is described herein that a first device is connected to a second device, it means that the first device may be directly connected to the second device, or indirectly connected to the second device through other devices.
  • first and second in this article are used to distinguish different devices, modules, structures, etc., and do not represent a sequence, nor do they limit that "first” and “second” are different types.
  • some processes described in the specification, claims, and the above-mentioned drawings of the present application contain multiple operations that appear in a specific order, and these operations may not be performed in the order in which they appear herein or performed in parallel. .
  • the serial numbers of the operations, such as 101, 102, etc. are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. Additionally, these processes can include more or fewer operations, and these operations can be performed sequentially or in parallel.
  • the optical interconnection device includes a plurality of digital electrical chips, a plurality of analog electrical chips and an optical interconnection.
  • the optical interconnection can realize the conversion of electrical signals and optical signals, as well as the information transmission of optical signals.
  • the plurality of digital electronic chips includes a first digital electronic chip and a second digital electronic chip, and among the plurality of analog electronic chips, the one that is respectively communicatively connected with the first digital electronic chip and the second digital electronic chip is called the first analog electronic chip and a second analog electrical chip.
  • “First” and “second” in this article are intended to distinguish different objects, rather than to sort objects and limit the number of objects.
  • the optical interconnection has a plurality of optical waveguides, for example, can be realized by using an optical interconnection.
  • the first digital electronic chip is communicatively connected to the first analog electronic chip
  • the second digital electronic chip is communicatively connected to the second analog electronic chip
  • the first analog electronic chip is connected to the second analog electronic chip.
  • the chip realizes the communication connection through the optical interconnection. That is to say, the information transmission path from the first digital electronic chip to the second digital electronic chip includes information successively passing through the first digital electronic chip, the first analog electronic chip, and the optical interconnection.
  • the optical waveguide, the second analog electrical chip, and the second digital electrical chip can realize information exchange, that is, a communication connection, through an analog electronic chip or an optical interconnect.
  • the optical interconnection device further includes a carrier substrate, and the optical interconnection is disposed on the carrier substrate.
  • the plurality of analog electrical chips are disposed on the optical interconnect, and the plurality of digital electrical chips are disposed around the optical interconnect.
  • the electrical connection path from the digital electronic chip to the analog electronic chip includes successively passing through the conductive wiring structure of the digital electronic chip, the conductive wiring structure of the carrier substrate, and the conductive wiring structure in the optical interconnection (for example, a conductive structure in a hole), and the electrical conduction path of the conductive wiring structure of the simulated electronic chip.
  • the ultra-short-range serial-parallel interface can be used for communication between digital electronic chips and analog electronic chips.
  • the optical interconnection device further includes a laser module, which generates optical signals.
  • the optical interconnection includes an optical coupling structure, which couples an optical signal of an external light source (including an optical fiber) into the optical interconnection device optical interconnection.
  • the optical coupling structure includes, for example, a grating coupler or an end face coupler.
  • the optical interconnect includes an electrical-to-optical conversion unit coupled to the first analog electrical chip for carrying the information carried by the analog electrical signal of the first analog electrical chip to the In the optical signal; the optical interconnect further includes a photoelectric conversion unit, which is coupled to the second analog electrical chip, and is used to convert the received optical signal into a signal to be transmitted to the second analog electrical chip analog electrical signal.
  • both the electro-optical conversion unit and the photoelectric conversion unit are integrated in a region of the optical interconnect corresponding to the analog electrical chip. In some embodiments, the electro-optical conversion unit and the photoelectric conversion unit are integrated under the corresponding analog electronic chip.
  • the digital electronic signal carrying the information sent by the first digital electronic chip can be converted into a high-speed serial electronic signal through the ultra-short-distance serial-parallel interface and transmitted to the first analog electronic chip, and the information carried by the analog electrical signal of the analog electronic chip is carried into the optical signal through the electro-optic conversion unit, and the optical signal is transmitted to the second analog electronic chip through the optical waveguide of the optical interconnection.
  • the photoelectric conversion unit under the chip, and the photoelectric conversion unit converts the optical signal into an analog electrical signal, that is, a high-speed serial electrical signal.
  • the second analog electrical chip sends the high-speed serial electrical signal to the second digital electrical signal.
  • the ultra-short-distance serial-parallel interface on the chip converts the high-speed serial electrical signal into a low-speed parallel signal carrying the information, that is, a digital electrical signal, and inputs it into the second digital electrical chip, Thus, the information transmission between the first digital electronic chip and the second digital electronic chip is completed.
  • the second digital electronic chip sends information to the first digital electronic chip, its transmission process is the same as that of sending information from the first digital electronic chip to the second digital electronic chip.
  • the electro-optic conversion unit includes a modulator array, which modulates the information carried by the analog electrical signal of the first analog electrical chip onto the optical signal of different wavelengths and performs wavelength division multiplexing. performing transmission; the photoelectric conversion unit includes a detector array, which performs wave division multiplexing on the received optical signal and converts it into an analog electrical signal for transmission to the second analog electrical chip.
  • the array of modulators includes a plurality of microring modulators.
  • the detector array includes a plurality of microring filtered detectors.
  • the number of chips used in the optical interconnection device is not particularly limited in the present invention, wherein the communication process between any two digital electronic chips is the same as that of the above-mentioned first digital electronic chip and second electronic digital chip.
  • the communication process of the chip is the same.
  • FIG. 1 is a schematic structural diagram of an optical interconnection device according to an exemplary embodiment of the present invention.
  • the optical interconnect device includes a carrier substrate 100, an optical interconnect 200, digital electronic chips A-D, and analog electronic chips a-d.
  • the optical interconnect 200 is disposed on the carrier substrate 100
  • the analog electronic chips a to d are disposed on the optical interconnect 200
  • the digital electronic chips A to D are disposed on the carrier substrate 100 and distributed around the optical interconnect 200 .
  • the digital electronic chip when the digital electronic chip is updated, it can be replaced conveniently and independently, while the optical interconnector and the analog electronic chip can be kept unchanged, and there is basically no need to modify other electrical wiring structures.
  • the optical interconnection includes a photonic integrated circuit
  • the photonic integration includes an optical waveguide unit, a plurality of electro-optic conversion units, and a plurality of photoelectric conversion units
  • the optical waveguide unit may include a plurality of optical waveguides.
  • the electro-optic conversion unit includes one or more optical modulators, and a plurality of modulators may constitute a modulator array.
  • the photoelectric conversion unit includes one or more photodetectors, and a plurality of photodetectors can form a detector array.
  • the modulator can modulate the initial light based on the electrical signal, so as to generate an optical signal carrying information, that is, carry the information carried by the electrical signal into the optical signal.
  • Optical interconnects have the function of converting electrical signals into optical signals, so that interconnection communication using light can be used instead of electrical signal communication.
  • FIG. 2 is a schematic diagram of the connection of an optical interconnection device according to an exemplary embodiment of the present invention, in which the electro-optical conversion unit and the photoelectric conversion unit formed in the region corresponding to the analog electronic chip in the optical interconnection are shown in perspective. conversion unit.
  • the connection and communication process between components in the optical interconnection device according to the embodiment of the present invention will be described below with reference to FIG. 2 .
  • the optical interconnect 200 includes a photonic integrated circuit including a plurality of optical waveguides, a plurality of electro-optical conversion units, and a plurality of photoelectric conversion units.
  • the electro-optic conversion unit includes one or more optical modulators, and a plurality of modulators may constitute a modulator array.
  • the photoelectric conversion unit includes one or more photodetectors, and a plurality of photodetectors can form a detector array.
  • the modulator can modulate the initial light based on the electrical signal, so as to generate an optical signal carrying information, that is, carry the information carried by the electrical signal into the optical signal.
  • Optical interconnects have the function of converting electrical signals into optical signals, so that interconnection communication using light can be used instead of electrical signal communication.
  • the installation areas a' ⁇ d' of the analog electrical chips in FIG. 2 correspond to the analog electrical chips a ⁇ d in FIG. .
  • a plurality of electro-optical conversion units and a plurality of photoelectric conversion units are provided in the optical interconnection 200.
  • the setting areas A' ⁇ D' of the digital electronic chips in Figure 2 correspond to the digital electronic chips A ⁇ D in Figure 1.
  • the digital electronic chips A ⁇ D are respectively equipped with ultra-short distance serial-to-parallel conversion interfaces, and the digital electronic chips A is communicatively connected with analog electronic chip a, digital electronic chip B is communicatively connected with analog electronic chip b, digital electronic chip C is communicatively connected with analog electronic chip c, and digital electronic chip D is communicatively connected with analog electronic chip d.
  • the electrical connection path from the digital electronic chip A to the analog electronic chip a includes successively passing through the conductive wiring structure (not shown) of the digital electronic chip A, the conductive wiring structure 301 of the carrier substrate 100, and the optical interconnection 200.
  • the conductive wiring structure in the middle, and the electrical conduction path of the conductive wiring structure (not shown) of the simulated electronic chip a may include a conductive through-silicon via 201 , and the conductive through-silicon via is arranged in the silicon substrate of the optical interconnection and penetrates through the silicon substrate.
  • the optical interconnect may also include other conductive structures in holes, and the conductive structures in holes pass through at least a part of the optical interconnect.
  • the electrical connection paths between other digital electronic chips and corresponding analog electronic chips are similar to the electrical connection paths from digital electronic chip A to analog electronic chip a.
  • the electrical connection path from the digital electronic chip A to the analog electronic chip a may also adopt other suitable connection methods in the field.
  • any digital electronic chip can communicate with any other digital electronic chip to form a point-to-point fully connected topological communication connection structure.
  • the laser module 300 outputs multiple wavelength lasers at the same time, and the optical signal is coupled into the optical interconnection 200 through the optical coupling structure in the optical interconnection, such as a grating coupler or an end coupler, and the beam splitting in the optical interconnection 200
  • the device evenly distributes the energy of the light to the corresponding electro-optical conversion units of different analog electronic chips in the optical interconnection 200 .
  • the beam splitter may be a broadband beam splitter.
  • the information transmission process from digital electronic chip A to other digital electronic chips B ⁇ D includes: the digital electronic signal of digital electronic chip A is converted via the ultra-short-distance serial-to-parallel conversion interface on digital electronic chip A It is a high-speed serial signal, and the high-speed serial signal is transmitted through the conductive wiring structure (such as metal wiring) on the carrier substrate 100 and the conductive wiring structure (such as conductive silicon via and/or other conductive lines) in the optical interconnection 200 After being processed by the analog electronic chip a, the electrical signal output by the analog electronic chip a is transmitted to the optical interconnection 200 and input to the electro-optic conversion unit in the optical interconnection 200 .
  • the conductive wiring structure such as metal wiring
  • the conductive wiring structure such as conductive silicon via and/or other conductive lines
  • the electro-optical conversion unit includes a plurality of modulators, which can constitute a modulator array, and the modulator array modulates light based on electrical signals, and loads the information carried by the electrical signals output by the analog electronic chip a on the optical signals of different wavelengths.
  • the signal is uplinked and wavelength-division multiplexed.
  • the optical waveguide passing through the optical interconnection 200 is transmitted into the photoelectric conversion unit.
  • the photoelectric conversion unit includes a plurality of photodetectors, which may form a detector array, and the detector array performs wave division multiplexing on the modulated optical signal, performs photoelectric conversion, and outputs it as an electrical signal.
  • the optical interconnect 200 outputs electrical signals carrying information to the analog electrical chips b to d for processing by the analog electrical chips.
  • the electrical signals output by the analog electronic chips b-d are transmitted to the corresponding digital electronic chips B-D.
  • the communication between the analog electronic chips b ⁇ d and the corresponding digital electronic chips B ⁇ D can be through an ultra-short-distance serial-to-parallel conversion interface.
  • the digital electronic chips A to D are closer to the carrier substrate than the analog electronic chips a to d, which shortens the connection distance between the digital electronic chips and the carrier substrate, and simplifies the packaging method.
  • the digital electronic chip is arranged around the optical interconnection, but not on the optical interconnection, and does not occupy the area of the optical interconnection.
  • the analog electrical chip is directly arranged on the optical interconnect, and the communication distance between it and the optical interconnect is optimized.
  • the digital electronic chips A-D and the analog electronic chips a-d are all chiplets.
  • the four digital electronic chips respectively go through digital-to-analog, electro-optical, photoelectric and analog-to-digital conversion through four analog electronic chips and optical interconnects to form a point-to-point full connection.
  • There is an independent data transmission channel between every two digital electronic chips so that there is no competition conflict between two digital electronic chips, the signal delay is low, and the information processing throughput is large.
  • the structure reuses four analog electrical chips and four digital electrical chips, which reduces the size of the electrical chips while improving the system energy efficiency ratio, thereby reducing chip design and processing costs, and effectively improving the yield rate of the chips.
  • one electro-optic conversion unit in the embodiment of the present invention includes a plurality of modulators, wherein the plurality of modulators form a modulator array.
  • the word modulator array only means Position arrangement, on the basis of meeting the functional requirements, the word array does not specifically limit the arrangement form and arrangement rules of each modulator, nor is it limited to a two-dimensional array.
  • the modulator array is composed of a series of microring modulators 401.
  • the microring modulators 401 can support high modulation rates based on the carrier depletion effect.
  • This type of waveguide structure is doped in different regions of the ridge waveguide , forming a horizontal or vertical PN junction structure 402 .
  • the PN junction works in the reverse bias mode.
  • the depletion region in the PN junction increases, the built-in electric field increases, there are no free carriers in the depletion region, and the corresponding refractive index of the ring waveguide 403 changes. , causing its resonance wavelength to shift, and the intensity of a specific wavelength near the resonance peak will change greatly, so as to achieve the purpose of intensity modulation.
  • the microring modulator has small size, low power consumption and high modulation efficiency.
  • the heating electrode 404 on the microring modulator can be adjusted to correspond to the carrier wave of a specific wavelength, and the modulated optical signals of different wavelengths propagate independently on the optical waveguide 407, realizing multiple Channel WDM signal transmission.
  • microrings may correspond to multiple different wavelengths. Because the microring modulator is sensitive to temperature, during the modulation process, the bias of the microring modulator can be adjusted by monitoring the photocurrent generated by the lateral or vertical PN junction itself for light absorption and using the feedback control on the analog circuit chip point so that the light modulation amplitude remains maximized.
  • a photoelectric conversion unit includes a plurality of detectors, wherein the plurality of detectors form a detector array.
  • the word detector array only means that it is arranged according to a certain position. On the basis of meeting the functional requirements, the word array does not specifically limit the arrangement form and arrangement rules of each detector, nor is it limited to a two-dimensional array.
  • the detector array is composed of a series of micro-ring filter detectors 501 , and the micro-ring filter detectors 501 include heating electrodes 502 , ring waveguides 503 , and signal light detectors 504 .
  • the heating electrode 502 on the microring filter detector 501 By adjusting the heating electrode 502 on the microring filter detector 501 to adjust the ring waveguide 503, the optical signal of a specific wavelength is filtered out from the optical waveguide 507, and downloaded to the signal optical detector 504 coupled with the electric chip to realize the optical signal to the Conversion of analog electrical signals.
  • multiple microrings may correspond to multiple different wavelengths.
  • the residual optical energy at the end of the waveguide is absorbed by the waveguide terminal 505 connected with the optical waveguide 507 and the signal light detector 504, so that it does not affect the signal transmission of other optical waveguides.
  • a large amount of information can be transmitted between analog electrical chips without being limited by power consumption and bandwidth density.
  • the position of the modulator array, the detector array and the position of the corresponding analog electronic chip in the optical interconnection can be arranged according to the needs, and multiple independent data transmission channels can be realized. Each channel is exclusively occupied by two digital chips communicating with each other. There is no competition conflict problem, the cross-sectional bandwidth is large, and the signal delay is low, which ultimately improves the information processing throughput.
  • the digital electronic chip may be one or more of CPU, GPU and memory chip.
  • An exemplary embodiment of the present invention provides a method for manufacturing an optical interconnection device, which can be used to manufacture the optical interconnection device in the foregoing embodiments.
  • the method includes:
  • each of the plurality of photonic integrated circuits may include a plurality of optical waveguides, an electro-optical conversion unit, and a photoelectric conversion unit, and the plurality of optical waveguides may be used to form an optical waveguide unit, that is, the optical waveguide unit includes a plurality of optical waveguides.
  • Each photonic integrated circuit in the plurality of photonic integrated circuits may further include a plurality of conductive wiring units, and the plurality of conductive wiring units may connect the electro-optic conversion unit and/or the photoelectric conversion unit to the corresponding analog electronic chip to receive signals from The electronic signal to be communicated is simulated and/or the electrical signal used for communication is sent to the simulated electronic chip.
  • the wafer is diced to form individual individual photonic integrated circuits that are used to form optical interconnects, That is, the optical interconnect includes the photonic integrated circuit.
  • the number of analog electrical chips can be one or more, for example, a first analog electrical chip and a second analog electrical chip are set so that the first analog electrical chip is electrically connected to the first conductive wiring unit, and the second analog electrical chip is electrically connected to the first conductive wiring unit.
  • the analog electronic chip is electrically connected to the second conductive wiring unit, and the first electro-optical conversion unit receives the first electrical signal of the first analog electronic chip through the first conductive wiring unit, and encodes and generates a first optical signal;
  • a photoelectric converter is used to convert the first optical signal into an electrical signal and transmit it to the second conductive wiring unit.
  • a single optical interconnection device includes a single photonic integrated circuit and the first analog electronic chip and the second analog electronic chip mounted (disposed) on the photonic integrated circuit.
  • the first analog electronic chip and the second analog electronic chip can pass through the first conductive wiring unit, the first electro-optical conversion unit, at least one of the plurality of optical waveguides, the first photoelectric conversion unit and the second conductive wiring unit to communicate.
  • An independent single optical interconnection device specifically includes one photonic integrated circuit.
  • the optical interconnection may be installed before the digital electronic chip is installed.
  • the optical interconnection may be installed after the digital electronic chip is installed, which is not particularly limited.
  • the wafer includes a semiconductor layer.
  • the above-mentioned wafer may be a semiconductor-on-insulator wafer, such as an SOI (Silicon-On-Insulator, silicon-on-insulator) wafer.
  • the semiconductor-on-insulator wafer may include: an insulating layer 602 , a semiconductor layer 603 formed on the insulating layer 602 , and a back substrate layer 601 located below the insulating layer 602 .
  • a photonic integrated circuit can be formed by performing processes such as patterning, deposition, and doping on the semiconductor layer 603.
  • the first analog electronic chip can be electrically connected to the first conductive wiring unit by bonding or welding, and the second analog electronic chip can be electrically connected to the second conductive wiring unit.
  • step S602 "forming a plurality of photonic integrated circuits on the wafer" can be specifically implemented by the following steps:
  • the first conductive wiring unit includes the first electrical connection structure; the second conductive wiring unit includes the second electrical connection structure.
  • the semiconductor layer 603 of the wafer can be patterned to obtain the corresponding regions of the optical waveguide unit 103 , the first electro-optical conversion unit 104 and the first photoelectric conversion unit 105 .
  • photolithography and etching techniques are used to remove unnecessary materials for patterning.
  • the above insulating layer may serve as an etch stop layer.
  • the electro-optic conversion unit includes one or more modulators, and a plurality of modulators may constitute a modulator array.
  • the photoelectric conversion unit includes one or more photodetectors, and a plurality of photodetectors can form a detector array. For simplicity, only one modulator and one detector are shown in FIG. 7 .
  • a dielectric layer 106 is deposited on the wafer on which the optical waveguide unit 103, the first electro-optical conversion unit 104 and the first photoelectric conversion unit 105 are formed, so as to cover all The optical waveguide unit 103, the first electro-optical conversion unit 104, the first photoelectric conversion unit 105 and the wafer.
  • the dielectric layer 106 is formed on the optical waveguide unit 103 , the first electro-optical conversion unit 104 , the first photoelectric conversion unit 105 , and the insulating layer 602 by deposition.
  • the material of the above-mentioned dielectric layer and the material of the insulating layer may be the same.
  • a first opening and a second opening are formed in the dielectric layer 106 .
  • the above-mentioned first opening and second opening may be formed by using an etching technique, and the number of the first opening and the second opening may be one or more according to connection requirements.
  • the dielectric layer 106 is a multi-layer structure formed by a plurality of sub-dielectric layers, multiple conductive layers may be formed in the dielectric layer, and the conductive layers are connected by conductive materials in the openings. For example, the first sub-dielectric layer is deposited first, then the first conductive layer is formed, then the second sub-dielectric layer is deposited, then the second conductive layer is formed, then the third sub-dielectric layer is formed, and the third conductive layer is formed. , and then form the fourth sub-dielectric layer. Wherein, in the first to third conductive layers, different conductive layers are interconnected through the conductive material in the opening, and each conductive layer may be a patterned metal material layer.
  • the first electrical connection structure 101a of the first conductive wiring unit 101 may be formed in the first opening and the second electrical connection structure 101a of the first conductive wiring unit 101 may be formed in the second opening by depositing a conductive material.
  • the second electrical connection structure 102 a of the conductive wiring unit 102 The first electrical connection structure 101 a passes through at least part of the dielectric layer 106 ; the second electrical connection structure 102 a passes through at least part of the dielectric layer 106 .
  • the excess conductive material can be removed along the mounting surface of the dielectric layer through a planarization process of chemical mechanical polishing or mechanical grinding, so that the first electrical connection structure 101a and the second electrical connection structure 102a are connected to the dielectric layer.
  • the mounting surface of layer 106 is flush.
  • first analog electronic chip and the second analog electronic chip on each photonic integrated circuit on the wafer, specifically, on the mounting surface of the dielectric layer 106/photonic integrated circuit corresponding to each photonic integrated circuit Install the first analog electronic chip and the second analog electronic chip in the area, that is, the area corresponding to each photonic integrated circuit on the mounting surface of the dielectric layer 106/photonic integrated circuit, the first analog electronic chip and the second analog electronic chip
  • the electrical chip is electrically connected to the first electrical connection structure and the second electrical connection structure in the area.
  • an encapsulant may also be formed on the dielectric layer 106 to bury or cover the first analog electrical chip and the second analog electrical chip. Afterwards, the encapsulant can be cured and can be planarized.
  • a process of thinning the back substrate layer 601 may be included.
  • S604 can be performed after S603, that is, before dividing the photonic integrated circuit wafer, the first analog electronic chip and the second analog electronic chip are installed in batches. The first analog electronic chip and the second analog electronic chip are packaged in batches. At this time, only the photonic integrated circuit wafer needs to be manufactured, and the photonic integrated circuit does not need to be formed into a single chip.
  • the optical interconnection when manufacturing photonic integrated circuits, it may also include manufacturing conductive wiring structures, which can be used to connect digital electronic chips and analog electronic chips, so that digital electronic chips and analog electronic chips can be realized.
  • the optical interconnection includes the above-mentioned conductive wiring structure.
  • the optical interconnection can serve as an intermediary layer.
  • the above-mentioned conductive wiring structure may include conductive through-silicon vias, and may also include other conductive lines.
  • the process of dividing the wafer can be carried out first, so as to form independent photonic integrated circuits/independent optical interconnects containing photonic integrated circuits, and then perform the first analog electronic chip and the second analog electronic chip
  • the installation process is to install the first analog electronic chip and the second analog electronic chip on the independent photonic integrated circuit.
  • multiple independent photonic integrated circuits can be packaged to a certain extent to form multiple independent photonic integrated circuit chips (including bare chips), and the photonic integrated circuit chips are used as optical interconnect chips, that is, optical interconnect
  • the components can use photonic integrated circuit chips.
  • the method includes:
  • each of the plurality of photonic integrated circuits includes a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, a first electro-optical conversion unit, and a first photoelectric conversion unit; the first electro-optical conversion unit and The first photoelectric conversion unit is respectively coupled to the optical waveguide unit; the first conductive wiring unit is electrically connected to the first electro-optical conversion unit; the second conductive wiring unit is electrically connected to the first photoelectric conversion unit connect.
  • the plurality of photonic integrated circuits are divided into independent photonic integrated circuits, so that each photonic integrated circuit chip includes an independent photonic integrated circuit.
  • S1004 may be performed after step S1003, but is not limited thereto.
  • the first analog electronic chip and the second analog electronic chip can pass through the first conductive wiring unit, the first electro-optical conversion unit, the optical waveguide unit, the first photoelectric conversion unit and the communicate with the second conductive wiring unit.
  • step S1002 For the specific implementation of the above step S1002, reference may be made to the corresponding content in the above embodiments, and details are not repeated here.

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Abstract

一种光互连装置及其制造方法、计算装置，该光互连装置包括:多个数字电芯片（A~D），包括第一数字电芯片和第二数字电芯片；多个模拟电芯片（a~d），包括第一模拟电芯片和第二模拟电芯片；光互连件（200）；第一数字电芯片与第一模拟电芯片通信连接，第二数字电芯片与第二模拟电芯片通信连接，第一模拟电芯片与第二模拟电芯片通过光互连件（200）实现通信连接;第一数字电芯片到第二数字电芯片的信息传输路径包括信息先后经过第一数字电芯片、第一模拟电芯片、光互连件（200）的光波导（507）、第二模拟电芯片、以及第二数字电芯片。光互连装置可以优化芯片之间的互连，并且针对不同类型的芯片进行单独升级或更换，优化了封装。

Description

光互连装置及其制造方法、计算装置
本申请要求于2021年12月14日提交中国专利局、申请号为202111527948.9、发明名称为“光互连装置及其制造方法、计算装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，更为具体而言，涉及一种光互连装置及其制造方法、计算装置。
背景技术
超大规模集成电路技术已经成为支撑信息化社会发展演进的支柱。在信息系统中广泛应用的各类芯片通常依赖于电芯片的工艺制程的升级以实现其性能提升和功耗优化。
数字电芯片的发展追逐更先进制程，强调的是运算速度与成本比。而模拟电芯片强调的是高信噪比、低失真、低耗电、高可靠性和稳定性，制程的缩小反而可能导致模拟电路性能的降低。而模拟电芯片研发周期普遍比数字电芯片长，在同一更先进制程，同时优化数字和模拟电路会限制产品迭代周期并且浪费研发和生产成本。
技术问题
本申请实施例提供一种光互连装置及其制造方法、计算装置，其不仅可以解决在不同工艺制程优化数字电芯片和模拟电芯片的各自性能，也解决了模拟电芯片产品迭代周期慢的问题，采用光互连代替电互连，光互连带宽大、时延低、功耗小、集成密度高和抗电磁干扰能力强。
技术解决方案
第一方面，本申请实施例提供一种光互连装置，所述光互连装置包括：多个数字电芯片，其包括第一数字电芯片和第二数字电芯片；多个模拟电芯片，其包括第一模拟电芯片和第二模拟电芯片；以及光互连件，其包括光子集成电 路，所述光子集成电路包括多个光波导；其中，所述第一数字电芯片与所述第一模拟电芯片通信连接，所述第二数字电芯片与所述第二模拟电芯片通信连接，所述第一模拟电芯片与所述第二模拟电芯片通过所述光互连件实现通信连接；其中，所述第一数字电芯片到所述第二数字电芯片的信息传输路径包括信息先后经过所述第一数字电芯片、所述第一模拟电芯片、所述光互连件的光波导、所述第二模拟电芯片、以及所述第二数字电芯片。
在一些实施方式中，所述光互连装置还包括承载基板；所述光互连件设置在所述承载基板上；所述多个模拟电芯片设置在所述光互连件上，所述多个数字电芯片设置在所述光互连件周围。
在一些实施方式中，所述多个数字电芯片相比所述多个模拟电芯片更接近于所述承载基板。
在一些实施方式中，所述第一数字电芯片到所述第一模拟电芯片的电连接路径先后经过所述承载基板的导电布线结构、所述光互连件中的导电布线结构。
在一些实施方式中，所述光互连件的光子集成电路还包括：第一电光转换单元，其与所述第一模拟电芯片电连接，用于将所述第一模拟电芯片的模拟电信号承载的信息承载到第一光信号中，所述第一光信号在所述光互连件的光波导中传输；第一光电转换单元，其与所述第二模拟电芯片电连接，用于将接收的第一光信号转换为传输至所述第二模拟电芯片的模拟电信号。
在一些实施方式中，，所述光互连件的光子集成电路还包括：第二电光转换单元，其与所述第二模拟电芯片电连接，用于将所述第二模拟电芯片的模拟电信号承载的信息承载到第二光信号中，所述第二光信号在所述光互连件的光波导中传输；第二光电转换单元，其与所述第一模拟电芯片电连接，用于将接收的第二光信号转换为传输至所述第一模拟电芯片的模拟电信号。
在一些实施方式中，所述第一电光转换单元、第二电光转换单元均各自包括多个调制器，用于将电信号承载的信息调制到不同波长的光信号上并以波分复用的方式进行传输；所述第一光电转换单元、第二光电转换单元均各自包括多个光电探测器，其对接收的所述光信号进行波分解复用并转化为电信号。
在一些实施方式中，所述调制器包括微环调制器；和/或所述探测器包括 微环滤波探测器。
在一些实施方式中，所述光互连件的光子集成电路还包括：介电层、多个导电布线单元；所述介电层覆盖所述多个光波导、所述第一电光转换单元、所述第一光电转换单元、所述第二电光转换单元、所述第二光电转换单元；所述多个导电布线单元被配置为将所述第一电光转换单元、所述第一光电转换单元、所述第二电光转换单元、所述第二光电转换单元与对应的模拟电芯片进行电连接；所述多个导电布线单元包括多个电连接结构，所述多个电连接结构中的每一个均各自穿过至少部分所述介电层。
在一些实施方式中，所述多个电芯片包括一个或多个小芯片。
在一些实施方式中，所述第一数字电芯片、所述第二数字电芯片还包括超短距串并行接口，以分别与用于第一模拟电芯片、第二模拟电芯片进行通信。
根据本发明的一方面，提供一种计算装置，其包括光互连装置。
根据本发明的一方面，提供一种光互连装置的制造方法，包括：提供晶圆；在所述晶圆上形成多个光子集成电路；其中，所述多个光子集成电路中的每一个包括多个光波导，以及电光转换单元、光电转换单元；在所述多个光子集成电路中的每一个上安装所需的至少一个模拟电芯片；对所述晶圆进行分割，得到多个独立的光互连件；将所述光互连件安装在承载基板上；将数字电芯片安装在承载基板上。
有益效果
本发明实施例的光互连装置及其制造方法、计算装置，采用小芯片(Chiplet)技术，可以突破芯片面积的物理瓶颈，是实现更高性能芯片的一个重要途径。由于每个裸片的面积变小，单片晶圆上可摆放的裸片数目增加从而可以提高良率和降低成本。
另外，本发明可在提高系统性能时可以灵活地只升级部分模块，因此可以加快系统升级的迭代周期。
根据本发明的实施方式，通过在光互连件上集成一系列模拟电芯片，而模拟电芯片和光互连件周围的一系列数字电芯片之间通过超短距串并转换接口相连。将不同模拟电芯片上的信息加载在光信号上，然后让光信号在光互连件 中高速穿梭，完成不同模拟电芯片之间的信息互连，再利用数字电芯片上的超短距串并转换接口将高速模拟电信号转换成数字芯片处理的低速并行信号，使得数字电芯片之间通过光电互连形成有机整体。对比电互连，光互连带宽大、时延低、功耗小、集成密度高和抗电磁干扰能力强。而且片上或片间光互连传输信息对距离不敏感，允许更多数据传递更远距离，使得计算机架构的设计具有更大的灵活度。
在一些实施方式中，调制器阵列采用高效率小面积的微环调制器阵列，探测器阵列采用具有波分解复用功能的微环滤波探测器。通过在不同模拟电芯片下方的光互连件中集成调制器阵列和探测器阵列，可以在模拟电芯片之间进行大量的信息传输而不会受功耗和带宽密度的限制。通过排布调制器阵列、探测器阵列和相应模拟电芯片的位置，可以实现多个独立的数据传输通道，每条通道由相互通信的两块数字电芯片独占，不存在竞争冲突的问题，横截面带宽大，信号延迟低，最终提高信息处理通量。
利用一系列模拟电芯片，数字电芯片在光互连件上可以实现点对点全连接，可以让一系列数字电芯片同时对信息进行并行处理，并且芯片间具有紧密的信息互连，能够更好地满足人工智能算法对计算能力和带宽的要求。对比现有的人工智能产品，该光互连装置能集成更多的计算单元和存储单元，而且利用光互连能保证它们之间有机的信息互连，从而提供更高的系统能效比。
本发明实施方式的各个方面、特征、优点等将在下文结合附图进行具体描述。根据以下结合附图的具体描述，本发明的上述方面、特征、优点等将会变得更加清楚。
参照后文的说明和附图，详细公开了本发明的特定实施例，指明了本发明的原理可以被采用的方式。应该理解，本发明的实施例在范围上并不因而受到限制。在所附权利要求的精神和条款的范围内，本发明的实施例包括许多改变、修改和等同。
针对一种实施例描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施例中使用，与其它实施例中的特征相组合，或替代其它实施例中的特征。
应该强调，术语“包括/包含”在本文使用时指特征、整件、步骤或组件的 存在，但并不排除一个或更多个其它特征、整件、步骤或组件的存在或附加。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据本发明的示例性实施方式的光互连装置的俯视示意图。
图2是根据本发明的示例性实施方式的光互连装置中光互连件的光波导布置、电光转换单元、光电转换单元布置示意图；
图3是光互连装置的剖面示意图；
图4是本发明实施方式中一个电光转换单元包括多个调制器时的结构示意图；
图5是本发明实施方式中一个光电转换单元包括多个探测器时的结构示意图。
图6为本申请一实施例制造光子集成电路时相关结构的剖面示意图。
图7为本申请一实施例制造光子集成电路时相关结构的剖面示意图。
图8为本申请一实施例制造光子集成电路时相关结构的剖面示意图。
本发明的实施方式
为了便于理解本发明技术方案的各个方面、特征以及优点，下面结合附图对本发明进行具体描述。应当理解，下述的各种实施方式只用于举例说明，而非用于限制本发明的保护范围。
在本文中提及的“包括”为一开放式用语，故应解释成“包括但不限定于”。“大致”是指在可接收的误差范围内，本领域技术人员能够在一定误差范围内解决所述技术问题，基本达到所述技术效果。
此外，“连接”一词在此包含任何直接及间接的连接手段。因此，若文中描述一第一装置连接于一第二装置，则代表所述第一装置可直接连接于所述第二装置，或通过其它装置间接地连接至所述第二装置。
本文中的“第一”、“第二”等描述，是用于区分不同的设备、模块、结构等，不代表先后顺序，也不限定“第一”和“第二”是不同的类型。此外，在本申请的说明书、权利要求书及上述附图中描述的一些流程中，包含了按照特定顺序出现的多个操作，这些操作可以不按照其在本文中出现的顺序来执行或并行执行。操作的序号如101、102等，仅仅是用于区分各个不同的操作，序号本身不代表任何的执行顺序。另外，这些流程可以包括更多或更少的操作，并且这些操作可以按顺序执行或并行执行。
在本发明的一种实施方式中，所述光互连装置包括多个数字电芯片、多个模拟电芯片和光互连件。其中，光互连件可以实现电信号与光信号的转换，以及光信号的信息传输。多个数字电芯片中包括第一数字电芯片和第二数字电芯片，多个模拟电芯片中与所述第一数字电芯片和第二数字电芯片分别通信连接的称为第一模拟电芯片和第二模拟电芯片。本文中的“第一”和“第二”旨在区分不同的对象，而非意在对对象进行排序和限制对象的数量。所述光互连件具有多个光波导，例如，可以采用光互连件实现。所述第一数字电芯片与所述第一模拟电芯片通信连接，所述第二数字电芯片与所述第二模拟电芯片通信连接，所述第一模拟电芯片与所述第二模拟电芯片通过所述光互连件实现通信连接。也就是说，所述第一数字电芯片到所述第二数字电芯片的信息传输路径包括信息先后经过所述第一数字电芯片、所述第一模拟电芯片、所述光互连件的所述光波导、所述第二模拟电芯片、以及所述第二数字电芯片。不限于以上示例，根据需要，所述多个数字电芯片中的任意两个芯片可以通过模拟电芯片、光互连件实现信息互通即通信连接。
在一些实施方式中，所述光互连装置还包括承载基板，所述光互连件设置在所述承载基板上。在所述光互连件上设置所述多个模拟电芯片，在所述光互连件周围设置所述多个数字电芯片。其中，所述数字电芯片到所述模拟电芯片的电连接路径包括先后经过所述数字电芯片的导电布线结构、所述承载基板的导电布线结构、所述光互连件中的导电布线结构(例如，孔中导电结构)、以及所述模拟电芯片的导电布线结构的电传导路径。在一些实施方式中，可采用所述超短距串并行接口用于数字电芯片与模拟电芯片之间的通信。
在一些实施方式中，所述光互连装置还包括激光模块，其产生光信号。在 一些实施方式中，所述光互连件括光耦合结构，其将外部光源(包括光纤)的光信号耦合至该光互连装置光互连件中。所述光耦合结构例如包括光栅耦合器或端面耦合器。在一些实施方式中，所述光互连件包括电光转换单元，其与所述第一模拟电芯片耦接，用于将所述第一模拟电芯片的模拟电信号承载的信息承载到所述光信号中；所述光互连件还包括光电转换单元，其与所述第二模拟电芯片耦接，用于将接收的所述光信号转换为将被传输至所述第二模拟电芯片的模拟电信号。在一些实施方式中，为了实现双向通信，在光互连件中与模拟电芯片对应的区域集成有电光转换单元和光电转换单元二者。在一些实施方式中，所述电光转换单元和光电转换单元集成在相应的模拟电芯片的下方。
根据本发明的实施方式，第一数字电芯片向第二数字电芯片发送信息时，第一数字电芯片发出的承载信息的数字电信号可通过超短距串并行接口转换为高速串行电信号并传输至第一模拟电芯片，通过电光转换单元将所述模拟电芯片的模拟电信号承载的信息承载到光信号中，所述光信号通过光互连件的光波导传输至第二模拟电芯片下方的光电转换单元，并由该光电转换单元将光信号转换成模拟电信号即高速串行电信号，所述第二模拟电芯片将该高速串行电信号发送至设于第二数字电芯片上的超短距串并行接口，该超短距串并行接口将该高速串行电信号转换成承载有所述信息的低速并行信号即数字电信号，并输入到第二数字电芯片中，从而完成第一数字电芯片和第二数字电芯片之间的信息传输。第二数字电芯片向第一数字电芯片发送信息时，其传输过程与从第一数字电芯片向第二数字电芯片发送信息的传输过程相同。
在一些实施方式中，所述电光转换单元包括调制器阵列，其将所述第一模拟电芯片的模拟电信号承载的信息调制到不同波长的所述光信号上并以波分复用的方式进行传输；所述光电转换单元包括探测器阵列，其对接收的所述光信号进行波分解复用并转化为向所述第二模拟电芯片传输的模拟电信号。在一些实施方式中，所述调制器阵列包括多个微环调制器。在一些实施方式中，所述探测器阵列包括多个微环滤波探测器。
需要说明的是，本发明对所述光互连装置使用的芯片的数量不做特别限定，其中，任意两个数字电芯片之间的通信过程与上述的第一数字电芯片与第二电数字芯片的通信过程相同。
图1是根据本发明的示例性实施方式的光互连装置的结构示意图。在本发明的一种示例性实施方式中，所述光互连装置包括承载基板100、光互连件200、数字电芯片A～D、以及模拟电芯片a～d。光互连件200设置在承载基板100上，模拟电芯片a～d设置在光互连件200上，数字电芯片A～D设置于承载基板100上且分布在光互连件200的周围。对此，当数字电芯片更新时，可以方便地、独立地对其进行更换，而可以保持光互连件及模拟电芯片不发生改变，也基本无需对其它电布线结构进行改动。
其中，示例性的，光互连件包括光子集成电路，所述光子集成包括光波导单元、多个电光转换单元和多个光电转换单元，其中，光波导单元可包括多个光波导。在一些实施方式中，所述电光转换单元包括一个或多个光调制器，多个调制器可构成调制器阵列。所述光电转换单元包括一个或多个光电探测器，多个探测器可构成探测器阵列。示例性的，调制器可基于电信号可对初始光进行调制，从而产生承载信息的光信号，亦即，将电信号承载的信息承载到光信号中。光互连件具备使电信号与光信号进行转换的功能，从而能够使用光的互连通信，代替电信号的通信。
图2是根据本发明的示例性实施方式的光互连装置的连接的示意图，图中以透视的方式示出了光互连件中与模拟电芯片对应的区域中形成的电光转换单元和光电转换单元。下面结合图2阐述本发明实施方式的光互连装置中部件之间的连接和通信过程。
光互连件200包括光子集成电路，所述光子集成包括多个光波导、多个电光转换单元和多个光电转换单元。在一些实施方式中，所述电光转换单元包括一个或多个光调制器，多个调制器可构成调制器阵列。所述光电转换单元包括一个或多个光电探测器，多个探测器可构成探测器阵列。示例性的，调制器可基于电信号可对初始光进行调制，从而产生承载信息的光信号，亦即，将电信号承载的信息承载到光信号中。光互连件具备使电信号与光信号进行转换的功能，从而能够使用光的互连通信，代替电信号的通信。
图2中模拟电芯片的设置区域a’～d’，对应设置图1中的模拟电芯片a～d，模拟电芯片a～d中任意两者之间通过光互连件200的光波导通信。在图2中，光互连件200中设有多个电光转换单元和多个光电转换单元，图2示出了，在 光互连件中与a’区域对应的部分，设置有12个电光转换单元、12个光电转换单元。图2中数字电芯片的设置区域A’～D’，对应设置图1中的数字电芯片A～D，数字电芯片A～D分别设有超短距串并转换接口，并且，数字电芯片A与模拟电芯片a通信连接，数字电芯片B与模拟电芯片b通信连接，数字电芯片C与模拟电芯片c通信连接，数字电芯片D与模拟电芯片d通信连接。如图3所示，数字电芯片A到模拟电芯片a的电连接路径包括先后经过数字电芯片A的导电布线结构(未示出)、承载基板100的导电布线结构301、光互连件200中导电布线结构、以及模拟电芯片a的导电布线结构(未示出)的电传导路径。示例性的，光互连件200中的导电布线结构可包括导电硅通孔201，导电硅通孔布置于光互连件的硅基底中并贯穿硅基底。示例性的，光互连件中亦可包括其它孔中导电结构，孔中导电结构穿过光互连件的至少一部分。其他数字电芯片与对应模拟电芯片之间的电连接路径与数字电芯片A到模拟电芯片a的电连接路径类似。在一些实施方式中，数字电芯片A到模拟电芯片a的电连接路径亦可以采用本领域合适的其他连接方式。
在示例性实施方式中，利用光互连件200中的所述光波导，任意一个数字电芯片能够与其他任意一个数字电芯片通信，形成点对点全连接的拓扑通信连接结构。激光模块300同时输出多个波长激光，通过光互连件中的光耦合结构，例如光栅耦合器或端面耦合器将光信号耦合进入光互连件200，在光互连件200中的分束器将光的能量平均分配到不同模拟电芯片在光互连件200中对应的电光转换单元。示例性的，分束器可以采用宽波段分束器。以数字电芯片A为例，数字电芯片A到其他数字电芯片B～D的信息传输过程包括：数字电芯片A的数字电信号经由该数字电芯片A上的超短距串并转换接口转换为高速串行信号，该高速串行信号经过承载基板100上的导电布线结构(例如金属走线)和光互连件200中的导电布线结构(例如导电硅通孔和/或其它导电线路)传输至模拟电芯片a上，经过模拟电芯片a处理，模拟电芯片a输出的电信号传输给光互连件200，输入到光互连件200中的电光转换单元。示例性的，电光转换单元包括多个调制器，可以构成调制器阵列，通过该调制器阵列基于电信号对光进行调制，将模拟电芯片a输出的电信号承载的信息加载在不同波长的光信号上并波分复用。通过光互连件200的光波导传输到光电转换单元中。 示例性的，光电转换单元包括多个光电探测器，可以构成探测器阵列，探测器阵列对调制的光信号进行波分解复用，并进行光电转换，以电信号输出。光互连件200输出承载信息的电信号至模拟电芯片b～d，经模拟电芯片处理。模拟电芯片b～d输出的电信号被传输至对应的数字电芯片B～D。模拟电芯片b～d与对应的数字电芯片B～D之间的通信可以通过超短距串并转换接口。
在示例性的实施方式中，数字电芯片A～D相比模拟电芯片a～d更接近于承载基板，缩短了数字电芯片与承载基板的连接距离，简化了封装方式。数字电芯片设置在光互连件周围，而无需设置在光互连件上，可不占用光互连件的面积。模拟电芯片直接设置在光互连件上，则优化了其与光互连件的通信距离。
在一些实施方式中，数字电芯片A～D和模拟电芯片a～d均为小芯片(Chiplet)。四个数字电芯片分别通过四个模拟电芯片和光互连件经过数模、电光、光电和模数转换，形成点对点全连接。每两个数字电芯片之间都具有独立的数据传输通道，使得两两数字电芯片之间不存在竞争冲突的问题，信号延迟低，信息处理通量大。该结构复用了四个模拟电芯片和四个数字电芯片，在提高系统能效比的同时，降低了电芯片的尺寸，从而降低了芯片设计和加工成本，并且有效提高了芯片的良率。
在一些实施方式中，如图4所示，本发明实施方式中一个电光转换单元包括多个调制器，其中，多个调制器构成调制器阵列，应指出，调制器阵列一词仅表示照一定位置排列，在满足功能需求的基础上，阵列一词并不对各调制器排列形式、排列规律等做特别限定，也不限定为是二维形式的阵列。所述调制器阵列由一系列微环调制器401组成，所述微环调制器401基于载流子耗尽效应，可以支持高调制速率，该类型的波导结构在脊形波导不同区域进行掺杂，形成横向或纵向的PN结结构402。PN结工作在反偏模式，当施加反偏电压后，PN结内的耗尽区增大，内建电场增强，耗尽区内没有自由载流子，对应的环形波导403的折射率发生改变，导致其共振波长发生平移，共振峰附近某一特定波长的强度会发生较大的改变，从而达到强度调制的目的。微环调制器的尺寸小，功耗低，调制效率高。将来自电芯片上的电信息数据调制时，可通过调节微环调制器上的加热电极404而对应特定波长的载波，经调制的不同波长的光信号在光波导407上独立传播，实现了多通道的波分复用的信号传输。其中， 多个微环可对应多个不同的波长。因为微环调制器对温度的敏感性，在调制过程中，可以通过监测横向或纵向PN结本身对光吸收产生的光电流和利用模拟电芯片上的反馈控制来调节微环调制器的偏置点使得光调制幅度保持最大化。
在一些实施方式中，如图5所示，一个光电转换的单元包括多个探测器，其中，多个探测器构成探测器阵列，应指出，探测器阵列一词仅表示照一定位置排列，在满足功能需求的基础上，阵列一词并不对各探测器排列形式、排列规律等做特别限定，也不限定为是二维形式的阵列。示例性的，所述探测器阵列由一系列微环滤波探测器501构成，微环滤波探测器501包括加热电极502、环形波导503、信号光探测器504。通过调节微环滤波探测器501上的加热电极502来调节环形波导503，从光波导507中过滤出特定波长的光信号，下载到与电芯片耦合的信号光探测器504上，实现光信号到模拟电信号的转换。其中，多个微环可对应多个不同的波长。另外，通过与光波导507、信号光探测器504连接的波导终端505来吸收波导末端的残余光能量，使其不影响其他光波导的信号传输。
模拟通过光互连件中设置合适的电光转换单元、光电转换单元、光波导，可以在模拟电芯片之间进行大量的信息传输而不会受功耗和带宽密度的限制。可根据需要排布光互连件中调制器阵列、探测器阵列的位置以及相应模拟电芯片的位置，可以实现多个独立的数据传输通道，每条通道由相互通信的两块数字芯片独占，不存在竞争冲突的问题，横截面带宽大，信号延迟低，最终提高信息处理通量。
在本发明的一些实施方式中，所述数字电芯片可以是CPU、GPU和存储芯片中的一种或多种。
本发明示例性的实施方式提供一种光互连装置的制造方法，可用于制造前述各实施方式中的光互连装置。该方法包括：
S601、提供晶圆。
S602、在所述晶圆上形成多个光子集成电路。
其中，所述多个光子集成电路中的每一个可包括多个光波导，以及电光转换单元、光电转换单元，多个光波导可用于构成光波导单元，即光波导单元包括多个光波导。所述多个光子集成电路中的每一个光子集成电路还可包括多个 导电布线单元，多个导电布线单元可将电光转换单元和/或光电转换单元连接至对应的模拟电芯片，以接收来自模拟电芯片的待通信的电信号和/或向模拟电芯片发送用于通信的电信号。通常，多个光子集成电路形成于晶圆上的多个区域，在后续步骤中，晶圆会被切割，以形成独立的单个光子集成电路，所述光子集成电路用于构成光互连件，即光互连件包括所述光子集成电路。
S603、在所述多个光子集成电路中的每一个上安装所需的至少一个模拟电芯片。模拟电芯片的数量可以是一个或多个，例如，设置第一模拟电芯片和第二模拟电芯片，使所述第一模拟电芯片与所述第一导电布线单元电连接，所述第二模拟电芯片与所述第二导电布线单元电连接，第一电光转换单元通过第一导电布线单元接收所述第一模拟电芯片的第一电信号，并编码产生第一光信号；所述第一光电转换器用于将第一光信号转换为电信号并传输给第二导电布线单元。
S604、对所述晶圆进行分割，得到多个独立的光互连件。
S605、将所述光互连件安装在承载基板上。
S606、将数字电芯片安装在承载基板上。
在一些实施例中，单个光互连装置中包括单个的光子集成电路以及安装(设置)在所述光子集成电路上的所述第一模拟电芯片和所述第二模拟电芯片。其中，第一模拟电芯片、第二模拟电芯片能够通过第一导电布线单元、所述第一电光转换单元、多个光波导中的至少一个、第一光电转换单元以及所述第二导电布线单元进行通信。独立的单个光互连装置中具体包括一个所述光子集成电路。
应指出，步骤的编号并不代表执行顺序。示例性的，可以在数字电芯片安装之前安装光互连件，示例性的，可以在数字电芯片安装之后，安装光互连件，对此不作特别的限定。
上述S601中，晶圆包括半导体层。在一实例中，上述晶圆可以是绝缘体上半导体晶圆，例如：SOI(Silicon-On-Insulator，绝缘衬底上硅)晶圆。如图6所示，绝缘体上半导体晶圆可包括：绝缘层602、形成在绝缘层602上的半导体层603以及位于所述绝缘层602下方的背衬底层601。
上述S602中，可通过在半导体层603上进行图形化、沉积、掺杂等工艺 形成光子集成电路。
上述S603中，在一实例中，可通过键合或焊接等电连接方式将第一模拟电芯片电连接到第一导电布线单元上，将第二模拟电芯片电连接到第二导电布线单元上。
在一具体实例中，上述步骤S602中“在所述晶圆上形成多个光子集成电路”，具体可采用如下步骤来实现：
S21、在所述晶圆上形成光波导单元、所述第一电光转换单元第一电光转换单元和所述第一光电转换单元。
S22、在形成有光波导单元、所述第一电光转换单元第一电光转换单元和所述第一光电转换单元的晶圆上沉积介电层，以覆盖所述光波导单元、所述第一电光转换单元、所述第一光电转换单元以及所述晶圆。
S23、在所述介电层中形成第一开孔和第二开孔。
S24、在所述第一开孔中形成第一电连接结构以及在所述第二开孔中形成第二电连接结构。
其中，所述第一导电布线单元包括所述第一电连接结构；所述第二导电布线单元包括所述第二电连接结构。
上述S21，如图6和图7所示，可对晶圆的半导体层603进行图形化得到光波导单元103、第一电光转换单元104和第一光电转换单元105对应区域。具体地，采用光刻和蚀刻技术，去除并不需要的材料，以进行图形化。在一些实施例中，上述绝缘层可以作为刻蚀停止层。在一些实施方式中，所述电光转换单元包括一个或多个调制器，多个调制器可构成调制器阵列。所述光电转换单元包括一个或多个光电探测器，多个探测器可构成探测器阵列。作为简化，图7中仅示出了一个调制器、一个探测器。
上述S22中，如图8所示，在形成有所述光波导单元103、所述第一电光转换单元104和所述第一光电转换单元105的晶圆上沉积介电层106，以覆盖所述光波导单元103、所述第一电光转换单元104、所述第一光电转换单元105以及所述晶圆。具体地，通过沉积，在光波导单元103、第一电光转换单元104、第一光电转换单元105、绝缘层602上形成介电层106。上述介电层的材料与绝缘层的材料可相同。
上述S23中，如图8所示，在所述介电层106中形成第一开孔和第二开孔。可采用刻蚀技术形成上述第一开孔和第二开孔，根据连接需要，第一开孔、第二开孔的个数可以为一个或多个。
在一些实施例中，介电层106是多层结构，通过多个子介电层形成，在介电层中可形成有多层导电层，导电层之间通过开孔中的导电材料连接。例如先沉积形成第一子介电层，再形成第一导电层，然后再沉积形成第二子介电层，再形成第二导电层然后形成第三子介电层，再形成第三导电层，然后形成第四子介电层。其中，第一至第三导电层中，不同的导电层通过开孔中的导电材料进行互连，各导电层可以为图案化的金属材料层。
上述S24中，如图8所示，可通过沉积导电材料，在所述第一开孔中形成第一导电布线单元101的第一电连接结构101a以及在所述第二开孔中形成第二导电布线单元102的第二电连接结构102a。所述第一电连接结构101a穿过至少部分所述介电层106；所述第二电连接结构102a穿过至少部分所述介电层106。
沉积导电材料后，可通过化学机械抛光或机械研磨的平坦化工艺以沿着介电层的安装面去除过量的导电材料，从而使得第一电连接结构101a和第二电连接结构102a与介电层106的安装面齐平。
后续，在晶圆上的每一个光子集成电路上安装第一模拟电芯片和第二模拟电芯片，具体地，在介电层106/光子集成电路的安装面上对应于每一个光子集成电路的区域内安装第一模拟电芯片和第二模拟电芯片，也即在介电层106/光子集成电路的安装面上对应于每一个光子集成电路的区域，将第一模拟电芯片和第二模拟电芯片与该区域内的第一电连接结构和第二电连接结构进行电连接。
后续，还可在介电层106上形成密封剂，以掩埋或覆盖第一模拟电芯片和第二模拟电芯片。之后，可固化并且可以平坦化密封剂。
在一些实施方式中，可包括对背衬底层601减薄的工序。
在一些实施例中，S604可在S603之后执行，亦即，在对光子集成电路晶圆进行分割前批量安装第一模拟电芯片、第二模拟电芯片，该种方式可以在晶圆级制程中对第一模拟电芯片、第二模拟电芯片进行批量封装，此时，仅需制 造光子集成电路晶圆，无需将光子集成电路形成单个的芯片。
在一些实施方式中，在制造光子集成电路时，还可包括制造导电布线结构，所述导电布线结构能用于连接数字电芯片、模拟电芯片，使得数字电芯片、模拟电芯片之间能实现电信号通信，此时，光互连件包括上述导电布线结构，示例性的，光互连件可以作为中介层。示例性的，上述导电布线结构可以包括导电硅通孔，亦可包括其它导电线路。
另外，可选的，可先进行晶圆分割的工序，以先形成独立的光子集成电路/独立的包含光子集成电路的光互连件，然后再进行第一模拟电芯片和第二模拟电芯片的安装工序，即将所述第一模拟电芯片、第二模拟电芯片安装在所述独立的光子集成电路上。
可选的，可对多个独立的光子集成电路进行一定程度的封装，以形成多个独立的光子集成电路芯片(包括裸芯片)，光子集成电路芯片作为光互连的芯片，即光互连件可采用光子集成电路芯片。具体地，该方法，包括：
S1001、提供晶圆。
S1002、在所述晶圆上形成多个光子集成电路。
其中，所述多个光子集成电路中的每一个包括第一导电布线单元、第二导电布线单元、光波导单元以及第一电光转换单元和第一光电转换单元；所述第一电光转换单元和所述第一光电转换单元分别耦合至所述光波导单元；所述第一导电布线单元与所述第一电光转换单元电连接；所述第二导电布线单元与所述第一光电转换单元电连接。
S1003、对所述晶圆进行分割，得到多个独立的光子集成电路。
其中，多个光子集成电路被分割独立的光子集成电路，从而每一个所述光子集成电路芯片中包括独立的光子集成电路。
S1004、在所述多个独立的光子集成电路芯片中的每一个上安装第一模拟电芯片和第二模拟电芯片，以使所述第一模拟电芯片与所述第一导电布线单元电连接，所述第二模拟电芯片与所述第二导电布线单元电连接。
作为一个示例，S1004可在步骤S1003之后执行，但不限于此。
其中，所述第一模拟电芯片、所述第二模拟电芯片能够通过所述第一导电布线单元、所述第一电光转换单元、所述光波导单元、所述第一光电转换单元 以及所述第二导电布线单元进行通信。
上述步骤S1002的具体实现可参见上述各实施例中相应内容，在此不在赘述。
这里需要说明的是：本申请实施例提供的所述方法中各步骤未尽详述的内容可参见上述实施例中的相应内容，此处不再赘述。此外，本申请实施例提供的所述方法中除了上述各步骤以外，还可包括上述各实施例中其他部分或全部步骤，具体可参见上述各实施例相应内容，在此不再赘述。
本领技术人员应当理解，以上所公开的仅为本发明的实施方式而已，当然不能以此来限定本发明之权利范围，依本发明实施方式所作的等同变化，仍属本发明权利要求所涵盖的范围。

Claims (19)

  1. 一种光互连装置，其特征在于，所述光互连装置包括：
    多个数字电芯片，其包括第一数字电芯片和第二数字电芯片；
    多个模拟电芯片，其包括第一模拟电芯片和第二模拟电芯片；以及
    光互连件，其包括光子集成电路，所述光子集成电路包括多个光波导；
    其中，所述第一数字电芯片与所述第一模拟电芯片通信连接，所述第二数字电芯片与所述第二模拟电芯片通信连接，所述第一模拟电芯片与所述第二模拟电芯片通过所述光互连件实现通信连接；
    其中，所述第一数字电芯片到所述第二数字电芯片的信息传输路径包括信息先后经过所述第一数字电芯片、所述第一模拟电芯片、所述光互连件的光波导、所述第二模拟电芯片、以及所述第二数字电芯片。
  2. 如权利要求1所述的光互连装置，其特征在于，所述光互连装置还包括承载基板；
    所述光互连件设置在所述承载基板上；
    所述多个模拟电芯片设置在所述光互连件上，所述多个数字电芯片设置在所述光互连件周围。
  3. 如权利要求2所述的光互连装置，其特征在于，所述多个数字电芯片相比所述多个模拟电芯片更接近所述承载基板。
  4. 如权利要求2所述的光互连装置，其特征在于，所述第一数字电芯片到所述第一模拟电芯片的电连接路径先后经过所述承载基板的导电布线结构、所述光互连件中的导电布线结构。
  5. 如权利要求1所述的光互连装置，其特征在于，所述光互连件的光子集成电路还包括：
    第一电光转换单元，其与所述第一模拟电芯片电连接，用于将所述第一模拟电芯片的模拟电信号承载的信息承载到第一光信号中，所述第一光信号在所述光互连件的光波导中传输；
    第一光电转换单元，其与所述第二模拟电芯片电连接，用于将接收的第一光信号转换为传输至所述第二模拟电芯片的模拟电信号。
  6. 如权利要求5所述的光互连装置，其特征在于，所述光互连件的光子 集成电路还包括：第二电光转换单元，其与所述第二模拟电芯片电连接，用于将所述第二模拟电芯片的模拟电信号承载的信息承载到第二光信号中，所述第二光信号在所述光互连件的光波导中传输；
    第二光电转换单元，其与所述第一模拟电芯片电连接，用于将接收的第二光信号转换为传输至所述第一模拟电芯片的模拟电信号。
  7. 如权利要求6所述的光互连装置，其特征在于，
    所述第一电光转换单元、第二电光转换单元均各自包括多个调制器，用于将电信号承载的信息调制到不同波长的光信号上并以波分复用的方式进行传输；
    所述第一光电转换单元、第二光电转换单元均各自包括多个光电探测器，其对接收的所述光信号进行波分解复用并转化为电信号。
  8. 如权利要求7所述的光互连装置，其特征在于，所述调制器包括微环调制器；和/或
    所述探测器包括微环滤波探测器。
  9. 如权利要求7所述的光互连装置，其特征在于，所述光互连件的光子集成电路还包括：介电层、多个导电布线单元；
    所述介电层覆盖所述多个光波导、所述第一电光转换单元、所述第一光电转换单元、所述第二电光转换单元、所述第二光电转换单元；
    所述多个导电布线单元被配置为将所述第一电光转换单元、所述第一光电转换单元、所述第二电光转换单元、所述第二光电转换单元与对应的模拟电芯片进行电连接；
    所述多个导电布线单元包括多个电连接结构，所述多个电连接结构中的每一个均各自穿过至少部分所述介电层。
  10. 如权利要求1所述的光互连装置，其特征在于，所述多个数字电芯片和所述多个模拟电芯片中的一个或多个包括小芯片。
  11. 如权利要求9所述的光互连装置，其特征在于，所述第一数字电芯片、所述第二数字电芯片还包括超短距串并行接口，以分别与用于第一模拟电芯片、第二模拟电芯片进行通信。
  12. 如权利要求2所述的光互连装置，其特征在于，所述光互连件的光子 集成电路还包括：
    第一电光转换单元，其与所述第一模拟电芯片电连接，用于将所述第一模拟电芯片的模拟电信号承载的信息承载到第一光信号中，所述第一光信号在所述光互连件的光波导中传输；
    第一光电转换单元，其与所述第二模拟电芯片电连接，用于将接收的第一光信号转换为传输至所述第二模拟电芯片的模拟电信号。
  13. 如权利要求12所述的光互连装置，其特征在于，所述光互连件的光子集成电路还包括：第二电光转换单元，其与所述第二模拟电芯片电连接，用于将所述第二模拟电芯片的模拟电信号承载的信息承载到第二光信号中，所述第二光信号在所述光互连件的光波导中传输；
    第二光电转换单元，其与所述第一模拟电芯片电连接，用于将接收的第二光信号转换为传输至所述第一模拟电芯片的模拟电信号。
  14. 如权利要求13所述的光互连装置，其特征在于，
    所述第一电光转换单元、第二电光转换单元均各自包括多个调制器，用于将电信号承载的信息调制到不同波长的光信号上并以波分复用的方式进行传输；
    所述第一光电转换单元、第二光电转换单元均各自包括多个光电探测器，其对接收的所述光信号进行波分解复用并转化为电信号。
  15. 如权利要求14所述的光互连装置，其特征在于，所述调制器包括微环调制器；和/或
    所述探测器包括微环滤波探测器。
  16. 如权利要求14所述的光互连装置，其特征在于，
    所述光互连件的光子集成电路还包括：介电层、多个导电布线单元；
    所述介电层覆盖所述多个光波导、所述第一电光转换单元、所述第一光电转换单元、所述第二电光转换单元、所述第二光电转换单元；
    所述多个导电布线单元被配置为将所述第一电光转换单元、所述第一光电转换单元、所述第二电光转换单元、所述第二光电转换单元与对应的模拟电芯片进行电连接；
    所述多个导电布线单元包括多个电连接结构，所述多个电连接结构中的每 一个均各自穿过至少部分所述介电层。
  17. 如权利要求16所述的光互连装置，其特征在于，所述第一数字电芯片、所述第二数字电芯片还包括超短距串并行接口，以分别与用于第一模拟电芯片、第二模拟电芯片进行通信。
  18. 一种计算装置，其包括如权利要求1-17中任意一项所述的光互连装置。
  19. 一种光互连装置的制造方法，其特征在于，包括：
    提供晶圆；
    在所述晶圆上形成多个光子集成电路；
    其中，所述多个光子集成电路中的每一个包括多个光波导，以及电光转换单元、光电转换单元；
    在所述多个光子集成电路中的每一个上安装所需的至少一个模拟电芯片；
    对所述晶圆进行分割，得到多个独立的光互连件；
    将所述光互连件安装在承载基板上；
    将数字电芯片安装在承载基板上。
PCT/CN2022/137593 2021-12-14 2022-12-08 光互连装置及其制造方法、计算装置 WO2023109645A1 (zh)

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