WO2023104060A1 - 驱动检测方法、开关电源、电子设备及存储介质 - Google Patents
驱动检测方法、开关电源、电子设备及存储介质 Download PDFInfo
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- 238000005070 sampling Methods 0.000 claims abstract description 125
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the embodiments of the present application relate to the technical field of power electronics, and in particular to a driving detection method, a switching power supply, electronic equipment, and a storage medium.
- each branch of the multi-phase interleaved switching power supply can work normally when leaving the factory and using it.
- the current value of each channel sampled in the control loop is generally directly used to judge whether each branch is working normally; or, the detection circuit is not added separately to judge whether the produced Whether the PFC and DCDC of each channel of the product work normally; but the production line passes the function test tool to test the working condition of each branch circuit after power-on.
- the embodiment of the present application provides a driving detection method, which is applied to a switching power supply, including: sampling the signal on the driving pin of the power semiconductor in the interleaved circuit topology, and obtaining the driving sampling signal of the power semiconductor; according to the interleaving The driving type of the circuit topology, obtain the reference signal; detect whether the driving sampling signal is consistent with the obtained reference signal, and determine whether the switching power supply has a driving abnormality if the level signal is inconsistent with the reference signal.
- an embodiment of the present application further provides an electronic device, including: at least one processor; and a memory connected to the at least one processor in communication; wherein, the memory stores instructions that can be executed by the at least one processor , the instructions are executed by at least one processor, so that the at least one processor can execute the driving detection method as described above.
- an embodiment of the present application further provides a computer-readable storage medium storing a computer program, and implementing the above-mentioned drive detection method when the computer program is executed by a processor.
- FIG. 2 is a schematic structural diagram of a driving abnormality detection circuit of an interleaved circuit topology in an embodiment of the present application
- FIG. 6 is a schematic structural diagram of a signal input circuit in an embodiment of the present application.
- FIG. 8 is a schematic structural diagram of a totem pole PFC circuit in an embodiment of the present application.
- FIG. 9 is a schematic structural diagram of another signal input circuit in the embodiment of the present application.
- Fig. 11 is a schematic structural diagram of an electronic device in another embodiment of the present application.
- an embodiment of the present application provides a driving detection method, which is applied to a switching power supply, including: sampling the signal on the driving pin of the power semiconductor in the interleaved circuit topology, and obtaining the driving sampling signal of the power semiconductor;
- the driving type of the interleaved circuit topology obtains the reference signal; detects whether the driving sampling signal is consistent with the obtained reference signal, and determines whether the switching power supply has a driving abnormality when the level signal is inconsistent with the reference signal.
- the signal on the drive pin of the power semiconductor is sampled to obtain the drive sampling signal of the power semiconductor, and then according to the drive type of the interleaved circuit topology, The corresponding reference signal is obtained, and an accurate judgment is made on whether there is a driving abnormality in the interleaved circuit topology of the switching power supply according to the consistency between the obtained driving sampling signal and the reference signal.
- Step 101 Sampling the signal on the driving pin of the power semiconductor in the interleaved circuit topology to obtain the driving sampling signal of the power semiconductor.
- the control chip in the switching power supply detects that the interleaved circuit topology can work normally, it controls the digital control chip, hardware circuit or timing wave circuit in the interleaved circuit topology according to the preset driving mode or driving type. Sends drive signals to individual power semiconductors in an interleaved circuit topology. After sending the driving signal to the power semiconductor, the signal on the driving pin of the power semiconductor in the interleaved circuit topology is sampled by the sampling circuit to obtain the driving sampling signal of the power semiconductor. By using the sampling circuit to adopt the driving signal on the driving pin of the power semiconductor, the driving signal received by the power semiconductor can be accurately obtained, which facilitates subsequent and accurate consistency detection of the driving signal.
- the power semiconductor in the interleaved circuit topology can be a semiconductor device such as a triode, a field effect transistor (MOSFET) and an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), or a composite power semiconductor device formed by integrating the above semiconductor devices.
- the semiconductor device is not limited in this embodiment.
- step 102 a reference signal is obtained according to the driving type of the interleaved circuit topology.
- the control chip determines the source of the reference signal in the driving detection process according to the generation mode of the driving signal in the interleaved circuit topology, that is, the driving type. And obtain the reference signal in the driving detection process.
- the complexity of the driving detection is simplified while ensuring the detection accuracy.
- the control chip obtains the reference signal according to the driving type of the interleaved circuit topology, including: when the driving type is digital chip driving, using the initial driving signal sent by the digital chip as the reference signal; when the driving type is hardware circuit In the case of driving or timer-triggered driving, the driving sampling signal of another power semiconductor in the interleaved circuit topology is used as a reference signal. Since the interleaved circuit topology of the switching power supply can be applied in different scenarios and circuit topologies, the control chip divides the driving types according to the generation method of the driving signals in the interleaved circuit topology, and determines the driving type to be used when obtaining the reference signal. The source of the reference signal to obtain the reference signal.
- the interleaved circuit topology can be that the digital control chip generates two weak driving signals, which are amplified by the driving amplifier circuit and then transmitted to the driving pins of the power semiconductors. At this time, since the digital control chip can easily obtain the level of the initial drive signal and the level of the drive signal on the drive pin of the power semiconductor, the initial drive signal sent by the digital control chip is directly used as a reference signal for comparison. Whether the level of the signal is consistent with the obtained driving sampling signal.
- the interleaved circuit topology can also be driven by a hardware circuit or a timer trigger circuit to generate a driving signal to drive a power semiconductor, for example, a critical continuous mode totem pole PFC.
- Step 103 detecting whether the driving sampling signal is consistent with the acquired reference signal, and if the driving sampling signal is inconsistent with the reference signal, it is determined that the switching power supply has a driving abnormality.
- the drive type of the interleaved circuit topology is digital chip drive, and there are two FET paths, A and B, in the interleaved circuit topology.
- the structural diagram of the drive anomaly detection circuit in the interleaved circuit topology is shown in Figure 2, where D1 to D4 are Optional diodes, R1 to R3 and R21 to R23 are optional resistors or a combination of resistors and inductors, C1 and C2 are sampling capacitors, and Q1 and Q2 are field effect transistors.
- the digital control chip before it obtains the level of the driving sampling signal, it can also perform signal isolation on the driving sampling signal through a preset optocoupler or signal isolator, so as to eliminate the interference signal in the driving sampling signal as much as possible. , to ensure the accuracy of the level of the acquired driving sampling signal.
- the control chip further includes: Perform digital-to-analog conversion on the signal to obtain two analog voltage signals after digital-to-analog conversion; detect whether the driving sampling signal is consistent with the obtained reference signal, including: detecting whether the voltage values of the two analog voltage signals are consistent.
- R1 to R5 and R21 R25 to R25 are optional resistors
- C1 to C3 and C21 to C23 are optional capacitors
- Q1 and Q2 are triodes
- R4, R5, R24 and R25 can be resistors or a combination of resistors and inductors.
- D1, D3, R1, R3, and C3 constitute the driving sampling circuit of Q1
- C1, C2, R2, R4, and R5 constitute the digital-to-analog conversion circuit of Q1.
- the circuit structure of the Q2 path is also similar, so I won’t repeat them here. .
- the level signal is converted into an analog voltage signal, which is convenient for accurate comparison of the consistency of the reference signal and the driving sampling signal, so as to accurately obtain the driving sampling signal and reference signal Consistency, to achieve accurate detection of whether there is a driving abnormality in the switching power supply.
- the switching power supply can also be controlled to automatically enter the power supply protection working mode.
- the schematic diagram of the circuit structure given in the embodiment is only a feasible structure, and it is also possible to set only one sampling and analog-to-digital conversion circuit, and input the driving sampling signal and reference signal respectively in a certain order Corresponding processing is carried out in a specified circuit, and this embodiment does not limit the specific setting method of the circuit.
- the control circuit and the power circuit often do not share the ground, which can improve the anti-interference ability and EMC of the circuit; even in the PFC where the control circuit and the power circuit share the ground, the control circuit ground is often Single-point capacitors or other locations in the power loop will cause the signal access circuit loop to be large, and the power loop may be connected to the line, resulting in inaccurate sampling. Therefore, adding a signal isolation device can achieve the effect of suppressing interference signals and obtain more accurate driving sampling signals and reference signals. Then digital-to-analog conversion is performed on the driving sampling signal and reference signal after signal isolation to ensure the correspondence between the analog voltage signal after digital-to-analog conversion and the original signal, thereby ensuring the accuracy of the detection results.
- control chip detects whether the voltage value error between the two analog voltage signals is smaller than a preset error threshold, including: using the two analog voltage signals as the two inputs of the preset differential amplifier circuit respectively, and obtaining the preset The output result of the differential amplifier circuit; when the output result is in the preset range, it is judged that the voltage value error is less than the preset error threshold; when the output result is not in the preset range, it is judged that the voltage value error is not less than the preset error threshold .
- a resistor R3 is connected in parallel at the diode end of U2 to divide the voltage. Because the driving signal has oscillating waveforms and interference spikes, and these interferences are often low in voltage, it is necessary to connect D3 in series in the line for anti-interference.
- the switching signal transmitted by the optocoupler or the signal isolator is converted into a stable analog voltage signal V-A through the digital-to-analog conversion circuit.
- the sampling and conversion of the driving signal of the B-way power semiconductor is also performed in a similar manner to obtain the analog voltage signal V-B.
- V-A and V-B are used as two input signals of the preset differential amplifier circuit, and are transmitted to the differential amplifier circuit for differential amplification.
- a structural schematic diagram of a differential amplifier circuit is shown in Figure 7, wherein R6 to R11 are optional resistors, U1 is a differential operator, Vref is a reference voltage, and Vcc is a power supply voltage.
- the power semiconductors in the interleaved circuit topology of the switching power supply may have the situation that the upper and lower transistors work alternately, for example, the totem pole PFC circuit.
- a structural schematic diagram of a totem pole PFC circuit is shown in FIG. 8 .
- Both the A-way power semiconductor and the B-way power semiconductor are composed of two field effect transistors with upper and lower structures, and the upper and lower transistors do not share the same ground. At this time, when acquiring the driving signal of each power semiconductor, only the driving signal of the upper transistor or the lower transistor may be sampled.
- this embodiment is an apparatus embodiment corresponding to the method embodiment, and this embodiment can be implemented in cooperation with the method embodiment.
- the relevant technical details mentioned in the method embodiments are still valid in this embodiment, and will not be repeated here in order to reduce repetition.
- the related technical details mentioned in this embodiment can also be applied in the method embodiment.
- modules involved in this embodiment are logical modules.
- a logical unit can be a physical unit, or a part of a physical unit, or multiple physical units. Combination of units.
- units that are not closely related to solving the technical problem proposed in the present application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.
- the memory 1102 and the processor 1101 are connected by a bus, and the bus may include any number of interconnected buses and bridges, and the bus connects one or more processors 1101 and various circuits of the memory 1102 together.
- the bus may also connect together various other circuits such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art and therefore will not be further described herein.
- the bus interface provides an interface between the bus and the transceivers.
- a transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing means for communicating with various other devices over a transmission medium.
- the data processed by the processor 1101 is transmitted on the wireless medium through the antenna, and further, the antenna also receives the data and transmits the data to the processor 1101 .
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Abstract
一种驱动检测方法、开关电源、电子设备及存储介质,驱动检测方法应用于开关电源,包括:对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号(101);根据交错电路拓扑的驱动类型,获取参考信号(102);检测驱动采样信号与获取的参考信号是否一致,在驱动采样信号与参考信号不一致的情况下,判定开关电源存在驱动异常并上报告警(103)。能够简单高效的对开关电源交错电路拓扑的驱动信号是否正常进行准确检测。
Description
相关申请
本申请要求于2021年12月8号申请的、申请号为202111493049.1的中国专利申请的优先权。
本申请实施例涉及电力电子技术领域,特别涉及一种驱动检测方法、开关电源、电子设备及存储介质。
随着通信技术的不断更新进步,运用开关电源为通信设备提供支持的场景也越来越多,开关电源不断往高功率密度和高效率方向发展,在这样的应用场景中,多相交错功率因素校正技术(Power Factor Correction,PFC)、直流转换(DC-DC)技术和软开关技术的应用也越来越多。
为了保证开关电源的安全性和可靠性,出厂和使用时需要对多相交错开关电源各支路能否正常工作进行核验。目前,对于传统的开关电源多相交错PFC或者DCDC,一般是直接使用控制环路中采样的各路电流值大小来判断各个支路是否正常工作;或者,不单独增加检测电路去判断生产出来的产品各路PFC及DCDC是否工作正常;而是产线通过功能测试工装去测试上电后各支路工作情况。但是,采用第一种方案时,对于临界模式PFC其控制环路中不需要采集功率回路中的电流大小,或者不单独采样各路PFC或者DCDC支路电流,为了检测多相交错电路中某一路工作是否正常,需在每一路单独增加电流检测电路,极大的增加成本和空间。采用第二种方案时,上电测试的过程中存在损坏电源的风险,同时裸机上电后去测试也会为测试人员带来触电风险,同时需要非常专业人员根据测试结果判定各支路是否工作正常,检测和判断过程风险和难度都较大。
因此,如何简单高效的对开关电源的多相交错电路能否正常工作进行检测,避免产品检测过程中损毁产品或者发生安全事故成为了迫在眉睫的问题。
发明内容
本申请实施例的目的在于解决上述问题,提供一种驱动检测方法、开关电源、电子设备及存储介质,通过对功率半导体驱动引脚的驱动信号进行采样和检测,简单高效的对开关电源交错电路拓扑的驱动信号是否正常进行准确检测。
为实现上述目的,本申请实施例提供了一种驱动检测方法,应用于开关电源,包括:对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号;根据交错电路拓扑的驱动类型,获取参考信号;检测驱动采样信号与获取的参考信号是否一致,在电平信号与参考信号不一致的情况下,判定开关电源存在驱动异常。
为实现上述目的,本申请实施例还提供了一种开关电源,包括:采样模块,用于对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号;获取 模块,用于根据交错电路拓扑的驱动类型,获取参考信号;检测模块,用于检测驱动采样信号与获取的参考信号是否一致,在驱动采样信号与参考信号不一致的情况下,判定开关电源存在驱动异常。
为实现上述目的,本申请实施例还提供了一种电子设备,包括:至少一个处理器;以及,与至少一个处理器通信连接的存储器;其中,存储器存储有可被至少一个处理器执行的指令,指令被至少一个处理器执行,以使至少一个处理器能够执行如上所述的驱动检测方法。
为实现上述目的,本申请实施例还提供了一种计算机可读存储介质,存储有计算机程序,计算机程序被处理器执行时实现如上所述的驱动检测方法。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明,这些示例性说明并不构成对实施例的限定,附图中具有相同参考数字标号的元件表示为类似的元件,除非有特别申明,附图中的图不构成比例限制。
图1是本申请实施例中的驱动检测方法流程图;
图2是本申请实施例中的一种交错电路拓扑的驱动异常检测电路的结构示意图;
图3是本申请实施例中的一种驱动采样信号电平波形的示意图;
图4是本申请实施例中的一种信号检测电路的结构示意图;
图5是本申请实施例中的一种模拟电压波形的示意图;
图6是本申请实施例中的一种信号输入电路的结构示意图;
图7是本申请实施例中的一种差分放大电路的结构示意图;
图8是本申请实施例中的一种图腾柱PFC电路的结构示意图;
图9是本申请实施例中的另一种信号输入电路的结构示意图;
图10是本申请另一实施例中的开关电源结构示意图;
图11是本申请另一实施例中的电子设备的结构示意图。
由背景技术可知,在当下较为常用的驱动异常检测方法中,增加电流检测电路,极大的增加成本和空间;通过工装进行上电测试的过程中存在损坏电源和触电的风险,并且结果分析较为复杂。因此,如何简单高效的对开关电源的多相交错电路能否正常工作进行检测,避免产品检测过程中损毁产品或者发生安全事故是一个迫切需要得到解决的问题。
为了解决上述问题,本申请的实施例提供了一种驱动检测方法,应用于开关电源,包括:对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号;根据交错电路拓扑的驱动类型,获取参考信号;检测驱动采样信号与获取的参考信号是否一致,在电平信号与参考信号不一致的情况下,判定开关电源存在驱动异常。
本申请实施例提供的驱动检测方法,在进行交错电路拓扑驱动检测的过程中,对功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号,然后根据交错电路拓扑的驱动类型,获取对应的参考信号,并根据获取的驱动采样信号和参考信号的一致性对开关电源的交错电路拓扑中是否存在驱动异常进行准确判断。通过对交错电路拓扑中功率半导体驱动引脚上的驱动信号进行采样,并将驱动采样信号与根据驱动类型确定的参考信号进行一 致性对比,实现对开关电源的交错电路拓扑中是否存在驱动缺失或异常的简单高效的自检测。避免了设置额外的电流检测电路带来的成本和空间需求,以及利用工装进行上电测试时存在的风险,保证驱动异常检测准确性的同时,极大地简化开关电源交错电路拓扑中驱动异常的检测过程。
为使本申请实施例的目的、技术方案和优点更加清楚,下面将结合附图对本申请的各实施例进行详细的阐述。然而,本领域的普通技术人员可以理解,在本申请各实施例中,为了使读者更好地理解本申请而提出了许多技术细节。但是,即使没有这些技术细节和基于以下各实施例的种种变化和修改,也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便,不应对本申请的具体实现方式构成任何限定,各个实施例在不矛盾的前提下可以相互结合相互引用。
下面将结合具体的实施例的对本申请记载的驱动检测方法的实现细节进行具体的说明,以下内容仅为方便理解提供的实现细节,并非实施本方案的必须。
本申请实施例的第一方面提供了一种驱动检测方法,驱动检测方法的流程参考图1,在一些实施例中,驱动检测方法应用于开关电源中的控制芯片,或者能够与开关电源中控制芯片通信的终端设备中,本实施例以应用于开关电源中的控制芯片为例进行说明,驱动检测方法包括以下步骤:
步骤101,对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号。
具体地说,开关电源中的控制芯片在对交错电路拓扑能够正常工作进行检测的时候,根据预先设置的驱动模式或者驱动类型,控制交错电路拓扑中的数字控制芯片、硬件电路或者定时发波电路向交错电路拓扑中各功率半导体发送驱动信号。在向功率半导体发送驱动信号后,通过采样电路对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号。通过利用采样电路对功率半导体驱动引脚上的驱动信号进行采用,准确的获取到功率半导体接收到的驱动信号,便于后续准确的对驱动信号进行一致性检测。
另外,交错电路拓扑中的功率半导体可以是三极管、场效应管(MOSFET)和绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor,IGBT)等半导体器件,或者是由上述半导体器件整合形成的复合式功率半导体器件,本实施例对此不做限制。
步骤102,根据交错电路拓扑的驱动类型,获取参考信号。
具体地说,控制芯片在控制采样电路分别对交错电路拓扑中各功率半导体进行驱动信号采样后,根据交错电路拓扑中驱动信号的发生方式,即驱动类型,确定驱动检测过程中参考信号的来源,并获取驱动检测过程中的参考信号。通过根据交错电路拓扑的驱动类型选择适当的参考信号来源以获取参考信号进行驱动检测,保证检测准确性的同时,简化驱动检测的复杂程度。
在一个例子中,控制芯片根据交错电路拓扑的驱动类型,获取参考信号,包括:在驱动类型为数字芯片驱动的情况下,将数字芯片发出的初始驱动信号作为参考信号;在驱动类型为硬件电路驱动或定时器触发驱动的情况下,将交错电路拓扑中另一功率半导体的驱动采样信号作为参考信号。由于开关电源交错电路拓扑可以应用在不同场景和电路拓扑下,因此,控制芯片根据交错电路拓扑中驱动信号的产生方式对驱动类型进行划分,并在获取参考信号时,根据驱动类型确定需要采用的参考信号的来源以获取参考信号。交错电路拓扑可以是数 字控制芯片发生两路驱动弱信号,经过驱动放大电路对驱动信号放大后传输到功率半导体的驱动引脚。此时,由于数字控制芯片能够较为简单的获取初始驱动信号的电平,以及功率半导体驱动引脚上的驱动信号的电平,则直接将数字控制芯片发出的初始驱动信号作为参考信号,比较参考信号与获取到的驱动采样信号的电平高低是否一致。交错电路拓扑还可以是由硬件电路或者定时器触发电路产生驱动信号对功率半导体进行驱动,例如,临界连续模式图腾柱PFC。直接利用软件自动识别功率半导体驱动引脚上的驱动信号和初始驱动信号是否一致时,需要对初始驱动信号和功率半导体驱动引脚上的驱动信号分别进行采样,并对采样后的结果进行时序对齐后再进行一致性比较,整个检测过程较为复杂,并且占用的芯片计算资源较大,实现难度较高。而在开关电源能够正常工作的情况下,两路功率半导体通路中至少有一路处于正常工作状态,此时,通过比较两路功率半导体驱动引脚上的驱动信号是否一致,即可检测是否存在驱动缺失或者异常的功率半导体通路。因此,控制芯片在驱动类型为硬件电路驱动或定时器触发驱动的情况下,直接将交错电路拓扑中另一路功率半导体的驱动采样信号作为参考信号,比较两个功率半导体驱动引脚上的驱动采样信号是否一致,对可能存在的驱动缺失或异常进行简单准确的检测。通过根据驱动类型确定参考信号来源以获取对应的参考信号,避免尽可能简化驱动异常检测的过程,提高检测效率的同时,保证检测的准确性。
步骤103,检测驱动采样信号与获取的参考信号是否一致,在驱动采样信号与参考信号不一致的情况下,判定开关电源存在驱动异常。
具体地说,控制芯片在获取到参考信号和功率半导体的驱动采样信号后,根据参考信号的类型,对参考信号和驱动采样信号的电平高低或者电平大小是否一致进行检测,并根据驱动采样信号和参考信号的一致性检测结果,在驱动采样信号与参考信号不一致的情况下,判定开关电源存在驱动异常。
例如,交错电路拓扑的驱动类型是数字芯片驱动,交错电路拓扑中有A和B两路场效应管通路,交错电路拓扑的驱动异常检测电路结构示意图如图2所示,其中,D1至D4为可选的二极管,R1至R3和R21至R23是可选的电阻或者电阻和电感组合,C1和C2为采样电容,Q1和Q2为场效应管。控制芯片指令数字控制芯片对Q1和Q2是否存在驱动异常进行检测时,修改芯片检测端口的滤波参数,使得数字控制芯片通过采样电路分别对Q1和Q2栅极和源极上的驱动信号进行采样,获取驱动采样信号的电平高低。然后控制数字控制芯片获取自身发送的初始驱动信号的电平高低,并对驱动采样信号与初始驱动信号的电平高低是否一致进行检测。数字控制芯片获取到的电平波形如图3所示,A路驱动采样信号的电平和参考信号的电平都是高电平,B路驱动采样信号的电平一直为低电平,判定A路驱动正常,B路驱动缺失,并向控制芯片输出判定结果。控制芯片根据数字控制芯片的输出结果,判定交错电路拓扑中B路驱动缺失。
另外,控制芯片在对交错电路拓扑中的驱动进行检测后,检测到驱动异常时,可以通过指示灯、通信指令、响铃等方式上报驱动异常告警,并且在上报告警后还可以自动启动故障关机保护,本实施例对根据检测到的驱动异常进行的具体告警处理不做限制。
在一实施例中,数字控制芯片在获取驱动采样信号的电平高低前,还可以通过预设的光耦或者信号隔离器对驱动采样信号进行信号隔离,从而尽量消除驱动采样信号中的干扰信号,保证获取到的驱动采样信号的电平高低的准确性。
在一个例子中,控制芯片在参考信号为交错电路拓扑中另一功率半导体的驱动采样信号 的情况下,在检测驱动采样信号与获取的参考信号是否一致前,还包括:对驱动采样信号和参考信号进行数模转换,获取数模转换后的两个模拟电压信号;检测驱动采样信号与获取的参考信号是否一致,包括:检测两个模拟电压信号的电压值是否一致。控制芯片在参考信号为另一功率半导体的驱动采样信号的情况下,为了便于比较驱动采样信号和参考信号的一致性,可以将参考信号和驱动采样信号输入到数模转换电路中进行数模转换,获取驱动采样信号和参考信号分别对应的模拟电压信号,并对模拟电压信号的电压值是否一致进行检测。例如,信号检测电路的结构示意图如图4所示,交错电路拓扑包括两路三极管通路,D1、D3和D21、D23为两组可选且导通方向可以互换的二极管,R1至R5和R21至R25为可选电阻,C1至C3和C21至C23为可选电容,Q1和Q2为三极管,且R4、R5、R24和R25可以是电阻,也可以是电阻电感组合。Q1通路中,D1、D3、R1、R3和C3构成Q1的驱动采样电路,C1、C2、R2、R4和R5构成Q1的数模转换电路,Q2通路的电路结构也是类似的,就不再赘述。通过驱动采样电路进行驱动采样信号获取后,将Q1的驱动采样信号和作为参考信号的Q2的驱动采样信号分别输入到数模转换电路,获取Q1驱动采样信号对应的模拟电压信号V-A和Q2驱动采样信号对应的模拟电压信号V-B,然后将模拟电压信号输入电源内部的检测电路进行判断或者通过外部工装进行检测判断。模拟电压波形如图5所示,Q1的驱动采样信号为一个平稳的电平信号,V-A的隔离后的电平大小为Q1驱动引脚上的驱动信号的电平,与占空比对应的反比例系数的乘积,对应的模拟电压信号的电压值为虚线代表的V-A,小于实线表示的驱动信号的电压值,Q2的驱动采样信号为一系列不稳定的干扰信号,此时V-B的电平接近或等于VDD电压的电平。外部工装或者电源内部的检测电路可以检测出V-A与V-B的电平不一致,上报开关电源的交错电路拓扑中存在驱动异常,并且可以进一步的对V-A和V-B的电压值进行检测,准确的上报发生驱动异常的具体通路。通过对参考信号和驱动采样信号分别进行数模转换,将电平信号转换为模拟电压信号,便于准确的对参考信号和驱动采样信号的一致性进行比较,从而准确的获取驱动采样信号和参考信号的一致性,实现对开关电源是否存在驱动异常的准确检测。在检测到开关电源存在驱动异常的情况下,还可以控制开关电源自动进入电源保护工作模式。
另外,值得一提的是,实施例中给出的电路结构示意图仅为一种可行的结构,也可以仅设置一路采样和模数转换电路,按照一定的顺序将驱动采样信号和参考信号分别输入到指定的电路中进行相应的处理,本实施例对电路的具体设置方式不做限制。
在一实施例中,控制芯片在对驱动采样信号和参考信号进行数模转换前,还包括:通过预设信号隔离装置对驱动采样信号进行信号隔离;对驱动采样信号和参考信号进行数模转换,获取数模转换后的两个模拟电压信号,包括:对经过信号隔离后的驱动采样信号和参考信号进行电平转换,获取转换后的两个模拟电压信号。控制芯片在对驱动采样信号和参考信号进行模数转换前,可以通过预设的光耦或者信号隔离器等信号隔离装置对驱动采样信号和参考信号进行隔离,使用信号隔离装置进行信号隔离的目的在于提高电路的抗干扰能力;在很多无桥PFC中控制电路往往与功率电路不共地,可以提高电路抗干扰能力和EMC;即使在控制电路和功率电路共地的PFC中,控制电路地往往单点取电容或者功率回路中其它位置,这样导致信号接入电路回路大,线路上可能串入功率回路,导致采样不精准。因此,添加信号隔离装置可以达到抑制干扰信号的效果,获取较为准确的驱动采样信号和参考信号。然后再对经过信号隔离后的驱动采样信号和参考信号进行数模转换,保证数模转换后的模拟电压 信号与原始信号的对应程度,进而保证检测结果的准确性。
在另一个例子中,控制芯片检测两个模拟电压信号的电压值是否一致,包括:检测两个模拟电压信号间的电压值误差是否小于预设误差门限;在电压值误差小于预设误差门限的情况下,判定驱动采样信号与参考信号一致;在电压值误差不小于预设误差门限的情况下,判定驱动采样信号与参考信号不一致。电压值误差和预设误差门限可以根据开关电源自身器件、设计精度以及功能需求等实际应用场景中的因素确定,本实施例对此不做限制。通过为电压值设置一个可以接受的误差门限,避免驱动检测过程中由于干扰信号或者信号转换过程中的误差对检测结果的准确性造成影响。
在另一个例子中,控制芯片检测两个模拟电压信号间的电压值误差是否小于预设误差门限,包括:将两个模拟电压信号分别作为预设差分放大电路的两个输入,并获取预设差分放大电路的输出结果;在输出结果处于预设区间的情况下,判定电压值误差小于预设误差门限;在输出结果不处于预设区间的情况下,判定电压值误差不小于预设误差门限。控制芯片通过如图6所示的信号输入电路对驱动电路中的A路功率半导体通路进行驱动信号的采样和转换,其中,G-A、S-A分别代表A路功率半导体的栅极和源极;D1、R1、R3、D3构成A路的信号采样电路;R2、R4、R5、C1、C2构成A路的数模转换电路,R4和R5可以是纯电阻也可以是电阻电感的组合;U2为光耦或者信号隔离器。控制芯片控制信号采样电路从A路功率半导体的栅极和源极获取驱动采样信号,由于驱动信号存在反向尖峰电压,所以设置D1保护U2,同时,为了避免U2的二极管端在反压时分压过大,在U2的二极管端并联电阻R3进行分压。由于驱动信号存在振荡波形及干扰尖刺,而这些干扰往往电压偏低,所以需要在线路中串接D3用于抗干扰。在完成驱动采样信号的获取后,通过数模转换电路将光耦或者信号隔离器传输来的开关信号转换为一个稳定的模拟电压信号V-A。B路功率半导体的驱动信号采样和转换也采用类似方式,得到模拟电压信号V-B。然后将V-A和V-B作为预设差分放大电路的两个输入信号,传输到差分放大电路进行差分放大。一种差分放大电路的结构示意图如图7所示,其中R6至R11为可选电阻,U1为差分运算器,Vref为参考电压,Vcc为电源电压。通过差分放大电路对两路模拟电压信号进行差分放大,得到结果V0,然后控制芯片根据V0是否处于预设区间对电压值误差是否小于预设误差门限进行判断,在输出结果V0处于预设区间的情况下,判定电压值误差小于预设误差门限;在输出结果V0不处于预设区间的情况下,判定电压值误差不小于预设误差门限,从而获取驱动采样信号和参考信号的一致性。通过根据差分放大电路的输出结果对驱动采样信号和参考信号的一致性进行检测,保证检测结果的准确性。
在另一个例子中,控制芯片检测两个模拟电压信号间的电压值误差是否小于预设误差门限,包括:将两个模拟电压信号输入数字芯片的数模采样接口,供数字芯片根据采样结果,输出两个模拟电压信号的电压差;在电压差小于第一预设门限的情况下,判定电压值误差小于预设误差门限;在电压差不小于第一预设门限的情况下,判定电压值误差不小于预设误差门限。控制芯片在对驱动采样信号和参考信号完成模数转换后,可以直接将两个模拟电压信号通过数字芯片的两个AD采样口输入数字芯片中,然后由数字芯片对两个模拟电压信号进行采样和转换后,输出两个模拟电压信号的电压差,控制芯片根据电压差和第一预设门限的关系对电压值误差是否小于预设误差门限进行判断。通过数字芯片对两个模拟电压信号的电压差进行检测,保证检测效率的同时,确保检测结果的准确性。
另外,值得一提的是,开关电源交错电路拓扑中的功率半导体可能存在上下管交替工作的情况,例如,图腾柱PFC电路。一种图腾柱PFC电路的结构示意图如图8所示,A路功率半导体和B路功率半导体均是由两个上下结构的场效应管构成,并且上下管不共地。此时,获取每一路功率半导体的驱动信号时,可以只采样上管或下管的驱动信号。或者,采用如图9所示的信号输入电路结构将上下管驱动开关信号隔离后汇聚成一个新的电平信号,并对新的电平信号进行模数转换得到每一路功率半导体的驱动信号对应的模拟电压信号。
在另一个例子中,控制芯片对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号,包括:获取预设时长内功率半导体驱动引脚上的多个驱动采样信号;检测驱动采样信号与获取的参考信号是否一致,包括:获取各驱动采样信号对应的参考信号;检测各驱动采样信号与各自对应的参考信号是否一致,获取与对应的参考信号不一致的驱动采样信号的数量;在数量大于第二预设门限的情况下,判定开关电源存在驱动异常。控制芯片对开关电源是否存在驱动异常进行检测的过程中,可以在一定时长内对功率半导体的驱动信号进行多次采样,并分别与对应的参考信号进行一致性比对,在检测到达到一定数量的驱动采样信号和参考信号不一致的情况下,再判定开关电源存在驱动异常。通过多次采样和检测,避免单次采样的时候由于偶然因素或者各种干扰信号对检测结果造成偶然性影响,进一步保证检测结果的准确性。
此外,应当理解的是,上面各种方法的步骤划分,只是为了描述清楚,实现时可以合并为一个步骤或者对某些步骤进行拆分,分解为多个步骤,只要包括相同的逻辑关系,都在本申请的保护范围内;对算法中或者流程中添加无关紧要的修改或者引入无关紧要的设计,但不改变其算法和流程的核心设计都在该申请的保护范围内。
本申请实施例的另一方面涉及一种开关电源,参考图10,包括:
采样模块1001,用于对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取功率半导体的驱动采样信号。
获取模块1002,用于根据交错电路拓扑的驱动类型,获取参考信号。
检测模块1003,用于检测驱动采样信号与获取的参考信号是否一致,在驱动采样信号与参考信号不一致的情况下,判定开关电源存在驱动异常。
不难发现,本实施例为与方法实施例相对应的装置实施例,本实施例可与方法实施例互相配合实施。方法实施例中提到的相关技术细节在本实施例中依然有效,为了减少重复,这里不再赘述。相应地,本实施例中提到的相关技术细节也可应用在方法实施例中。
值得一提的是,本实施例中所涉及到的各模块均为逻辑模块,在实际应用中,一个逻辑单元可以是一个物理单元,也可以是一个物理单元的一部分,还可以以多个物理单元的组合实现。此外,为了突出本申请的创新部分,本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入,但这并不表明本实施例中不存在其它的单元。
本申请实施例的另一方面还提供了一种电子设备,参考图11,包括:包括至少一个处理器1101;以及,与至少一个处理器1101通信连接的存储器1102;其中,存储器1102存储有可被至少一个处理器1101执行的指令,指令被至少一个处理器1101执行,以使至少一个处理器1101能够执行上述任一方法实施例所描述的驱动检测方法。
其中,存储器1102和处理器1101采用总线方式连接,总线可以包括任意数量的互联的总线和桥,总线将一个或多个处理器1101和存储器1102的各种电路连接在一起。总线还可 以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路连接在一起,这些都是本领域所公知的,因此,本文不再对其进行进一步描述。总线接口在总线和收发机之间提供接口。收发机可以是一个元件,也可以是多个元件,比如多个接收器和发送器,提供用于在传输介质上与各种其他装置通信的单元。经处理器1101处理的数据通过天线在无线介质上进行传输,进一步,天线还接收数据并将数据传输给处理器1101。
处理器1101负责管理总线和通常的处理,还可以提供各种功能,包括定时,外围接口,电压调节、电源管理以及其他控制功能。而存储器1102可以被用于存储处理器1101在执行操作时所使用的数据。
本申请实施例的另一方面还提供了一种计算机可读存储介质,存储有计算机程序。计算机程序被处理器执行时实现上述方法实施例。
即,本领域技术人员可以理解,实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成,该程序存储在一个存储介质中,包括若干指令用以使得一个设备(可以是单片机,芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括:U盘、移动硬盘、只读存储器(ROM,Read-OnlyMemory)、随机存取存储器(RAM,RandomAccessMemory)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的普通技术人员可以理解,上述各实施例是实现本申请的具体实施例,而在实际应用中,可以在形式上和细节上对其作各种改变,而不偏离本申请的精神和范围。
Claims (11)
- 一种驱动检测方法,应用于开关电源,包括:对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取所述功率半导体的驱动采样信号;根据所述交错电路拓扑的驱动类型,获取参考信号;检测所述驱动采样信号与获取的所述参考信号是否一致,在所述驱动采样信号与所述参考信号不一致的情况下,判定所述开关电源存在驱动异常。
- 根据权利要求1所述的驱动检测方法,其中,所述交错电路拓扑包括至少两路功率半导体,所述根据所述交错电路拓扑的驱动类型,获取参考信号,包括:在所述驱动类型为数字芯片驱动的情况下,将所述数字芯片发出的初始驱动信号作为所述参考信号;在所述驱动类型为硬件电路驱动或定时器触发驱动的情况下,将所述交错电路拓扑中另一所述功率半导体的所述驱动采样信号作为所述参考信号。
- 根据权利要求2所述的驱动检测方法,其中,在所述参考信号为所述交错电路拓扑中另一所述功率半导体的所述驱动采样信号的情况下,在所述检测所述驱动采样信号与获取的所述参考信号是否一致前,还包括:对所述驱动采样信号和所述参考信号进行数模转换,获取数模转换后的两个模拟电压信号;所述检测所述驱动采样信号与获取的所述参考信号是否一致,包括:检测两个所述模拟电压信号的电压值是否一致。
- 根据权利要求3所述的驱动检测方法,其中,所述检测两个所述模拟电压信号的电压值是否一致,包括:检测两个所述模拟电压信号间的电压值误差是否小于预设误差门限;在所述电压值误差小于所述预设误差门限的情况下,判定所述驱动采样信号与所述参考信号一致;在所述电压值误差不小于所述预设误差门限的情况下,判定所述驱动采样信号与所述参考信号不一致。
- 根据权利要求4所述的驱动检测方法,其中,所述检测两个所述模拟电压信号间的电压值误差是否小于预设误差门限,包括:将两个所述模拟电压信号分别作为预设差分放大电路的两个输入,并获取所述预设差分放大电路的输出结果;在所述输出结果处于预设区间的情况下,判定所述电压值误差小于所述预设误差门限;在所述输出结果不处于所述预设区间的情况下,判定所述电压值误差不小于所述预设误差门限。
- 根据权利要求4所述的驱动检测方法,其中,所述检测两个所述模拟电压信号间的电压值误差是否小于预设误差门限,包括:将两个所述模拟电压信号输入所述数字芯片的数模采样接口,供所述数字芯片根据采样结果,输出两个所述模拟电压信号的电压差;在所述电压差小于第一预设门限的情况下,判定所述电压值误差小于所述预设误差门限;在所述电压差不小于所述第一预设门限的情况下,判定所述电压值误差不小于所述预设误差门限。
- 根据权利要求3至6中任一项所述的驱动检测方法,其中,在所述对所述驱动采样信号和所述参考信号进行数模转换前,还包括:通过预设信号隔离装置对所述驱动采样信号进行信号隔离;所述对所述驱动采样信号和所述参考信号进行数模转换,获取数模转换后的两个模拟电压信号,包括:对经过信号隔离后的所述驱动采样信号和所述参考信号进行电平转换,获取转换后的两个所述模拟电压信号。
- 根据权利要求1至6中任一项所述的驱动检测方法,其中,所述对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取所述功率半导体的驱动采样信号,包括:获取预设时长内所述功率半导体驱动引脚上的多个所述驱动采样信号;所述检测所述驱动采样信号与获取的所述参考信号是否一致,包括:获取各所述驱动采样信号对应的所述参考信号;检测各所述驱动采样信号与各自对应的所述参考信号是否一致,获取与对应的所述参考信号不一致的所述驱动采样信号的数量;在所述数量大于第二预设门限的情况下,判定所述开关电源存在驱动异常。
- 一种开关电源,包括:采样模块,设置为对交错电路拓扑中功率半导体驱动引脚上的信号进行采样,获取所述功率半导体的驱动采样信号;获取模块,设置为根据所述交错电路拓扑的驱动类型,获取参考信号;检测模块,设置为检测所述驱动采样信号与获取的所述参考信号是否一致,在所述驱动采样信号与所述参考信号不一致的情况下,判定所述开关电源存在驱动异常。
- 一种电子设备,包括:至少一个处理器;以及,与所述至少一个处理器通信连接的存储器;其中,所述存储器存储有可被所述至少一个处理器执行的指令,所述指令被所述至少一个处理器执行,以使所述至少一个处理器能够执行如权利要求1至8中任一项所述的驱动检测方法。
- 一种计算机可读存储介质,存储有计算机程序,其中,所述计算机程序被处理器执行时实现权利要求1至8中任一项所述的驱动检测方法。
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Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5744986A (en) * | 1993-04-28 | 1998-04-28 | Kabushiki Kaisha Toshiba | Source driver circuit device having improved level correction circuit for driving liquid crystal display |
CN103533703A (zh) * | 2012-06-28 | 2014-01-22 | 三星电机株式会社 | 用于驱动led灯的电路及方法 |
CN104486891A (zh) * | 2014-12-30 | 2015-04-01 | 杭州士兰微电子股份有限公司 | Led驱动电路及恒定电流驱动器 |
CN109638785A (zh) * | 2019-01-31 | 2019-04-16 | 杭州士兰微电子股份有限公司 | 开关电源的控制电路、开关电源及其控制方法 |
CN110391806A (zh) * | 2018-04-23 | 2019-10-29 | 三菱电机株式会社 | 半导体元件的驱动装置 |
CN110798939A (zh) * | 2019-11-11 | 2020-02-14 | 杰华特微电子(张家港)有限公司 | Led驱动电路及方法 |
CN111404525A (zh) * | 2020-03-25 | 2020-07-10 | 美的集团股份有限公司 | 信号检测电路、开关管驱动控制电路、控制方法及空调器 |
CN112345982A (zh) * | 2020-09-29 | 2021-02-09 | 歌尔科技有限公司 | 电路元件焊接情况检测方法及装置 |
CN112787505A (zh) * | 2019-11-11 | 2021-05-11 | 圣邦微电子(北京)股份有限公司 | 一种dc-dc变换器及其控制电路和控制方法 |
CN112996189A (zh) * | 2021-04-09 | 2021-06-18 | 杭州士兰微电子股份有限公司 | Led驱动装置及其驱动控制电路 |
-
2021
- 2021-12-08 CN CN202111493049.1A patent/CN116299020A/zh active Pending
-
2022
- 2022-12-06 WO PCT/CN2022/137035 patent/WO2023104060A1/zh unknown
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5744986A (en) * | 1993-04-28 | 1998-04-28 | Kabushiki Kaisha Toshiba | Source driver circuit device having improved level correction circuit for driving liquid crystal display |
CN103533703A (zh) * | 2012-06-28 | 2014-01-22 | 三星电机株式会社 | 用于驱动led灯的电路及方法 |
CN104486891A (zh) * | 2014-12-30 | 2015-04-01 | 杭州士兰微电子股份有限公司 | Led驱动电路及恒定电流驱动器 |
CN110391806A (zh) * | 2018-04-23 | 2019-10-29 | 三菱电机株式会社 | 半导体元件的驱动装置 |
CN109638785A (zh) * | 2019-01-31 | 2019-04-16 | 杭州士兰微电子股份有限公司 | 开关电源的控制电路、开关电源及其控制方法 |
CN110798939A (zh) * | 2019-11-11 | 2020-02-14 | 杰华特微电子(张家港)有限公司 | Led驱动电路及方法 |
CN112787505A (zh) * | 2019-11-11 | 2021-05-11 | 圣邦微电子(北京)股份有限公司 | 一种dc-dc变换器及其控制电路和控制方法 |
CN111404525A (zh) * | 2020-03-25 | 2020-07-10 | 美的集团股份有限公司 | 信号检测电路、开关管驱动控制电路、控制方法及空调器 |
CN112345982A (zh) * | 2020-09-29 | 2021-02-09 | 歌尔科技有限公司 | 电路元件焊接情况检测方法及装置 |
CN112996189A (zh) * | 2021-04-09 | 2021-06-18 | 杭州士兰微电子股份有限公司 | Led驱动装置及其驱动控制电路 |
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