WO2023103296A1

WO2023103296A1 - Write data cache method and system, device, and storage medium

Info

Publication number: WO2023103296A1
Application number: PCT/CN2022/095380
Authority: WO
Inventors: 王江; 李树青; 孙华锦
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2021-12-09
Filing date: 2022-05-26
Publication date: 2023-06-15
Also published as: CN113918101B; CN113918101A; US20240264940A1

Abstract

A write data cache method and system, a device, and a storage medium. The method comprises: in response to receiving a write data operation instruction sent by a host, creating a control page table and sequentially filling the control page table with a plurality of control blocks; submitting an entry pointer of a first control block to a work queue scheduling engine so as to alternately execute in the work queue scheduling engine tasks corresponding to the plurality of control blocks; sending a completion response to the host in advance and notifying firmware to perform subsequent data processing and writing to a disk; and, in response to the completion of the execution of the task corresponding to the last control block, releasing the used control page table resource.

Description

Method, system, device and storage medium for writing data cache

Cross References to Related Applications

This application claims the priority of the Chinese patent application submitted to the China Patent Office on December 09, 2021, with the application number 202111497794.3, and the application name is "A method, system, device and storage medium for writing data cache", all of which The contents are incorporated by reference in this application.

technical field

The present application relates to a method, system, device and storage medium for writing data cache.

Background technique

With the rise of computing storage (Computational Storage) technology in recent years, the computing storage architecture reduces the corresponding data by offloading data calculation from the host CPU (Central Processing Unit, central processing unit) to the data processing acceleration unit close to the storage unit. The moving operation, thus releasing the system performance as much as possible.

Computational Storage introduces three product forms: Computational Storage Processor (CSP), Computational Storage Drive (CSD) and Computational Storage Array (CSA), and looks forward to redefining the architecture To reduce CPU usage, reduce network and DDR (Double Data Rate, double-rate synchronous dynamic random access memory) bandwidth consumption, reduce system power consumption, and support potential large-scale parallel computing processing.

In the computing storage system, a typical application is to use the built-in DDR in the computing storage system as a data cache (cache), cache the data of the host read/write operation, and the purpose is to reduce the system IO (Input Output, input and output ) operation delay. Take the IO write operation of the host as an example. Normally, the host can only respond after the data is reliably written to the disk. However, after the Write Cache function is enabled, the computing storage system will send a response signal to the host after moving the data to be dropped from the host DDR to the power-failure protected area of the local DDR, so that the host thinks The data has completed the "drop" operation. In fact, the calculation and storage system for this data block is still carried out step by step within the system. After the processing is completed, it will be merged and other conditions will be met, and finally the storage operation will be performed.

The inventor realizes that how to realize the write IO data cache function in the computing storage-oriented general computing acceleration architecture is a problem that needs to be solved.

Contents of the invention

Based on the various embodiments disclosed in the present application, one aspect of the embodiments of the present application provides a method for writing data cache, including the following steps: in response to receiving a write data operation command sent by the host, creating a control page table and writing to the Filling in a plurality of control blocks in turn in the control page table; submitting the entry pointer of the first control block to the work queue scheduling engine to intersperse and execute the tasks corresponding to the multiple control blocks in the work queue scheduling engine; Send a completion response to the host in advance and notify the firmware to perform subsequent data processing and storage; and release the used control page table resources in response to the completion of the task execution corresponding to the last control block.

In one or more embodiments, the last control block refers to the control block of steps required for subsequent operations after the firmware takes over.

In one or more embodiments, the creating a control page table and sequentially filling a plurality of control blocks into the control page table includes: filling the first control block into the control page table to double setting a memory area in the double rate synchronous dynamic random access memory; filling the second control block into the control page table to migrate the data to be written in the host double rate synchronous dynamic random access memory to the memory area; Fill in the third control block in the control page table to answer the host and end the current input and output.

In one or more embodiments, the method further includes: performing power-off protection for the written data in the memory area of the local double-rate synchronous DRAM.

In one or more embodiments, it also includes: in response to insufficient control page table space, applying for a new control page table space to create a new control page table, and combining the new control page table with the original control page table Initialized as a chained control page table.

In one or more embodiments, the method further includes: in response to receiving a data read operation instruction from the host, creating an empty control page table and backing up the data read operation instruction into the empty control page table.

In one or more embodiments, the method further includes: storing on-chip a continuous storage space as a resource pool of the control page table, and initializing the address pointer of each control page table into a list of free control page table entries.

In one or more embodiments, it also includes: judging whether the count of the firmware's claimed control page table is less than a threshold; The count is increased by one, and the count of the host interface management engine's claimed control page table is decreased by one.

Another aspect of the embodiment of the present application provides a system for writing data cache, including: a creation module configured to create a control page table and write to the control page in response to receiving a write data operation command sent by the host A plurality of control blocks are filled in the table in turn; a submission module is configured to submit the entry pointer of the first control block to the work queue scheduling engine to intersperse the tasks corresponding to the multiple control blocks in the work queue scheduling engine Execution; notification module, configured to send a completion response to the host in advance and notify the firmware to perform subsequent data processing and disk placement; and release module, configured to respond to the end of the task execution corresponding to the last control block, to control the used Page table resources are released.

In yet another aspect of the embodiments of the present application, there is also provided a computer device, including: one or more processors and a memory, the memory stores computer-readable instructions that can be run on the processors, and the computer When the readable instructions are executed by the one or more processors, the one or more processors are executed to perform the steps of any one of the methods for writing data cache.

In yet another aspect of the embodiments of the present application, one or more non-volatile computer-readable storage media storing computer-readable instructions is provided. When the computer-readable instructions are executed by one or more processors, one or more A plurality of processors execute the steps of any one of the methods for writing data cache described above.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features and advantages of the application will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application, and those skilled in the art can obtain other embodiments according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a method for writing a data cache provided by the present application.

FIG. 2 is a schematic diagram of a general computing acceleration architecture provided by the present application.

FIG. 3 is a schematic diagram of the processing flow of the general computing acceleration framework provided by the present application.

FIG. 4 is a schematic diagram of the management of the control page table resource pool provided by the present application.

FIG. 5 is a schematic diagram of an embodiment of a system for writing a data cache provided by the present application.

FIG. 6 is a schematic diagram of a hardware structure of an embodiment of a computer device for writing a data cache provided by the present application.

FIG. 7 is a schematic diagram of an embodiment of a computer storage medium for writing data cache provided by the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of this application are to distinguish between two entities with the same name but different parameters or parameters that are not the same, see "first" and "second" It is only for the convenience of expression, and should not be construed as a limitation on the embodiments of the present application, which will not be described one by one in the subsequent embodiments.

The first aspect of the embodiments of the present application provides an embodiment of a method for writing a data cache. FIG. 1 is a schematic diagram of an embodiment of a method for writing a data cache provided by the present application. As shown in Figure 1, the embodiment of the present application includes the following steps:

S1. Create a control page table and sequentially fill a plurality of control blocks into the control page table in response to receiving a write data operation instruction sent by the host;

S2. Submit the entry pointer of the first control block to the work queue scheduling engine to intersperse and execute the tasks corresponding to the multiple control blocks in the work queue scheduling engine;

S3. Send a completion response to the host in advance and notify the firmware to perform subsequent data processing and storage; and

S4. In response to the completion of execution of the task corresponding to the last control block, release the used control page table resources.

The core idea of this application is that special hardware is needed to offload some of the functions of the firmware, and the two are organically integrated. Figure 2 is a schematic diagram of the general computing acceleration architecture provided by the present application. As shown in Figure 2, the embodiment of the present application introduces two new engines in the control plane: HDMA (Host Direct Memory Access, host direct memory access) engine: responsible for Move data between host DDR and local DDR; dynamic memory management engine (Hmalloc: HW Malloc, hardware dynamic memory management): the hardware module is responsible for managing the allocation and release of local DDR. The embodiment of this application expands the function of AEM (Acceleration Engine Manager, host interface management engine), so that it can also create CP (Control Page, control page table) and compile CB (Control Block, control block), so that Before the firmware operation is introduced, a series of curing operations are completed relying solely on the hardware module.

FIG. 3 is a schematic diagram of the processing flow of the general computing acceleration framework provided by the present application, and the embodiment of the present application will be described with reference to FIG. 3 .

In response to receiving a write data operation command sent by the host, create a control page table and fill in multiple control blocks in sequence into the control page table. The host interface management engine is responsible for interface host instructions, and analyze the host instructions. If it is a write IO operation instruction, the host interface management engine will create a common control page table and fill it with multiple control blocks accordingly. The embodiment of the present application has the following beneficial technical effects: through the cooperative scheduling process of the host interface management engine and the firmware system, the scenario where the write cache is enabled is applicable, and the control page table is transferred from the host interface management engine to the firmware in a "zero copy" manner. The transfer can significantly reduce the latency performance of the computing storage system to respond to the host.

In one or more embodiments, the creating a control page table and sequentially filling a plurality of control blocks into the control page table includes: filling the first control block into the control page table to double setting a memory area in the rate synchronous DRAM; filling the second control block into the control page table to migrate the data to be written in the host double rate synchronous DRAM to the memory area; The third control block is filled in the control page table to answer the host and end the current input and output. For example: "Hmalloc" CB: used to open a piece of memory in the local DDR through the hardware engine; "HDMA" CB: used to move the data to be written in the host DDR to the storage space opened in the local DDR through the hardware engine ; "AEM-Response" CB: used to respond to the host through the hardware engine, indicating that the data to be written has been processed and the current IO can be ended.

The entry pointer of the first control block is submitted to the work queue scheduling engine so that the tasks corresponding to the multiple control blocks are interspersed and executed in the work queue scheduling engine. After the host interface management engine completes the above operations, it will submit the entry pointer of the first control block to WQS (Work Queue Scheduler, work queue scheduling engine) for automatic hardware scheduling. WQS is responsible for scheduling these three tasks in sequence and interspersed between engines implement.

Send a completion response to the host in advance and notify the firmware to perform subsequent data processing and storage. While giving the host a false "Complete" response in advance, the firmware is notified to perform subsequent data processing and disk placement. This constitutes a fast response path for writing to the Cache, which greatly shortens the delay characteristic of responding to the host.

In one or more embodiments, the method further includes: performing power-off protection for the written data in the memory area of the local double-rate synchronous DRAM. After the write cache function is turned on, because the host has responded in advance, it is necessary to perform power-off protection on the pending write data of the local DDR, otherwise it will cause a fatal error.

In one or more embodiments, it also includes: in response to insufficient control page table space, applying for a new control page table space to create a new control page table, and combining the new control page table with the original control page table Initialized as a chained control page table. After the firmware takes over, the control blocks of the steps required for subsequent operations can continue to be filled in the first common control page table. When the control page table space is not enough, you can continue to apply for a new control page table space and initialize it into a chain Control the page table, and fill the remaining steps to the corresponding positions of the chained control page table.

In response to the end of execution of the task corresponding to the last control block, the used control page table resources are released. The firmware submits the entry pointer of the subsequent first control block to WQS for automatic hardware scheduling. After the execution of the last control block is completed, the firmware will be notified and release the control page table resources used by the IO.

In one or more embodiments, the method further includes: in response to receiving a data read operation instruction from the host, creating an empty control page table and backing up the data read operation instruction into the empty control page table. When receiving other IO commands, such as read commands and management command commands, the host interface management engine only needs to create an "empty" control page table, and after backing up the original IO commands into the control page table, it can pass WQS. The hardware event queue notifies the firmware to take over processing.

In the architecture definition of the general computing acceleration architecture, the size of the control page table can be 512 bytes, 1024 bytes or 2048 bytes. Except for the control page table header, data cache and original host IO command backup, the remaining space is all Used to store control blocks. All control page tables are placed in a continuous memory space, thus forming a resource pool of control page tables. In addition, in order to facilitate the management of the control page table resource pool, the granularity of the control page table in a single resource pool needs to be consistent, that is, only one size of the control page table can be selected. In order to achieve the optimal write data cache performance, there are two problems to be solved: 1. The allocation and release of CP resources; 2. In the process of interaction between AEM and firmware, how to quickly transfer the CP claimed by AEM to the firmware transfer.

To solve the first problem above, the CP resource pool is managed through a unified hardware logic. Assuming that the total number of CP resources in the CP resource pool is K, because both AEM and firmware will apply for CP, assuming that the upper limit of the number of CP pages used by AEM and firmware is m and n respectively, then it is necessary to ensure that K=m+n .

In one or more embodiments, the method further includes: storing on-chip a continuous storage space as a resource pool of the control page table, and initializing the address pointer of each control page table into a list of free control page table entries. FIG. 4 is a schematic diagram of the management of the control page table resource pool provided by the present application. On-chip storage opens up a continuous storage space as a CP resource pool, and initializes the address pointer of each CP into a "free CP entry list". The "head" and "tail" pointers of the list are managed by hardware. When applying for CP resources, read the CP entry address from the head pointer and update the applied count value of AEM/firmware. When releasing CP resources, store the CP entry address to be released from the tail pointer and update the applied count of AEM/firmware value. When AEM wants to apply for or release CP, it directly operates through hardware logic; the firmware completes it by accessing the "claim CP" and "release CP" registers. When claiming, it directly tries to read the "claim CP" register. And judge whether it is a valid CP entry address from a certain flag bit of the read content. When releasing, directly write the entry address of the CP to be released into the "Release CP" register, and write it into the "Idle CP" register with hardware logic. entry list". Every time AEM and firmware apply for CP resources, they will compare the counters they have claimed with the corresponding upper limit. If the upper limit has been reached, the current claim fails, and you can wait for a period of time and try again.

In one or more embodiments, it also includes: judging whether the count of the firmware's claimed control page table is less than a threshold; The count is increased by one, and the count of the host interface management engine's claimed control page table is decreased by one. In response to the second problem above, when AEM passes the CP created at the beginning to the firmware for subsequent processing, if the CP content is copied to the CP newly claimed by the firmware, and then the CP claimed by AEM is released, it will increase Bus bandwidth consumption, and additional delay. In the embodiment of the present application, through the unified management of the aforementioned CP resource pool, it is realized by handing over the ownership of the CP when the AEM hands over the CP to the firmware. After AEM notifies the firmware through the hardware event queue, it completes the transfer of CP ownership by adding "AEM has claimed CP count -1" and "firmware has claimed CP count +1". Through this "zero copy" method, AEM can use the increased available CP resources to receive the next host management or IO request, and the firmware will continue to be responsible for subsequent processing until the CP resources are released after the end.

The universal computing acceleration architecture of the embodiment of the present application unloads the firmware by hardening some fixed steps, which can significantly reduce the latency performance of the computing storage system responding to the host in the application scenario of writing IO to the Cache.

It should be pointed out in particular that each step in each embodiment of the method for writing data cache can be interleaved, replaced, added, or deleted. It should belong to the protection scope of the present application, and should not limit the protection scope of the present application to the embodiment.

It should be understood that although the various steps in the flow chart of FIG. 1 are displayed sequentially as indicated by the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Fig. 1 may include multiple sub-steps or multiple stages, these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, the execution of these sub-steps or stages The order is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

Based on the above purpose, a second aspect of the embodiments of the present application proposes a system for writing data cache. As shown in FIG. 5, the system 200 includes the following modules: a creation module configured to create a control page table and fill in multiple control blocks in sequence in the control page table in response to receiving a write data operation command sent by the host; The submission module is configured to submit the entry pointer of the first control block to the work queue scheduling engine so that the tasks corresponding to the multiple control blocks are interspersed and executed in the work queue scheduling engine; the notification module is configured to advance to the The host sends a completion response and notifies the firmware to perform subsequent data processing and storage; and the release module is configured to release the used control page table resources in response to the end of execution of the task corresponding to the last control block.

In one or more embodiments, the last control block is configured as a control block for steps required for subsequent operations after the firmware takes over.

In one or more embodiments, the creation module is configured to: fill the first control block into the control page table to set a memory area in the local double-rate synchronous dynamic random access memory; Fill in the second control block in the table to migrate the data to be written in the double rate synchronous DRAM of the host to the memory area; and fill in the third control block in the control page table to answer the host and end current input and output.

In one or more embodiments, the system further includes a protection module configured to: perform power-off protection on data written in the memory area of the local double-rate synchronous dynamic random access memory.

In one or more embodiments, the system further includes an application module configured to: in response to insufficient control page table space, apply for a new control page table space to create a new control page table, and assign the new The control page table and the original control page table are initialized as chained control page tables.

In one or more embodiments, the system further includes a second creation module, and the second creation module is configured to: in response to receiving a read data operation command sent by the host, create an empty control page table and perform the read data operation Instructions are backed up into the empty control page table.

In one or more embodiments, the system further includes a resource module, and the resource module is configured to: open up a continuous storage space on the chip as a resource pool of the control page table, and initialize the address pointer of each control page table into a list of free control page table entries.

In one or more embodiments, the system further includes a judging module configured to: judge whether the count of the firmware's claimed control page table is less than a threshold; and in response to the count of the firmware's claimed control page table being less than the threshold, Increment the count of the control page table claimed by the firmware by one, and decrement the count of the control page table claimed by the host interface management engine by one.

Based on the above purpose, the third aspect of the embodiments of the present application proposes a computer device, including: a memory and one or more processors, the memory stores computer-readable instructions, and the computer-readable instructions are processed by one or more When executed by a processor, the one or more processors are executed to execute the method for writing a data cache in any of the foregoing embodiments.

As shown in FIG. 6 , it is a schematic diagram of the hardware structure of one or more embodiments of the computer device for writing data cache provided in this application.

Taking the device shown in FIG. 6 as an example, the device includes a processor 301 and a memory 302 .

The processor 301 and the memory 302 may be connected through a bus or in other ways, and connection through a bus is taken as an example in FIG. 6 .

The memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the method for writing data cache in the embodiment of the present application. program instructions/modules. The processor 301 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 302 , that is, implements the method of writing data cache.

The memory 302 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created by using the method of writing data cache, etc. . In addition, the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 302 may optionally include memory that is remotely located relative to the processor 301, and these remote memories may be connected to the local module through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

One or more computer-readable instructions 303 corresponding to the method of writing data cache are stored in memory 302 , and when executed by processor 301 , execute the method of writing data cache in any of the above method embodiments.

Any one or more embodiments of a computer device that executes the above-mentioned method for writing a data cache can achieve the same or similar effect as any of the foregoing method embodiments corresponding thereto.

The present application also provides one or more non-volatile computer-readable storage media storing computer-readable instructions, the computer-readable storage medium storing computer-readable instructions for performing a method of writing data cache when executed by a processor .

As shown in FIG. 7 , it is a schematic diagram of one or more embodiments of the computer storage medium for writing data cache provided in this application. Taking the non-volatile computer-readable storage medium shown in FIG. 7 as an example, the computer-readable storage medium 401 stores computer-readable instructions 402 for executing the above method when executed by a processor.

Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be realized by computer-readable instructions to instruct related hardware to complete, and the program of the method of writing data cache can be stored in a In the computer-readable storage medium, when the program is executed, it may include the processes of the embodiments of the above-mentioned methods. Wherein, the storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), and the like. The above embodiments of computer-readable instructions can achieve the same or similar effect as any of the above-mentioned method embodiments corresponding thereto.

The above are the exemplary embodiments disclosed in the present application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed in the present application defined by the claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present application may be described or required in an individual form, they may also be understood as plural unless explicitly limited to a singular number.

It should be understood that as used herein, the singular form "a" and "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The serial numbers of the embodiments disclosed in the above-mentioned embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above-mentioned embodiments can be completed by hardware, or can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. The above-mentioned The storage medium may be a read-only memory, a magnetic disk or an optical disk, and the like.

Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is exemplary only, and is not intended to imply that the scope (including claims) disclosed by the embodiments of the present application is limited to these examples; under the idea of the embodiments of the present application , the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present application, which are not provided in details for the sake of brevity. Therefore, within the spirit and principle of the embodiments of the present application, any omissions, modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the embodiments of the present application.

Claims

A method for writing a data cache, comprising:

In response to receiving a write data operation command sent by the host, creating a control page table and sequentially filling a plurality of control blocks into the control page table;

Submitting the entry pointer of the first control block to the work queue scheduling engine to intersperse the tasks corresponding to the multiple control blocks in the work queue scheduling engine;

Send a completion response to the host in advance and notify the firmware to perform subsequent data processing and storage; and

In response to the end of execution of the task corresponding to the last control block, the used control page table resources are released.
The method according to claim 1, wherein said creating a control page table and sequentially filling a plurality of control blocks into said control page table comprises:

filling the first control block into the control page table to set the memory area in the local double rate synchronous dynamic random access memory;

Filling the second control block into the control page table to migrate the data to be written in the host double rate synchronous DRAM to the memory area; and

Fill the third control block into the control page table to answer the host and end the current input and output.
The method according to claim 2, further comprising:

Power-down protection is performed on the written data in the memory area of the local double-rate synchronous dynamic random access memory.
The method according to claim 1, further comprising:

In response to insufficient control page table space, apply for new control page table space to create a new control page table, and initialize the new control page table and the original control page table as chained control page tables.
The method according to claim 1, further comprising:

In response to receiving a read data operation instruction from the host, create an empty control page table and back up the read data operation instruction into the empty control page table.
The method according to claim 1, further comprising:

On-chip storage opens up a continuous storage space as a resource pool for the control page table, and initializes the address pointer of each control page table into a free control page table entry list.
The method according to claim 6, further comprising:

judging whether the count of the firmware's claimed control page table is less than a threshold; and

In response to the count of the firmware's claimed control page table being less than a threshold, the count of the firmware's claimed control page table is increased by one, and the count of the host interface management engine's claimed control page table is decreased by one.
The method according to claim 1, characterized in that, the last control block refers to a control block of steps required for subsequent operations after the firmware takes over.
A system for writing data caches, comprising:

Create a module configured to create a control page table and fill in a plurality of control blocks sequentially in the control page table in response to receiving a write data operation instruction sent by the host;

The submission module is configured to submit the entry pointer of the first control block to the work queue scheduling engine so that the tasks corresponding to the multiple control blocks are interspersed and executed in the work queue scheduling engine;

The notification module is configured to send a completion response to the host in advance and notify the firmware to perform subsequent data processing and storage; and

The release module is configured to release the used control page table resources in response to the end of execution of the task corresponding to the last control block.
A computer device, characterized in that it includes a memory and one or more processors, the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the one or more processors, the One or more processors execute the steps of the method according to any one of claims 1-8.
One or more non-transitory computer-readable storage media storing computer-readable instructions, wherein when the computer-readable instructions are executed by one or more processors, the one or more processors Performing the steps of the method according to any one of claims 1-8.