WO2023102702A1 - 一种信号采集电路及可穿戴设备 - Google Patents

一种信号采集电路及可穿戴设备 Download PDF

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Publication number
WO2023102702A1
WO2023102702A1 PCT/CN2021/135877 CN2021135877W WO2023102702A1 WO 2023102702 A1 WO2023102702 A1 WO 2023102702A1 CN 2021135877 W CN2021135877 W CN 2021135877W WO 2023102702 A1 WO2023102702 A1 WO 2023102702A1
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Prior art keywords
capacitance
negative
circuit
signal acquisition
amplifier
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PCT/CN2021/135877
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English (en)
French (fr)
Inventor
邓文俊
张宇翔
廖风云
齐心
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深圳市韶音科技有限公司
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Application filed by 深圳市韶音科技有限公司 filed Critical 深圳市韶音科技有限公司
Priority to EP21966630.2A priority Critical patent/EP4362330A4/en
Priority to PCT/CN2021/135877 priority patent/WO2023102702A1/zh
Priority to KR1020247004406A priority patent/KR20240032101A/ko
Priority to CN202180099578.5A priority patent/CN117529881A/zh
Priority to JP2024515694A priority patent/JP2024530830A/ja
Publication of WO2023102702A1 publication Critical patent/WO2023102702A1/zh
Priority to US18/411,062 priority patent/US20240154581A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/25—Bioelectric electrodes therefor
    • A61B5/251—Means for maintaining electrode contact with the body
    • A61B5/256—Wearable electrodes, e.g. having straps or bands
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/30—Input circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/011—Arrangements for interaction with the human body, e.g. for user immersion in virtual reality
    • G06F3/015—Input arrangements based on nervous system activity detection, e.g. brain waves [EEG] detection, electromyograms [EMG] detection, electrodermal response detection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/46—One-port networks
    • H03H11/52—One-port networks simulating negative resistances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/261—Amplifier which being suitable for instrumentation applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45138—Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45151—At least one resistor being added at the input of a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45156—At least one capacitor being added at the input of a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45512—Indexing scheme relating to differential amplifiers the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45546—Indexing scheme relating to differential amplifiers the IC comprising one or more capacitors feedback coupled to the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45548—Indexing scheme relating to differential amplifiers the IC comprising one or more capacitors as shunts to earth or as short circuit between inputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45594—Indexing scheme relating to differential amplifiers the IC comprising one or more resistors, which are not biasing resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45601—Indexing scheme relating to differential amplifiers the IC comprising one or more passive resistors by feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45604—Indexing scheme relating to differential amplifiers the IC comprising a input shunting resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45632—Indexing scheme relating to differential amplifiers the LC comprising one or more capacitors coupled to the LC by feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45698—Indexing scheme relating to differential amplifiers the LC comprising one or more resistors coupled to the LC by feedback (active or passive)

Definitions

  • This application relates to the field of circuit design, in particular to a signal acquisition circuit and a wearable device.
  • One of the embodiments of the present application provides a signal acquisition circuit, including: a differential amplifier, a first electrode and a second electrode, wherein the first electrode is connected to the first input terminal of the differential amplifier through a first lead, The second electrode is connected to the second input terminal of the differential amplifier through a second lead; and a first negative capacitance circuit and a second negative capacitance circuit, wherein the first negative capacitance circuit is electrically connected to the first negative capacitance circuit.
  • a lead wire and a ground wire, the second negative capacitance circuit electrically connects the second lead wire and the ground wire, and both the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect.
  • the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit and the parasitic capacitance value of the first lead to ground is less than 50%
  • the second negative capacitance circuit The relative error between the absolute value of the equivalent capacitance value and the parasitic capacitance value of the second lead to ground is less than 50%.
  • the relative error between the absolute value of the capacitance value and the sum of the ground parasitic capacitance of the first lead and the first equivalent input capacitance is less than 50%
  • the absolute value of the equivalent capacitance value of the second negative capacitance circuit The relative error between the value and the sum of the parasitic capacitance of the second lead wire to ground and the second equivalent input capacitance is less than 50%.
  • the circuit further includes a third negative capacitance circuit, wherein the third negative capacitance circuit electrically connects the first lead and the second lead, and the third negative capacitance circuit has a negative capacitive effect.
  • the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit and the parasitic capacitance between the first lead and the second lead is less than 50%.
  • the first negative capacitance circuit includes a first operational amplifier, a first resistor, a second resistor and a first capacitor
  • the second negative capacitance circuit includes a second operational amplifier, a third resistor, a fourth Resistor and second capacitance;
  • the inverting input end of described first operational amplifier is grounded through described first resistance, and the output of the inverting input end of described first operational amplifier simultaneously through described second resistance and first operational amplifier
  • the same input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier through the first capacitor;
  • the inverting input terminal of the second operational amplifier is grounded through the third resistor, and at the same time
  • the inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier through the fourth resistor, and the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier through the second capacitor and the output terminal of the second operational amplifier. connected to the output.
  • the non-inverting input terminal of the first operational amplifier is connected to the first lead, and the non-inverting input terminal of the second operational amplifier is connected to the second lead.
  • the circuit further includes a feedback control circuit to adjust the equivalent capacitance values of the first negative capacitance circuit and the second negative capacitance circuit.
  • the input impedance of the differential amplifier is greater than one hundred megohms.
  • the differential amplifier is double-terminal powered with positive and negative voltages.
  • the differential amplifier is powered by a single voltage.
  • One of the embodiments of the present application provides a signal acquisition circuit, including: a differential amplifier, a first electrode and a second electrode, and a fourth negative capacitance circuit, wherein the first electrode is connected to the first electrode through the first lead wire The first input terminals of the four negative capacitance circuits are connected, the second electrode is connected with the second input terminal of the fourth negative capacitance circuit through the second lead, and the first output terminal of the fourth negative capacitance circuit is connected to the first input terminal of the differential amplifier, the second output terminal of the fourth negative capacitance circuit is connected to the second input terminal of the differential amplifier, and the fourth negative capacitance circuit has a negative capacitance effect.
  • the fourth negative capacitance circuit includes a two-terminal differential amplifier, a first negative feedback capacitor, and a second negative feedback capacitor, wherein the first input terminal of the two-terminal differential amplifier and the two-terminal differential The first negative feedback capacitance is connected between the first output terminals of the amplifier, and the second negative feedback capacitance is connected between the second input terminal of the double-ended differential amplifier and the second output terminal of the double-terminal differential amplifier. .
  • the double-ended differential amplifier is a fixed-gain amplifier.
  • the fourth negative capacitance circuit includes a first unit and a second unit, the first unit includes a first amplifier and a third negative feedback capacitor, and the second unit includes a second amplifier and a fourth A negative feedback capacitor, wherein the third negative feedback capacitor is connected between the input terminal of the first amplifier and the output terminal of the first amplifier, and the input terminal of the second amplifier and the output of the second amplifier The fourth negative feedback capacitor is connected between the terminals.
  • the relative error between the absolute value of the equivalent capacitance value of the first unit of the fourth negative capacitance circuit and the parasitic capacitance value of the first lead to ground is less than 50%
  • the fourth The relative error between the absolute value of the equivalent capacitance value of the second unit of the negative capacitance circuit and the parasitic capacitance value of the second lead wire to ground is less than 50%
  • the first amplifier and the second amplifier are equal and fixed gain amplifiers.
  • the circuit further includes a feedback control circuit to adjust the equivalent capacitance of the fourth negative capacitance circuit.
  • the input impedance of the differential amplifier is greater than one hundred megohms.
  • the differential amplifier is double-terminal powered with positive and negative voltages.
  • the differential amplifier is powered by a single voltage.
  • One of the embodiments of the present application further provides a wearable device, including the above-mentioned signal acquisition circuit.
  • the first negative capacitance circuit and the second negative capacitance circuit are connected to the lead wire of the acquisition terminal, the first negative capacitance circuit and the second negative capacitance circuit have negative capacitance effect, so that they can be connected with
  • the parasitic capacitance of the leads to the ground is offset to reduce the influence of the parasitic capacitance on signal acquisition, and further improve the performance of the signal acquisition circuit and the effect of signal acquisition.
  • Fig. 1 is a schematic diagram showing the principle of power frequency interference according to some embodiments of the present application
  • 2A-2B are schematic diagrams of differential amplifier power supply methods according to some embodiments of the present application.
  • Fig. 3 is a schematic diagram of a signal acquisition circuit according to some embodiments of the present application.
  • FIG. 4 is a schematic structural diagram of a negative capacitance circuit in a signal acquisition circuit according to some embodiments of the present application.
  • Fig. 5 is a schematic diagram of a signal acquisition circuit according to some embodiments of the present application.
  • Fig. 6A is a schematic structural diagram of a fourth negative capacitance circuit in a signal acquisition circuit according to some embodiments of the present application.
  • Fig. 6B is another schematic structural diagram of the fourth negative capacitance circuit in the signal acquisition circuit according to some embodiments of the present application.
  • Fig. 7A is a schematic diagram of an effect circuit before eliminating power frequency interference according to some embodiments of the present application.
  • Fig. 7B is a schematic circuit diagram showing the effect of eliminating power frequency interference according to some embodiments of the present application.
  • system means for distinguishing different components, elements, components, parts or assemblies of different levels.
  • the words may be replaced by other expressions if other words can achieve the same purpose.
  • the signal acquisition circuit described in the embodiments of the present application can be applied to various signal monitoring devices that need to collect signals, especially physiological signal monitoring devices, such as smart wearable devices.
  • the wearable device for example, clothing, wristbands, shoulder straps, etc.
  • the wearable device can be placed on various parts of the human body (for example, calves, thighs, waist, back, chest, shoulders, neck, etc.) , used to collect physiological signals of various parts of the user's body in different states, and the collected signals can be further processed later.
  • the physiological signal is a signal that can be detected and can reflect the physical state of the user, for example, it may include a respiratory signal, an electrocardiograph (ECG), an electromyography (EMG), an EEG Signal (electroencephalograph, EEG), blood pressure signal, temperature signal and other signals.
  • ECG electrocardiograph
  • EEG electromyography
  • EEG electroencephalograph
  • blood pressure signal temperature signal and other signals.
  • wearable devices that collect physiological signals can be applied to cross emerging industries such as medical care, game entertainment, and health education. For example, it can be combined with virtual reality (VR), EMG acquisition and other technologies to promote the development of immersive entertainment, education, etc.; it can be combined with mechanical electronics, exoskeleton machines and other technologies to reduce medical costs and promote medical treatment. purpose of healthy development.
  • VR virtual reality
  • Fig. 1 is a schematic diagram showing the principle of power frequency interference according to some embodiments of the present application.
  • the signal acquisition circuit 100 shown in FIG. 1 includes one or more sensor units in contact with the user's body (for example, the first electrode 110 and the second electrode 120), a differential amplifier 130, and one or more A lead wire (for example, a first lead L1 and a second lead L2 ) connecting the sensor unit and the differential amplifier 130 .
  • the sensor unit may be used to acquire one or more physiological signals of the user.
  • the sensor unit may include but not limited to one of myoelectric sensor, attitude sensor, ECG sensor, respiration sensor, temperature sensor, humidity sensor, inertial sensor, blood oxygen saturation sensor, Hall sensor, electrodermal sensor, rotation sensor, etc. one or more species.
  • the physiological signal may include one or more of myoelectric signal, posture signal, electrocardiogram signal, respiratory rate, temperature signal, humidity signal and the like.
  • the sensor unit can be placed in different positions of the wearable device according to the type of motion signal to be acquired.
  • different signal acquisition circuits can be arranged at different positions of the user's body for collecting physiological signals of the same or different types of users.
  • the signal acquisition circuits arranged on different sides of the user's thighs can all be used to acquire the electromyography signals at the thighs.
  • the signal acquisition circuit arranged at the forearm of the user can be used to collect the electromyographic signal at the forearm, and the signal acquisition circuit arranged at the heart of the user can be used to collect the electrocardiographic signal of the user.
  • the sensor unit may include one or more electrode elements in contact with the user's body, through which the electromyographic signals on the user's body surface can be collected.
  • the electrode element may be a dry electrode or a wet electrode.
  • the dry electrode is a metal structure electrode formed by weaving metal sheets or metal wires.
  • the wet electrode is formed by applying conductive colloid between the human skin and the electrode components, which can increase the contact strength with the human body. Since the human body is not an absolute conductor, there is contact impedance between the dry electrode and the wet electrode and the human body, and the impedance is different under different physiological conditions. Different electrode types can be selected in different situations.
  • the electrode element includes a first electrode 110 and a second electrode 120 .
  • the first electrode 110 is connected to the first input terminal A point of the differential amplifier 130 through the first lead L1
  • the second electrode 120 is connected to the second input terminal B point of the differential amplifier 130 through the second lead L2
  • the first lead L1 And the second lead L2 transmits the physiological signal collected by the electrode element to the differential amplifier for proper processing (for example, noise reduction, amplification, etc.).
  • the differential amplifier 130 can differentially amplify the physiological signals acquired by the electrode elements.
  • the physiological signal processed by the differential amplifier 130 that is, the Vout output from the output terminal, will be transmitted to other components in the wearable device for subsequent processing.
  • the processed physiological signal can be converted into a digital signal by an analog-to-digital converter ADC, and then processed by a processor, such as signal analysis.
  • the differential amplifier 130 may include two power supply modes, namely single-end power supply mode and double-end power supply mode.
  • the first power supply terminal (111) of the differential amplifier 130 is connected to the positive power supply +Vcc
  • the second power supply terminal (112) is connected to the negative power supply -Vcc
  • one terminal (113) receiving the bias voltage is grounded at the same time
  • the first power supply terminal (114) of the differential amplifier 130 is connected to the positive power supply +Vcc
  • the second power supply terminal (116) is grounded
  • the terminal (117) receiving the bias voltage receives a bias voltage value of +Vcc/2 set the voltage.
  • the contact impedance between the first electrode 110 and the second electrode 120 is inconsistent with the user's body, that is, when the impedances of the two input ends of the differential amplifier 130 are inconsistent (impedance imbalance)
  • the common-mode power frequency on the surface of the human body will be The signal is converted into a differential mode power frequency noise input amplifier, thereby reducing the signal-to-noise ratio, and even causing circuit saturation to fail.
  • the environmental interference can be equivalent to the capacitive coupling model C0, and the impedance between the human body and the earth can be expressed as Z0, then the power frequency interference model can be equivalent to the left half of Figure 1, that is, the power frequency power line Through the equivalent capacitance C0, the human body, and the grounding impedance are connected in series to ground.
  • the distance from the power frequency power line changes, and the value of the equivalent capacitance C0 also changes accordingly.
  • the power-frequency current coupled to the human body is Icm
  • the common-mode power-frequency potential Vcm on the surface of the human body can be expressed as:
  • Vcm Icm*Z0.
  • the impedance to ground of the first input terminal A is Zin1
  • the common-mode input impedance can be expressed as:
  • the potentials of the first input terminal A and the second input terminal B of the differential amplifier 130 are not equal, and the differential amplifier 130 130 will further amplify the potential difference between the two points AB, resulting in circuit saturation or failure.
  • the potential difference V AB between the first input terminal A and the second input terminal B of the differential amplifier 130 can be expressed by the following formula (3):
  • Z1 is the contact resistance value of the first electrode 110
  • Z2 is the contact resistance value of the second electrode 120 .
  • the potential difference between the two input terminals of the differential amplifier can be reduced by reducing the contact impedance of the electrode element, and the ground electrode can also be added to the human body
  • the ground electrode can also be added to the human body
  • a method of increasing the (common mode) input impedance of the differential amplifier may also be adopted.
  • a differential amplifier with high (common mode) input impedance for example, both the first input terminal A and the second input terminal B have high impedance to ground
  • the (common-mode) input impedance of the differential amplifier 130 is greater than 100 M ⁇ , preferably, the (common-mode) input impedance of the differential amplifier 130 is greater than 1 G ⁇ .
  • parasitic capacitances when the signal acquisition circuit 100 is applied to a wearable device, the presence of parasitic capacitance in the actual circuit will reduce the input impedance of the differential amplifier.
  • parasitic capacitances are connected in parallel with various equivalent impedances in the signal acquisition circuit, which greatly reduces the input impedance of the overall circuit, thereby aggravating power frequency interference, and cannot be achieved by using a higher input impedance differential amplifier solution. It can be seen that the existence of these parasitic capacitances limits the performance and acquisition effect of the signal acquisition circuit.
  • Fig. 3 is a schematic diagram of a signal acquisition circuit 200 according to some embodiments of the present application.
  • the signal acquisition circuit 200 shown in FIG. 3 may include a first electrode 210, a second electrode 220, a differential amplifier 230, a first lead L1, a second lead L2, a first negative capacitance circuit C10, and a second lead. Two negative capacitance circuits C20.
  • the first electrode 210 is connected to the first input terminal A of the differential amplifier 230 through the first lead L1
  • the second electrode 220 is connected to the second input terminal B of the differential amplifier 230 through the second lead L2.
  • the relevant descriptions about the first electrode 210 , the second electrode 220 , the differential amplifier 230 , the first lead L1 and the second lead L2 can refer to the relevant description in FIG. 1 , and will not be repeated here.
  • a first pair of ground parasitic capacitance C1 exists between the first lead L1 and the ground line
  • a second pair of ground parasitic capacitance C2 exists between the second lead L2 and the ground line
  • the first pair of ground parasitic capacitance C2 exists between the first lead L1 and the second lead L2.
  • the parasitic capacitance C1 of the first pair of grounds can be regarded as being equivalently connected between the first lead L1 and the ground, and the parasitic capacitance C1 of the first pair of grounds is connected with the grounding of the first input terminal A of the differential amplifier 230
  • the impedance Zin1 is connected in parallel;
  • the second pair of ground parasitic capacitance C2 can be regarded as being equivalently connected between the second lead L2 and the ground wire, and the second pair of ground parasitic capacitance C2 and the ground impedance of the second input terminal B of the differential amplifier 230 Zin2 is connected in parallel;
  • the parasitic capacitance C3 between the leads can be regarded as being equivalently connected between the first lead L1 and the second lead L2.
  • the first pair of ground parasitic capacitance C1 and the second pair of ground parasitic capacitance C2 are respectively connected in parallel with the ground impedance Zin1 and ground impedance Zin2 of the differential amplifier, the overall input impedance of the circuit is greatly reduced, and the power frequency interference is aggravated. impact on signal acquisition.
  • the change of the parasitic capacitance cannot be measured in real time, but because it is related to the circuit design, the parasitic capacitance can be measured after the circuit is designed. That is to say, the parasitic capacitance C1 of the first pair of grounds, the parasitic capacitance C2 of the second pair of grounds and the parasitic capacitance C3 between the leads can be measured after the circuit design of the signal acquisition circuit is completed.
  • the parasitic capacitance value between the human body and the human body cannot be accurately measured, but it can be measured when the human body is not moving to determine the reference value of the parasitic capacitance. When the human body moves, the parasitic capacitance value between the human body and the human body changes, and a rough fluctuation range can be determined according to the parasitic capacitance and the preparation.
  • the signal acquisition circuit 200 is provided with a first negative capacitance circuit C10 and a second negative capacitance circuit C20 .
  • the first negative capacitance circuit C10 is electrically connected to the first lead L1 and the ground wire
  • the second negative capacitance circuit C20 is electrically connected to the second lead L2 and the ground wire
  • the circuit C20 has a negative capacitance effect, which can offset the parasitic capacitance of the lead wire to the ground, so as to reduce the influence of the parasitic capacitance on the circuit input impedance and signal collection, and further improve the performance of the signal collection circuit and the effect of signal collection.
  • the negative capacitance effect mentioned here can be understood as the change trend of the charge quantity in the first negative capacitance circuit C10 and the second negative capacitance circuit C20 is opposite to the change tendency of the voltage applied thereto, that is to say, as the voltage decreases, The charge quantity in the first negative capacitance circuit C10 and the second negative capacitance circuit C20 will increase accordingly.
  • the manner of electrically connecting the first negative capacitance circuit C10 and/or the second negative capacitance circuit C20 to the ground may include connecting the first negative capacitance circuit C10 and/or the second negative capacitance circuit C20 to a Or a common ground terminal in multiple printed circuit boards (PCB).
  • PCB printed circuit boards
  • the first negative capacitance circuit C10 can be regarded as being connected in parallel with the first pair of ground parasitic capacitance C1
  • the second negative capacitance circuit C20 can be regarded as being connected in parallel with the second pair of ground parasitic capacitance C2 .
  • the first negative capacitance circuit C10 and the second negative capacitance circuit C20 respectively cancel the parasitic capacitances of the two input terminals of the differential amplifier, thereby reducing the capacitance value of the input terminals of the differential amplifier and achieving the effect of increasing the input impedance.
  • the equivalent capacitance value of the first negative capacitance circuit C10 and the equivalent capacitance value of the second negative capacitance circuit C20 can be expressed as:
  • the absolute value of the negative capacitance circuit is not completely equal to the parasitic capacitance, considering that in the actual working environment, the parasitic capacitance may slightly change with the movement of the leads.
  • the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the parasitic capacitance value C1 of the first lead L1 to ground is less than 50%
  • the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit C20 and the parasitic capacitance C2 of the second lead L2 to ground is less than 50%.
  • the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the parasitic capacitance value C1 of the first lead L1 to ground is less than 30%
  • the relative error between the absolute value of the equivalent capacitance of the second negative capacitance circuit C20 and the parasitic capacitance C2 of the second lead L2 to ground is less than 30%
  • the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the parasitic capacitance value of the first lead L1 to ground refers to the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 The ratio of the difference between the value and the parasitic capacitance value of the first lead L1 to ground and the parasitic capacitance value of the first lead L1 to ground.
  • the equivalent input impedance Zin1 of the first input terminal A of the differential amplifier 230 can be equivalent to a capacitor Rin1 connected in parallel with the capacitor Cin1, and the equivalent input impedance Zin2 of the second input terminal B of the differential amplifier 230 can be equal to The effect is a parallel connection of capacitor Rin2 and capacitor Cin2.
  • the first negative capacitance circuit C10 and the second negative capacitance circuit C20 can be adjusted to further cancel the effect of the equivalent input capacitance of the differential amplifier 230 .
  • the equivalent capacitance value of the first negative capacitance circuit C10 and the equivalent capacitance value of the second negative capacitance circuit C20 can be adjusted as:
  • the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the parasitic capacitance value C1 of the first lead L1 to ground and the differential amplifier 230 The relative error of the sum of the equivalent input capacitance value Cin1 of the first input terminal A is less than 50%, the absolute value of the equivalent capacitance value of the second negative capacitance circuit C20 and the parasitic capacitance value C2 of the second lead L2 to the ground and the difference
  • the relative error of the sum of the equivalent input capacitances Cin2 of the second input terminal B of the amplifier 230 is less than 50%.
  • the absolute value of the equivalent capacitance value of the first negative capacitance circuit C10 and the parasitic capacitance value C1 of the first lead L1 to ground and the differential amplifier 230 The relative error of the sum of the equivalent capacitance value Cin1 of the first input terminal A is less than 30%, the absolute value of the equivalent capacitance value of the second negative capacitance circuit C20 and the parasitic capacitance value C2 of the second lead L2 to the ground and the differential amplifier
  • the relative error of the sum of the equivalent capacitance values Cin2 of the second input terminal B of the 230 is less than 30%.
  • the absolute value of the equivalent capacitance of the first negative capacitance circuit C10 and the relative ratio of the sum of the parasitic capacitance of the first lead L1 to ground and the first equivalent input capacitance Cin1 of the differential amplifier The smaller the error, the more the parasitic capacitance to ground of the first lead L1 offset by the first negative capacitance circuit C10 and the first equivalent input capacitance Cin1 of the differential amplifier, the greater the input impedance of the entire signal acquisition circuit. The effect of the final signal acquisition will be better. The same is true for the second negative capacitance circuit C20 , which will not be repeated here.
  • the first negative capacitance circuit C10 and the second negative capacitance circuit C20 respectively cancel the parasitic capacitance of the first lead L1 to the ground, the first equivalent input capacitance Cin1 of the differential amplifier, and the parasitic capacitance of the second lead L2 to the ground and the second equivalent input capacitance Cin2 of the differential amplifier, thereby further increasing the input impedance of the entire signal acquisition circuit.
  • the signal acquisition circuit 200 may further include a third negative capacitance circuit C30.
  • the third negative capacitance circuit C30 is electrically connected between the first lead L1 and the second lead L2, and is connected in parallel with the parasitic capacitance C3 between the leads.
  • the signal acquisition circuit 200 since the existence of the parasitic capacitance C3 between leads has little influence on the circuit performance, the signal acquisition circuit 200 does not need to set the third negative capacitance circuit C30.
  • the signal acquisition circuit 200 may be provided with a third negative capacitance circuit C30.
  • the value of the third negative capacitance circuit C30 can be expressed as:
  • the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit C30 and the parasitic capacitance C3 between the two leads is less than 50%. In some embodiments, the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit C30 and the parasitic capacitance C3 between the two leads is less than 30%.
  • the signal acquisition circuit may further include a feedback control circuit to adjust the equivalent capacitance values of the first negative capacitance circuit C10 and the second negative capacitance circuit C20, for example, by changing the resistance value in the negative capacitance circuit.
  • FIG. 4 is a schematic structural diagram of the negative capacitance circuit in the signal acquisition circuit 200 according to some embodiments of the present application.
  • the first negative capacitance circuit C10 may have the structure shown in FIG. 4. As shown in FIG. 4, the first negative capacitance circuit C10 may include a first operational amplifier 410, a first resistor R1, a second resistor R2 and a A capacitor C401. In some embodiments, the inverting input terminal of the first operational amplifier 410 is connected to the ground through the first resistor R1, while the inverting input terminal of the first operational amplifier 410 is connected to the output terminal of the first operational amplifier 410 through the second resistor R2, The non-inverting input terminal of the first operational amplifier 410 is connected to the output terminal of the first operational amplifier 410 through the first capacitor C401 . In some embodiments, point m in FIG. 4 and point a in FIG. 3 are two points of equal potential, and lead wires can be used to electrically connect the two points a and m.
  • the second negative capacitance circuit C20 can also be the structure shown in FIG. 4. At this time, point m in FIG. 4 and point b in FIG. Two point electrical connection.
  • the negative capacitance circuit shown in FIG. 4 is an equivalent circuit with a negative capacitance effect.
  • the equivalent impedance of the negative capacitance circuit is the impedance between point m and GND.
  • the impedance of za can be expressed by the following formula (9):
  • the impedance between point m and GND may equivalently include or be generated by a negative capacitance.
  • the equivalent capacitance value of C a can be expressed by the following formula (10):
  • C a is the equivalent capacitance of the negative capacitance circuit shown in FIG. 4 .
  • the resistors R1 and R2 can be resistors with adjustable resistance (eg, sliding rheostats, resistance boxes, and potentiometers), or resistors with fixed resistance.
  • the resistance values of the resistors R1 and R2 may be equal or unequal. It can be understood that, in some embodiments, the size of the equivalent capacitance C a can be adjusted by adjusting the resistance values of the resistors R1 and R2 .
  • the capacitor C401 may be a paper capacitor, a metallized paper capacitor, a ceramic capacitor, a film capacitor, an oil-immersed paper capacitor, an aluminum electrolytic capacitor, a semi-variable capacitor, or a variable capacitor.
  • the equivalent capacitance C a can be adjusted by adjusting the capacitance of the capacitor C401 .
  • the operational amplifier 410 can be powered by dual power supplies, for example, the voltage +Vcc (411) is used as a positive power supply and the voltage -Vcc (412) is used as a negative power supply, and the amplified signal generated by the operational amplifier 410 is output at 413 .
  • the operational amplifier 410 may also be powered by a single power supply, which will not be repeated here.
  • the first negative capacitance circuit C10 and the second negative capacitance circuit C20 may also have other structures than those shown in FIG. 4 .
  • the signal acquisition circuit 200 may further include a third negative capacitance circuit C30, wherein the third negative capacitance circuit C30 is electrically connected to the first lead L1 and the second lead L2, and the third negative capacitance circuit C30 has negative capacitance effect.
  • the third negative capacitance circuit C30 can be the structure of FIG. 4, at this time, point m in FIG. 4 and point c in FIG. 3 are two points of equipotential, GND point and Point d in Figure 3 is two points of equal potential, and lead wires can be used to electrically connect point c in Figure 3 to point m in Figure 4 and point d in Figure 3 to GND in Figure 4.
  • the third negative capacitance circuit C30 can also have other structures than those shown in the figure, as long as it can offset the parasitic capacitance C3 between leads, it is all satisfactory.
  • Fig. 5 is a schematic diagram of a signal acquisition circuit 300 according to some embodiments of the present application.
  • the signal acquisition circuit 300 shown in FIG. 5 may include a first electrode 210 , a second electrode 220 , a differential amplifier 230 , a first lead L1 , a second lead L2 and a fourth negative capacitance circuit C40 .
  • first electrode 210 the second electrode 220
  • differential amplifier 230 the first lead L1 and the second lead L2
  • FIGS. 1-4 which will not be repeated here.
  • first pair of ground parasitic capacitance C1 between the first lead L1 and the ground line
  • second pair of ground parasitic capacitance C2 exists between the second lead L2 and the ground line. Due to the first pair of ground parasitic capacitance C1 and the second ground parasitic capacitance C2 are respectively connected in parallel with the ground impedance Zin1 and the ground impedance Zin2 of the differential amplifier, which greatly reduces the overall input impedance of the circuit and intensifies the impact of power frequency interference on signal acquisition.
  • the signal acquisition circuit 300 is provided with a fourth negative capacitance circuit C40.
  • the first electrode 210 is connected to the first input terminal P of the fourth negative capacitance circuit C40 through the first lead L1
  • the second electrode 220 is connected to the second input terminal P of the fourth negative capacitance circuit C40 through the second lead L2.
  • the input terminal Q is connected
  • the first output terminal M of the fourth negative capacitance circuit C40 is connected to the first input terminal A of the differential amplifier 230
  • the second output terminal N of the fourth negative capacitance circuit C40 is connected to the second terminal of the differential amplifier 230.
  • Input B is connected to the first input terminal P of the fourth negative capacitance circuit C40 through the first lead L1
  • the second electrode 220 is connected to the second input terminal P of the fourth negative capacitance circuit C40 through the second lead L2.
  • the fourth negative capacitance circuit C40 has a negative capacitance effect, which can offset the parasitic capacitance of the lead wire to the ground, so as to reduce the influence of the parasitic capacitance on the circuit input impedance and signal acquisition, and further improve the performance of the signal acquisition circuit and the effect of signal acquisition .
  • the negative capacitance circuit C40 can be realized by using an amplifier with a fixed gain and a feedback capacitance, so as to simultaneously cancel the effects of the first pair-to-ground parasitic capacitance C1 and the second-to-ground parasitic capacitance C2.
  • the negative capacitance circuit C40 please refer to the relevant descriptions in FIGS. 6A and 6B.
  • the signal acquisition circuit 300 may further include a third negative capacitance circuit C30.
  • the third negative capacitance circuit C30 is electrically connected between the first lead L1 and the second lead L2, and is connected in parallel with the parasitic capacitance C3 between the leads.
  • the signal acquisition circuit 200 since the existence of the parasitic capacitance C3 between leads has little influence on the circuit performance, the signal acquisition circuit 200 does not need to set the third negative capacitance circuit C30.
  • the signal acquisition circuit 200 may be provided with a third negative capacitance circuit C30.
  • the specific implementation manner of the third negative capacitance circuit C30 reference may be made to the related descriptions in FIG. 3 and FIG. 4 , which will not be repeated here.
  • the signal acquisition circuit may further include a feedback control circuit to adjust the equivalent capacitance of the fourth negative capacitance circuit C40, for example, by changing the resistance value or capacitance value in the negative capacitance circuit.
  • FIG. 6A is a schematic structural diagram of the fourth negative capacitance circuit C40 in the signal acquisition circuit 300 according to some embodiments of the present application.
  • the fourth negative capacitance circuit C40 may include a first unit C402 and a second unit C404, the first unit C402 includes a first amplifier G2 and a third negative feedback capacitor C46, and the second unit C404 includes a second amplifier G3 and the fourth negative feedback capacitor C48. In some embodiments, both the first amplifier G2 and the second amplifier G3 are fixed-gain amplifiers.
  • the input terminal of the first amplifier G2 is the first input terminal P of the fourth negative capacitance circuit C40
  • the input terminal of the second amplifier G3 is the second input terminal Q of the fourth negative capacitance circuit C40
  • the output terminal of the first amplifier G2 is the first output terminal M of the fourth negative capacitance circuit C40
  • the output terminal of the second amplifier G3 is the second output terminal N of the fourth negative capacitance circuit C40.
  • the input terminal P of the first amplifier G2 and the output terminal M of the first amplifier G2 are connected in series through a third negative feedback capacitor C46, and the input terminal Q of the second amplifier G3 and the output terminal of the second amplifier G3 N are connected in series through a fourth negative feedback capacitor C48.
  • the equivalent capacitance value of the first unit C402 of the fourth negative capacitance circuit C40 can be expressed as:
  • the equivalent capacitance value of the second unit C404 of the fourth negative capacitance circuit C40 can be expressed as:
  • the first amplifier G2 and the second amplifier G3 have equal and fixed gains. For example, if the gain of the first amplifier G2 is constant at g1, the gain of the second amplifier G3 is also constant at g1. In some embodiments, the gains of the first amplifier G2 and the second amplifier G3 may range from 0 to 100 dB. Preferably, the gains of the first amplifier G2 and the second amplifier G3 range from 0 to 10 dB.
  • the values of the third negative feedback capacitor C46 and the fourth negative feedback capacitor C48 are equal. In this way, the first unit C402 and the second unit C404 of the fourth negative capacitance circuit C40 form a highly symmetrical structure, so that the overall signal acquisition circuit 300 can obtain a larger common mode rejection ratio. In some embodiments, if the gains of the first amplifier G2 and the second amplifier G3 are not equal, the common mode rejection ratio of the circuit will decrease, and the effect of reducing power frequency interference cannot be achieved.
  • each of the first amplifier G2 and the second amplifier G3 may be formed by cascading multi-stage fixed-gain amplifiers.
  • the first unit C402 of the fourth negative capacitance circuit C40 can be used to cancel the first parasitic capacitance C1 to ground, and the second unit C404 of the fourth negative capacitance circuit C40 can be used to cancel the second parasitic capacitance to ground C2. Therefore, the fourth negative capacitance circuit C40 can be used to simultaneously offset the first pair-to-ground parasitic capacitance C1 and the second-to-ground parasitic capacitance C2 .
  • the equivalent capacitance value of the first unit C402 and the equivalent capacitance value of the second unit C404 can be expressed as:
  • the total capacitance to ground of the first lead L1 and the total capacitance to ground of the second lead L2 are both zero.
  • the parasitic capacitance at the input terminal of the differential amplifier 230 is completely canceled out, and the overall input impedance of the signal acquisition circuit 300 is greatly improved, thereby enhancing the ability to resist power frequency interference.
  • the parasitic capacitance may slightly change with the movement of the leads, correspondingly, the absolute value of the equivalent capacitance value of the first unit C402 of the fourth negative capacitance circuit C40 and the first
  • the relative error of the ground parasitic capacitance C1 of the lead L1 is less than 50%
  • the relative error between the equivalent capacitance of the second unit C404 of the fourth negative capacitance circuit C40 and the ground parasitic capacitance C2 of the second lead L2 is less than 50%.
  • the relative error between the absolute value of the equivalent capacitance of the first unit C402 of the fourth negative capacitance circuit C40 and the parasitic capacitance C1 of the first lead L1 to ground is less than 30%, and the fourth negative capacitance The relative error between the equivalent capacitance of the second unit C404 of the circuit C40 and the parasitic capacitance C2 of the second lead L2 to ground is less than 30%.
  • FIG. 6B is another schematic structural diagram of the fourth negative capacitance circuit C40 in the signal acquisition circuit 300 according to some embodiments of the present application.
  • the fourth negative capacitance circuit C40 may include a two-terminal differential amplifier G1, a first negative feedback capacitor C42 and a second negative feedback capacitor C44.
  • the first input terminal of the two-terminal differential amplifier G1 is the first input terminal P of the fourth negative capacitance circuit C40
  • the second input terminal of the two-terminal differential amplifier G1 is the fourth negative capacitance circuit C40
  • the second input terminal Q similarly, the first output terminal of the double-ended differential amplifier G1 is the first output terminal M of the fourth negative capacitance circuit C40
  • the second output terminal of the double-ended differential amplifier G1 is the fourth negative capacitance The second output terminal N of the circuit C40.
  • the first input terminal P of the double-ended differential amplifier G1 and the first output terminal M of the double-ended differential amplifier G1 are connected in series through a first negative feedback capacitor C42, and the second input terminal Q of the double-ended differential amplifier G1 and the double-ended differential amplifier G1 are connected in series.
  • the second output terminals N of the amplifier G1 are connected in series through a second negative feedback capacitor C44.
  • the double-ended differential amplifier G1 is a fixed-gain amplifier.
  • the gain g0 of the double-ended differential amplifier G1 may range from 0 to 100 dB, preferably, the range of g0 is 0 to 10 dB.
  • the fourth negative capacitance circuit C40 can be used to cancel the first parasitic capacitance C1 to ground and the second parasitic capacitance C2 to ground simultaneously.
  • the double-ended differential amplifier G1 may be composed of a combination of amplifiers with fixed gains.
  • the double-ended differential amplifier G1 may be composed of two amplifiers G11 and G12 with a gain of g0, wherein the amplifiers G11 and G12 are Amplifiers with fixed gain and the same gain can also have the same structure.
  • the input terminal of the amplifier G11 is point P
  • the output terminal is point M.
  • the first negative feedback capacitor C42 is connected in series with point P and point M.
  • the circuit structure composed of the amplifier G11 and the first negative feedback capacitor C42 can be Used to offset the parasitic capacitance C1 of the first pair of grounds.
  • the input terminal of the amplifier G12 is the Q point
  • the output terminal is the N point
  • the second negative feedback capacitor C44 is connected in series with the Q point and the N point
  • the circuit structure composed of the amplifier G12 and the second negative feedback capacitor C44 can be used To offset the parasitic capacitance C1 of the first pair of grounds.
  • the equivalent capacitance value C11 of the circuit structure composed of the amplifier G11 and the first negative feedback capacitor C42 and the equivalent capacitance value C12 of the circuit structure composed of the amplifier G12 and the second negative feedback capacitor C44 can be expressed as:
  • the circuit structure composed of the amplifier G11 and the first negative feedback capacitor C42 can be used to cancel the first ground parasitic capacitance C1
  • the circuit structure composed of the amplifier G12 and the second negative feedback capacitor C44 can be used to cancel the second ground parasitic Capacitor C2
  • the parasitic capacitance at the input terminal of the differential amplifier is offset, and the overall input impedance of the signal acquisition circuit is greatly improved, thereby enhancing the ability to resist power frequency interference.
  • the absolute value of the equivalent capacitance C11 of the circuit structure composed of the amplifier G11 and the first negative feedback capacitor C42 and the ground of the first lead L1 is less than 50%, and the relative error of the absolute value of the equivalent capacitance value C12 of the circuit structure composed of the amplifier G12 and the second negative feedback capacitance C44 and the parasitic capacitance value C2 of the second lead L2 to the ground is less than 50%. %.
  • the absolute value of the equivalent capacitance C11 of the circuit structure composed of the amplifier G11 and the first negative feedback capacitor C42 and the grounding of the first lead L1 is less than 30%, and the relative error of the absolute value of the equivalent capacitance value C12 of the circuit structure composed of the amplifier G12 and the second negative feedback capacitance C44 and the parasitic capacitance value C2 of the second lead L2 to the ground is less than 30%. %.
  • the structure of the fourth negative capacitance circuit C40 can also be other structures than those shown in FIG. 6A and FIG. 6B, as long as the equivalent capacitance value of C40 can offset the first pair-to-ground parasitic capacitance value C1 of the first lead L1 and the ground parasitic capacitance C2 of the second lead L2 is enough, and there is no excessive limitation here.
  • Fig. 7A is a schematic diagram of an effect circuit before eliminating power frequency interference according to some embodiments of the present application.
  • Fig. 7B is a schematic circuit diagram showing the effect of eliminating power frequency interference according to some embodiments of the present application.
  • an analog signal acquisition circuit 400 is provided.
  • the signal acquisition circuit 400 includes a common-mode power frequency source 501, a differential amplifier 530, a resistor R5 with a resistance value of 10M ⁇ , and a resistance value of 100K ⁇ .
  • Resistor R6 capacitors C5 and C6 with a capacitance value of 6PF, wherein, resistor R5 is connected to the first input terminal (A1) of the differential amplifier 530 through the first lead L11, and resistor R6 is connected to the differential amplifier 530 through the second lead L22 connected to the second input terminal (B1) of the capacitor C5, one end of the capacitor C5 is connected to the first input terminal (A1) of the differential amplifier 530, and is also connected to the first lead L11, the other end of the capacitor C5 is grounded, and the capacitor C6 One end is connected to the second input end ( B1 ) of the differential amplifier 530 and also connected to the second lead L22 , and the other end of the capacitor C6 is grounded.
  • the common-mode power frequency source 501 is an AC power supply with a peak voltage of 300mv and a frequency of 50Hz, which is used to simulate the common-mode power frequency signal generated by the human body.
  • the resistance values of R5 and R6 can be different, which is used to simulate the impedance mismatch formed between the two electrodes when the actual wearable device collects human body signals.
  • Capacitors C5 and C6 are used to simulate the parasitic capacitance formed by the two leads to the ground when the actual wearable device collects human body signals.
  • the differential amplifier 530 adopts a double-terminal power supply mode, the first power supply terminal (511) of the differential amplifier 530 is connected to the positive power supply +Vcc, and the second power supply terminal (512) is connected to the negative power supply -Vcc, and simultaneously receives the bias One end (513) of the voltage is grounded.
  • the positive power supply +Vcc provides a voltage of 3.3V
  • the negative power supply -Vcc provides a voltage of -3.3V.
  • the signal acquisition circuit 400 further includes a first probe T1 and a second probe T2, the first probe T1 is arranged on the input side of the signal and connected to the first input terminal (A1) of the differential amplifier 530 , the second probe T2 is disposed on the output side of the signal and connected to the output terminal ( 514 ) of the differential amplifier 530 .
  • the first probe T1 and the second probe T2 are respectively used to measure the voltage peak value, effective value, frequency, etc. of the voltage signal before and after being input to the differential amplifier 530 . After testing, the obtained data are as follows in Table 1:
  • FIG. 7B is a schematic circuit diagram showing the effect of eliminating power frequency interference according to some embodiments of the present application.
  • FIG. 7B adds a negative capacitance circuit C510 and a negative capacitance circuit C520 on the basis of FIG. 7A .
  • the structures of the negative capacitance circuit C510 and the negative capacitance circuit C520 both adopt the structure of FIG. Point Y on lead L22 is electrically connected.
  • the first power supply terminal (521) of the operational amplifier 502 of the negative capacitance circuit C510 is connected to the positive power supply +Vcc
  • the second power supply terminal (522) is connected to the negative power supply -Vcc
  • the positive power supply +Vcc provides a voltage of 3.3V
  • the negative power supply -Vcc provides a voltage of -3.3V
  • the capacitor C501 is 6PF
  • the resistors R51 and R51 are both 10K ⁇ .
  • the negative capacitance circuit C520 adopts the same structure and elements with the same value as the negative capacitance circuit C510, so the capacitance value of the negative capacitance circuit C520 is also -6PF.
  • the signal acquisition circuit 200 and the signal acquisition circuit 300 described above can be applied in wearable devices.
  • the wearable device for example, clothing, wristbands, shoulder straps, etc.
  • the physiological signals of various parts of the body in different states can be further processed in the follow-up.
  • the above-mentioned signal acquisition circuit can be used in scenarios where it is necessary to detect signals that can reflect the physical state of the user.
  • the physiological signals can include respiratory signals, electrocardiographic signals, electromyographic signals, electroencephalogram signals, Various signals such as temperature signals.
  • wearable devices that collect physiological signals can be applied to cross emerging industries such as medical care, game entertainment, and health education. For example, it can be combined with virtual reality, EMG acquisition and other technologies to promote the development of immersive entertainment, education, etc.; it can be combined with mechanical electronics, exoskeleton machines and other technologies to achieve the purpose of reducing medical costs and promoting the development of medical health. This application does not limit the specific application scenarios of the signal acquisition circuit and the wearable device.
  • the possible beneficial effects of the embodiments of the present application include but are not limited to: offsetting the parasitic capacitance in the signal acquisition circuit by setting a negative capacitance circuit, thereby effectively increasing the input impedance of the entire signal acquisition circuit, and finally greatly reducing the parasitic capacitance.
  • the interference of the entire signal acquisition circuit improves the effectiveness of signal acquisition by the signal acquisition circuit.
  • the possible beneficial effects may be any one or a combination of the above, or any other possible beneficial effects.
  • aspects of the present application may be illustrated and described in several patentable categories or circumstances, including any new and useful process, machine, product or combination of substances, or any combination of them Any new and useful improvements.
  • various aspects of the present application may be entirely executed by hardware, may be entirely executed by software (including firmware, resident software, microcode, etc.), or may be executed by a combination of hardware and software.
  • the above hardware or software may be referred to as “block”, “module”, “engine”, “unit”, “component” or “system”.
  • aspects of the present application may be embodied as a computer product comprising computer readable program code on one or more computer readable media.
  • a computer storage medium may contain a propagated data signal embodying a computer program code, for example, in baseband or as part of a carrier wave.
  • the propagated signal may have various manifestations, including electromagnetic form, optical form, etc., or a suitable combination.
  • a computer storage medium may be any computer-readable medium, other than a computer-readable storage medium, that can be used to communicate, propagate, or transfer a program for use by being coupled to an instruction execution system, apparatus, or device.
  • Program code residing on a computer storage medium may be transmitted over any suitable medium, including radio, electrical cable, fiber optic cable, RF, or the like, or combinations of any of the foregoing.
  • numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of the embodiments use the modifiers "about”, “approximately” or “substantially” in some examples. grooming. Unless otherwise stated, “about”, “approximately” or “substantially” indicates that the stated figure allows for a variation of ⁇ 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that can vary depending upon the desired characteristics of individual embodiments. In some embodiments, numerical parameters should take into account the specified significant digits and adopt the general digit reservation method. Although the numerical ranges and parameters used in some embodiments of the present application to confirm the breadth of the scope are approximate values, in specific embodiments, such numerical values are set as precisely as practicable.

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Abstract

本申请实施例公开了一种信号采集电路。所述信号采集电路包括差分放大器、第一电极、第二电极、第一负电容电路和第二负电容电路。其中，第一电极通过第一引线与差分放大器的第一输入端相连接，第二电极通过第二引线与差分放大器的第二输入端相连接。第一负电容电路电气地连接第一引线和地线，第二负电容电路电气地连接第二引线和地线，第一负电容电路和第二负电容电路都具有负电容效应。

Description

一种信号采集电路及可穿戴设备 技术领域
本申请涉及电路设计领域，特别涉及一种信号采集电路及可穿戴设备。
背景技术
现有的生物电(心电、肌电等)信号采集电路中，往往会将共模工频信号转化为差模工频噪声输入放大器，导致信号信噪比降低，甚至电路饱和失效。鉴于此，便需要较大的输入阻抗来减少工频干扰。然而，在实际电路中，寄生电容往往会导致电路的输入阻抗降低，进而加剧工频干扰。即，寄生电容的存在限制了生物电信号采集的效果。
因此，希望提供一种信号采集电路及可穿戴设备，可以减少寄生电容的对信号采集造成的影响。
发明内容
本申请实施例之一提供一种信号采集电路，包括：差分放大器，第一电极和第二电极，其中，所述第一电极通过第一引线与所述差分放大器的第一输入端相连接，所述第二电极通过第二引线与所述差分放大器的第二输入端相连接；以及第一负电容电路和第二负电容电路，其中，所述第一负电容电路电气地连接所述第一引线和地线，所述第二负电容电路电气地连接所述第二引线和地线，所述第一负电容电路和所述第二负电容电路都具有负电容效应。
在一些实施例中，所述第一负电容电路的等效电容值的绝对值和所述第一引线的对地寄生电容值的相对误差小于50％，以及，所述第二负电容电路的等效电容值的绝对值和所述第二引线的对地寄生电容值的相对误差小于50％。
在一些实施例中，所述差分放大器的第一输入端存在第一等效输入电容，所述差分放大器的第二输入端存在第二等效输入电容，所述第一负电容电路的等效电容值的绝对值和所述第一引线的对地寄生电容与所述第一等效输入电容之和的相对误差小于50％，以及，所述第二负电容电路的等效电容值的绝对值和所述第二引线的对地寄生电容与所述第二等效输入电容之和的相对误差小于50％。
在一些实施例中，所述电路还包括第三负电容电路，其中，所述第三负电容电路电气地连接所述第一引线和所述第二引线，所述第三负电容电路具有负电容效应。
在一些实施例中，所述第三负电容电路的等效电容值的绝对值和所述第一引线和所述第二引线间的寄生电容值的相对误差小于50％。
在一些实施例中，所述第一负电容电路包括第一运算放大器、第一电阻、第二电阻和第一电容，所述第二负电容电路包括第二运算放大器、第三电阻、第四电阻和第二电容；所述第一运算放大器的反向输入端经所述第一电阻接地，同时所述第一运算放大器的反向输入端经所述第二电阻和第一运算放大器的输出端相连，所述第一运算放大器的同向输入端经所述第一电容和第一运算放大器的输出端相连；所述第二运算放大器的反向输入端经所述第三电阻接地，同时所述第二运算放大器的反向输入端经所述第四电阻和第二运算放大器的输出端相连，所述第二运算放大器的同向输入端经所述第二电容和第二运算放大器的输出端相连。
在一些实施例中，所述第一运算放大器的同向输入端和所述第一引线相连，所述第二运算放大器的同向输入端和所述第二引线相连。
在一些实施例中，所述电路还包括反馈控制电路调节所述第一负电容电路和所述第二负电容电路的等效电容值。
在一些实施例中，所述差分放大器的输入阻抗大于一百兆欧。
在一些实施例中，所述差分放大器为正负电压双端供电。
在一些实施例中，所述差分放大器为单电压供电。
本申请实施例之一提供一种信号采集电路，包括：差分放大器，第一电极和第二电极，以及第四负电容电路，其中，所述第一电极通过所述第一引线与所述第四负电容电路的第一输入端相连接，所述第二电极通过第二引线与所述第四负电容电路的第二输入端相连接，所述第四负电容电路的第一输出端连接到所述差分放大器的第一输入端，所述第四负电容电路的第二输出端连接到所述差分放大器的第二输入端，所述第四负电容电路具有负电容效应。
在一些实施例中，所述第四负电容电路包括双端差分放大器、第一负反馈电容和第二负反馈电容，其中，所述双端差分放大器的第一输入端和所述双端差分放大器的第一输出端之间连接所述第一负反馈电容，所述双端差分放大器的第二输入端和所述双端差分放大器的第二输出端之间连接所述第二负反馈电容。
在一些实施例中，所述双端差分放大器为增益固定的放大器。
在一些实施例中，所述第四负电容电路包括第一单元和第二单元，所述第一单元包括第一放大器和第三负反馈电容，所述第二单元包括第二放大器和第四负反馈电容，其中，所述第一放大器的输入端和所述第一放大器的输出端之间连接所述第三负反馈电容，所述第二放大器的输入端和所述第二放大器的输出端之间连接所述第四负反馈电容。
在一些实施例中，所述第四负电容电路的第一单元的等效电容值的绝对值和所述第一引线的对地寄生电容值的相对误差小于50％，以及，所述第四负电容电路的第二单元的等效电容值的绝对值和所述第二引线的对地寄生电容值的相对误差小于50％。
在一些实施例中，所述第一放大器和所述第二放大器为增益相等且固定的放大器。
在一些实施例中，所述电路还包括反馈控制电路调节所述第四负电容电路的等效电容值。
在一些实施例中，所述差分放大器的输入阻抗大于一百兆欧。
在一些实施例中，所述差分放大器为正负电压双端供电。
在一些实施例中，所述差分放大器为单电压供电。
本申请实施例之一还提供一种可穿戴设备，包括如上所述的信号采集电路。
本申请实施例所提供的信号采集电路，通过在采集端的引线上连接第一负电容电路和第二负电容电路，该第一负电容电路和第二负电容电路具有负电容效应，从而能与引线的对地寄生电容抵消，以减少寄生电容的对信号采集造成的影响，进一步提高信号采集电路的性能和信号采集的效果。
附图说明
本申请将以示例性实施例的方式进一步说明，这些示例性实施例将通过附图进行详细描述。这些实施例并非限制性的，在这些实施例中，相同的编号表示相同的结构，其中：
图1是根据本申请的一些实施例所示的工频干扰原理的示意图；
图2A-2B是根据本申请的一些实施例所示的差分放大器供电方式的示意图；
图3是根据本申请的一些实施例所示的信号采集电路的示意图；
图4是根据本申请的一些实施例所示的信号采集电路中的负电容电路的结构示意图；
图5是根据本申请一些实施例所示的信号采集电路的示意图；
图6A是根据本申请一些实施例所示的信号采集电路中第四负电容电路的一种结构示意图；
图6B是根据本申请一些实施例所示的信号采集电路中第四负电容电路的另一种结构示意图；
图7A是根据本申请的一些实施例所示的消除工频干扰前的效果电路示意图；
图7B是根据本申请的一些实施例所示的消除工频干扰后的效果电路示意图。
具体实施方式
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单的介绍。显而易见地，下面描述中的附图仅仅是本申请的一些示例或实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图将本申请应用于其它类似情景。除非从语言环境中显而易见或另做说明，图中相同标号代表相同结构或操作。
应当理解，本文使用的“系统”、“装置”、“单元”和/或“模组”是用于区分不同级别的不同组件、元件、部件、部分或装配的一种方法。然而，如果其他词语可实现相同的目的，则可通过其他表达来替换所述词语。
如本申请和权利要求书中所示，除非上下文明确提示例外情形，“一”、“一个”、“一种”和/或“该”等词并非特指单数，也可包括复数。一般说来，术语“包括”与“包含”仅提示包括已明确标识的步骤和元素，而这些步骤和元素不构成一个排它性的罗列，方法或者设备也可能包含其它的步骤或元素。
本申请实施例中描述的信号采集电路可以应用于各种需要采集信号的信号监测装置，特别是生理信号的监测装置，例如智能的可穿戴设备。在一些实施例中，所述可穿戴设备(例如，服装、护腕、肩带等)可以设置在人体各个部位(例如，小腿、大腿、腰、后背、胸部、肩部、颈部等)，用于采集用户在不同状态时其身体各个部位的生理信号，后续还可以进一步对采集的信号进行处理。在一些实施例中，所述生理信号为可以被检测的能够体现用户身体状态的信号，例如，可以包括呼吸信号、心电信号(electrocardiograph，ECG)、肌电信号(electromyography，EMG)、脑电信号(electroencephalograph，EEG)、血压信号、温度信号等多种信号。在一些实施例中，采集生理信号的可穿戴设备可以被应用于医疗、游戏娱乐、健康教育等交叉新兴产业。例如，可以与虚拟现实(virtual reality，VR)、EMG采集等技术结合，促进沉浸式娱乐、教育等的发展；可以与机械电子、外骨骼机器等技术的结合，以达到降低医疗成本、促进医疗健康发展的目的。
图1是根据本申请的一些实施例所示的工频干扰原理的示意图。
在一些实施例中，如图1所示的信号采集电路100包括一个或多个与用户身体 接触的传感器单元(例如，第一电极110和第二电极120)、差分放大器130、以及一条或多条连接传感器单元与差分放大器130的引线(例如，第一引线L1、第二引线L2)。
在一些实施例中，传感器单元可以用于获取用户的一种或多种生理信号。传感器单元可以包括但不限于肌电传感器、姿态传感器、心电传感器、呼吸传感器、温度传感器、湿度传感器、惯性传感器、血氧饱和度传感器、霍尔传感器、皮电传感器、旋转传感器等中的一种或多种。在一些实施例中，生理信号可以包括肌电信号、姿态信号、心电信号、呼吸频率、温度信号、湿度信号等中的一种或多种。传感器单元可以根据所要获取的动作信号类型放置在可穿戴设备的不同位置。
在一些实施例中，不同的信号采集电路可以布置在用户身体的不同位置，用于采集同种或不同种用户的生理信号。例如，分别布置在用户大腿不同侧的信号采集电路可以都用来采集大腿处的肌电信号。再例如，布置在用户小臂处的信号采集电路可以用来采集小臂处的肌电信号，而布置在用户心脏部位的信号采集电路可以用来采集用户的心电信号。
在一些实施例中，所述传感器单元可以包括一个或多个与用户身体接触的电极元件，通过电极元件可以采集用户身体表面的肌电信号。所述电极元件可以是干电极或湿电极。其中，干电极是通过金属片或金属线纺织而成的金属结构电极，通过在人体皮肤与电极元件之间涂抹导电胶体形成湿电极，能够增大与人体的接触强度。由于人体并不是绝对的导体，干电极和湿电极与人体之间都存在接触阻抗，在不同生理状态下的阻抗不一样，在不同的情况下可以选用不同的电极类型。
在一些实施例中，所述电极元件包括第一电极110和第二电极120。第一电极110通过第一引线L1与差分放大器130的第一输入端A点相连接，第二电极120通过第二引线L2与差分放大器130的第二输入端B点相连接，第一引线L1和第二引线L2将电极元件采集的生理信号传输至差分放大器进行适当的处理(例如，降噪、放大等)。
在一些实施例中，差分放大器130可以将电极元件获取的生理信号进行差分放大处理。在一些实施例中，差分放大器130处理后的生理信号，即输出端输出的Vout会传递给可穿戴设备中的其他元件进行后续处理。例如，处理后的生理信号可以通过模数转换器ADC，将模拟信号转换为数字信号，再通过处理器进行后续处理，例如信号分析。
在一些实施例中，差分放大器130可以包括两种供电方式，即单端供电和双端供电模式。如图2A所示，差分放大器130的第一供电端(111)连接正电源+Vcc，第 二供电端(112)连接负电源-Vcc，同时接收偏置电压的一端(113)接地；如图2B所示，差分放大器130的第一供电端(114)连接正电源+Vcc，第二供电端(116)接地，同时接收偏置电压的一端(117)接收电压值为+Vcc/2的偏置电压。
在一些实施例中，当第一电极110和第二电极120与用户身体的接触阻抗不一致，即差分放大器130的两个输入端的阻抗不一致时(阻抗失衡)，会将人体表面的共模工频信号转化为差模工频噪声输入放大器，进而降低信号信噪比，严重地甚至导致电路饱和失效。
由于人体所处的环境中存在各种50/60Hz的工频电源线(在中国为50Hz电线，在国外为60Hz电线)，这些工频电源线会发射电磁波，与人体相耦合从而使人体产生电势变化，其幅值一般在毫伏量级，可以为几mV至几百mV，并且和人体与工频电源线的位置有关。为方便理解，可以将环境干扰等效为电容耦合模型C0，将人体和大地之间的阻抗表示为Z0，则工频干扰的模型可以等效为图1中左半部分，即工频电源线通过等效电容C0、人体、以及接地阻抗串联接地。当人体移动时，与工频电源线的距离变化，等效电容C0的值也会随之变化。
在一些实施例中，耦合到人体的工频电流为Icm，人体表面的共模工频电势Vcm可以表示为：
Vcm＝Icm*Z0.   (1)
第一输入端A的对地阻抗为Zin1，第二输入端B的对地阻抗为Zin2，通常情况下Zin1＝Zin2＝Zin。共模输入阻抗可以表示为：
Zcm＝Zin/2.    (2)
在一些实施例中，当第一电极110和第二电极120与用户身体的接触阻抗不一致时，会导致差分放大器130的第一输入端A和第二输入端B的电势不相等，且差分放大器130会进一步将AB两点之间的电势差放大，从而导致电路饱和或失效。当人体存在共模工频电势Vcm时，差分放大器130的第一输入端A和第二输入端B之间的电势差V AB可以通过下述公式(3)表示：
Figure PCTCN2021135877-appb-000001
其中，Z1为第一电极110的接触阻抗值，Z2为第二电极120的接触阻抗值。从上述公式可知，差分放大器130的第一输入端A和第二输入端B之间的差模工频信号强度与差分放大器130的共模输入阻抗成反比，共模输入阻抗越低，则工频干扰越大。
在一些实施例中，为了减小工频干扰对信号采集产生的影响，可以采用减小电 极元件的接触阻抗的方式来降低差分放大器两输入端之间的电势差，还可以采用在人体增加接地电极的方式来降低共模工频电势，进而降低差分放大器两输入端之间的电势差，例如，将电极一端与人体接触，另一端与电路的GND连接。但因为电极元件始终存在接触阻抗，因此共模工频电势不可能完全消除。
在一些实施例中，为了减小工频干扰对信号采集产生的影响，还可以采用增大差分放大器的(共模)输入阻抗的方式。例如，可以采用具有高(共模)输入阻抗(例如，第一输入端A和第二输入端B均具有高对地阻抗)的差分放大器作为信号采集电路的输入前端。在一些实施例中，差分放大器130的(共模)输入阻抗大于100MΩ，优选地，差分放大器130的(共模)输入阻抗大于1GΩ。
然而，当信号采集电路100应用于可穿戴设备时，实际电路中存在寄生电容会导致差分放大器的输入阻抗降低。在实际应用中，不仅引线之间存在寄生电容，引线与地之间也存在寄生电容。尤其在对生理信号的采集场景中，一些生理信号(例如肌电信号、心电信号等)的信号较为微弱，这些寄生电容的影响尤为明显。在一些实施例中，这些寄生电容与信号采集电路中的各种等效阻抗并联，极大的降低了整体电路的的输入阻抗，进而加剧了工频干扰，且无法通过使用更高输入阻抗的差分放大器解决。由此可知，这些寄生电容的存在限制了信号采集电路的性能以及采集效果。
图3是根据本申请一些实施例所示的信号采集电路200的示意图。
在一些实施例中，如图3所示的信号采集电路200可以包括第一电极210、第二电极220、差分放大器230、第一引线L1、第二引线L2、第一负电容电路C10以及第二负电容电路C20。
在一些实施例中，第一电极210通过第一引线L1与差分放大器230的第一输入端A相连接，第二电极220通过第二引线L2与差分放大器230的第二输入端B相连接。其中，关于第一电极210、第二电极220、差分放大器230、第一引线L1、第二引线L2的相关描述可以参考图1中的相关描述，在此不再赘述。
在一些实施例中，第一引线L1与地线间存在第一对地寄生电容C1，第二引线L2与地线间存在第二对地寄生电容C2，第一引线L1与第二引线L2之间存在引线间寄生电容C3。如图3所示，第一对地寄生电容C1可以视为等效连接在第一引线L1和地线之间，第一对地寄生电容C1与差分放大器230的第一输入端A的对地阻抗Zin1相并联；第二对地寄生电容C2可以视为等效连接在第二引线L2和地线之间，第二对地寄生电容C2与差分放大器230的第二输入端B的对地阻抗Zin2相并联；引线间寄生 电容C3可以视为等效连接在第一引线L1与第二引线L2之间。其中，由于第一对地寄生电容C1和第二对地寄生电容C2分别与差分放大器的对地阻抗Zin1和对地阻抗Zin2相并联，极大地降低了电路整体的输入阻抗，加剧了工频干扰对信号采集的影响。
在一些实施例中，寄生电容值的变化无法实时进行测量，但由于跟电路设计相关，寄生电容值可以在电路设计好后测量出来。也就是说，可以在信号采集电路的电路设计好后测量出第一对地寄生电容C1、第二对地寄生电容C2和引线间寄生电容C3。在实际应用过程中，和人体之间的寄生电容值无法精确进行测量，但可以在人体不运动时进行测量，确定寄生电容的基准值。当人体动作时，和人体之间的寄生电容值发生变化，可以根据寄生电容的及准备确定一个大致的波动范围。
在一些实施例中，为了减少寄生电容产生的影响，以增大差分放大器的输入阻抗，信号采集电路200设置了第一负电容电路C10和第二负电容电路C20。第一负电容电路C10电气地连接所述第一引线L1和地线，第二负电容电路C20电气地连接所述第二引线L2和地线，且第一负电容电路C10和第二负电容电路C20具有负电容效应，从而能与引线的对地寄生电容抵消，以减少寄生电容的对电路输入阻抗和信号采集造成的影响，进一步提高信号采集电路的性能和信号采集的效果。这里所说的负电容效应可以理解为第一负电容电路C10和第二负电容电路C20中电荷数量的变化趋势与附加在其上的电压的变化趋势相反，也就是说随着电压的降低，第一负电容电路C10和第二负电容电路C20中的电荷数量会相应增加。
在一些实施例中，将第一负电容电路C10和/或第二负电容电路C20电气地连接地线的方式可以包括将第一负电容电路C10和/或第二负电容电路C20连接到一个或多个印刷电路板(printed circuit board，PCB)中的公用接地端。
在一些实施例中，第一负电容电路C10可以视为与第一对地寄生电容C1相并联，第二负电容电路C20可以视为与第二对地寄生电容C2相并联。第一负电容电路C10和第二负电容电路C20分别与差分放大器两个输入端的寄生电容相抵消，从而减小了差分放大器输入端的电容值，实现提高输入阻抗的效果。在一些实施例中，当第一负电容电路C10的等效电容值和第二负电容电路C20的等效电容值可以表示为：
C10＝-C1.   (4)
C20＝-C2.    (5)
则第一引线L1的对地总电容和第二引线L2的对地总电容均为0，此时差分放大器输入端的对地寄生电容被完全抵消，信号采集电路的整体输入阻抗被大幅度提高，进而增强 了抗工频干扰能力。
在一些实施例中，考虑到实际工作环境中，寄生电容可能随着引线运动而略有变化，因此负电容电路的绝对值并不完全等于寄生电容。在一些实施例中，为了较好地抵消差分放大器输入端对地寄生电容，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容值C1的相对误差小于50％，第二负电容电路C20的等效电容值的绝对值和第二引线L2的对地寄生电容值C2的相对误差小于50％。在一些实施例中，为了使得差分放大器的输入端具有更大的输入阻抗，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容值C1的相对误差小于30％，第二负电容电路C20的等效电容值的绝对值和第二引线L2的对地寄生电容值C2的相对误差小于30％。
应当理解的是，在实际应用过程中，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容C1的相对误差越小，说明第一负电容电路C10所抵消掉的第一引线L1的对地寄生电容C1越多，整个信号采集电路的输入阻抗也就越大，最终信号采集的效果也就越好。第二负电容电路C20同理，在此不过多赘述。
在一些实施例中，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容值的相对误差是指，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容值的差值与第一引线L1的对地寄生电容值的比值。
在一些实施例中，差分放大器230的第一输入端A的等效输入阻抗Zin1可以等效为一个电容Rin1和电容Cin1并联，差分放大器230的第二输入端B的等效输入阻抗Zin2可以等效为一个电容Rin2和电容Cin2并联。在一些实施例中，为了进一步提高信号采集电路200的输入阻抗性能，第一负电容电路C10和第二负电容电路C20可以调节为进一步抵消差分放大器230的等效输入电容的影响。在一些实施例中，第一负电容电路C10的等效电容值和第二负电容电路C20的等效电容值可以调节为：
C10＝-(C1+Cin1).   (6)
C20＝-(C2+Cin2).    (7)
在一些实施例中，为了较好地抵消差分放大器输入端的等效输入电容，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容值C1以及差分放大器230的第一输入端A的等效输入电容值Cin1之和的相对误差小于50％，第二负电容电路C20的等效电容值的绝对值和第二引线L2的对地寄生电容值C2以及差分放大器230的第二输入端B的等效输入电容值Cin2之和的相对误差小于50％。在一些实施 例中，为了使得差分放大器的输入端具有更大的输入阻抗，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容值C1以及差分放大器230的第一输入端A的等效电容值Cin1之和的相对误差小于30％，第二负电容电路C20的等效电容值的绝对值和第二引线L2的对地寄生电容值C2以及差分放大器230的第二输入端B的等效电容值Cin2之和的相对误差小于30％。
应当理解的是，在实际应用过程中，第一负电容电路C10的等效电容值的绝对值和第一引线L1的对地寄生电容与差分放大器的第一等效输入电容Cin1之和的相对误差越小，说明第一负电容电路C10所抵消掉的第一引线L1的对地寄生电容与差分放大器的第一等效输入电容Cin1越多，整个信号采集电路的输入阻抗也就越大，最终信号采集的效果也就越好。第二负电容电路C20同理，在此不过多赘述。
由此，使第一负电容电路C10和第二负电容电路C20各自抵消掉第一引线L1的对地寄生电容与差分放大器的第一等效输入电容Cin1以及第二引线L2的对地寄生电容与差分放大器的第二等效输入电容Cin2，进而进一步增大整个信号采集电路的输入阻抗。
在一些实施例中，信号采集电路200还可以包括第三负电容电路C30。第三负电容电路C30电气地连接在第一引线L1和第二引线L2之间，与引线间寄生电容C3相并联。在一些实施例中，由于引线间寄生电容C3的存在对电路性能影响较低，信号采集电路200可以无需设置第三负电容电路C30。在一些实施例中，当信号采集电路200的要求较高时，信号采集电路200可以设置有第三负电容电路C30。在一些实施例中，第三负电容电路C30的值可以表示为：
C30＝-C3.    (8)
在一些实施例中，第三负电容电路C30的等效电容值的绝对值和两引线间寄生电容值C3的相对误差小于50％。在一些实施例中，第三负电容电路C30的等效电容值的绝对值和两引线间寄生电容值C3的相对误差小于30％。应当理解的是，在实际应用过程中，第三负电容电路C30的等效电容值的绝对值和两引线间的对地寄生电容值C3的相对误差越小，说明第三负电容电路C30所抵消掉的引线间寄生电容C3越多，整个信号采集电路的输入阻抗也就越大，最终信号采集的效果也就越好。
在一些实施例中，信号采集电路还可以包括反馈控制电路调节第一负电容电路C10和第二负电容电路C20的等效电容值，例如，通过改变负电容电路中电阻值进行调节。
关于第一负电容电路C10、第二负电容电路C20、第三负电容电路C30的具体结构可以参见附图4A-4B的相关内容。
图4是根据本申请的一些实施例所示的信号采集电路200中负电容电路的结构示意图。
在一些实施例中，第一负电容电路C10可以是图4的结构，如图4所示，第一负电容电路C10可以包括第一运算放大器410、第一电阻R1、第二电阻R2和第一电容C401。在一些实施例中，第一运算放大器410的反向输入端经第一电阻R1接地，同时第一运算放大器410的反向输入端经第二电阻R2和第一运算放大器410的输出端相连，第一运算放大器410的同向输入端经第一电容C401和第一运算放大器410的输出端相连。在一些实施例中，图4中的m点和图3中的a点为等电势的两点，可以采用引线使a、m两点电连接。
在一些实施例中，第二负电容电路C20也可以是图4的结构，此时，图4中的m点和图3中的b点为等电势的两点，可以采用引线使m、b两点电连接。
需要说明的是，图4所示的负电容电路为具有负电容效应的等效电路。具体地，对于图4所示的负电容电路，该负电容电路的等效阻抗即为m点和GND之间的阻抗。假设m点和GND之间的阻抗为z a，则z a的阻抗可以通过下列公式(9)表示：
Figure PCTCN2021135877-appb-000002
即，m点和GND之间的阻抗可以等效为包括一个负电容或者由一个负电容产生。假设m点和GND之间的负电容为C a，则C a的等效电容值可用下列公式(10)表示：
Figure PCTCN2021135877-appb-000003
可以理解的是，C a即为图4所示的负电容电路的等效电容。
在一些实施例中，电阻R1和R2可以为阻值可调的电阻(例如，滑动变阻器、电阻箱和电位器)，也可以为阻值固定的电阻。在一些实施例中，电阻R1和R2的阻值可以相等，也可以不相等。可以理解的是，在一些实施例中，可以通过调整电阻R1和R2的阻值来调整等效电容C a的大小。
在一些实施例中，电容C401可以为纸介电容、金属化纸介电容、陶瓷电容、薄膜电容、油浸纸介电容、铝电解电容、半可变电容、可变电容等。在一些实施例中，可以通过调整电容C401的容值来调整等效电容C a的大小。
在一些实施例中，运算放大器410可以采用双电源供电，例如，电压+Vcc(411)作为正电源以及电压-Vcc(412)作为负电源，在413输出由运算放大器410产生的放大信号。在一些实施例中，运算放大器410也可以采用单电源供电，在此不过多赘述。
在一些实施例中，第一负电容电路C10和第二负电容电路C20还可以是图4以外的其他结构。
在一些实施例中，信号采集电路200还可以包括第三负电容电路C30，其中，第三负电容电路C30电气地连接所述第一引线L1和第二引线L2，第三负电容电路C30具有负电容效应。
在一些实施例中，第三负电容电路C30可以是图4的结构，此时，图4中的m点和图3中的c点为等电势的两点，图4中的GND点和图3中的d点为等电势的两点，可以采用引线使分别图3中c点与图4中m点电连接以及使图3中d点与图4中GND点电连接。
在一些实施例中，第三负电容电路C30还可以是图以外的其他结构，只要能够抵消引线间寄生电容C3，都是符合要求的。
需要注意的是，以上对于信号采集电路100、信号采集电路200及其结构的描述，仅为描述方便，并不能把本申请限制在所举实施例范围之内。
图5是根据本申请一些实施例所示的信号采集电路300的示意图。
如图5所示的信号采集电路300可以包括第一电极210、第二电极220、差分放大器230、第一引线L1、第二引线L2和第四负电容电路C40。关于第一电极210、第二电极220、差分放大器230、第一引线L1、第二引线L2的相关描述可以参考前述图1-4的相关描述，此处不再赘述。
结合前述实施例所描述的，第一引线L1与地线间存在第一对地寄生电容C1，第二引线L2与地线间存在第二对地寄生电容C2，由于第一对地寄生电容C1和第二对地寄生电容C2分别与差分放大器的对地阻抗Zin1和对地阻抗Zin2相并联，极大地降低了电路整体的输入阻抗，加剧了工频干扰对信号采集的影响。
因此，在一些实施例中，为了减少寄生电容产生的影响，以增大差分放大器230的输入阻抗，信号采集电路300设置了第四负电容电路C40。在一些实施例中，第一电极210通过第一引线L1与第四负电容电路C40的第一输入端P相连接，第二电极220通过第二引线L2与第四负电容电路C40的第二输入端Q相连接，第四负电容电路C40的第一输出端M连接到差分放大器230的第一输入端A，第四负电容电路C40的第二 输出端N连接到差分放大器230的第二输入端B。第四负电容电路C40具有负电容效应，从而能与引线的对地寄生电容抵消，以减少寄生电容的对电路输入阻抗和信号采集造成的影响，进一步提高信号采集电路的性能和信号采集的效果。
在一些实施例中，所述负电容电路C40可以通过采用具有固定增益的放大器和反馈电容进行实现，从而达到同时抵消第一对地寄生电容C1和第二对地寄生电容C2的效果。关于负电容电路C40的具体实现方式，详见图6A和6B的相关描述。
在一些实施中，信号采集电路300还可以包括第三负电容电路C30。第三负电容电路C30电气地连接在第一引线L1和第二引线L2之间，与引线间寄生电容C3相并联。在一些实施例中，由于引线间寄生电容C3的存在对电路性能影响较低，信号采集电路200可以无需设置第三负电容电路C30。在一些实施例中，当信号采集电路200的要求较高时，信号采集电路200可以设置有第三负电容电路C30。关于第三负电容电路C30的具体实现方式可以参考图3和图4中的相关描述，在此不再赘述。
在一些实施例中，信号采集电路还可以包括反馈控制电路调节第四负电容电路C40等效电容值，例如，通过改变负电容电路中电阻值或是电容值进行调节。
图6A是根据本申请一些实施例所示的信号采集电路300中第四负电容电路C40的一种结构示意图。
在一些实施例中，第四负电容电路C40可以包括第一单元C402和第二单元C404，第一单元C402包括第一放大器G2和第三负反馈电容C46，第二单元C404包括第二放大器G3和第四负反馈电容C48。在一些实施例中，第一放大器G2和第二放大器G3均为固定增益的放大器。
在一些实施例中，第一放大器G2的输入端即为第四负电容电路C40的第一输入端P，第二放大器G3的输入端即为第四负电容电路C40的第二输入端Q，同样地，第一放大器G2的输出端即为第四负电容电路C40的第一输出端M，第二放大器G3的输出端即为第四负电容电路C40的第二输出端N。
在一些实施例中，第一放大器G2的输入端P和第一放大器G2的输出端M之间通过第三负反馈电容C46串联，第二放大器G3的输入端Q和第二放大器G3的输出端N之间通过第四负反馈电容C48串联连接。
在一些实施例中，若第一放大器G2的增益恒定为g1，则第二放大器G3的增益也恒定为g1，第四负电容电路C40的第一单元C402的等效电容值可以表示为：
C402＝-C46(g1-1).    (11)
第四负电容电路C40的第二单元C404的等效电容值可以表示为：
C404＝-C48(g1-1).    (12)
在一些实施例中，第一放大器G2和第二放大器G3为增益相等且固定的放大器，例如，若第一放大器G2的增益恒定为g1，则第二放大器G3的增益也恒定为g1。在一些实施例中，第一放大器G2和第二放大器G3增益的范围可以为0～100dB，优选地，第一放大器G2和第二放大器G3增益的范围为0～10dB。
在一些实施例中，第三负反馈电容C46和第四负反馈电容C48的值相等。如此，第四负电容电路C40的第一单元C402和第二单元C404形成高度对称的结构，使得信号采集电路300整体能够获得较大的共模抑制比。在一些实施例中，若第一放大器G2和第二放大器G3的增益不相等，则电路的共模抑制比下降，无法达到减小工频干扰的效果。
在一些实施例中，第一放大器G2和第二放大器G3各自可以由多级增益固定的放大器级联构成。
在一些实施例中，第四负电容电路C40的第一单元C402可以用于抵消第一对地寄生电容C1，第四负电容电路C40的第二单元C404可以用于抵消第二对地寄生电容C2。由此，第四负电容电路C40可以用于同时抵消第一对地寄生电容C1与第二对地寄生电容C2。在一些实施例中，第一单元C402的等效电容值和第二单元C404的等效电容值可以表示为：
C402＝-C1.    (13)
C404＝-C2.   (14)
如此，第一引线L1的对地总电容和第二引线L2的对地总电容均为0。此时差分放大器230输入端的对地寄生电容被完全抵消，信号采集电路300的整体输入阻抗被大幅度提高，进而增强了抗工频干扰能力。
在一些实施例中，考虑到实际工作环境中，寄生电容可能随着引线运动而略有变化，相应地，第四负电容电路C40的第一单元C402的等效电容值的绝对值和第一引线L1的对地寄生电容值C1的相对误差小于50％，以及，第四负电容电路C40的第二单元C404的等效电容值和第二引线L2的对地寄生电容值C2的相对误差小于50％。在一些实施例中，第四负电容电路C40的第一单元C402的等效电容值的绝对值和第一引线L1的对地寄生电容值C1的相对误差小于30％，以及，第四负电容电路C40的第二单元C404的等效电容值和第二引线L2的对地寄生电容值C2的相对误差小于30％。
图6B是根据本申请一些实施例所示的信号采集电路300中第四负电容电路C40的另一种结构示意图。
在一些实施例中，第四负电容电路C40可以包括双端差分放大器G1、第一负反馈电容C42和第二负反馈电容C44。
在一些实施例中，双端差分放大器G1的第一输入端即为第四负电容电路C40的第一输入端P，双端差分放大器G1的第二输入端即为第四负电容电路C40的第二输入端Q，同样地，双端差分放大器G1的第一输出端即为第四负电容电路C40的第一输出端M，双端差分放大器G1的第二输出端即为第四负电容电路C40的第二输出端N。双端差分放大器G1的第一输入端P和双端差分放大器G1的第一输出端M之间通过第一负反馈电容C42串联连接，双端差分放大器G1的第二输入端Q和双端差分放大器G1的第二输出端N之间通过第二负反馈电容C44串联连接。
在一些实施例中，双端差分放大器G1为一个增益固定的放大器。在一些实施例中，双端差分放大器G1的增益g0的范围可以为0～100dB，优选地，g0的范围为0～10dB。
在一些实施例中，第四负电容电路C40可以用于同时抵消第一对地寄生电容C1与第二对地寄生电容C2。在一些实施例中，双端差分放大器G1可以由多个增益固定的放大器组合构成，例如，该双端差分放大器G1可以由两个增益为g0的放大器G11和G12构成，其中放大器G11和G12为固定增益且增益相同的放大器，其结构也可完全相同。在一些实施例中，放大器G11的输入端为P点，输出端即为M点，第一负反馈电容C42串联连接P点与M点，放大器G11与第一负反馈电容C42组成的电路结构可以用于抵消第一对地寄生电容C1。在一些实施例中，放大器G12的输入端为Q点，输出端为N点，第二负反馈电容C44串联连接Q点与N点，放大器G12与第二负反馈电容C44组成的电路结构可以用于抵消第一对地寄生电容C1。在一些实施例中，放大器G11与第一负反馈电容C42组成的电路结构的等效电容值C11以及放大器G12与第二负反馈电容C44组成的电路结构的等效电容值C12可以表示为：
C11＝-C42(g0-1).    (15)
C12＝-C45(g0-1).    (16)
此时，放大器G11与第一负反馈电容C42组成的电路结构可以用于抵消第一对地寄生电容C1，放大器G12与第二负反馈电容C44组成的电路结构可以用于抵消第二对地寄生电容C2，此时差分放大器输入端的对地寄生电容被抵消，信号采集电路的整 体输入阻抗被大幅度提高，进而增强了抗工频干扰能力。
在一些实施例中，为了较好地抵消差分放大器输入端对地寄生电容，放大器G11与第一负反馈电容C42组成的电路结构的等效电容值C11的绝对值和第一引线L1的对地寄生电容值C1的相对误差小于50％，放大器G12与第二负反馈电容C44组成的电路结构的等效电容值C12的绝对值和第二引线L2的对地寄生电容值C2的相对误差小于50％。在一些实施例中，为了使得差分放大器的输入端具有更大的输入阻抗，放大器G11与第一负反馈电容C42组成的电路结构的等效电容值C11的绝对值和第一引线L1的对地寄生电容值C1的相对误差小于30％，放大器G12与第二负反馈电容C44组成的电路结构的等效电容值C12的绝对值和第二引线L2的对地寄生电容值C2的相对误差小于30％。
应当理解的是，在实际应用过程中，放大器G11与第一负反馈电容C42组成的电路结构的等效电容值C11的绝对值和第一引线L1的对地寄生电容值C1的相对误差越小，且放大器G12与第二负反馈电容C44组成的电路结构的等效电容值C12和第二引线L2的对地寄生电容值C2的相对误差越小，说明第四负电容电路C40所抵消掉的第一引线L1的对地寄生电容C1以及第二引线L2的对地寄生电容值C2越多，整个信号采集电路的输入阻抗也就越大，最终信号采集的效果也就越好。
在一些实施例中，第四负电容电路C40的结构还可以为图6A和图6B以外的其他结构，只要C40的等效电容值可以抵消掉第一引线L1的第一对地寄生电容值C1和第二引线L2的对地寄生电容值C2即可，在此不做过多限制。
图7A是根据本申请的一些实施例所示的消除工频干扰前的效果电路示意图。图7B是根据本申请的一些实施例所示的消除工频干扰后的效果电路示意图。
在一些实施例中，如图7A所示提供了一个模拟的信号采集电路400，该信号采集电路400包括共模工频源501、差分放大器530、阻值为10MΩ的电阻R5、阻值为100KΩ的电阻R6、电容值都为6PF的电容C5和C6，其中，电阻R5通过第一引线L11和差分放大器530的第一输入端(A1)相连接，电阻R6通过第二引线L22和差分放大器530的第二输入端(B1)相连接，电容C5的一端和差分放大器530的第一输入端(A1)相连接，同时也连接在第一引线L11上，电容C5的另一端接地，电容C6的一端和差分放大器530的第二输入端(B1)相连接，同时也连接在第二引线L22上，电容C6的另一端接地。
需要说明的是，共模工频源501为一个电压峰值为300mv、频率为50Hz的交 流电源，用于模拟人体所产生的共模工频信号。R5和R6的阻值可以具有差异，用于模拟实际的可穿戴设备在采集人体信号时，在两电极间形成的阻抗失配。电容C5和C6用于模拟实际的可穿戴设备在采集人体信号时，两引线各自对地形成的寄生电容。
在一些实施例中，差分放大器530采用双端供电的方式，差分放大器530的第一供电端(511)连接正电源+Vcc，第二供电端(512)连接负电源-Vcc，同时接收偏置电压的一端(513)接地。在一些实施例中，正电源+Vcc提供3.3V的电压，负电源-Vcc提供-3.3V的电压。
在一些实施例中，信号采集电路400还包括第一探针T1和第二探针T2，第一探针T1设置在信号的输入侧，与差分放大器530的第一输入端(A1)相连接，第二探针T2设置在信号的输出侧，与差分放大器530的输出端(514)相连接。第一探针T1和第二探针T2分别用于测量电压信号在输入差分放大器530前和输入差分放大器530后的电压峰值、有效值、频率等。经测试后，得到的数据如下表1：
表1
  电压峰值 电压有效值 电压直流 电压频率
第一探针T1 11.4mV 196mV 196mV 50Hz
第二探针T2 11.4mV 195mV 195mV 50.2Hz
图7B是根据本申请的一些实施例所示的消除工频干扰后的效果电路示意图。图7B在图7A的基础上，加入了负电容电路C510和负电容电路C520。其中，负电容电路C510和负电容电路C520的结构都采用了图4的结构，负电容电路C510的x点与第一引线L11上的X点电连接，负电容电路C520的y点与第二引线L22上的Y点电连接。
在一些实施例中，负电容电路C510的运算放大器502的第一供电端(521)连接正电源+Vcc，第二供电端(522)连接负电源-Vcc，运算放大器502的输出端(523)输出放大的电压。在一些实施例中，正电源+Vcc提供3.3V的电压，负电源-Vcc提供-3.3V的电压，电容C501的大小为6PF，电阻R51和电阻R51的大小都为10KΩ。
根据上述公式(10)，可计算得出负电容电路C510的电容值大小为-6PF。
负电容电路C520采用和负电容电路C510相同的结构和相同取值的元件，因此负电容电路C520的电容值大小也为-6PF。
为了验证加入两负电容电路后，整个信号采集电路400的工频干扰确实下降了，再次用第一探针T1和第二探针T2进行测试，得到的数据如下表2：
表2
  电压峰值 电压有效值 电压直流 电压频率
第一探针T1 1.17mV 196mV 196mV 50Hz
第二探针T2 1.10mV 195mV 195mV 50.2Hz
对比表1和表2的数据可知，在加入负电容电路C510和负电容电路C520前，第一探针T1和第二探针T2所测得的电压峰值都为11.4mV；在加入负电容电路C510和负电容电路C520后，第一探针T1所测得的电压峰值为1.17mV，第二探针T2所测得的电压峰值为1.10mV。由此可见，在加入负电容电路C510和负电容电路C520后，整个电路的工频干扰下降了10倍以上。
这一结果表明，通过在差分放大器的输入端引入负电容电路，能够显著增大输入阻抗，进而降低电极阻抗失配导致的工频共模转差模带来的干扰，从而极大降低电路饱和风险。
在一些实施例中，以上所描绘的信号采集电路200和信号采集电路300可以应用在可穿戴设备中。所述可穿戴设备(例如，服装、护腕、肩带等)可以设置在人体各个部位(例如，小腿、大腿、腰、后背、胸部、肩部、颈部等)，用于采集用户在不同状态时其身体各个部位的生理信号，后续还可以进一步对采集的信号进行处理。
需要说明的是，上述信号采集电路可以用于需要检测能够体现用户身体状态的信号的场景，例如，所述生理信号可以包括呼吸信号、心电信号、肌电信号、脑电信号、血压信号、温度信号等多种信号。在一些实施例中，采集生理信号的可穿戴设备可以被应用于医疗、游戏娱乐、健康教育等交叉新兴产业。例如，可以与虚拟现实、EMG采集等技术结合，促进沉浸式娱乐、教育等的发展；可以与机械电子、外骨骼机器等技术的结合，以达到降低医疗成本、促进医疗健康发展的目的。本申请不限定信号采集电路以及可穿戴设备的具体应用场景。
本申请实施例可能带来的有益效果包括但不限于：通过设置负电容电路来抵消信号采集电路中的寄生电容，进而整个信号采集电路的输入阻抗得到了有效增加，最终大大减少了寄生电容对整个信号采集电路的干扰，提高了信号采集电路采集信号的有效性。
需要说明的是，不同实施例可能产生的有益效果不同，在不同的实施例里，可能产生的有益效果可以是以上任意一种或几种的组合，也可以是其他任何可能获得的有益效果。
上文已对基本概念做了描述，显然，对于本领域技术人员来说，上述详细披露仅仅作为示例，而并不构成对本申请的限定。虽然此处并没有明确说明，本领域技术人员可能会对本申请进行各种修改、改进和修正。该类修改、改进和修正在本申请中被建议，所以该类修改、改进、修正仍属于本申请示范实施例的精神和范围。
同时，本申请使用了特定词语来描述本申请的实施例。如“一个实施例”、“一实施例”、和/或“一些实施例”意指与本申请至少一个实施例相关的某一特征、结构或特点。因此，应强调并注意的是，本说明书中在不同位置两次或多次提及的“一实施例”或“一个实施例”或“一个替代性实施例”并不一定是指同一实施例。此外，本申请的一个或多个实施例中的某些特征、结构或特点可以进行适当的组合。
此外，本领域技术人员可以理解，本申请的各方面可以通过若干具有可专利性的种类或情况进行说明和描述，包括任何新的和有用的工序、机器、产品或物质的组合，或对他们的任何新的和有用的改进。相应地，本申请的各个方面可以完全由硬件执行、可以完全由软件(包括固件、常驻软件、微码等)执行、也可以由硬件和软件组合执行。以上硬件或软件均可被称为“数据块”、“模块”、“引擎”、“单元”、“组件”或“系统”。此外，本申请的各方面可能表现为位于一个或多个计算机可读介质中的计算机产品，该产品包括计算机可读程序编码。
计算机存储介质可能包含一个内含有计算机程序编码的传播数据信号，例如在基带上或作为载波的一部分。该传播信号可能有多种表现形式，包括电磁形式、光形式等，或合适的组合形式。计算机存储介质可以是除计算机可读存储介质之外的任何计算机可读介质，该介质可以通过连接至一个指令执行系统、装置或设备以实现通讯、传播或传输供使用的程序。位于计算机存储介质上的程序编码可以通过任何合适的介质进行传播，包括无线电、电缆、光纤电缆、RF、或类似介质，或任何上述介质的组合。
此外，除非权利要求中明确说明，本申请所述处理元素和序列的顺序、数字字母的使用、或其他名称的使用，并非用于限定本申请流程和方法的顺序。尽管上述披露中通过各种示例讨论了一些目前认为有用的发明实施例，但应当理解的是，该类细节仅起到说明的目的，附加的权利要求并不仅限于披露的实施例，相反，权利要求旨在覆盖所有符合本申请实施例实质和范围的修正和等价组合。例如，虽然以上所描述的系统组件可以通过硬件设备实现，但是也可以只通过软件的解决方案得以实现，如在现有的处理设备或移动设备上安装所描述的系统。
同理，应当注意的是，为了简化本申请披露的表述，从而帮助对一个或多个发 明实施例的理解，前文对本申请实施例的描述中，有时会将多种特征归并至一个实施例、附图或对其的描述中。但是，这种披露方法并不意味着本申请对象所需要的特征比权利要求中提及的特征多。实际上，实施例的特征要少于上述披露的单个实施例的全部特征。
一些实施例中使用了描述成分、属性数量的数字，应当理解的是，此类用于实施例描述的数字，在一些示例中使用了修饰词“大约”、“近似”或“大体上”来修饰。除非另外说明，“大约”、“近似”或“大体上”表明所述数字允许有±20％的变化。相应地，在一些实施例中，说明书和权利要求中使用的数值参数均为近似值，该近似值根据个别实施例所需特点可以发生改变。在一些实施例中，数值参数应考虑规定的有效数位并采用一般位数保留的方法。尽管本申请一些实施例中用于确认其范围广度的数值域和参数为近似值，在具体实施例中，此类数值的设定在可行范围内尽可能精确。
针对本申请引用的每个专利、专利申请、专利申请公开物和其他材料，如文章、书籍、说明书、出版物、文档等，特此将其全部内容并入本申请作为参考。与本申请内容不一致或产生冲突的申请历史文件除外，对本申请权利要求最广范围有限制的文件(当前或之后附加于本申请中的)也除外。需要说明的是，如果本申请附属材料中的描述、定义、和/或术语的使用与本申请所述内容有不一致或冲突的地方，以本申请的描述、定义和/或术语的使用为准。
最后，应当理解的是，本申请中所述实施例仅用以说明本申请实施例的原则。其他的变形也可能属于本申请的范围。因此，作为示例而非限制，本申请实施例的替代配置可视为与本申请的教导一致。相应地，本申请的实施例不仅限于本申请明确介绍和描述的实施例。

Claims (22)

  1. 一种信号采集电路，其特征在于，包括：
    差分放大器，
    第一电极和第二电极，其中，所述第一电极通过第一引线与所述差分放大器的第一输入端相连接，所述第二电极通过第二引线与所述差分放大器的第二输入端相连接；以及
    第一负电容电路和第二负电容电路，其中，所述第一负电容电路电气地连接所述第一引线和地线，所述第二负电容电路电气地连接所述第二引线和地线，所述第一负电容电路和所述第二负电容电路都具有负电容效应。
  2. 根据权利要求1所述的信号采集电路，其特征在于，所述第一负电容电路的等效电容值的绝对值和所述第一引线的对地寄生电容值的相对误差小于50％，以及，
    所述第二负电容电路的等效电容值的绝对值和所述第二引线的对地寄生电容值的相对误差小于50％。
  3. 根据权利要求1所述的信号采集电路，其特征在于，所述差分放大器的第一输入端存在第一等效输入电容，所述差分放大器的第二输入端存在第二等效输入电容，
    所述第一负电容电路的等效电容值的绝对值和所述第一引线的对地寄生电容与所述第一等效输入电容之和的相对误差小于50％，以及，
    所述第二负电容电路的等效电容值的绝对值和所述第二引线的对地寄生电容与所述第二等效输入电容之和的相对误差小于50％。
  4. 根据权利要求1所述的信号采集电路，其特征在于，所述信号采集电路还包括第三负电容电路，其中，
    所述第三负电容电路电气地连接所述第一引线和所述第二引线，所述第三负电容电路具有负电容效应。
  5. 根据权利要求4所述的信号采集电路，其特征在于，所述第三负电容电路的等效电容值的绝对值和所述第一引线和所述第二引线间的寄生电容值的相对误差小于50％。
  6. 根据权利要求1所述的信号采集电路，其特征在于，所述第一负电容电路包括第一运算放大器、第一电阻、第二电阻和第一电容，所述第二负电容电路包括第二运算放大器、第三电阻、第四电阻和第二电容；
    所述第一运算放大器的反向输入端经所述第一电阻接地，同时所述第一运算放大器的反向输入端经所述第二电阻和第一运算放大器的输出端相连，所述第一运算放大器的同向输入端经所述第一电容和第一运算放大器的输出端相连；
    所述第二运算放大器的反向输入端经所述第三电阻接地，同时所述第二运算放大器的反向输入端经所述第四电阻和第二运算放大器的输出端相连，所述第二运算放大器的同向输入端经所述第二电容和第二运算放大器的输出端相连。
  7. 根据权利要求6所述的信号采集电路，其特征在于，所述第一运算放大器的同向输入端和所述第一引线相连，所述第二运算放大器的同向输入端和所述第二引线相连。
  8. 根据权利要求1所述的信号采集电路，其特征在于，所述信号采集电路还包括反馈控制电路调节所述第一负电容电路和所述第二负电容电路的等效电容值。
  9. 根据权利要求1所述的信号采集电路，其特征在于，所述差分放大器的输入阻抗大于一百兆欧。
  10. 根据权利要求1所述的信号采集电路，其特征在于，所述差分放大器为正负电压双端供电。
  11. 根据权利要求1所述的信号采集电路，其特征在于，所述差分放大器为单电压供电。
  12. 一种信号采集电路，其特征在于，包括：
    差分放大器，
    第一电极和第二电极，以及
    第四负电容电路，其中，所述第一电极通过所述第一引线与所述第四负电容电路的第一输入端相连接，所述第二电极通过第二引线与所述第四负电容电路的第二输入端相 连接，所述第四负电容电路的第一输出端连接到所述差分放大器的第一输入端，所述第四负电容电路的第二输出端连接到所述差分放大器的第二输入端，所述第四负电容电路具有负电容效应。
  13. 根据权利要求12所述的信号采集电路，其特征在于，所述第四负电容电路包括双端差分放大器、第一负反馈电容和第二负反馈电容，其中，
    所述双端差分放大器的第一输入端和所述双端差分放大器的第一输出端之间连接所述第一负反馈电容，所述双端差分放大器的第二输入端和所述双端差分放大器的第二输出端之间连接所述第二负反馈电容。
  14. 根据权利要求13所述的信号采集电路，其特征在于，所述双端差分放大器为增益固定的放大器。
  15. 根据权利要求12所述的信号采集电路，其特征在于，所述第四负电容电路包括第一单元和第二单元，所述第一单元包括第一放大器和第三负反馈电容，所述第二单元包括第二放大器和第四负反馈电容，其中，
    所述第一放大器的输入端和所述第一放大器的输出端之间连接所述第三负反馈电容，所述第二放大器的输入端和所述第二放大器的输出端之间连接所述第四负反馈电容。
  16. 根据权利要求15所述的信号采集电路，其特征在于，所述第四负电容电路的第一单元的等效电容值的绝对值和所述第一引线的对地寄生电容值的相对误差小于50％，以及，
    所述第四负电容电路的第二单元的等效电容值的绝对值和所述第二引线的对地寄生电容值的相对误差小于50％。
  17. 根据权利要求15所述的信号采集电路，其特征在于，所述第一放大器和所述第二放大器为增益相等且固定的放大器。
  18. 根据权利要求12所述的信号采集电路，其特征在于，所述信号采集电路还包括反馈控制电路调节所述第四负电容电路的等效电容值。
  19. 根据权利要求12所述的信号采集电路，其特征在于，所述差分放大器的输入阻抗大于一百兆欧。
  20. 根据权利要求12所述的信号采集电路，其特征在于，所述差分放大器为正负电压双端供电。
  21. 根据权利要求12所述的信号采集电路，其特征在于，所述差分放大器为单电压供电。
  22. 一种可穿戴设备，其特征在于，包括如权利要求1～21中任一项所述的信号采集电路。
PCT/CN2021/135877 2021-12-06 2021-12-06 一种信号采集电路及可穿戴设备 WO2023102702A1 (zh)

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