WO2023102310A1 - Système de mémoire hybride à bande passante accrue - Google Patents

Système de mémoire hybride à bande passante accrue Download PDF

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Publication number
WO2023102310A1
WO2023102310A1 PCT/US2022/079564 US2022079564W WO2023102310A1 WO 2023102310 A1 WO2023102310 A1 WO 2023102310A1 US 2022079564 W US2022079564 W US 2022079564W WO 2023102310 A1 WO2023102310 A1 WO 2023102310A1
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Prior art keywords
pins
conductors
data
clock
twenty
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Application number
PCT/US2022/079564
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English (en)
Inventor
Jungwon Suh
Original Assignee
Qualcomm Incorporated
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Priority claimed from US17/658,846 external-priority patent/US20230170037A1/en
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of WO2023102310A1 publication Critical patent/WO2023102310A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4013—Coupling between buses with data restructuring with data re-ordering, e.g. Endian conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1009—Data masking during input/output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Definitions

  • the technology of the disclosure relates generally to memory systems and, more particularly, to memory systems that operate in the loint Electron Device Engineering Council (IEDEC) low-power double data rate (LPDDR) specification space.
  • IEDEC loint Electron Device Engineering Council
  • LPDDR low-power double data rate
  • aspects disclosed in the detailed description include a hybrid memory system with improved bandwidth.
  • a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four.
  • bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed.
  • coding techniques tailored to the pin count and pin layout are provided.
  • an integrated circuit includes a memory bus interface including thirty-two pins. Twenty-four pins correspond to data conductors, four pins correspond to clock conductors, and four pins correspond to read strobe clock (RDQS) conductors.
  • the IC also includes routing and encoding logic associated with the memory bus interface and configured to route signals to pins within the memory bus interface.
  • a computing device in another aspect, includes a host.
  • the host includes a physical layer (PHY) including thirty-two pins. Twenty-four pins correspond to data conductors, four pins correspond to clock conductors, and four pins correspond to RDQS conductors.
  • the host also includes routing and encoding logic associated with the PHY and configured to route signals to pins within a memory bus interface.
  • the computing device also includes a memory bus.
  • the memory bus includes twenty-four data conductors, two differential clock channels, and two differential RDQS channels.
  • the computing device also includes a memory module.
  • the memory module includes an input-output (IO) block including the thirty-two pins corresponding to the conductors of the memory bus.
  • IO input-output
  • an IC in another aspect, includes a memory bus interface.
  • the memory bus interface includes a plurality of data pins corresponding to data conductors.
  • the memory bus interface also includes a plurality of clock pins corresponding to clock conductors.
  • the IC also includes routing and encoding logic associated with the memory bus interface and configured to encode a byte onto a plurality of data conductors associated with the plurality of data pins.
  • Figure 1 A is a block diagram of an exemplary memory system using a memory bus according to exemplary aspects of the present disclosure
  • Figure IB is a block diagram of an exemplary memory system with a first arrangement of banks within two pseudo-channels
  • Figure 1C is a block diagram of an exemplary memory system with a second arrangement of banks within two pseudo-channels
  • Figure 2A is a signaling chart illustrating a two data conductor per byte encoding scheme according to an exemplary aspect of the present disclosure
  • Figure 2B is a signaling chart illustrating a three data conductor per byte encoding scheme according to an exemplary aspect of the present disclosure
  • Figure 2C is a signaling chart illustrating a four data conductor per byte encoding scheme according to an exemplary aspect of the present disclosure
  • Figure 3A is an exemplary data receiver structure used with the encoding scheme of Figure 2A;
  • Figure 3B is an exemplary data receiver structure used with the encoding scheme of Figure 2B;
  • Figure 4 is a block diagram showing details of the receiver structure of Figure 3 A.
  • Figure 5 is a block diagram of an exemplary processor-based system that can include the memory system of Figure 1.
  • a hybrid memory system with improved bandwidth.
  • a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four.
  • bandwidth may be further improved by increasing a clock frequency from a first value to a second value.
  • EMC electromagnetic compatibility
  • power burden may occur by increasing the clock frequency, this burden is less than would be present from merely doubling the clock frequency.
  • coding techniques tailored to the pin count and pin layout are provided.
  • DDR double data rate
  • SDR single data rate
  • a typical one channel LPDDR5 system interface consists of sixteen data conductors (DQs), two data mask inversion (DMI) conductors that include data mask and data bus inversion information, two differential clock channels (i.e., four conductors), two differential read strobe clock (RDQS) channels (i.e., four conductors), a command and address (CA) channel, a command clock channel, a chip select channel, and a reset channel.
  • DQs data conductors
  • DMI data mask inversion
  • RQS read strobe clock
  • CA command and address
  • a second way that the bandwidth may be doubled is by doubling the number of data conductors of the existing standard. While this approach avoids the power penalty and stability issues associated with the faster clock, this approach consumes substantially more space to accommodate pins for the additional conductors. Likewise, routing conductors within the memory bus becomes increasingly challenging with that many conductors.
  • Exemplary aspects of the present disclosure strike a compromise by increasing a number of conductors, but not doubling the number of conductors and increasing a clock frequency, but not doubling the clock frequency. While there is some additional burden imposed by the extra conductors, the routing is not insurmountable. Likewise, while some burden is applied by the increased frequency, the increased frequency is not insurmountable.
  • Figure 1A is a block diagram of a memory system 100 that includes a host 102 and a plurality of memory devices 104(l)-104(N) coupled by one or more memory buses 106 (only one shown).
  • the host 102 may be an integrated circuit (IC) that performs as a system on a chip (SoC), application processor, main modem, or other control circuit that is designed to access the memory devices 104(l)-104(N).
  • the host 102 may include a neural processing unit 108, a graphics processing unit (GPU) and multimedia engine 110, and/or a multi-core central processing unit (CPU) 112.
  • the neural processing unit 108, the GPU and multimedia engine 110, and/or the multi-core CPU 112 may communicate with a memory controller 114 through a system bus 116.
  • the memory controller 114 may send data to a physical layer (PHY) 118 across a data line 120.
  • PHY physical layer
  • the PHY 118 is a memory bus interface and includes a routing and encoding logic 122 (or comparable circuit performing the same functions) that routes the data from the data line 120 to appropriate pins (e.g., data pins) coupled to the memory bus 106.
  • the memory devices 104(l)-104(N) may be identical, and accordingly, a discussion of a generic memory device 104 is provided.
  • the memory device 104 may include an input-output (I/O) block 124.
  • the I/O block 124 is a memory bus interface and communicates with banks 126 of data cell arrays 128 using read and write commands as is well understood.
  • the I/O block 124 also includes a routing and encoding logic 130 that routes the data from the data line to appropriate pins coupled to the memory bus 106.
  • the memory bus 106 includes twenty-four data conductors, four clock conductors, and four RDQS conductors.
  • the memory bus interfaces 118, 124 may include twenty-four pins (e.g., data pins) corresponding to the data conductors, four pins (e.g., clock pins) corresponding to the clock conductors, and four pins corresponding to the RDQS conductors. Additional conductors may be provided for command and address signals, an additional clock signal, a chip select signal, and/or a reset signal.
  • pins e.g., data pins
  • clock pins e.g., clock pins
  • Additional conductors may be provided for command and address signals, an additional clock signal, a chip select signal, and/or a reset signal.
  • the conductors of the memory bus 106 are arranged in a specific layout that helps minimize crosstalk and generally simplify routing. Namely, from a first edge moving inwards, there are six data conductors (DQ0 [0:5]), a differential clock channel having two conductors (WCKO t, WCKO c), a differential RDQS channel having two conductors (RDQSO t, RDQSO c) and six data conductors (DQ0[6: l l]) shown generally as a first group 132.
  • DQ0 [0:5] there are six data conductors (DQ0 [0:5]), a differential clock channel having two conductors (WCKO t, WCKO c), a differential RDQS channel having two conductors (RDQSO t, RDQSO c) and six data conductors (DQ0[6: l l]) shown generally as a first group 132.
  • a command and address (CA[0:k]) channel conductor In a center section of the memory bus 106, a command and address (CA[0:k]) channel conductor, a differential command clock channel having two conductors (CK_t, CK_c), a chip select channel conductor, and a reset channel conductor may be positioned shown generally as a middle group 134. Then, moving outwards toward a second edge of the memory bus, there are six data conductors (DQ1 [6: 11]), a differential clock channel having two conductors (WCKl t, WCKl c), a differential RDQS channel having two conductors (RDQSl t, RDQSl c) and six data conductors (DQl [0:5]) shown generally as a second group 136. While there are reasons for this arrangement in terms of ease of routing, electromagnetic interference (EMI), and/or electromagnetic compatibility (EMC) (e.g., crosstalk), it should be appreciated that other arrangements may also
  • the memory controller 114 may include an error correcting code (ECC) circuit 140, which may encode and decode ECC signals.
  • ECC error correcting code
  • the data cell arrays 128 may include an ECC cell 142 that stores parity bits and works with the ECC circuit 140 for error correction.
  • ECC parity bits (p, as opposed to data 2*n) may be transmitted over an RDQS pin (e.g., RDQS t, RDQS c, or both) from the host 102 to the memory device 104 such as during a write operation.
  • the ECC parity bits may be transmitted over data mask slots (e.g., M[0:31] detailed further below) during a read operation.
  • the host 102 may use the data mask slots (e.g., M[0:31]) for a write operation.
  • the data cell arrays 128 may be arranged into banks in various configurations. Two exemplary bank arrangements are provided in Figures IB and 1C.
  • Figure IB illustrates a data cell array 128B, which is related to the existing LPDDR5 standard and has a first memory block 150A having eight bank groups (BG), each with two banks and a second memory block 150B also having eight bank groups (BG), each with two banks, for a total of thirty-two banks.
  • the thirty-two banks are divided into two pseudo-channels 152A, 152B.
  • the data cell array 128B may include an interface 154 that has a first 12 DQ conductors (DQ[l l :0]), two conductors that form a first differential write clock (WCK0), and a pair of conductors that form a first redundant data strobe (RDQS0) in a first group 156; and a second twelve DQ conductors (DQ[23:12]), two conductors that form a second differential write clock (WCK1), and two conductors that form a second redundant data strobe (RDQS1) in a second group 158.
  • DQ[l l :0] first 12 DQ conductors
  • WCK0 differential write clock
  • RQS0 redundant data strobe
  • the groups 156, 158 share a differential clock (CK), seven command and address conductors (CA[7:0]), a chip select conductor (CS), and a reset conductor (all shown in middle group 160).
  • the memory device(s) 104 may have: a maximum bandwidth of 25.6 gigabytes per second (GB/s), an input/output (IO) speed of 6400 megabits per second (Mbps), a maximum CK frequency of 1600 megahertz (MHz), a maximum WCK frequency of 3200 MHz, a CA speed of 3200 megatransfers per second (MT/s), and operate on a pulse amplitude modulation (PAM) and/or a non-retum-to-zero (NRZ) signaling scheme.
  • PAM pulse amplitude modulation
  • NZ non-retum-to-zero
  • the interface 154 is configured to receive commands and/or data from a remote source such as, for example, the host 102.
  • the data cell array 128B is one possible implementation of an improved memory configuration, there are other architectures such as data cell array 128C illustrated in Figure 1C.
  • the data cell array 128C includes a first memory block 170(0) having sixteen banks and a second memory block 170(1) having sixteen banks, for a total of thirty -two banks.
  • the thirty -two banks are divided into two pseudo-channels 172(0), 172(1).
  • the pin/conductors of an interface 174 are somewhat different. Specifically, the conductors are mirrored around a central reset conductor 176 that is common to both pseudo-channels 172(0), 172(1).
  • Each pseudo-channel 172(0), 172(1) includes a respective chip select conductor 178(0), 178(1) and four command and address conductors 180(0), 180(1) (CA0[3:0], CAl[3:0]). Additionally, a differential clock conductor 182(0), 182(1) (also referred to as CK0_t/c and CKl_t/c) may be provided to each pseudo-channel 172(0), 172(1).
  • a first set of data channel conductors 184(0), 184(1) (DQ0[15:8], DQ1 [8: 15]) may be next.
  • Breaking up the data channels are a differential write clock conductor pair 186(0), 186(1) (WCK0_t/c, WCKl_t/c) and a differential RDQS conductor pair 188(0), 188(1) (RDQS0_t/c, RDQSl_t/c).
  • the final data channel conductors 190(0), 190(1) (DQ0[7:0], DQ1[O:7]) provide the external conductors.
  • the position of the data conductors DQ are spread apart and separated by other conductors to reduce crosstalk and other EMI/EMC concerns. Likewise, by pairing the positive and negative differential signals on conductors adjacent to one another, emissions are likewise reduced.
  • Figure 2A is a signaling chart illustrating two data conductors being used for a single byte (Dx-Dx+7, e.g., D0-D7 or other arrangements such as DQ[48:51] + DQ[64:67]) as generally shown at 200(l)-200(3).
  • a data mask signal (Mx-Mx+7, e.g., M0-M7)) is provided as generally shown by 202(1 )-202(2).
  • a clock signal 206 is 4.8 GHz.
  • the clock signal 206 is 6.4 GHz.
  • the routing and encoding logic 122 or 130 may combine data signals and data mask signals so as to encode a byte across three conductors as shown in Figure 2B.
  • a byte is generally shown at 250(l)-250(2) encoded across three conductors.
  • the data mask bit 252(l)-252(2) is encoded in the ninth slot for each byte.
  • the clock signal 206 is 4.8 GHz.
  • the clock signal 206 is 6.4 GHz.
  • the routing and encoding logic 122 or 130 may combine data signals and data mask signals so as to encode a byte across four conductors as shown in Figure 2C.
  • a byte is generally shown at 260(l)-260(2) encoded across four conductors.
  • the data mask bits 262(1 )-262(8) are grouped and encoded in one byte after eight bytes.
  • the clock signal 206 is 4.8 GHz.
  • the clock signal 206 is 6.4 GHz.
  • Figure 3A is an exemplary data receiver structure within the memory bus interface 118 or 124 used with the encoding scheme of Figure 2A.
  • pins 300(l)-300(6) may be used to couple to the data conductors DQ[0:5] in the first group 132.
  • Clock pins 302(l)-302(2) may be used to couple to the data clock conductors in the first group 132.
  • RDQS pins 304(l)-304(2) may be used to couple to the RDQS conductors in the first group 132, and pins 300(7)-300(12) may be used to couple to the data conductors DQ[6: 11] in the first group 132.
  • the pins 300(l)-300(12) are coupled to respective receiver/transmitter circuitry 306(l)-306(12).
  • the receiver/transmitter circuitry 306(l)-306(12) may be coupled in pairs to data registers 308(l)-308(6).
  • the RDQS pins 304(l)-304(2) may be coupled to an RDQS driver 310.
  • the clock pins 302(l)-302(2) may be coupled to a clock receiver and quad phase generator 312.
  • Figure 3B is an exemplary data receiver structure within the memory bus interface 118 or 124 used with the encoding scheme of Figure 2B.
  • the pins 300(l)-300(6) may be used to couple to the data conductors DQ[0:5] in the first group 132.
  • the clock pins 302(l)-302(2) may be used to couple to the data clock conductors in the first group 132.
  • the RDQS pins 304(l)-304(2) may be used to couple to the RDQS conductors in the first group 132, and the pins 300(7)-300(12) may be used to couple to the data conductors DQ[6: 11] in the first group 132.
  • the pins 300(l)-300(12) are coupled to respective receiver/transmitter circuitry 306(l)-306(12).
  • the receiver/transmitter circuitry 306(l)-306(12) may be coupled in sets of three to data registers 350(l)-350(4).
  • the RDQS pins 304(l)-304(2) may be coupled to the RDQS driver 310.
  • the clock pins 302(l)-302(2) may be coupled to the clock receiver and quad phase generator 312.
  • Figure 4 is a block diagram showing details of how a receiver 306 may accommodate quad phased data.
  • a pin 300(1) may be coupled to four delay and comparators 400(l)-400(4) to populate bit register slots 402(l)-402(4).
  • a pin 300(2) may be coupled to four delay and comparators 400(5)-400(8) to populate bit register slots 402(5)-402(8).
  • a comparator 400(l)-400(8) exceeds a threshold, a logical high (or low) may be output to the bit register slots 402(l)-402(8).
  • two clock cycles (2 WCK) may generate four phase data clocks where the first rising edge of WCK is WCK 0, the first falling edge of WCK is WCK 90, the second rising edge of WCK is WCK 180, and the second falling edge of WCK is WCK 270.
  • the hybrid memory system with improved bandwidth may be provided in or integrated into any processor-based device.
  • Examples include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video
  • GPS global positioning system
  • PDA personal
  • FIG. 5 is a system-level block diagram of an exemplary mobile communication device or mobile terminal 500 such as a smart phone, mobile computing device tablet, or the like. While a mobile terminal is particularly contemplated as being capable of benefiting from exemplary aspects of the present disclosure, it should be appreciated that the present disclosure is not so limited and may be useful in any system having a memory bus that will be compliant with existing or emerging memory standards.
  • the mobile terminal 500 includes an application processor 504 (sometimes referred to as a host or an SoC) that communicates with a mass storage element 506 through a universal flash storage (UFS) bus 508.
  • an application processor 504 sometimes referred to as a host or an SoC
  • UFS universal flash storage
  • the application processor 504 may also communicate with a DDR memory element 506A through a memory bus 508A according to exemplary aspects of the present disclosure.
  • the application processor 504 may further be connected to a display 510 through a display serial interface (DSI) bus 512 and a camera 514 through a camera serial interface (CSI) bus 516.
  • Various audio elements such as a microphone 518, a speaker 520, and an audio codec 522 may be coupled to the application processor 504 through a serial low-power interchip multimedia bus (SLIMbus) 524. Additionally, the audio elements may communicate with each other through a SOUNDWIRE bus 526.
  • a modem 528 may also be coupled to the SLIMbus 524 and/or the SOUNDWIRE bus 526.
  • the modem 528 may further be connected to the application processor 504 through a peripheral component interconnect (PCI) or PCI express (PCIe) bus 530 and/or a system power management interface (SPMI) bus 532.
  • PCI peripheral
  • the SPMI bus 532 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 534, a power management integrated circuit (PMIC) 536, a companion IC (sometimes referred to as a bridge chip) 538, and a radio frequency IC (RFIC) 540.
  • LAN or WLAN local area network
  • PMIC power management integrated circuit
  • companion IC sometimes referred to as a bridge chip
  • RFIC radio frequency IC
  • separate PCI buses 542 and 544 may also couple the application processor 504 to the companion IC 538 and the WLAN IC 534.
  • the application processor 504 may further be connected to sensors 546 through a sensor bus 548.
  • the modem 528 and the RFIC 540 may communicate using a bus 550.
  • the RFIC 540 may couple to one or more RFFE elements, such as an antenna tuner 552, a switch 554, and a power amplifier 556 through a radio frequency front end (RFFE) bus 558. Additionally, the RFIC 540 may couple to an envelope tracking power supply (ETPS) 560 through a bus 562, and the ETPS 560 may communicate with the power amplifier 556.
  • RFFE elements including the RFIC 540, may be considered an RFFE system 564. It should be appreciated that the RFFE bus 558 may be formed from a clock line and a data line (not illustrated).
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
  • RAM Random Access Memory
  • ROM Read Only Memory
  • EPROM Electrically Programmable ROM
  • EEPROM Electrically Erasable Programmable ROM
  • registers a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in a remote station.
  • processor and the storage medium may reside as discrete components in a remote station, base station, or server.
  • the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques.
  • An integrated circuit comprising: a memory bus interface comprising thirty -two pins, wherein: twenty-four pins correspond to data conductors; four pins correspond to clock conductors; and four pins correspond to read strobe clock (RDQS) conductors; and routing and encoding logic associated with the memory bus interface and configured to route signals to pins within the memory bus interface.
  • a memory bus interface comprising thirty -two pins, wherein: twenty-four pins correspond to data conductors; four pins correspond to clock conductors; and four pins correspond to read strobe clock (RDQS) conductors; and routing and encoding logic associated with the memory bus interface and configured to route signals to pins within the memory bus interface.
  • RQS read strobe clock
  • the thirty-two pins comprise a first group and a second group, wherein the first group comprises: a first six pins of the twenty -four pins corresponding to the data conductors; a first two pins of the four pins corresponding to the clock conductors positioned adjacent to the first six pins; a second two pins of the four pins corresponding to the RDQS conductors adjacent to the first two pins; and a second six pins of the twenty-four pins corresponding to the data conductors adjacent to the second two pins.
  • the second group comprises: a third six pins of the twenty-four pins corresponding to the data conductors; a third two pins of the four pins corresponding to the clock conductors positioned adjacent to the third six pins; a fourth two pins of the four pins corresponding to the RDQS conductors adjacent to the third two pins; and a fourth six pins of the twenty-four pins corresponding to the data conductors adjacent to the fourth two pins.
  • the third group of additional pins comprises: a first command clock pair of pins; a second command clock pair of pins; a first set of four command and address pins; a second set of four command and address pins; a first chip select pin; a second chip select pin; and a reset pin.
  • the memory bus interface further comprises a command and address (CA) pin, a command clock pin, a chip select pin, and a reset pin.
  • CA command and address
  • a device selected from the group consisting of: a settop box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
  • GPS global positioning system
  • routing and encoding logic is further configured to send a first error correcting code (ECC) parity bit through two of the four pins corresponding to an RDQS conductor and receive a second ECC parity bit through eight of the twenty-four pins corresponding to a data conductor.
  • ECC error correcting code
  • the routing and encoding logic is further configured to send a first error correcting code (ECC) parity bit through eight of the twenty-four pins corresponding to a data conductor and receive a second ECC parity bit through the eight of the twenty -four pins corresponding to the data conductor.
  • routing and encoding logic is further configured to send a first error correcting code (ECC) parity bit through one of the four pins corresponding to an RDQS conductor and receive a second ECC parity bit through one of the twenty -four pins corresponding to a data conductor.
  • ECC error correcting code
  • routing and encoding logic is further configured to send a first error correcting code (ECC) parity bit through one of the twenty- four pins corresponding to a data conductor and receive a second ECC parity bit through the one of the twenty-four pins corresponding to the data conductor.
  • ECC error correcting code
  • a computing device comprising: a host comprising: a physical layer (PHY) comprising thirty-two pins, wherein: twenty-four pins correspond to data conductors; four pins correspond to clock conductors; and four pins correspond to read strobe clock (RDQS) conductors; and routing and encoding logic associated with the PHY and configured to route signals to pins within a memory bus interface; a memory bus comprising: twenty-four data conductors; two differential clock channels; and two differential RDQS channels; and a memory module comprising: an input-output (IO) block comprising the thirty-two pins corresponding to the conductors of the memory bus.
  • PHY physical layer
  • RQS read strobe clock
  • An integrated circuit comprising: a memory bus interface comprising: a plurality of data pins corresponding to data conductors; and a plurality of clock pins corresponding to clock conductors; and routing and encoding logic associated with the memory bus interface and configured to encode a byte onto a plurality of data conductors associated with the plurality of data pins.
  • routing and encoding logic is configured to encode the byte onto two data conductors of the plurality of data conductors.
  • routing and encoding logic is configured to encode the byte onto three data conductors of the plurality of data conductors.
  • routing and encoding logic is configured to encode the byte onto four data conductors of the plurality of data conductors.
  • routing and encoding logic is configured to encode data mask inversion (DMI) information onto at least one data conductor of the plurality of data conductors.
  • DMI data mask inversion
  • routing and encoding logic is further configured to send a first error correcting code (ECC) parity bit through one data conductor of the plurality of data conductors and receive a second ECC parity bit.
  • ECC error correcting code

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Abstract

Est divulgué un système de mémoire hybride à bande passante améliorée. Selon un aspect, un système de mémoire est fourni, lequel augmente une bande passante par rapport à la norme JEDEC de faible puissance à double débit de données version 5 (LPDDR5). Cette amélioration est rendue possible par l'augmentation d'un nombre de conducteurs de données de seize à vingt-quatre. Facultativement, la bande passante peut être davantage améliorée en augmentant une fréquence d'horloge d'une première valeur à une seconde valeur. Cela permet au système de mémoire hybride de fournir une bande passante améliorée sans les complications d'un simple doublement du nombres de broches ou doublement de la vitesse d'horloge. En outre, l'invention concerne des techniques de codage adaptées au nombre de broches et à la disposition des broches.
PCT/US2022/079564 2021-11-30 2022-11-09 Système de mémoire hybride à bande passante accrue WO2023102310A1 (fr)

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US202163284439P 2021-11-30 2021-11-30
US63/284,439 2021-11-30
US17/658,846 US20230170037A1 (en) 2021-11-30 2022-04-12 Hybrid memory system with increased bandwidth
US17/658,846 2022-04-12

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