WO2023101630A1 - A transistor device structure containing two-dimensional hole gas and operating in e-mode - Google Patents

A transistor device structure containing two-dimensional hole gas and operating in e-mode Download PDF

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WO2023101630A1
WO2023101630A1 PCT/TR2022/050366 TR2022050366W WO2023101630A1 WO 2023101630 A1 WO2023101630 A1 WO 2023101630A1 TR 2022050366 W TR2022050366 W TR 2022050366W WO 2023101630 A1 WO2023101630 A1 WO 2023101630A1
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Engin ARSLAN
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Antalya Bilim Universitesi Rektorlugu
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02483—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer

Definitions

  • This invention relates to a quantum well structure containing a high mobility hole gas and a transistor device, operating in E-mode (enhancement mode), fabricated using this structure, especially; It is related to lnN/[3-Ga2O3/GaN quantum well, containing two-dimensional hole gas (2DHG), based high hole mobility transistor (HHMT) device structure, which operates in E-mode, and has a high positive threshold voltage value and suitable for use in power switching studies applications.
  • 2DHG two-dimensional hole gas
  • HHMT high hole mobility transistor
  • Optoelectronic device components such as field effect transistor (FET), light emitting diode (LED), laser diode (LD), solar cell (SC) are heavily needed in high- tech device applications.
  • FET field effect transistor
  • LED light emitting diode
  • LD laser diode
  • SC solar cell
  • GaN-based high electron mobility (HEMT) transistors with high cut-off frequency and high breakdown electrical filed are used in the production of transmitter power amplifiers (PAs) which have a basic function in wireless communication stations and commercialized for this purpose. Also, GaN-based HEMT’s are considered as good candidates for next-generation power conversion devices. Due to its strong polarization fields, GaN-based alloys are extensively used in transistor device applications operating in depletion mode (D-mode).
  • D-mode depletion mode
  • Heterojunctions contains two-dimensional electron gas (2DEG) are used in the production of conventional D-mode field-effect transistor devices.
  • 2DEG two-dimensional electron gas
  • the threshold voltage value (Vth) for transistors operating in D-mode is in the order of -3,-4 V.
  • the threshold voltage value of AIGaN/GaN HEMT is determined by the design of the epitaxial layers, the Al composition, the type and concentration of doped atoms, as well as the thickness of the AIGaN barrier layer (Xintong Lyu, He Li, Yousef Abdullah, Ke Wang, Boxue Hu, Zhi Yang, Jiawei Liu, Jin Wang, Liming Liu, and Sandeep Bala, A Reliable Ultrafast Short-Circuit Protection Method for E-Mode GaN HEMT, IEEE Transactions on Power Electronics, Vol. 35, No. 9, September 2020).
  • the fabrication step to change the threshold voltage of the device. These useful methods provide much more opportunity to use in circuit applications. If the threshold voltage of the transistor devices has a positive value, the device can operate in E-mode.
  • Transistor devices that can operate in E-mode unlike transistors that can operate in D-mode, have a positive threshold voltage, eliminating the necessity to convert the power supplies connected to the circuit to negative polarity. This provides significant advantages in circuit designs. Another advantage of the device is that it has fail-safe capabilities. All of these advantages significantly reduce circuit complexity and system cost.
  • Power factor corrector (PFC) or power supply applications for servers are the other applications that require transistor devices that can operate in E-mode.
  • transistors with positive threshold voltage can prevent the wrong operation problem caused by electromagnetic noise in the system and ensure safe power switching.
  • the threshold voltage should be nearly 2-3 V interval.
  • Quantum wells or heterojunctions structures containing two-dimensional hole gas allow the production of transistor devices that can operate in E-mode with less cost and effort, since the carriers that provide the conduction are positively charged holes.
  • the hole gas formed in quantum wells or heterojunctions must have high mobility and high density values.
  • the mentioned structure and method are provided by our invention.
  • Using InN and GaN alloys as channel layer in lnN/[3-Ga2O3/GaN quantum well structure containing two-dimensional hole gas; InN and GaN channels will ensure high mobility of the 2DHG that will form in the channel layers. It will be possible for the E-mode transistor device to be produced by using a quantum well containing high mobility 2DHG to have high drain current and operate at high frequency/power values.
  • the [3-Ga2O3 alloy, which is used as a barrier layer in the quantum well structure, is a material with a high breakdown electric field (8-10 MV/cm) value.
  • the use of this alloy as a barrier layer in the quantum well structure will provide fabrication of a transistor device which have higher breakdown electric field value.
  • the invention provides the production of a E-mode transistor device with high drain-source current and can operate in high power/frequency regions by using lnN/[3-Ga2O3/GaN quantum well.
  • the invention which was fabricated using the above-described singlecrystal [3-Ga2O3 barrier layer, InN and GaN channel layer, and a quantum well containing two-dimensional hole gas formed in these two channel layers, solved the problem of high breakdown electric field and inability to reach high threshold voltage values experienced in the transistor device. In order to eliminate it and due to the inadequacy of the existing solutions on the subject, it reveals an unexpected technical effect in the relevant technical field, which cannot be inferred with the available information.
  • the invention relates to high hole mobility transistor devices operating in enhancement mode (E-mode), especially; lnN/[3-Ga2O3/GaN quantum well-based high hole mobility transistor (HHMT) device operating in E-mode, capable of operating at high and positive threshold voltage suitable for use in power switching studies, and containing two-dimensional hole gas (2DHG) with high breakdown electric field value and relates to its structure.
  • E-mode enhancement mode
  • HHMT quantum well-based high hole mobility transistor
  • HHMT high hole mobility transistor
  • the indium nitrate (InN) channel layer in which two-dimensional hole gas (2DHG) is formed,
  • This invention compensating the above-mentioned requirements, it eliminates all the disadvantages and offers some advantages. Solves the problem of low hole gas mobility (1 -5 cm 2 /Vs) and low breakdown electric field (Si (0.4 MV/cm), SiC (2 MV/cm), GaN (3.3 MV/cm)) in quantum wells.
  • this is the lnN/[3-Ga2O3/GaN quantum well structure consisting of a buffer layer, a HR-GaN interlayer, a undoped GaN channel layer, a single crystal [3-Ga2O3 barrier layer, an InN channel layer, respectively grown on a substrate, and it allows the production of transistor devices with high positive threshold voltage using this quantum wells.
  • the primary aim of this invention is to provide a HHMT device and a growth method that prevents the malfunctioning problem that arises due to electromagnetic noise in the system and enables the power switching in safety mode.
  • Another purpose of the present invention is to provide a practical HHMT growth method with a simpler circuit, low cost and simple process steps by eliminating the need to convert the power supplies connected to the circuit to negative polarity.
  • Another aim of the invention is to increase the mobility of 2DHG formed at the interfaces at the InN and GaN channel layer in the lnN/[3-Ga2O3/GaN quantum well structure grown on the supplied substrate and to provide an lnN/[3-Ga2O3/GaN quantum well structure that eliminates the low breakdown electric field problem by using a single crystal [3-Ga2O3 barrier layer, and a production method of a transistor device that can operate at high positive threshold voltage using this quantum well.
  • An aim of the invention is to provide an lnN/[3-Ga2O3/GaN quantum well contains high mobility two-dimensional hole gas, and its production method.
  • Another aim of the invention is to provide an lnN/[3-Ga2O3/GaN quantum well with high breakdown electric field value and its production method.
  • Another aim of the invention is to develop a high-hole mobility lnN/
  • Another aim of the invention is to provide lnN/[3-Ga2O3/GaN quantum wellbased transistor device with positive threshold voltage in the range of 2-3 volts and its production method.
  • HHMT high hole mobility transistor
  • Figure 1 An exemplary epitaxial view of the quantum well structure described in the invention.
  • FIG. 1 An exemplary epitaxial view of the transistor device that can operate in E-mode described in the invention.
  • the lnN/[3-Ga2O3/GaN quantum well (20) structure with mobility of at least 80-100 cm 2 /Vs and breakdown electric field value in the range of at least 8-10 MV/cm and the manufacturing method of the E-mode transistor device (200) using this quantum well structure is described.
  • This quantum well structure (20) consists of a supplied substrate (1 ), a buffer layer (2), HR-GaN interlayer (3), undoped GaN channel layer (4), single crystal beta phase gallium oxide (P-Ga2Os) barrier layer (5), InN channel layer (7), two-dimensional hole gas (2DHG) (6) formed in these two channel layers.
  • P-Ga2Os single crystal beta phase gallium oxide
  • Quantum well structure (20) in the preferred application of the invention contains a semi-insulating substrate (1 ) with a thickness between 500pm and 600pm, with only the front surface or both surfaces polished.
  • substrate (1 ) preferably oriented silicon carbide (SiC) is used as substrate (1 ); oriented silicon (Si) or oriented sapphire (AI2O3) are also used in general applications.
  • SiC silicon carbide
  • Si oriented silicon
  • AI2O3 oriented sapphire
  • the crystal defects in the HR-GaN intermediate layer (3) must be minimum.
  • a buffer layer (2) is used between the HR-GaN interlayer (3) and the substrate (1 ) in order to minimize the crystal defects that will occur in the lnN/[3-Ga2O3/GaN quantum well structure grown on substrates such as SiC, Si or sapphire.
  • the type of the buffer layer (2) (such as AIN, GaN, AIGaN layer with different Al and Ga ratios), their thickness and growth temperatures (AIN grown at high temperature (HT-AIN), AIN grown at low temperature (LT-AIN), grown at low temperature GaN (LT-GaN)) changes with respect to the used substrate materials (1 ).
  • a low temperature grown GaN layer is used as a buffer layer (2).
  • the LT-GaN buffer layer (2) is preferably grown in 570°C, in general applications grown in the temperature range of 550°C to 590°C.
  • LT-AIN and HT-AIN layers are used as buffer layer (2) between HR-GaN and substrate, respectively, in growth on SiC or Si substrates.
  • the thickness of the LT- AIN layer is preferably 25nm, and in general applications, the LT-AIN layer with a thickness between 20nm and 30nm is used.
  • the thickness of the HT-AIN layer used as the buffer layer is preferably 90nm. In general applications, the thickness of the layer is between 90nm and 120nm.
  • the growth temperature of the LT-AIN layer used in the buffer structure is preferably 650°C, in general applications it is in the range of 630°C to 680°C.
  • the growth temperature of the HT-AIN layer is preferably 1050°C, and in general applications it is in the range of 1030°C to 1100°C.
  • the thickness of the HR-GaN interlayer (3) used in the quantum well (20) structure is preferably 1.2pm; in general applications it is in the range of 1 m to 1 ,5pm.
  • the interlayer (3) is preferably grown in the temperature of 950°C, in general applications it is grown temperature change between 920°C and 980°C.
  • p-type doping is done to the HR- GaN interlayer (3).
  • P-type doping is preferably done with iron (Fe) atoms.
  • magnesium (Mg) and carbon (C) atoms are also used for doping.
  • the doping ratio is preferably in the order of 1x10 18 crrr 3
  • the thickness of the GaN channel layer (4), in which the two-dimensional hole gas is located is preferably 700nm, and in general applications it is in the range of 600nm to 800nm.
  • a single crystal [3-Ga2O3 alloy which is a material with high breakdown electric field value, is used as the barrier layer (5) in order to obtain a HHMT device (200) with a high breakdown electric field value.
  • the thickness of the barrier layer (5) is preferably 20nm, and in general applications it is value between 18nm and 25nm.
  • Growth process of single crystal [3-Ga2O3 barrier layer (5) is carried out with MDE technique under suitable growth conditions.
  • MDE molecular beam epitaxy
  • FIG. - 2 an example view of an lnN/[3-Ga2O3/GaN quantum well-based HHMT device (200) operating in the E-mode is given;
  • This device (200) includes the quantum well structure (20) and the source terminal (8), drain terminal (9), gate terminal (10) provided on this quantum well structure (20), and a passivation layer inserted between these terminals.
  • HHMT device there is an ohmic source terminal (10), a ohmic drain terminal (8) and a non-ohmic gate terminal (9), which is in direct contact with the InN channel layer (7) on the quantum well structure (20).
  • the source terminal (10) and the drain terminal (8) located on the structure preferably consist of 60nm thick titanium (Ti), 50nm thick gold (Au), 100nm thick nickel (Ni) metal, respectively.
  • These metals are evaporated by electron beam evaporation (e-beam) method, preferably under high vacuum ( ⁇ 10 -7 Torr) on quantum well structures (20) described in the invention.
  • e-beam electron beam evaporation
  • quantum well structures (20) described in the invention preferably under high vacuum ( ⁇ 10 -7 Torr) on quantum well structures (20) described in the invention.
  • metals are annealed at 750°C for 45s in nitrogen gas (N2) environment with rapid heat treatment.
  • gate terminal (9) on quantum well structures (20) is preferably composed of nickel (Ni) and gold (Au) metal, respectively, coated by electron beam evaporation method.
  • the gate terminal (10) described in the present invention preferably contains 10Onm thick nickel (Ni) metal and 50nm thick gold (Au) metal, and in general applications the thickness of the nickel (Ni) and gold (Au) metal in the range of 80nm to 120nm and 40nm to 90nm, respectively.
  • at least one of the metals titanium (Ti), indium (Ir), ruthenium (Ru), palladium (Pd), platinum (Pt) is used instead of Ni metal in the formation of the gate terminal (10).
  • a passivation layer (11 ) is inserted between the source (10), drain terminal (8) and the gate terminals (9).
  • SisN4 alloy is used as the passivation layer (11 ), but, in general applications, at least one of the SiC>2, AI2O3, HfO2 alloys is also used.
  • the thickness of the passivation layer is preferably 50nm; in general applications it can be in the range 40nm to 70nm.

Abstract

This invention relates to a quantum well structure containing a high mobility hole gas and a transistor device, operating in E-mode (enhancement mode), fabricated using this structure, especially; It is related to lnN/β-Ga2O3/GaN quantum well, containing two-dimensional hole gas (2DHG), based high hole mobility transistor (HHMT) device structure, which operates in E-mode, and has a high positive threshold voltage value and suitable for use in power switching studies applications.

Description

A TRANSISTOR DEVICE STRUCTURE CONTAINING TWO-DIMENSIONAL HOLE GAS AND OPERATING IN E-MODE
TECHNICAL AREA
This invention relates to a quantum well structure containing a high mobility hole gas and a transistor device, operating in E-mode (enhancement mode), fabricated using this structure, especially; It is related to lnN/[3-Ga2O3/GaN quantum well, containing two-dimensional hole gas (2DHG), based high hole mobility transistor (HHMT) device structure, which operates in E-mode, and has a high positive threshold voltage value and suitable for use in power switching studies applications.
BACKGROUND
Recent technological developments have made GaN, AIN, InN binary, AIGaN, AllnN, InGaN ternary and AllnGaN quaternary semiconductor alloys as most preferred due to their superior electrical and optical properties.
Optoelectronic device components such as field effect transistor (FET), light emitting diode (LED), laser diode (LD), solar cell (SC) are heavily needed in high- tech device applications. In the production of these optoelectronic device components, the semiconductor materials mentioned above meet a great need (Chao-Tsung Ma and Zhen-Huang Gu, Review of GaN HEMT Applications in Power Converters over 500 W, Electronics 2019, 8, 1401 ).
GaN-based high electron mobility (HEMT) transistors with high cut-off frequency and high breakdown electrical filed are used in the production of transmitter power amplifiers (PAs) which have a basic function in wireless communication stations and commercialized for this purpose. Also, GaN-based HEMT’s are considered as good candidates for next-generation power conversion devices. Due to its strong polarization fields, GaN-based alloys are extensively used in transistor device applications operating in depletion mode (D-mode).
Heterojunctions, contains two-dimensional electron gas (2DEG, are used in the production of conventional D-mode field-effect transistor devices. In conventional AIGaN/GaN HEMTs with high density 2DEG induced by spontaneous and piezoelectric polarization fields, the threshold voltage value (Vth) for transistors operating in D-mode is in the order of -3,-4 V. The threshold voltage value of AIGaN/GaN HEMT is determined by the design of the epitaxial layers, the Al composition, the type and concentration of doped atoms, as well as the thickness of the AIGaN barrier layer (Xintong Lyu, He Li, Yousef Abdullah, Ke Wang, Boxue Hu, Zhi Yang, Jiawei Liu, Jin Wang, Liming Liu, and Sandeep Bala, A Reliable Ultrafast Short-Circuit Protection Method for E-Mode GaN HEMT, IEEE Transactions on Power Electronics, Vol. 35, No. 9, September 2020).
There are a number of methods developed for the fabrication step to change the threshold voltage of the device. These useful methods provide much more opportunity to use in circuit applications. If the threshold voltage of the transistor devices has a positive value, the device can operate in E-mode.
Transistor devices that can operate in E-mode, unlike transistors that can operate in D-mode, have a positive threshold voltage, eliminating the necessity to convert the power supplies connected to the circuit to negative polarity. This provides significant advantages in circuit designs. Another advantage of the device is that it has fail-safe capabilities. All of these advantages significantly reduce circuit complexity and system cost. Power factor corrector (PFC) or power supply applications for servers are the other applications that require transistor devices that can operate in E-mode. In addition, transistors with positive threshold voltage can prevent the wrong operation problem caused by electromagnetic noise in the system and ensure safe power switching. Although great efforts have been spending to realize GaN-based HEMT operating in E-mode, but structures with threshold voltages suitable for use in power switching studies have not been realized yet. In order to prevent the wrong operation problem that may be caused by electromagnetic noise in the system, the threshold voltage should be nearly 2-3 V interval. Quantum wells or heterojunctions structures containing two-dimensional hole gas allow the production of transistor devices that can operate in E-mode with less cost and effort, since the carriers that provide the conduction are positively charged holes. In order to produce transistor devices that can operate in E-mode in the high power and frequency region, the hole gas formed in quantum wells or heterojunctions must have high mobility and high density values.
In the state of the art, although HHMT devices have been developed using lll-V group and lll-nitride group member alloys operating in E-mode, it is seen that transistor devices containing a high threshold voltage and high-mobility hole gas have not been developed yet, suitable for use in power switching studies.
As a result, there is a need for new structure and related growth technique that will eliminate the disadvantages mentioned above and give a solution to the technique.
The mentioned structure and method are provided by our invention. Using InN and GaN alloys as channel layer in lnN/[3-Ga2O3/GaN quantum well structure containing two-dimensional hole gas; InN and GaN channels will ensure high mobility of the 2DHG that will form in the channel layers. It will be possible for the E-mode transistor device to be produced by using a quantum well containing high mobility 2DHG to have high drain current and operate at high frequency/power values.
The [3-Ga2O3 alloy, which is used as a barrier layer in the quantum well structure, is a material with a high breakdown electric field (8-10 MV/cm) value. The use of this alloy as a barrier layer in the quantum well structure will provide fabrication of a transistor device which have higher breakdown electric field value.
In the invention, the detailed description of which is given below; It provides the production of a E-mode transistor device with high drain-source current and can operate in high power/frequency regions by using lnN/[3-Ga2O3/GaN quantum well. As a result, the invention, which was fabricated using the above-described singlecrystal [3-Ga2O3 barrier layer, InN and GaN channel layer, and a quantum well containing two-dimensional hole gas formed in these two channel layers, solved the problem of high breakdown electric field and inability to reach high threshold voltage values experienced in the transistor device. In order to eliminate it and due to the inadequacy of the existing solutions on the subject, it reveals an unexpected technical effect in the relevant technical field, which cannot be inferred with the available information.
BRIEF DESCRIPTION OF THE INVENTION
The invention relates to high hole mobility transistor devices operating in enhancement mode (E-mode), especially; lnN/[3-Ga2O3/GaN quantum well-based high hole mobility transistor (HHMT) device operating in E-mode, capable of operating at high and positive threshold voltage suitable for use in power switching studies, and containing two-dimensional hole gas (2DHG) with high breakdown electric field value and relates to its structure.
In order to realize all the advantages mentioned above and which will be understood from the detailed description below; It is an lnN/[3-Ga2O3/GaN quantum well-based high hole mobility transistor (HHMT) device structure, containing two- dimensional hole gas (2DHG) operating in E-mode and have a high positive threshold voltage which suitable for use in power switching studies. Properties;
- a suitable substrate
- buffer layer and high resistive (HR) gallium nitrate (GaN) interlayer in wurtzite crystal phase on this substrate, respectively,
- undoped GaN channel layer in wurtzite crystal phase on HR-GaN layer,
- Single crystal [3-Ga2O3 barrier layer on the GaN channel layer,
- on the barrier layer, the indium nitrate (InN) channel layer, in which two-dimensional hole gas (2DHG) is formed,
- ohmic source and drain terminal and non-ohmic gate terminal on InN channel layer
- SisN4 passivation layer inserted between contact terminals, are characterized.
This invention; compensating the above-mentioned requirements, it eliminates all the disadvantages and offers some advantages. Solves the problem of low hole gas mobility (1 -5 cm2/Vs) and low breakdown electric field (Si (0.4 MV/cm), SiC (2 MV/cm), GaN (3.3 MV/cm)) in quantum wells. In addition, this is the lnN/[3-Ga2O3/GaN quantum well structure consisting of a buffer layer, a HR-GaN interlayer, a undoped GaN channel layer, a single crystal [3-Ga2O3 barrier layer, an InN channel layer, respectively grown on a substrate, and it allows the production of transistor devices with high positive threshold voltage using this quantum wells.
The primary aim of this invention is to provide a HHMT device and a growth method that prevents the malfunctioning problem that arises due to electromagnetic noise in the system and enables the power switching in safety mode.
Another purpose of the present invention is to provide a practical HHMT growth method with a simpler circuit, low cost and simple process steps by eliminating the need to convert the power supplies connected to the circuit to negative polarity. Another aim of the invention is to increase the mobility of 2DHG formed at the interfaces at the InN and GaN channel layer in the lnN/[3-Ga2O3/GaN quantum well structure grown on the supplied substrate and to provide an lnN/[3-Ga2O3/GaN quantum well structure that eliminates the low breakdown electric field problem by using a single crystal [3-Ga2O3 barrier layer, and a production method of a transistor device that can operate at high positive threshold voltage using this quantum well.
An aim of the invention is to provide an lnN/[3-Ga2O3/GaN quantum well contains high mobility two-dimensional hole gas, and its production method.
Another aim of the invention is to provide an lnN/[3-Ga2O3/GaN quantum well with high breakdown electric field value and its production method.
Another aim of the invention is to develop a high-hole mobility lnN/|3- Ga20s/GaN quantum well-based transistor device fabrication method.
Another aim of the invention is to provide lnN/[3-Ga2O3/GaN quantum wellbased transistor device with positive threshold voltage in the range of 2-3 volts and its production method.
LIST OF FIGURES
In this invention, lnN/[3-Ga2O3/GaN quantum well and high hole mobility transistor (HHMT) device structure containing this quantum well structure is shown in the attached figures, of which:
Figure 1 . An exemplary epitaxial view of the quantum well structure described in the invention.
Figure 2. An exemplary epitaxial view of the transistor device that can operate in E-mode described in the invention.
Definitions of the enumerations given in the figures;
(20) quantum well structure
(200) device
(1 ) substrate
(2) buffer layer
(3) HR-GaN interlayer
(4) undoped GaN channel layer
(5) single crystal 3-Ga20s barrier layer
(6) two dimensional hole gas (2DHG) (7) InN channel layer
(8) drain terminal
(9) gate terminal
(10) source terminal
(11 ) passivation layer
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, a buffer layer (2), HR-GaN interlayer (3), undoped GaN channel layer (4), single crystal beta phase gallium oxide (P-Ga20s) barrier layer (5), InN channel layer (7) sequentially grown on a supplied substrate (1 ), which has high hole mobility and ensures high values of the breakdown electric field generated by applied voltage under reverse bias. The lnN/[3-Ga2O3/GaN quantum well (20) structure with mobility of at least 80-100 cm2/Vs and breakdown electric field value in the range of at least 8-10 MV/cm and the manufacturing method of the E-mode transistor device (200) using this quantum well structure is described.
An example epitaxial view of the quantum well structure (20) mentioned in Figure-1 is given. This quantum well structure (20) consists of a supplied substrate (1 ), a buffer layer (2), HR-GaN interlayer (3), undoped GaN channel layer (4), single crystal beta phase gallium oxide (P-Ga2Os) barrier layer (5), InN channel layer (7), two-dimensional hole gas (2DHG) (6) formed in these two channel layers.
Quantum well structure (20) in the preferred application of the invention; It contains a semi-insulating substrate (1 ) with a thickness between 500pm and 600pm, with only the front surface or both surfaces polished. In the invention, preferably oriented silicon carbide (SiC) is used as substrate (1 ); oriented silicon (Si) or oriented sapphire (AI2O3) are also used in general applications. In order for the 2DHG (6) formation in the GaN channel layer (4) and the InN channel layer (7) in the quantum well (20) structure, which is the subject of the invention, to have high mobility, the crystal defects in the HR-GaN intermediate layer (3) must be minimum. A buffer layer (2) is used between the HR-GaN interlayer (3) and the substrate (1 ) in order to minimize the crystal defects that will occur in the lnN/[3-Ga2O3/GaN quantum well structure grown on substrates such as SiC, Si or sapphire. The type of the buffer layer (2) (such as AIN, GaN, AIGaN layer with different Al and Ga ratios), their thickness and growth temperatures (AIN grown at high temperature (HT-AIN), AIN grown at low temperature (LT-AIN), grown at low temperature GaN (LT-GaN)) changes with respect to the used substrate materials (1 ). When sapphire material is used as the substrate (1 ) a low temperature grown GaN layer is used as a buffer layer (2). Whose thickness preferably 10nm and in general applications its thickness between 8nm and 13nm. The LT-GaN buffer layer (2) is preferably grown in 570°C, in general applications grown in the temperature range of 550°C to 590°C.
LT-AIN and HT-AIN layers are used as buffer layer (2) between HR-GaN and substrate, respectively, in growth on SiC or Si substrates. The thickness of the LT- AIN layer is preferably 25nm, and in general applications, the LT-AIN layer with a thickness between 20nm and 30nm is used. The thickness of the HT-AIN layer used as the buffer layer is preferably 90nm. In general applications, the thickness of the layer is between 90nm and 120nm. The growth temperature of the LT-AIN layer used in the buffer structure is preferably 650°C, in general applications it is in the range of 630°C to 680°C. On the other hand, the growth temperature of the HT-AIN layer is preferably 1050°C, and in general applications it is in the range of 1030°C to 1100°C. The thickness of the HR-GaN interlayer (3) used in the quantum well (20) structure is preferably 1.2pm; in general applications it is in the range of 1 m to 1 ,5pm. The interlayer (3) is preferably grown in the temperature of 950°C, in general applications it is grown temperature change between 920°C and 980°C. In order to obtain the high resistive HR-GaN interlayer (3), p-type doping is done to the HR- GaN interlayer (3). P-type doping is preferably done with iron (Fe) atoms. But, in general applications, magnesium (Mg) and carbon (C) atoms are also used for doping. The doping ratio is preferably in the order of 1x1018crrr3 The thickness of the GaN channel layer (4), in which the two-dimensional hole gas is located, is preferably 700nm, and in general applications it is in the range of 600nm to 800nm.
In the invention, a single crystal [3-Ga2O3 alloy, which is a material with high breakdown electric field value, is used as the barrier layer (5) in order to obtain a HHMT device (200) with a high breakdown electric field value. The thickness of the barrier layer (5) is preferably 20nm, and in general applications it is value between 18nm and 25nm. Growth process of single crystal [3-Ga2O3 barrier layer (5) is carried out with MDE technique under suitable growth conditions. In order to obtain high mobility 2DHG (6) within the InN channel layer (7), the crystal structure of the InN channel layer (7) must be low defective. For this reason, the InN channel layer (7) is grown under suitable conditions using the molecular beam epitaxy (MBE) technique. In Figure - 2, an example view of an lnN/[3-Ga2O3/GaN quantum well-based HHMT device (200) operating in the E-mode is given; This device (200) includes the quantum well structure (20) and the source terminal (8), drain terminal (9), gate terminal (10) provided on this quantum well structure (20), and a passivation layer inserted between these terminals.
In the structure of the HHMT device (200), there is an ohmic source terminal (10), a ohmic drain terminal (8) and a non-ohmic gate terminal (9), which is in direct contact with the InN channel layer (7) on the quantum well structure (20).
In the HHMT device (200) described in the present invention, the source terminal (10) and the drain terminal (8) located on the structure preferably consist of 60nm thick titanium (Ti), 50nm thick gold (Au), 100nm thick nickel (Ni) metal, respectively. These metals are evaporated by electron beam evaporation (e-beam) method, preferably under high vacuum (~10-7Torr) on quantum well structures (20) described in the invention. In order to provide electrical conduction of two- dimensional hole gas (2DHG) (6), metals are annealed at 750°C for 45s in nitrogen gas (N2) environment with rapid heat treatment.
In the invention, gate terminal (9) on quantum well structures (20) is preferably composed of nickel (Ni) and gold (Au) metal, respectively, coated by electron beam evaporation method. The gate terminal (10) described in the present invention preferably contains 10Onm thick nickel (Ni) metal and 50nm thick gold (Au) metal, and in general applications the thickness of the nickel (Ni) and gold (Au) metal in the range of 80nm to 120nm and 40nm to 90nm, respectively. In general applications of the invention, at least one of the metals titanium (Ti), indium (Ir), ruthenium (Ru), palladium (Pd), platinum (Pt) is used instead of Ni metal in the formation of the gate terminal (10).
In the device (200) structure, a passivation layer (11 ) is inserted between the source (10), drain terminal (8) and the gate terminals (9). Preferably SisN4 alloy is used as the passivation layer (11 ), but, in general applications, at least one of the SiC>2, AI2O3, HfO2 alloys is also used. The thickness of the passivation layer is preferably 50nm; in general applications it can be in the range 40nm to 70nm.

Claims

CLAIMS A transistor device structure that contains two-dimensional hole gas in quantum well structure and can operate in E-mode characterized in that comprising;
- a substrate (1 ),
- on this substrate, in the wurtzite crystalline phase; a buffer layer
(2) to minimize crystal defects that will occur in the quantum well structure and a high resistive (HR) gallium nitrate (GaN) interlayer (3), respectively, are located,
- an undoped GaN channel layer (4) in wurtzite crystal phase on the HR- GaN interlayer
(3),
- single crystal [3-Ga2O3 barrier layer (5) on the undoped GaN channel layer
(4),
- on a single crystal [3-Ga2O3 barrier layer (5) with high breakdown electric field value, an indium nitrate (InN) channel layer (7), in which a two- dimensional hole gas (2DHG) (6) is formed,
- an ohmic source terminal (10), a ohmic drain terminal (8) and a nonohm ic gate terminal (9), on the InN channel layer (7) with direct contact,
- a passivation layer (11 ) inserted between the contact terminals (between the source (10), the drain terminal (8) and the gate terminal (9)). The substrate (1 ) mentioned in Claim 1 characterized in that only the front surface or both surfaces are polished and have a thickness value between 500pm and 600pm. The substrate (1 ) mentioned in Claim 2 characterized by being at least one of an oriented silicon carbide (SiC), an oriented silicon (Si) or an oriented sapphire (AI2O3). The buffer layer (2) mentioned in Claim 1 characterized by being a low temperature grown GaN layer, preferably 10nm thick, and thickness between the 8nm and 13nm in general applications in cases of using sapphire material as the substrate (1 ).
9
5. The temperature mentioned in Claim 4 characterized by being preferably 570°C, and in general applications in the range of 550°C to 590°C.
6. The buffer layer (2) mentioned in Claim 1 characterized by the formation of LT-AIN and HT-AIN layers grown on it, respectively if SiC or Si material is used as the substrate (1 ).
7. The buffer layer (2) mentioned in Claim 6 characterized by the formation of LT-AIN layers, preferably 25nm thick, have thickness between 20nm and 30nm in general applications, and HT-AIN layers, preferably 100nm, have a thickness between 90nm and 120nm in general applications, respectively.
8. The buffer layer (2) mentioned in Claim 7 characterized by the growth temperature of the LT-AIN layer is preferably 650°C, in general applications it is between 630°C and 680°C; the growth temperature of the HT-AIN layer is preferably in the range of 1050°C, and in general applications it is in the range of 1030°C to 1100°C.
9. The HR-GaN interlayer (3) mentioned in Claim 1 characterized by comprising a thickness of preferably 1.2pm, in general applications in the range of 1 pm to 1 ,5pm.
10. The HR-GaN interlayer (3) mentioned in Claim 9 characterized by its growth temperature being preferably 950°C, and in general applications in the range of 920°C to 980°C.
11. The HR-GaN interlayer (3) mentioned in Claim 10 characterized by comprising a p-type doping, preferably using iron (Fe), magnesium (Mg) and carbon (C) atoms in order to be done high resistive.
12. The doping process mentioned in Claim 11 characterized by comprising a doping ratio of 1x1018crrr3
13. The GaN channel layer (4) mentioned in Claim 1 characterized by a thickness of preferably 700nm, in general applications in the range of 600nm to 800nm.
14. The barrier layer (5) mentioned in Claim 1 characterized by its thickness being preferably 20nm and it is thickness value between 18nm and 25nm in general applications.
15. The barrier layer (5) mentioned in Claim 14 characterized by the growth process is done with the MBE technique.
16. The InN channel layer (7) mentioned in Claim 1 characterized by being grown with molecular beam epitaxy technique in order for the 2DHG (6) moving in the channel to have a high mobility and a certain level of crystal quality.
17. The drain terminal (8) mentioned in Claim 1 characterized by the formation of preferably 60nm thick titanium (Ti), 50nm thick gold (Au), and 100nm thick nickel (Ni) metals that evaporated under high vacuum (~10’7Torr) by electron beam evaporation (e-beam) system, in order to obtain ohmic properties and to provide electrical conduction in two-dimensional hole gas (2DHG) (6) and it is annealed with rapid heat treatment in nitrogen gas (N2) atmosphere at 750°C for 45s.
18. The source terminal (8) mentioned in Claim 1 characterized by the formation of preferably 60nm thick titanium (Ti), 50nm thick gold (Au), and 100nm thick nickel (Ni) metals that evaporated under high vacuum (~10’7Torr) by electron beam evaporation (e-beam) system, in order to obtain ohmic properties and to provide electrical conduction in two-dimensional hole gas (2DHG) (6) and it is annealed with rapid heat treatment in nitrogen gas (N2) atmosphere at 750°C for 45s.
19. The gate terminal (9) mentioned in Claim 1 characterized by the formation of at least one of the metals nickel (Ni), titanium (Ti), iridium (Ir), ruthenium (Ru), palladium (Pd), platinum (Pt) and gold (Au) metal coated by electron beam evaporation method.
20. The gate terminal (9) mentioned in Claim 19 characterized by preferably comprising a 100nm thickness and in general application have a thickness between 80nm and 120nm of nickel (Ni) metal and preferably 50nm thickness and in general application have a thickness between 40nm and 90nm of gold (Au) metal.
21. The passivation layer (11 ) mentioned in Claim 1 characterized by being preferably SisN4, in general applications at least one of the alloys SiC>2, AI2O3, HfO2.
22. The passivation layer (11 ) mentioned in Claim 21 characterized in that comprising a thickness is preferably 50nm and in general applications in a range of 40nm to 70nm.
11
PCT/TR2022/050366 2022-04-20 2022-04-25 A transistor device structure containing two-dimensional hole gas and operating in e-mode WO2023101630A1 (en)

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