WO2023101111A1 - Precharge method and precharge circuit using same - Google Patents

Abstract

A precharge circuit according to the present embodiment comprises: a sample unit for sampling, at least twice at an interval, an input signal that has passed through a filter, and sampling in the same phase; a comparison unit for calculating a comparison result by comparing the size of sample values; an accumulator for updating a precharge level by combining the precharge level and a correction value corresponding to the comparison result; and a precharge unit for precharging an input node, with a precharge voltage corresponding to the updated precharge level.

Description

Precharge method and precharge circuit using the same

The present technology relates to a precharge method and a precharge circuit using the same.

Low-power implementation of communication circuits is required due to the extension of the lifespan of wireless sensor nodes and mitigation of heat. duty cycling). In duty cycling, the faster the start-up is during driving and the closer the start-up energy is to 0, the higher the operating efficiency. Since the power amplifier consumes the most power in the transmission terminal, the startup energy of the entire transmission terminal can be significantly reduced by improving the startup characteristics of the power amplifier.

A conventional power amplifier uses a bias circuit composed of a resistor and a capacitor to obtain a transfer conductance (gm), but driving start-up is slowed down by a time constant of the bias circuit. In addition, if the input node of the power amplifier is not properly precharged, excessive AC components are transferred to the input stage of the power amplifier during start-up, resulting in DC component errors, which in turn lead to output stage signal errors, resulting in errors. The time for attenuation of is proportional to the time constant of the bias circuit, and the efficiency of duty cycling decreases accordingly.

The present embodiment is intended to solve the above-described problems caused by the prior art, and includes a pre-charge circuit capable of instantly driving the power amplifier by shortening start-up during driving and a power amplifier including the pre-charge circuit. is to provide

This embodiment is a method of precharging an input node, which includes: sampling an input signal that has passed through a filter at least twice with a time difference, sampling at the same phase, and comparing the magnitudes of sample values to obtain a comparison result. calculating, updating the precharge level by combining a correction value corresponding to the comparison result and the precharge level, and precharging the input node with the precharge voltage corresponding to the updated precharge level. include

According to one aspect of the present embodiment, the sampling is performed by storing a result of sampling the input signals that have passed through the filter, and the calculating of the comparison result is performed by using any one of an analog comparator and a sense amplifier. do it using

According to one aspect of the present embodiment, in the step of sampling, the precharge level combined with the correction value is a precharge level formed in a previously performed precharge method.

According to one aspect of this embodiment, the precharging method includes a coarse calibration mode and a fine calibration mode.

According to one aspect of the present embodiment, the magnitude of the correction value combined with the precharge level in the coarse adjustment mode is greater than the magnitude of the correction value combined with the precharge level in the fine adjustment mode.

According to one aspect of the present embodiment, the step of summing the correction value corresponding to the comparison result and the precharge level performs a subtraction operation and a summation operation between the correction value and the precharge level. When the subtraction operation and the sum operation are performed, a carry signal corresponding to each is formed, and when an oscillation of the carry signal is detected in the coarse adjustment mode, the mode is switched to the fine adjustment mode. .

According to one aspect of the present embodiment, the precharging method is terminated when vibration of the carry signal is detected in the fine adjustment mode.

According to one aspect of the present embodiment, a time interval for sampling the input signal passing through the filter at least twice in the same phase in the fine tuning mode is longer than the time interval in the coarse tuning mode.

According to one aspect of the present embodiment, the step of sampling the input signal that has passed through the filter at least twice in the same phase includes forming a first trigger pulse, and providing the first trigger pulse to a sampler so that the sampler activating the input signal as a sampling clock, sampling a voltage at a predetermined level to form a retimed clock signal, and sampling the input signal that has passed through the filter with the retimed clock signal. includes

According to one aspect of the present embodiment, the step of sampling the input signal that has passed through the filter at least twice in the same phase includes forming a second trigger pulse by delaying a first trigger pulse; providing a sampler to activate the sampler, and sampling a voltage of a predetermined level using the input signal as a sampling clock to form a second retimed clock signal, and using the second retimed clock signal to and sampling the input signal that has passed through the filter.

According to one aspect of the present embodiment, when the precharge method is finished, the calculated precharge level is stored, and the input node is precharged with the stored precharge level without performing the precharge method again. do.

The precharge circuit according to the present embodiment includes: a sample unit for sampling an input signal that has passed through a filter at least twice with a time difference, but in the same phase; a comparator for calculating a comparison result by comparing the magnitudes of the sample values; and an accumulator for updating the precharge level by summing the correction value corresponding to the comparison result and the precharge level, and a precharge unit for the input node with a precharge voltage corresponding to the updated precharge level.

According to one aspect of the present embodiment, the sample unit stores a result of sampling input signals that have passed through the filter, including a semiconductor switch that is provided with a sampling clock and is conductive, and the comparator is selected from among an analog comparator and a sense amplifier. include any one

According to one aspect of the present embodiment, the precharge level combined with the correction value in the accumulator is a previously performed precharge level.

According to one aspect of the present embodiment, the precharge circuit calculates the precharge voltage in a coarse calibration mode and a fine calibration mode.

According to one aspect of the present embodiment, the accumulator increases the magnitude of the correction value combined with the precharge level in the coarse adjustment mode as compared to the magnitude of the correction value combined with the precharge level in the fine adjustment mode. do it together

According to one aspect of the present embodiment, the accumulator performs any one of a subtraction operation and a summation operation between the correction value and the precharge level, and carries out a carry signal corresponding to each operation. ) is output.

According to one aspect of the present embodiment, the precharge circuit further includes a determination unit, and the determination unit switches from the coarse adjustment mode to the fine adjustment mode when detecting an oscillation of the carry signal.

According to one aspect of the present embodiment, the determination unit terminates the precharge method when oscillation of the carry signal is detected in the fine adjustment mode.

According to one aspect of the present embodiment, the sample unit performs samples such that the time difference in the fine adjustment mode is greater than the time difference in the coarse adjustment mode.

According to one aspect of the present embodiment, the precharge circuit includes a trigger forming unit that generates a trigger pulse, is activated by the trigger pulse, and samples a predetermined voltage from the input signal as a sampling clock to form a retiming clock. and a clock retimer including a first sampler to provide the data to the sample unit.

According to one aspect of the present embodiment, the trigger forming unit further includes a delay line for forming a second trigger pulse in which the trigger pulse is delayed by the time difference, and the clock retimer is activated by the second trigger pulse. and a second sampler configured to sample the predetermined voltage using the input signal as a sampling clock to form a second retiming clock, and to provide the second retiming clock to the sample unit.

According to one aspect of the present embodiment, when the precharging method ends, the calculated precharge level is stored, and the input node is precharged with the stored precharge level without performing the precharging method again.

According to one aspect of this embodiment, the precharge circuit precharges an input terminal of a power amplifier included in a wireless transmission circuit.

According to this embodiment, an advantage is provided that an accurate pre-charge voltage can be formed despite environmental changes such as process differences, voltage fluctuations provided to the device, and temperature, and immediate start-up (start-up) after calculating the pre-charge level. up) is provided.

1 is a flowchart showing an outline of a precharging method according to the present embodiment.

Fig. 2 is a block diagram showing the outline of the precharge circuit according to the present embodiment.

FIG. 3(a) is a diagram showing an outline of an input signal provided to an input node, and FIG. 3(b) is a diagram showing an outline of a signal that has passed through a band pass filter (BPF).

4 is a diagram illustrating an embodiment of a pre-charge unit.

Fig. 5 is a block diagram showing the outline of a trigger forming unit and a clock retimer.

6 is a schematic timing diagram of a trigger forming unit and a clock retimer.

7 is a diagram illustrating the experimental results of the implementation of the present embodiment.

8 is a diagram illustrating a voltage change of an input node when a precharge voltage is formed from a stored precharge level and provided to an input node after precharge level calculation is completed.

Hereinafter, a precharging method and a precharging circuit according to the present embodiment will be described with reference to the accompanying drawings. 1 is a flowchart showing an outline of a precharging method according to this embodiment, and FIG. 2 is a block diagram showing an outline of a precharging circuit 1 according to this embodiment. Referring to FIG. 1, a method of precharging an input node according to the present embodiment includes: sampling an input signal that has passed through a filter at least twice with a time difference, and sampling at the same phase (S100), and comparing sample values. calculating a comparison result (S200), adding a correction value corresponding to the comparison result and a precharge level (S300), and precharging the input node with the precharge voltage corresponding to the precharge level Step S400 is included.

Referring to FIG. 2, the precharge circuit 1 according to the present embodiment samples the input signal that has passed through the filter at least twice with a time difference, the sample unit 100 sampling at the same phase, and the size of the sample values. A comparison unit 200 that compares and calculates a comparison result, an accumulator 300 that combines a correction value corresponding to the comparison result and a precharge level, and the precharge voltage corresponding to the precharge level. The node includes a precharge unit 500.

Figure 3 (a) is a diagram showing the outline of the input signal (input) provided to the input node (X), Figure 3 (b) shows the outline of the signal that has passed through the band pass filter (BPF) it is a drawing

Referring to FIGS. 1 to 3(a) , an input signal provided to the input node X may be a carrier signal for communication output from a local oscillator (not shown). If the input node (X) provided with the input signal (input) is not sufficiently precharged, the output node (Y) of the band pass filter (BPF) receives a direct current (DC) as illustrated in (b) of FIG. Overshoot occurs due to the influence of the components.

Conversely, in an example not shown, if the input node (X) to which the input signal (input) is provided is excessively precharged, the output node (Y) of the band pass filter (BPF) has a direct current (DC) component As a result, undershoot occurs.

The sample unit 100 samples the output signal of the band pass filter (BPF) two or more times, each sampled at the same phase (S100). The sample unit 100 includes a semiconductor switch that receives the retimed clock signals CLK_r1 and CLK_r2 and is conducted to sample the output signal of the band pass filter BPF, and a capacitor connected to the semiconductor switch to store the sampled value. can include As an example, the capacitor may be a capacitor connected to the semiconductor switch, and as another example, the capacitor may be a parasitic capacitor formed in the semiconductor switch.

In the embodiment illustrated in (b) of FIG. 3 , values sampled by the sample unit 100 are shown as dots S1 and S2 in S1 and S2, and the input signal passed through the filter by the sample unit 100 An example of sampling twice. However, this is only an embodiment, and the sample unit 100 may sample the input signal that has passed through the filter three or more times.

In one embodiment, in an embodiment in which the sample unit 100 samples an input signal that has passed through the filter BPF twice, the sample unit 100 may include two semiconductor switches each performing samples, The semiconductor switches perform sampling by providing the retimed clock signals CLK_r1 and CLK_r2 to control electrodes. In addition, the sample unit 100 may further include a capacitor connected to each switch to store a value sampled by the switch.

In one embodiment, the semiconductor switches included in the sample unit 100 are provided with a signal input to the sample unit 100 in a conducting state. As the retimed clock signals CLK_r1 and CLK_r2 are provided to the control electrodes, the semiconductor switches change from a conducting state to a blocking state, and a signal provided at a sampling time point may be stored and sampled.

In another embodiment, the semiconductor switches included in the sample unit 100 may be in a cut-off state. The semiconductor switches in the cut-off state change from a cut-off state to a conduction state as the retimed clock signals CLK_r1 and CLK_r2 are provided to the control electrodes, and may sample the signal provided at the sampling point.

The values sampled by the sample unit 100 are provided to the comparison unit 200 for comparison (S200). As an example, the comparator 200 may be any one of an analog comparator and a sense amplifier. As described above, if the input node (X) is not sufficiently precharged, the signal output from the band pass filter (BPF) as shown in (b) of FIG. It is larger than the size of the value (S2). Conversely, if the input node (X) is excessively precharged, the size of the first sampled value is smaller than that of subsequent sampled values.

The comparison unit 200 is activated by the activation signal en output from the trigger forming unit 600 and compares the input sampled values S1 and S2. The comparator 200 outputs the comparison result signal C corresponding to the comparison result to the accumulator ACC 300 . In one embodiment, the accumulator 300 stores the precharge level PC_LEVEL formed in the previously performed precharge voltage calculation step.

The accumulator 300 calculates a new precharge level (PC_LEVEL) by summing the precharge level (PC_LEVEL) formed in the previous step and the correction value corresponding to the comparison result signal (S300). The adding process may be performed by adding the correction value to the precharge level PC_LEVEL formed in the previous step or subtracting the correction value from the precharge level PC_LEVEL formed in the previous step.

As an example, if the signal output from the comparator 200 corresponds to the case where the input node X is not sufficiently precharged, the correction value may be formed to increase the precharge level PC_LEVEL formed in the previous step. there is. Conversely, if the signal output from the comparator 200 corresponds to the case where the input node X is excessively precharged, the correction value may be formed to decrease the precharge level PC_LEVEL formed in the previous step.

In addition, the precharge method and the precharge circuit operate in one of two operation modes, a coarse calibration mode and a fine calibration mode.

Even if the accumulator 300 receives the same comparison result signal C from the comparator 200, the correction value combined with the precharge level PC_LEVEL formed in the previous step can be different for each coarse adjustment mode and fine adjustment mode. . For example, in the rough adjustment mode, the precharge level (PC_LEVEL) is greatly changed to quickly reach an appropriate precharge voltage. Therefore, the correction value combined with the precharge level PC_LEVEL formed in the previous step in the coarse adjustment mode is greater than the correction value combined in the fine adjustment mode.

In contrast, in the fine adjustment mode, the precharge level (PC_LEVEL) is finely changed to reach an appropriate precharge voltage. Accordingly, the correction value combined with the precharge level PC_LEVEL formed in the previous step in the fine adjustment mode is smaller than the correction value in the coarse adjustment mode.

As an embodiment, when the precharge level (PC_LEVEL) is calculated when the input node (X) is not sufficiently precharged, the accumulator 300 calculates the correction value to reach the target precharge level (PC_LEVEL). It can be summed with the precharge level (PC_LEVEL). On the other hand, if the precharge level (PC_LEVEL) is calculated when the input node (X) is excessively precharged, the accumulator 300 applies the correction value to the previously calculated precharge level to reach the target precharge level (PC_LEVEL). It can be subtracted from (PC_LEVEL).

The precharge level PC_LEVEL formed by combining the correction values is provided to the precharge unit 500 . 4 is a diagram illustrating an embodiment of a pre-charger 500. Referring to FIG. Referring to FIG. 4 , the precharge unit 500 includes a resistor string 510 connected in series between the upper voltage VH and the lower voltage VL to provide divided voltages and the divided voltages and a multiplexer (MUX) receiving the precharge level (PC_LEVEL) and outputting a precharge voltage corresponding to the precharge level (PC_LEVEL). In one embodiment, the precharge unit 500 further includes a precharge switch 530 that is conducted and provides a precharge voltage to the input node X to precharge the input node X. For example, conduction and blocking of the precharge switch 530 may be controlled by the trigger formation unit 600 .

In another embodiment not shown, the precharge unit may be formed of a digital-to-analog converter (DAC) that receives a precharge level signal, which is a digital code, and outputs a corresponding voltage.

In the illustrated embodiment, the upper voltage VH may be the driving voltage Vdd, and the lower voltage VL may be any one of a positive reference voltage VSS, a negative reference voltage, and a ground voltage. In addition, in the embodiment illustrated in FIG. 4, a single multiplexer (MUX) is illustrated, but the multiplexer is a signal (not shown) formed by performing a logic operation on some bits of the precharge level (PC_LEVEL) or the precharge level (PC_LEVEL). It may include a plurality of multiplexers controlled by .

The precharge voltage PC_V corresponding to the precharge level PC_LEVEL is supplied to the input node X through the energized precharge switch 530 to precharge the input node X (S400).

1 to 4, when the precharge level (PC_LEVEL) calculated by the accumulator 300 converges to the target precharge level (PC_LEVEL), the precharge level (PC_LEVEL) calculated in the previous step and In the calculation of summing the correction values, summing and subtraction of the correction values are repeated. The accumulator 300 outputs a first-state carry signal when summing the precharge level PC_LEVEL calculated in the previous step and the correction value. On the other hand, when the accumulator 300 performs a subtraction operation, it outputs a carry signal in the second state. Accordingly, when the precharge level PC_LEVEL calculated by the accumulator 300 converges to the target precharge level PC_LEVEL, the carry signal oscillates in the first state and the second state.

The determination unit 400 receives the carry signal from the accumulator 300 and controls a precharge method and a precharge circuit. For example, when the carry signal vibrating in the coarse adjustment mode is detected, the determination unit 400 switches the precharge method and the precharge circuit to the fine adjustment mode. Also, when the determination unit 400 detects the carry signal vibrating in the fine adjustment mode, the pre-charging method and the pre-charging circuit are terminated.

5 is a block diagram showing an outline of a trigger generator 600 and a clock retimer 700, and FIG. 6 is a schematic diagram of the trigger generator 600 and the clock retimer 700. It is also the timing. Referring to FIGS. 5 and 6 , the trigger generator 600 includes a pulse generator 610 and a first delay line for delaying the pulse formed by the pulse generator 610 by a first delay time ( 620), the second delay line 630 delays the pulse formed by the pulse generator by the second delay time, and any one of the signals output by the first delay line 610 and the second delay line 620 according to the control signal and a trigger multiplexer 640 outputting one.

As an example, the pulse generator 610 may output a signal transitioning from a logic high state to a logic low state. In another embodiment, the pulse generator 610 outputs a signal transitioning from a logic high state to a logic low state, and is connected to an inverter (not shown) to form a signal transitioning from a logic high state to a logic low state. there is. Accordingly, as shown in FIG. 6 , the first trigger signal T1 and the second trigger signal T2 may be signals having a falling edge transitioning from a logic high state to a logic low state.

In the illustrated embodiment, the signal output from the pulse generator 610 is input to the clock retimer 700 as the first trigger signal T1, and the signal output from the trigger multiplexer 640 is the second trigger signal. (T2) is input to the clock retimer 700.

The first delay line 620 delays the input signal that has passed through the filter in the adjustment step of the pulse output by the pulse generator 610 by a delay time corresponding to a sampling time difference and outputs the delayed signal. In addition, the second delay line 630 delays the pulse output from the pulse generator 610 by a delay time corresponding to a time difference between sampling the input signal that has passed through the filter in the fine adjustment step, and outputs the delayed pulse. In one embodiment, a time difference (delay) for sampling an input signal that has passed through a filter in the fine adjustment step may be longer than that in the coarse adjustment step, and an advantage of obtaining a sample value with high sensitivity is provided.

Accordingly, in the rough adjustment step, the trigger multiplexer 640 is controlled by the control signal and outputs the signal output from the first delay line 620 to the clock retimer 700 as the second trigger signal T2. In the fine adjustment step, the trigger multiplexer 640 is controlled by the control signal and outputs the signal output from the second delay line 630 to the clock retimer 700 as the second trigger signal T2.

In an embodiment not shown, the trigger forming unit 600 forms a coarse adjustment flag, a fine adjustment flag, and an adjustment completion flag signal. In the coarse adjustment step, the trigger forming unit 600 activates the coarse adjustment flag, in the fine adjustment step, the trigger forming unit 600 activates the fine adjustment flag, and when the fine adjustment step ends, the trigger forming unit 600 completes the adjustment. activate the flag

Accordingly, in a state where the adjustment completion flag is activated, precharging may be immediately performed using the calculated precharge level (PC_LEVEL) without performing the precharge level process again.

Also, the trigger forming unit 600 forms a control signal for controlling the trigger multiplexer 640 and provides it to the trigger multiplexer 640 . The trigger generator 600 activates the comparator 200 by providing an activation signal en after a predetermined time elapses after the sampling unit 100 performs sampling.

The clock retimer 700 includes a first sampler 710 and a second sampler 720 . In the illustrated embodiment, the first sampler 710 and the second sampler 720 are D flip-flops. However, in an embodiment not shown, the first and second samplers may be implemented as sampling elements that sample an input signal.

A voltage in a logic high state is provided to inputs D of the first sampler 710 and the second sampler 720, and an input signal input is provided as a clock. The first trigger signal T1 is provided as a reset input to the first sampler 710 and the second trigger signal T2 is provided as a reset input to the second sampler 710 .

When the first trigger signal T1 is in a logic high state, the first sampler 710 outputs a logic low in a reset state. As the first trigger signal T1 transitions to a logic low state, the first sampler 710 exits the reset state, samples an input at the rising edge of the input signal provided as a clock, and outputs the sampled signal. The signal output from the first sampler 710 is provided to the sample unit 100 as a retimed clock signal CLK_r1. The semiconductor switch included in the sample unit 100 performs a sample by providing a retimed clock signal CLK_r1 to a control electrode.

Subsequently, when the second trigger signal T2 delayed by a predetermined time difference (delay) transitions to the logic low state, the second sampler 720 is out of the reset state, and input at the rising edge of the input signal (input) provided as a clock. Sample and print. The signal output from the second sampler 710 is provided to the sample unit 100 as a retimed clock signal CLK_r2. The semiconductor switch included in the sample unit 100 performs a sample by providing a retimed clock signal CLK_r2 to a control electrode.

Since the retimed clock signals CLK_r1 and CLKr2 output from the clock retimer 700 are all clock signals formed by sampling the same rising edge of the input signal input, the retimed clock signals CLK_r1 and CLKr2 If the input signal is sampled, the input signal that has passed through the filter can be sampled at the same phase.

In one embodiment, the retimed clock signals CLK_r1 and CLK_r2 may be reset to a logic low state after the accumulator 300 performs the precharge level PC_LEVEL operation.

embodiment

Hereinafter, an implementation example of this embodiment will be described with reference to FIG. 7 . Referring to FIG. 7 , the precharge voltage is calculated from when the precharge circuit is driven until 10 μsec, coarse adjustment is made between 0 and 4.5 μsec, and fine adjustment is made between 4.5 μsec and 10 μsec.

An initial rough adjustment is made at 0 ~ 0.5 μsec, and it is noticed that the input node (X) is precharged excessively compared to the desired precharge level, and an undershoot is formed on the waveform as shown by the broken line in the upper left corner. can To compensate for this, a rough adjustment step is performed to increase the precharge level.

It can be seen that the degree of undershoot gradually decreases by referring to the broken line circles ①, ②, and ③ shown in red in the subsequent rough adjustment step. Next, referring to the broken line circle ④, it can be seen that the input node X is precharged to a lower degree than the desired precharge level, and overshoot is formed in the upper left corner. In the dashed circle ⑤, it can be seen that the input node X is precharged higher than the desired precharge level and undershoot occurs, and converges to the desired precharge level through a rough adjustment step. In addition, since the carry value oscillates between the first state and the second state during this process, the determination unit 400 terminates the coarse adjustment step and subsequently performs the fine adjustment step.

A fine-tuning step is performed from 4.5 μsec to 10 μsec. As shown, each step of fine adjustment has a longer duration than each step of coarse adjustment. This is because the time difference between sampling the input signals that have passed through the filter in the fine tuning step is greater than the time difference in the coarse tuning step, and through this, a signal change can be sensitively detected for a longer time.

In the steps exemplified by broken line circles ⑥, ⑦, and ⑧ of the fine adjustment step, an overshoot is formed when the voltage precharged at the input node X is lower than the desired precharge level, but as the fine adjustment step is performed, an overshoot is formed. It can be confirmed that the shoot gradually decreases, and in the process of the broken line circle ⑨, it can be seen that the input node X is precharged higher than the precharge level and undershoot occurs.

Overshoot occurs in the process of ⑩ exemplified by a rectangle, but overshoot and undershoot are repeated in the processes of ⑧ and ⑨, and the accumulator outputs an oscillating carry signal. The decision unit 400 determines that the carry signal output from the accumulator has converged to a desired precharge level and ends the procedure.

When the precharge level is calculated in this way, the accumulator 300 stores the calculated precharge level (PC_LEVEL) and outputs the stored precharge level (PC_LEVEL) at the next drive, and the precharge unit 500 stores the corresponding precharge level (PC_LEVEL). A charge voltage (PC_V) is formed and supplied to the input node (X) to precharge. 8 shows the voltage of the input node X when the precharge unit 500 forms the precharge voltage PC_V from the precharge level PC_LEVEL stored in the accumulator 300 and provides it to the input node X. It is a diagram showing the change.

As illustrated in FIG. 8 , it can be confirmed that 18 nsec is required as a startup time after calculation of the precharge voltage is completed. This embodiment can precharge the input node of the power amplifier in wireless communication, and provides an advantage that direct driving is possible therefrom.

According to this embodiment, an advantage is provided that the circuit can be driven immediately after the precharge level calculation process is finished.

Although it has been described with reference to the embodiments shown in the drawings to aid understanding of the present invention, this is an embodiment for implementation and is only exemplary, and those having ordinary knowledge in the field can make various modifications and equivalents therefrom. It will be appreciated that other embodiments are possible. Therefore, the true technical scope of protection of the present invention will be defined by the appended claims.

Claims (24)

1. A method of precharging an input node, the method comprising:

   sampling the input signal that has passed through the filter at least twice with a time difference, but sampling at the same phase;

   Comparing the magnitudes of sample values and calculating a comparison result;

   Updating a precharge level by summing a correction value corresponding to the comparison result and a precharge level; and

   and precharging the input node with the precharge voltage corresponding to the updated precharge level.
2. According to claim 1,

   The sampling step is

   Performing by storing a result of sampling the input signals that have passed through the filter,

   Calculating the comparison result,

   A precharge method performed using either an analog comparator or a sense amplifier.
3. According to claim 1,

   The precharge level combined with the correction value,

   A precharge method that is a precharge level formed in a previously performed precharge method.
4. According to claim 1,

   The precharge method,

   Precharge method including coarse calibration mode and fine calibration mode.
5. According to claim 4,

   The magnitude of the correction value combined with the precharge level in the coarse adjustment mode is

   A precharge method that is greater than the magnitude of the correction value combined with the precharge level in the fine adjustment mode.
6. According to claim 4,

   The step of combining the correction value corresponding to the comparison result and the precharge level,

   Performing any one of a subtraction operation and a summation operation between the correction value and the precharge level,

   When the subtraction operation and the sum operation are performed, corresponding carry signals are formed, respectively,

   and switching to the fine tuning mode when an oscillation of the carry signal is detected in the coarse tuning mode.
7. According to claim 6,

   If vibration of the carry signal is detected in the fine adjustment mode,

   A precharge method for terminating the precharge method.
8. According to claim 4,

   The precharge method of claim 1 , wherein a time interval for sampling the input signal passing through the filter at least twice in the same phase in the fine tuning mode is longer than that in the coarse tuning mode.
9. According to claim 1,

   The step of sampling the input signal that has passed through the filter at least twice at the same phase,

   forming a first trigger pulse;

   activating the sampler by providing the first trigger pulse to the sampler; and

   forming a retimed clock signal by sampling a voltage of a predetermined level using the input signal as a sampling clock; and

   and sampling an input signal that has passed through the filter with the retimed clock signal.
10. According to claim 9,

    The step of sampling the input signal that has passed through the filter at least twice in the same phase,

    delaying the first trigger pulse to form a second trigger pulse;

    activating the sampler by providing the second trigger pulse to the sampler; and

    forming a second retimed clock signal by sampling a voltage of a predetermined level using the input signal as a sampling clock; and

    and sampling an input signal that has passed through the filter with the second retimed clock signal.
11. According to claim 7,

    When the precharge method ends,

    The calculated pre-charge level is stored,

    The precharging method of the input node is performed with the stored precharge level without performing the precharging method again.
12. a sample unit for sampling the input signal that has passed through the filter at least twice with a time difference, but in the same phase;

    a comparator for calculating a comparison result by comparing the magnitudes of the sample values;

    an accumulator for updating the precharge level by summing a correction value corresponding to the comparison result and the precharge level; and

    and a precharge unit precharging the input node with a precharge voltage corresponding to the updated precharge level.
13. According to claim 12,

    The sample part,

    Storing a sampled result of input signals that have passed through the filter, including a semiconductor switch in which a sampling clock is provided and conducted;

    The comparison unit,

    A precharge circuit comprising either an analog comparator and a sense amplifier.
14. According to claim 12,

    the accumulator

    The precharge level combined with the correction value is a previously performed precharge level.
15. According to claim 12,

    The precharge circuit is

    A precharge circuit that calculates the precharge voltage in coarse calibration mode and fine calibration mode.
16. According to claim 12,

    the accumulator

    a precharge circuit that increases the magnitude of the correction value combined with the precharge level in the coarse adjustment mode compared to the magnitude of the correction value combined with the precharge level in the fine adjustment mode.
17. According to claim 15,

    the accumulator

    Performing any one of a subtraction operation and a summation operation between the correction value and the precharge level;

    A precharge circuit that outputs a carry signal corresponding to each operation.
18. According to claim 17,

    The precharge circuit,

    further comprising a judgment unit;

    The judge,

    A precharge circuit for switching to the fine adjustment mode when oscillation of the carry signal is detected in the coarse adjustment mode.
19. According to claim 18,

    The judge,

    A precharge circuit that terminates the precharge method when oscillation of the carry signal is detected in the fine adjustment mode.
20. According to claim 17,

    The sample part,

    The time difference in the fine adjustment mode

    A precharge circuit for sampling so as to be larger than the time difference in the coarse adjustment mode.
21. According to claim 12,

    The precharge circuit,

    A trigger forming unit for generating a trigger pulse;

    and a clock retimer including a first sampler that is activated by the trigger pulse and samples a predetermined voltage of the input signal as a sampling clock to form a retiming clock and provide the retiming clock to the sample unit.
22. According to claim 21,

    The trigger formation part,

    Further comprising a delay line for forming a second trigger pulse in which the trigger pulse is delayed by the time difference,

    The clock retimer,

    and a second sampler that is activated by the second trigger pulse, samples the predetermined voltage using the input signal as a sampling clock, forms a second retiming clock, and provides the sample to the sample unit.
23. According to claim 12,

    When the precharge method ends

    The calculated pre-charge level is stored,

    A precharge circuit in which precharging of the input node is performed at the stored precharge level without performing the precharging method again.
24. According to claim 12,

    The precharge circuit,

    A precharge circuit for precharging an input stage of a power amplifier included in a wireless transmission circuit.

Images