WO2023100299A1

WO2023100299A1 - Time synchronization device, time synchronization method, and program

Info

Publication number: WO2023100299A1
Application number: PCT/JP2021/044154
Authority: WO
Inventors: 佳祐山形; 慎一吉原; 豪矢沢; 隆中西
Original assignee: 日本電信電話株式会社
Priority date: 2021-12-01
Filing date: 2021-12-01
Publication date: 2023-06-08
Also published as: JPWO2023100299A1

Abstract

A Boundary Clock (100) as a time synchronization device according to the present disclosure comprises: an offset calculation unit (102) for calculating an offset, which is a difference between the intra-device time of a higher-level device and the intra-device time of the Boundary Clock itself; a transmission delay time calculation unit (103) for calculating a transmission delay time of a packet transmitted and received between the higher-level device and the Boundary Clock itself; an offset pattern determination unit (107) for determining a variation pattern of the offset; a transmission delay time pattern determination unit (107) for determining a variation pattern of the transmission delay time; and a failure part determination unit (111) for determining, on the basis of the variation pattern of the offset and the variation pattern of the transmission delay time, a part where a failure has occurred in the time synchronization with the higher-level device.

Description

Time synchronization device, time synchronization method and program

The present disclosure relates to a time synchronization device, time synchronization method and program.

The PTP (Precision Time Protocol) defined by the IEEE-1588 standard is a protocol that synchronizes the time (device time) of computers on a LAN (Local Area Network) with high accuracy (see Non-Patent Document 1). FIG. 11 is a diagram showing a configuration example of a time synchronization system 1 that synchronizes the time of devices on a network using the PTP protocol.

The time synchronization system 1 shown in FIG. 11 includes a Grand Master Clock 2, a conventional Boundary Clock 100a, and a client device 3. Grand Master Clock 2 and Boundary Clock 100a can communicate via a network such as a LAN. Also, the Boundary Clock 100a and the client device 3 can communicate via a network such as a LAN.

The Grand Master Clock 2 is equipped with a GNSS antenna that receives signals (GNSS signals) from satellites of a global positioning satellite system (GNSS: Global Navigation Satellite System) such as GPS (Global Positioning System). Grand Master Clock 2 receives GNSS signals via a GNSS antenna and obtains Coordinated Universal Time (UTC) from the received GNSS signals. The Grand Master Clock 2 has a master function that distributes the obtained UTC as a reference time via the network.

The Boundary Clock 100a functions as a device with a slave function that synchronizes the internal time of its own device with the time delivered from the host device for the host device with the master function, and for the slave device with the slave function functions as a device with master functionality. In the time synchronization system 1 shown in FIG. 11, the Boundary Clock 100a functions as a device with a slave function for the Grand Master Clock 2, and functions as a device with a master function for the client device 3. Therefore, the Boundary Clock 100a synchronizes the internal time of the Boundary Clock 100a with the time (reference time) delivered from the Grand Master Clock 2 by transmitting and receiving PTP packets to and from the Grand Master Clock 2. Further, the Boundary Clock 100a distributes the device internal time to the client device 3 by transmitting/receiving a PTP packet to/from the client device 3, and synchronizes the device internal time of the client device 3 with the internal device time of its own device.

The client device 3 has a slave function that synchronizes the internal time of the device with the time delivered from the device with the master function. In the time synchronization system 1 shown in FIG. 11, the client device 3 synchronizes the device internal time with the time delivered from the Boundary Clock 100a. The client device 3 is, for example, a base station device in a mobile phone network.

In the time synchronization system 1 shown in FIG. 11, if a failure occurs in the GNSS antenna provided by the Grand Master Clock 2, the Grand Master Clock 2 itself, or the transmission path between the Grand Master Clock 2 and the Boundary Clock 100a, the internal time of the Grand Master Clock 2 and the internal time of the Boundary Clock 100a.

　In the event of a failure in the transmission path, the time delivered from the Grand Master Clock 2 itself is accurate, and the Boundary Clock 100a does not synchronize with the incorrect time.

On the other hand, if the GNSS antenna provided by the Grand Master Clock 2 or the Grand Master Clock 2 itself fails, the time itself delivered from the Grand Master Clock 2 may be incorrect due to a large discrepancy from UTC. In this case, the conventional Boundary Clock 100a synchronizes with the internal time of the Grand Master Clock 2, which includes a large error, and may continue to deliver an erroneous time to the subordinate client device 3 due to a large error from UTC. If such an erroneous time is delivered, there is a possibility that the internal time of the user device under the control of the client device 3 will be shifted, resulting in system failure or communication failure. In addition to the user devices under the client device 3, the system failure or the It may cause communication failure. Thus, synchronization to the wrong time can cause very high impact problems. Therefore, it is necessary to more accurately determine the occurrence of a failure in synchronizing the internal time of the host device and the internal time of the local device and the location of the failure.

The object of the present disclosure, which has been made in view of the above problems, is to synchronize the device internal time of the device with the time delivered from the host device, and synchronize the device internal time of the lower device with the device internal time of the device itself. Provide a time synchronization device, a time synchronization method, and a program that can more accurately determine the occurrence of a failure in synchronizing the internal time of a host device and the internal time of its own device and the location of the failure when the time is synchronized. to do.

In order to solve the above problems, the time synchronization device according to the present disclosure synchronizes the device internal time of the own device with the device internal time of the host device by transmitting and receiving packets with the host device, and synchronizes the device internal time of the lower device. A time synchronizing device for synchronizing with the device internal time of the own device, the offset calculation unit calculating an offset that is a difference between the device internal time of the host device and the device internal time of the host device; and the host device A transmission delay time calculation unit for calculating a transmission delay time of a packet transmitted/received to/from the device itself, an offset pattern determination unit for determining the variation pattern of the offset, and a transmission delay for determining the variation pattern of the transmission delay time. a time pattern determination unit; and a failure location determination unit that determines a location where a failure occurs in time synchronization with the host device based on the offset variation pattern and the transmission delay time variation pattern.

Further, in order to solve the above problems, a time synchronization method according to the present disclosure synchronizes the device internal time of the device with the device internal time of the host device by transmitting and receiving packets with the host device, A time synchronization method for synchronizing a time with an internal device time of a host device, comprising: calculating an offset, which is a difference between the device internal time of the host device and the device internal time of the host device; a step of calculating a transmission delay time of a packet transmitted/received between itself; a step of determining a variation pattern of said offset; a step of determining a variation pattern of said transmission delay time; , determining a location where a failure occurs in time synchronization with the host device based on the variation pattern of the transmission delay time.

Also, in order to solve the above problems, a program according to the present disclosure causes a computer to operate as the time synchronization device described above.

According to the time synchronization device, time synchronization method, and program according to the present disclosure, the internal time of the own device is synchronized with the time delivered from the upper device, and the internal time of the lower device is synchronized with the internal time of the own device. In this case, it is possible to more accurately determine the occurrence of a failure in synchronization between the internal time of the host device and the internal time of the own device and the location of the failure.

1 is a diagram showing a configuration example of a Boundary Clock as a time synchronization device according to the first embodiment of the present disclosure; FIG. FIG. 4 is a diagram for explaining calculation of offset and transmission delay time; FIG. 2 is a flow chart showing an example of the operation of the Boundary Clock shown in FIG. 1; FIG. FIG. 5 is a diagram showing an example of an offset variation pattern; FIG. 10 is a diagram showing another example of an offset variation pattern; FIG. 4 is a diagram showing an example of a variation pattern of transmission delay time; FIG. 10 is a diagram showing another example of a variation pattern of transmission delay time; FIG. 10 is a diagram showing still another example of a transmission delay time variation pattern; 2 is a diagram for explaining determination of a failure location by a failure location determination unit shown in FIG. 1; FIG. 2 is a diagram showing an example of the hardware configuration of the Boundary Clock shown in FIG. 1; FIG. FIG. 7 is a diagram showing a configuration example of a Boundary Clock as a time synchronization device according to the second embodiment of the present disclosure; FIG. FIG. 9 is a flow chart showing an example of the operation of the Boundary Clock shown in FIG. 8; FIG. FIG. 9 is a diagram for explaining selection of time synchronization targets by the time selection unit shown in FIG. 8 ; It is a figure which shows the structural example of the conventional time synchronous system.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a configuration example of a Boundary Clock 100 as a time synchronization device according to the first embodiment of the present disclosure. The Boundary Clock 100 according to this embodiment distributes the time distributed from the Grand Master Clock 2 to the client device 3 instead of the Boundary Clock 100a in the time synchronization system 1 shown in FIG. That is, the Boundary Clock 100 as a time synchronization device according to the present embodiment synchronizes the device internal time of its own device with the device internal time of the host device by transmitting and receiving packets (PTP packets) with the host device (Grand Master Clock 2). , the device internal time of the subordinate device (client device 3) is synchronized with the device internal time of the own device.

As shown in FIG. 1, the Boundary Clock 100 according to this embodiment includes packet transmission/

reception units

101 and 105, an offset calculation unit 102, a transmission delay time calculation unit 103, a time synchronization processing unit 104, and a threshold storage unit 106. , an offset pattern determination section 107 , a transmission delay time pattern determination section 108 , a count flag section 109 , a Clock Class rewrite section 110 and a failure location determination section 111 .

The packet transmitting/receiving unit 101 transmits/receives PTP packets to/from the Grand Master Clock2. Packet transmitting/receiving section 101 outputs the packet received from Grand Master Clock 2 to offset calculating section 102 and transmission delay time calculating section 103 .

The offset calculation unit 102 calculates an offset, which is the difference between the Grand Master Clock 2, which is a higher-level device, and the internal device time of its own device (Boundary Clock 100). Specifically, the offset calculation unit 102 acquires the time stamp from the packet output from the packet transmission/reception unit 101, and calculates the offset based on the acquired time stamp. Calculation of the offset by the offset calculator 102 will be described below with reference to FIG.

As shown in FIG. 2, Grand Master Clock 2 sends a Sync message to Boundary Clock 100. The Grand Master Clock 2 transmits to the Boundary Clock 100 a Sync message including a time stamp indicating time T1, which is the transmission time of the Sync message.

When the Boundary Clock 100 receives the Sync message transmitted from the Grand Master Clock 2 at time T2, it transmits a Delay_Req message (delay request message) to the Grand Master Clock 2 at time T3.

When the Grand Master Clock 2 receives the Delay_Req message sent from the Boundary Clock 100 at time T 4 , it sends a Delay_Resp message (delayed response message) to the Boundary Clock 100 . The Grand Master Clock 2 transmits to the Boundary Clock 100 a Delay_Resp message including a time stamp indicating time T4, which is the time at which the Delay_Req message was received.

The offset calculation unit 102 calculates the time stamp indicating the time T1 when the Grand Master Clock 2 transmitted the Sync message, the time stamp indicating the time T2 when the Boundary Clock 100 received the Sync message, and the Boundary Clock 100 transmitting the Delay_Req message, which are included in the Sync message. and a time stamp indicating time T4 at which Grand Master Clock 2 transmitted the Delay_Req message included in the Delay_Resp message. Then, the offset calculator 102 calculates the offset based on Equation 1 below.
Offset = ((T2-T1)-(T4-T3))/2 Expression 1

Referring to FIG. 1 again, the offset calculation unit 102 outputs the offset calculation result to the time synchronization processing unit 104 and the offset pattern determination unit 107 .

The transmission delay time calculation unit 103 calculates the transmission delay time of PTP packets transmitted and received between the Grand Master Clock 2 and the Boundary Clock 100, which are host devices. The transmission delay time calculation unit 103 calculates the difference between the time T2 at which the Boundary Clock 100 received the Sync message and the time T1 at which the Grand Master Clock 2 transmitted the Sync message, the time T4 at which the Grand Master Clock 2 received the Delay_Req message, The average difference from the time T3 when the Boundary Clock 100 transmitted the Delay_Req message is calculated as the transmission delay time. That is, transmission delay time calculation section 103 calculates the transmission delay time based on Equation 2 below using time stamps respectively indicating times T1, T2, T3, and T4 described with reference to FIG.
Transmission delay time=((T2-T1)+(T4-T3))/2 Equation 2

The transmission delay time calculation unit 103 outputs the calculation result of the transmission delay time to the time synchronization processing unit 104 and the transmission delay time pattern determination unit 108 .

Based on the offset calculated by the offset calculation unit 102 and the transmission delay time calculated by the transmission delay time calculation unit 103, the time synchronization processing unit 104 converts the internal time of the Boundary Clock 100 to the internal time of the Grand Master Clock 2. sync to

The packet transmission/reception unit 105 transmits/receives PTP packets to/from the client device 3 . A packet transmitted/received to/from the client device 3 includes time information of the internal time of the Boundary Clock 100, and by transmitting/receiving the packet, the internal time of the client device 3 is synchronized with the internal time of the Boundary Clock 100. be able to.

Threshold storage unit 106 stores thresholds (first threshold TH1, second threshold TH2, third threshold TH3 and fourth threshold TH4) of is stored. Methods of setting each threshold include a method of setting a predetermined fixed value, a method of obtaining offset and transmission delay time data for a certain period of time, and a method of setting based on an average value thereof, and the like.

The offset pattern determination unit 107 determines the offset variation pattern calculated by the offset calculation unit 102 . Specifically, the offset pattern determination unit 107 determines whether or not the absolute value of the offset is greater than the first threshold TH1. Then, the offset pattern determination unit 107 determines whether or not the time or the number of times that the absolute value of the offset is greater than the first threshold TH1 is greater than the second threshold TH2, as the variation pattern of the offset. Offset pattern determination section 107 outputs the determination result to fault location determination section 111 .

The transmission delay time pattern determination unit 108 determines the variation pattern of the transmission delay time calculated by the transmission delay time calculation unit 103 . Specifically, transmission delay time pattern determining section 108 determines whether or not the transmission delay is greater than third threshold TH3. Then, transmission delay time pattern determining section 108 determines whether or not the time or the number of times that the transmission delay time is determined to be greater than the third threshold TH3 is greater than the fourth threshold TH4 as the variation pattern of the transmission delay time. do. Transmission delay time pattern determination section 108 outputs the determination result to fault point determination section 111 .

The count flag unit 109 manages an offset count flag that indicates whether or not the time or the number of times it is determined that the absolute value of the offset is greater than the first threshold TH1 is being counted. The count flag unit 109 also manages a transmission delay time count flag indicating whether or not the time or the number of times the transmission delay time is determined to be greater than the third threshold TH3 is being counted.

The Clock Class rewriting section 110 rewrites the Clock Class indicating whether or not the internal time of the Boundary Clock 100 is synchronized with the internal time of the Grand Master Clock 2 under the control of the failure point determining section 111 and outputs the Clock Class to the packet transmitting/receiving section 105 . do. The Clock Class is included in the PTP packet transmitted and received between the Boundary Clock 100 and the client device 3 and transmitted to the client device 3 . In the client device 3, if the Clock Class indicates that the internal time of the Boundary Clock 100 is synchronized with the internal time of the Grand Master Clock 2, the internal time of the client device 3 is synchronized with the internal time of the Boundary Clock 100. is done. Also, if the Clock Class indicates that the internal time of the Boundary Clock 100 is not synchronized with the internal time of the Grand Master Clock 2, the synchronization of the internal time of the client device 3 with the internal time of the Boundary Clock 100 is stopped. be.

Based on the offset variation pattern determined by the offset pattern determination unit 107 and the transmission delay time variation pattern determined by the transmission delay time pattern determination unit 108, the failure location determination unit 111 determines the Grand Determine the occurrence of a time synchronization failure with Master Clock 2 and the location of the failure.

　The location of the time synchronization failure can be the GNSS antenna provided by the Grand Master Clock 2, the Grand Master Clock 2 itself, or the transmission path between the Grand Master Clock 2 and the Boundary Clock 100. If the point of failure is the GNSS antenna, it is conceivable that it has been subjected to signal attacks such as jamming or spoofing. Also, if the location of the failure is the Grand Master Clock 2 itself, it is conceivable that some functions within the Grand Master Clock 2 have failed. Also, if the location of the failure is the transmission path between the Grand Master Clock 2 and the Boundary Clock 100, for example, a temporary cable failure may have occurred.

The failure location determination unit 111 determines that the location of the failure is the Grand Master Clock 2 (the GNSS antenna provided by the Grand Master Clock 2, or the Grand Master Clock 2 itself) or the transmission path between the Grand Master Clock 2 and the Boundary Clock 100. determine whether The details of the determination of the failure location by the failure location determination unit 111 will be described later.

When the failure location determining unit 111 determines that the failure location is the Grand Master Clock 2, it stops synchronizing the internal device time of the client device 3 with the internal device time of its own device. Specifically, the failure point determination unit 111 rewrites the Clock Class so that the Clock Class indicates that the internal time of the Boundary Clock 100 is not synchronized with the internal time of the Grand Master Clock 2. direct to.

Next, the operation of the Boundary Clock 100 according to this embodiment will be described.

FIG. 3 is a flowchart showing an example of the operation of the Boundary Clock 100 according to this embodiment, and is a diagram for explaining the time synchronization method by the Boundary Clock 100. FIG.

The offset calculation unit 102 acquires the time stamp from the packet output from the packet transmission/reception unit 101 and calculates the offset (step S101).

The offset pattern determination unit 107 determines whether the absolute value of the offset calculated by the offset calculation unit 102 is greater than the first threshold TH1 stored in the threshold storage unit 106 (step S102). The first threshold TH1 is a threshold for determining whether or not the offset has changed significantly. For example, normally, if the absolute value of the offset between the device time of Grand Master Clock 2 and the device time of Boundary Clock 100 is less than 1 ms, the first threshold TH1 is set to 1 ms, for example. In this case, the offset pattern determination unit 107 sequentially determines whether the absolute value of the offset is greater than 1 ms. The offset pattern determination unit 107 counts the number of consecutive determinations that the absolute value of the offset is greater than the first threshold TH1. This count value is hereinafter referred to as an offset count.

Note that, as described above, the average value of data for a certain period of time may be set as the first threshold TH1. For example, in one minute from the start of PTP communication between Grand Master Clock 2 and Boundary Clock 100, the offset is calculated every second, and the average value of the 60 pieces of data is used as the first threshold value TH1. may be set.

When determining that the absolute value of the offset is greater than the first threshold TH1 (step S102: Yes), the offset pattern determination unit 107 increases the offset count by 1 (step S103) and turns on the offset count flag. If the offset count flag is already on, the offset pattern determination unit 107 keeps the offset count flag on.

Next, the offset pattern determination unit 107 determines whether or not the offset count is greater than the second threshold TH2 (step S104). The second threshold TH2 is a threshold for determining whether the change in offset is temporary. The second threshold TH2 is set to 10 times, for example. In this case, the offset pattern determination unit 107 determines whether or not the absolute value of the offset is greater than the first threshold TH1 (for example, 1 ms) ten consecutive times.

If the offset pattern determination unit 107 determines that the offset count is equal to or less than the second threshold TH2 (0<offset count≦second threshold TH2) (step S104: No), the process is repeated from step S101. .

If it is determined that the offset count is greater than the second threshold TH2 (second threshold TH2<offset count) (step S104: Yes), the offset pattern determination unit 107 determines that the offset count is greater than the second threshold TH2. This is notified to the failure location determination unit 111 . In other words, the offset pattern determination unit 107 detects, as the offset variation pattern, that the state in which the absolute value of the offset is greater than the first threshold TH1 continues for a predetermined time corresponding to the second threshold TH2. can be notified to

When determining that the absolute value of the offset is equal to or less than the first threshold TH1 (step S102: No), the offset pattern determining unit 107 sets the offset count to 0 and turns off the offset count flag (step S105). . When the absolute value of the offset continues to be equal to or less than the first threshold TH1, the offset count is 0 and the offset count flag remains off. Therefore, the offset pattern determination unit 107 can notify the fault location determination unit 111 that the offset variation pattern is that the absolute value of the offset continues to be equal to or less than the first threshold TH1.

Even if the absolute value of the offset is greater than the first threshold TH1, the Boundary Clock 100 synchronizes the device internal time of its own device with the device internal time of the Grand Master Clock 2, so that the offset eventually reaches the first threshold TH1. be smaller than Therefore, the offset pattern determination unit 107 determines whether the offset variation pattern is a pattern (pattern 0) in which the offset remains smaller than the first threshold TH1 shown in FIG. is larger than the threshold TH1, and after a predetermined period of time corresponding to the second threshold TH2 has elapsed, it is determined whether the pattern (pattern 1) is smaller than the first threshold TH1. output to

In parallel with the processing from step S101 to step S105 described above, the processing from step S106 to step S109 described below is performed.

The transmission delay time calculation unit 103 acquires the time stamp from the packet output from the packet transmission/reception unit 101 and calculates the transmission delay time (step S106).

The transmission delay time pattern determination unit 108 determines whether or not the transmission delay time calculated by the transmission delay time calculation unit 103 is greater than the third threshold TH3 stored in the threshold storage unit 106 (step S107). . The third threshold TH3 is a threshold for determining whether or not the transmission delay time has changed significantly. For example, normally, when packets are transmitted and received between the Grand Master Clock 2 and the Boundary Clock 100 within 10 ms, the third threshold TH3 is set to 10 ms, for example. In this case, transmission delay time pattern determination section 108 successively determines whether or not the transmission delay time is greater than 10 ms. The transmission delay time pattern determination unit 108 counts the number of consecutive determinations that the transmission delay time is greater than the third threshold TH3. This count value is hereinafter referred to as a transmission delay time count.

Note that, as described above, the average value of data for a certain period of time may be set as the third threshold TH3. For example, in one minute after the start of PTP communication between Grand Master Clock 2 and Boundary Clock 100, the transmission delay time is calculated every second, and the average value of the 60 pieces of data is the third threshold. It may be set as TH3.

If it is determined that the transmission delay time is greater than the third threshold TH3 (step S107: Yes), the transmission delay time pattern determination unit 108 increases the transmission delay time count by 1 (step S108), and turns on the transmission delay time count flag. to If the transmission delay time count flag is already on, transmission delay time pattern determination section 108 keeps the transmission delay time count flag on.

Next, the transmission delay time pattern determination unit 108 determines whether or not the transmission delay time count is greater than the fourth threshold TH4 (step S109). A fourth threshold TH4 is a threshold for determining whether the change in transmission delay time is temporary. The fourth threshold TH4 is set to ten times, for example. In this case, the transmission delay time pattern determination unit 108 determines whether or not the transmission delay time is greater than the third threshold TH3 (for example, 10 ms) ten consecutive times.

If the transmission delay time pattern determining unit 108 determines that the transmission delay time count is equal to or less than the fourth threshold TH (0<transmission delay time count≤fourth threshold TH4) (step S109: No), step The process is repeated from S106.

When it is determined that the transmission delay time count is greater than the fourth threshold TH4 (fourth threshold TH4<transmission delay time count) (step S109: Yes), the transmission delay time pattern determination unit 108 determines that the transmission delay time count is greater than the fourth threshold TH4. It notifies the failure point determination unit 111 that the threshold value TH4 of 4 has been exceeded. That is, the transmission delay time pattern determination unit 108 determines that the state in which the transmission delay time is greater than the third threshold TH3 continues for a predetermined time corresponding to the fourth threshold TH4 as the variation pattern of the transmission delay time. The determination unit 111 can be notified.

If it is determined that the transmission delay time is equal to or less than the third threshold TH3 (step S107: No), the transmission delay time pattern determination unit 108 sets the transmission delay time count to 0 and turns off the transmission delay time count flag. (step S105). When the transmission delay time continues to be equal to or less than the third threshold TH3, the transmission delay time count is 0 and the transmission delay time count flag remains off. Therefore, the transmission delay time pattern determination unit 108 can notify the failure location determination unit 111 that the transmission delay time is continuously equal to or less than the third threshold TH3 as the variation pattern of the transmission delay time. . Further, when the transmission delay time becomes larger than the third threshold TH3 and becomes less than or equal to the third threshold TH3 before the predetermined time corresponding to the fourth threshold TH4 elapses, the transmission delay time count is 0, and the transmission delay time count flag is changed from on to off. Therefore, the transmission delay time pattern determination unit 108 determines that the transmission delay time becomes larger than the third threshold TH3 and the transmission delay time before the predetermined time corresponding to the fourth threshold TH4 elapses as the variation pattern of the transmission delay time. has become equal to or less than the third threshold TH3.

Therefore, the transmission delay time pattern determination unit 108 determines whether the variation pattern of the transmission delay time is a pattern (pattern 0) in which the transmission delay time remains smaller than the third threshold TH3 shown in FIG. 5C, in which the transmission delay time becomes larger than the third threshold TH3 and becomes smaller than the third threshold TH3 before the predetermined time corresponding to the fourth threshold TH4 elapses (pattern 1), or FIG. is a pattern in which the transmission delay time is greater than the third threshold TH3 continues even after a predetermined period of time corresponding to the fourth threshold TH4 has passed. output to

In response to the judgment result of the offset fluctuation pattern by the offset pattern judging unit 107 and the judgment result of the transmission delay time fluctuation pattern by the transmission delay time pattern judging unit 108 (after the process of step S104, step S105 or step S109), a fault is detected. The location determination unit 111 determines the occurrence of a failure in time synchronization with the Grand Master Clock 2 and the location of the failure based on the variation pattern of the offset and the variation pattern of the transmission delay time (step S110). Determination of the failure location by the failure location determination unit 111 will be described with reference to FIG.

As described with reference to FIGS. 4A and 4B, there are two patterns, pattern 0 and pattern 1, as offset variation patterns. Also, as described with reference to FIGS. 5A, 5B, and 5C, there are three patterns, pattern 0, pattern 1, and pattern 2, as transmission delay time variation patterns. Therefore, by combining the offset variation pattern and the transmission delay time variation pattern, there are six patterns (pattern A to pattern F) as shown in FIG.

Pattern A is a pattern in which pattern 0 is the variation pattern of the offset and pattern 0 is the variation pattern of the transmission delay time. That is, in pattern A, the absolute value of the offset is equal to or less than the first threshold TH1 (FIG. 4A), and the transmission delay time is equal to or less than the third threshold TH3. Therefore, there is no abnormality in the offset and the transmission delay time, and it is considered that there is no failure in synchronizing the internal time of the Grand Master Clock 2 and the internal time of the Boundary Clock 100 .

Pattern B is a pattern in which pattern 1 is the variation pattern of the offset and pattern 0 is the variation pattern of the transmission delay time. That is, pattern B is a state in which the absolute value of the offset is greater than the first threshold TH1 and the transmission delay time is less than or equal to the third threshold TH3. In this case, in pattern B, although there is no abnormality in the transmission path between the Grand Master Clock 2 and the Boundary Clock 100, the absolute value of the offset has a deviation larger than the first threshold TH1. It is considered that an abnormality has occurred in the internal time of Grand Master Clock 2 (a failure occurred in Grand Master Clock 2).

Pattern C is a pattern in which pattern 0 is the variation pattern of the offset and pattern 1 is the variation pattern of the transmission delay time. That is, pattern C is a state in which the absolute value of the offset is less than or equal to the first threshold TH1, and the transmission delay time is greater than the third threshold TH3 and then less than the third threshold TH3. In this case, in pattern C, even if the transmission delay time fluctuates greatly temporarily, the offset does not deviate more than the first threshold TH1, so the transmission line between Grand Master Clock 2 and Boundary Clock 100 It is considered that a temporary failure (eg, congestion) occurred in

Pattern D is a pattern in which pattern 1 is the variation pattern of the offset and pattern 1 is the variation pattern of the transmission delay time. That is, in pattern D, the absolute value of the offset becomes larger than the first threshold TH1, then becomes equal to or smaller than the first threshold TH1, and the transmission delay time becomes larger than the third threshold TH3, and then the third threshold TH3. is smaller than the threshold TH3. In this case, in pattern D, even if the transmission delay time temporarily increases, it returns to the original value. It is possible that a failure occurred on its own.

Pattern E is a pattern in which pattern 0 is the variation pattern of the offset and pattern 2 is the variation pattern of the transmission delay time. That is, in pattern E, the absolute value of the offset remains equal to or less than the first threshold TH1 and the transmission delay time remains greater than the third threshold TH3. Pattern F is a pattern in which pattern 1 is the variation pattern of the offset and pattern 2 is the variation pattern of the transmission delay time. That is, in pattern F, the absolute value of the offset becomes greater than the first threshold TH1, then becomes equal to or less than the first threshold TH1, and the transmission delay time remains greater than the third threshold TH3. In patterns E and F, since the transmission delay time anomaly continues for a long time, it is considered that an anomaly has occurred in the transmission line (for example, cable) between the Grand Master Clock 2 and the Boundary Clock 100 .

The fault location determining unit 111 determines the location of the failure based on the combination of the offset variation pattern and the transmission delay time variation pattern as described with reference to FIG. Specifically, in the case of patterns A, C, E, and F, the failure point determination unit 111 determines that no failure has occurred or that a failure has occurred in the transmission line between the Grand Master Clock 2 and the Boundary Clock 100. judge. On the other hand, in the case of patterns B and D, the failure location determining unit 111 determines that a failure has occurred in the Grand Master Clock2.

Referring to FIG. 3 again, if the failure location determining unit 111 determines that no failure has occurred or that a failure has occurred in the transmission path between the Grand Master Clock 2 and the Boundary Clock 100 (offset fluctuation pattern and If the combination with the variation pattern of the transmission delay time is pattern A, C, E, F), the time itself delivered from the Grand Master Clock 2 is accurate, so the internal time of the client device 3 continues to be the own device. Synchronize with the device internal time.

When the failure location determining unit 111 determines that a failure has occurred in the Grand Master Clock 2 (when the combination of the offset fluctuation pattern and the transmission delay time fluctuation pattern is patterns B and D), the failure occurs in the Grand Master Clock 2. The occurrence is notified to the Clock Class rewriting unit 110 (step S111).

Upon receiving the notification from the failure location determining unit 111, the Clock Class rewriting unit 110 rewrites the Clock Class so that the Clock Class indicates that the internal time of the Boundary Clock 100 is not synchronized with the internal time of the Grand Master Clock 2. . As a result, synchronization of the device internal time of the client device 3 with the device internal time of the Boundary Clock 100 is stopped.

In FIG. 3, the second threshold TH2 is the number of times the absolute value of the offset is determined to be greater than the first threshold TH1, but it is not limited to this. The second threshold TH2 may be the time during which the absolute value of the offset is continuously determined to be greater than the first threshold TH1. In this case, the offset pattern determination unit 107 determines, for example, whether the time period during which the absolute value of the offset exceeds the first threshold TH1 is longer than the second threshold TH2 (eg, 30 seconds).

Also, in FIG. 3, the fourth threshold TH4 is the number of times the transmission delay time is determined to be greater than the third threshold TH3, but it is not limited to this. The fourth threshold TH4 may be a period of time during which the transmission delay time is continuously determined to be greater than the third threshold TH3. In this case, the transmission delay time pattern determination unit 108 determines, for example, whether or not the time during which the transmission delay time exceeds the third threshold TH3 is longer than the fourth threshold TH4 (eg, 30 seconds).

Then, the failure point determination unit 111 determines that the time or the number of times that the absolute value of the offset is greater than the first threshold TH1 is greater than the second threshold TH2, and the transmission delay time is equal to or less than the third threshold TH3. If there is, it is determined that the location of the fault is Grand Master Clock2. Alternatively, the failure point determination unit 111 determines that the time or number of times that the absolute value of the offset is greater than the first threshold TH1 is greater than the second threshold TH2, and the transmission delay time is greater than the third threshold TH3. If the determined time or number of times is smaller than the fourth threshold TH4, it is determined that the fault has occurred at Grand Master Clock2.

A method of determining the occurrence of a failure and the location of the failure using only the variation pattern of the transmission delay time is also conceivable. For example, if the transmission delay time fluctuation pattern fluctuates like pattern 1 shown in FIG. 5B, a failure occurs in Grand Master Clock 2, and if it fluctuates like pattern 2 shown in FIG. A method of determining that a failure has occurred in the transmission line between the Master Clock 2 and the Boundary Clock 100 is conceivable. However, this method may not be able to accurately determine the occurrence of a fault and the location of the fault.

For example, when time T1 and time T4 are shifted by the same amount of time, time T1 and time T4 cancel each other out, as is clear from the above-described equation 2, and the change in transmission delay time due to the shift between time T1 and time T4 is determined. Sometimes I can't.

On the other hand, in this embodiment, by using not only the transmission delay time variation pattern but also the offset variation pattern, it is possible to more accurately determine the occurrence of a failure and the location of the failure. In the example described above, even if the time T1 and the time T4 are shifted by the same amount of time, the time T1 and the time T4 do not cancel each other out, as is clear from the above equation 1. Therefore, the time T1 and the time T4 Misalignment can be determined as a variation in offset.

In addition, in this embodiment, the time synchronization device according to the present disclosure has been described using an example in which time synchronization is performed between the Grand Master Clock 2 and the client device 3, but it is not limited to this. The time synchronization device according to the present disclosure may perform time synchronization between one Boundary Clock and another Boundary Clock, for example.

Next, the hardware configuration of the Boundary Clock 100 as the time synchronization device according to this embodiment will be described.

FIG. 7 is a diagram showing an example of the hardware configuration of the Boundary Clock 100 as the time synchronization device according to this embodiment. FIG. 7 shows an example of the hardware configuration of the Boundary Clock 100 when the Boundary Clock 100 is configured by a computer capable of executing program instructions. Here, the computer may be a general-purpose computer, a dedicated computer, a workstation, a PC (Personal computer), an electronic notepad, or the like. Program instructions may be program code, code segments, etc. for performing the required tasks.

As shown in FIG. 7, the Boundary Clock 100 includes a processor 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a storage 14, an input section 15, a display section 16 and a communication interface (I/F) 17. have. Each component is communicatively connected to each other via a bus 19 . The processor 11 is specifically a CPU (Central Processing Unit), MPU (Micro Processing Unit), GPU (Graphics Processing Unit), DSP (Digital Signal Processor), SoC (System on a Chip), and the like. may be configured by a plurality of processors of

The processor 11 is a control unit that controls each configuration and executes various arithmetic processing. That is, the processor 11 reads a program from the ROM 12 or the storage 14 and executes the program using the RAM 13 as a work area. The processor 11 performs control of each configuration and various arithmetic processing according to programs stored in the ROM 12 or the storage 14 . In this embodiment, the ROM 12 or storage 14 stores a program for causing a computer to function as the Boundary Clock 100 according to the present disclosure. By reading and executing the program by the processor 11, each configuration of the Boundary Clock 100, that is, the offset calculation unit 102, the transmission delay time calculation unit 103, the time synchronization processing unit 104, the offset pattern determination unit 107, the transmission delay A time pattern determination section 108, a count flag section 109, a Clock Class rewrite section 110, and a fault point determination section 111 are implemented.

Programs are stored in non-transitory storage media such as CD-ROM (Compact Disk Read Only Memory), DVD-ROM (Digital Versatile Disk Read Only Memory), USB (Universal Serial Bus) memory, etc. may be provided in Also, the program may be downloaded from an external device via a network.

The ROM 12 stores various programs and various data. RAM 13 temporarily stores programs or data as a work area. The storage 14 is configured by a HDD (Hard Disk Drive) or SSD (Solid State Drive) and stores various programs including an operating system and various data. The ROM 12 or storage 14 stores, for example, the above-described first threshold TH1, second threshold TH2, third threshold TH3 and fourth threshold TH4.

The input unit 15 includes a pointing device such as a mouse and a keyboard, and is used for various inputs.

The display unit 16 is, for example, a liquid crystal display, and displays various information. The display unit 16 may employ a touch panel system and function as the input unit 15 .

The communication interface 17 is an interface for communicating with other devices (eg, Grand Master Clock 2 and client device 3), for example, an interface for LAN.

A computer can be suitably used to function as each part of the Boundary Clock 100 described above. Such a computer can be implemented by storing a program describing the processing details for realizing the function of each part of the Boundary Clock 100 in the memory of the computer, and reading and executing this program by the processor of the computer. can be done. That is, the program can cause the computer to function as the Boundary Clock 100 described above. It is also possible to record the program in a non-temporary storage medium. It is also possible to provide the program via a network.

As described above, the Boundary Clock 100 as a time synchronization device according to this embodiment includes an offset calculation unit 102, a transmission delay time calculation unit 103, an offset pattern determination unit 107, a transmission delay time pattern determination unit 108, and a fault location determination unit. and a section 111 . The offset calculation unit 102 calculates an offset, which is the difference between the internal device time of the host device and the internal device time of the own device. The transmission delay time calculator 103 calculates the transmission delay time of packets transmitted and received between the host device and its own device. The offset pattern determination unit 107 determines an offset variation pattern. Transmission delay time pattern determining section 108 determines a variation pattern of transmission delay time. The failure location determination unit 111 determines the location of a failure in time synchronization with a higher-level device based on the variation pattern of the offset and the variation pattern of the transmission delay time.

In the time synchronization method according to the embodiment, the offset calculation unit 102 calculates an offset that is the difference between the device internal time of the host device and the device internal time of the own device (step S101), and the transmission delay time calculation and a step (step S106) of calculating a transmission delay time of a packet transmitted/received between the host device and the own device by the unit 103 . Further, in the time synchronization method according to the present embodiment, the offset pattern determination unit 107 determines the offset variation pattern (steps S102 to S104), and the transmission delay time pattern determination unit 108 determines the transmission delay time variation. A step of determining a pattern (steps S107 to S109), and a failure location determination unit 111 determines a failure location of time synchronization with a higher-level device based on an offset variation pattern and a transmission delay time variation pattern. and (step S110).

By judging the location of the failure based on the variation pattern of the offset and the variation pattern of the transmission delay time, it is possible to more accurately detect the occurrence of the failure without being affected by the time shift in the Grand Master Clock 2. It is possible to accurately determine the location of the failure. As a result, it is possible to reduce the possibility of synchronizing the device internal time of the lower device with an incorrect time.

(Second embodiment)
FIG. 8 is a diagram showing a configuration example of a Boundary Clock 100A as a time synchronization device according to the second embodiment of the present disclosure.

As shown in FIG. 8, the Boundary Clock 100A according to this embodiment includes packet transmission/

reception units

101, 101A, and 105, an offset calculation unit 102, a transmission delay time calculation unit 103, a time synchronization processing unit 104, and a threshold storage unit. 106 , an offset pattern determination unit 107 , a transmission delay time pattern determination unit 108 , a count flag unit 109 , a failure location determination unit 111 A, and a time selection unit 112 . The Boundary Clock 100A according to this embodiment differs from the Boundary Clock 100 according to the first embodiment in that a packet transmission/reception section 101A and a time selection section 112 are added, and the Clock Class rewrite section 110 is removed. , in that the failure location determination unit 111 is changed to a failure location determination unit 111A.

The packet transmitting/receiving unit 101A transmits/receives packets to/from the Grand Master Clock 2A, which is different from the Grand Master Clock 2 with which the packet transmitting/receiving unit 101 transmits/receives packets. That is, the Boundary Clock 100A according to this embodiment can communicate with a plurality of Grand Master Clocks 2 and 2A. Packet transmitting/receiving section 101A outputs the packet received from Grand Master Clock 2A to offset calculating section 102 and transmission delay time calculating section 103 .

The time selection unit 112 selects a target for synchronizing the internal time of the device from among a plurality of Grand Master Clocks 2 and 2A with which the Boundary Clock 100A can communicate. The time selection unit 112 selects a target for synchronizing the internal time according to, for example, BMCA (Best Master Clock Algorithm) defined by IEEE Std 1588 ^™ -2019.

Similar to the failure location determination unit 111, the failure location determination unit 111A determines the occurrence of a time synchronization failure with the host device and the location of the failure based on the variation pattern of the offset and the variation pattern of the transmission delay time. . Then, when the failure location determination unit 111A determines that the location of the failure is the host device with which the device internal time of the device itself is synchronized, the time selection unit 112 selects the target device to synchronize the device internal time of the device itself. to switch.

Next, the operation of the Boundary Clock 100A according to this embodiment will be described.

FIG. 9 is a flow chart showing an example of the operation of the Boundary Clock 100A according to this embodiment. In FIG. 9, the same reference numerals are assigned to the same processes as in FIG. 3, and the description thereof is omitted.

The time selection unit 112 performs time synchronization by synchronizing the internal time of the own device by BMCA in parallel with the processing from step S101 to step S104 and the processing from step S106 to step S109 described with reference to FIG. is selected (step S201). The selection of targets for time synchronization by BMCA is described in IEEE Std 1588 ^TM -2019 and the like, so a detailed description will be omitted, but an outline will be described with reference to FIG. 10 . In FIG. 10, an example of selecting a target for time synchronization from two host devices (Grand Master Clock A and Grand Master Clock B) will be described.

The time selection unit 112 acquires packets including the parameters shown below, which are respectively transmitted from Grand Master Clock A and Grand Master Clock B via the packet transmission/

reception units

101 and 101A.
Identification code (GM Identity): Identification code unique to the Grand Master Clock Priority 1 (GM priority 1): First priority for each Grand Master Clock set by the administrator GM class (GM class): Identification code for each Grand Master Clock A value that indicates traceability (ability to trace to UTC (index indicating reliability of time)) GM clock accuracy: (GM accuracy value): A value that indicates the accuracy of time for each Grand Master Clock GM clock stability (GM offsetScaledLogVariance) : Value indicating stability for each Grand Master Clock Priority 2 (GM priority 2): Second priority for each Grand Master Clock set by the administrator

First, the time selection unit 112 compares the identification codes of Grand Master Clock A and Grand Master Clock B, and determines whether the identification codes of Grand Master Clock A and Grand Master Clock B are the same (step S301). . If it is determined that the identification codes of Grand Master Clock A and Grand Master Clock B are the same (step S301: Yes), the time selection unit 112 determines the number of stages connected from each Grand Master Clock to Boundary Clock 100A. , the upstream port number, the receiving port number, and the receiving side port number of the same data set are compared to select a target for time synchronization.

When it is determined that the identification codes of Grand Master Clock A and Grand Master Clock B are not the same (step S301: No), the time selection unit 112 compares the priority 1 of Grand Master Clock A and Grand Master Clock B (step S302).

When the priority 1 of Grand Master Clock A is lower than the priority 1 of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as a target for time synchronization.

When the priority 1 of Grand Master Clock B is lower than the priority 1 of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as a target for time synchronization.

When Grand Master Clock A and Grand Master Clock B have the same priority 1 (A=B), the time selection unit 112 compares the GM classes of Grand Master Clock A and Grand Master Clock B (step S303).

When the GM class of Grand Master Clock A is smaller than the GM class of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as a target for time synchronization.

When the GM class of Grand Master Clock B is smaller than the GM class of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as a target for time synchronization.

When the GM classes of Grand Master Clock A and Grand Master Clock B are the same (A=B), the time selection unit 112 compares the GM clock accuracy of Grand Master Clock A and Grand Master Clock B (step S304).

When the GM clock precision of Grand Master Clock A is smaller than the GM clock precision of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as a target for time synchronization.

When the GM clock precision of Grand Master Clock B is smaller than the GM clock precision of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as a target for time synchronization.

When the GM clock accuracy of Grand Master Clock A and Grand Master Clock B are the same (A=B), the time selection unit 112 compares the GM clock stability of Grand Master Clock A and Grand Master Clock B (step S305 ).

When the GM clock stability of Grand Master Clock A is less than the GM clock stability of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as a target for time synchronization.

When the GM clock stability of Grand Master Clock B is smaller than the GM clock stability of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as a target for time synchronization.

When the GM clock stability of Grand Master Clock A and Grand Master Clock B are the same (A=B), the time selection unit 112 compares the priority 2 of Grand Master Clock A and Grand Master Clock B (step S306 ).

When the priority 2 of Grand Master Clock A is lower than the priority 2 of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as a target for time synchronization.

When the priority 2 of Grand Master Clock B is lower than the priority 2 of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as a target for time synchronization.

When the priority 2 of Grand Master Clock A and Grand Master Clock B are the same (A=B), the time selection unit 112 compares the identification codes of Grand Master Clock A and Grand Master Clock B (step S307).

When the identification code of Grand Master Clock A is smaller than the identification code of Grand Master Clock B (A<B), the time selection unit 112 selects Grand Master Clock A as a target for time synchronization.

When the identification code of Grand Master Clock B is smaller than the identification code of Grand Master Clock A (B<A), the time selection unit 112 selects Grand Master Clock B as a target for time synchronization.

Through the above-described processing, the time selection unit 112 appropriately selects a host device (Grand Master Clock 2 or Grand Master Clock 2A) with which to synchronize the internal time of the Boundary Clock 100A.

Referring to FIG. 9 again, when the failure location determination unit 111A determines that the failure location is a higher-level device (for example, Grand Master Clock 2) that synchronizes the internal time of its own device, the failure occurs in Grand Master Clock 2. has occurred to the time selection unit 112 (step S202).

Upon receiving the notification from the failure point determination unit 111A, the time selection unit 112 switches the target of time synchronization for synchronizing the internal time of the own device. For example, in a state in which the device internal time of the own device is synchronized with the device internal time of Grand Master Clock 2, when notified by the fault location determination unit 111A that a fault has occurred in Grand Master Clock 2, the time selection unit 112 , the target of time synchronization is switched from Grand Master Clock 2 to Grand Master Clock 2A. For example, in the process of selecting a target for time synchronization by BMCA described with reference to FIG. 10, the time selection unit 112 switches the target for time synchronization when determining that A=B in step S305.

As described above, the Boundary Clock 100A as a time synchronization device according to this embodiment has a time selection unit 112 that selects a host device with which to synchronize the internal time of its own device from among a plurality of host devices (Grand Master Clocks 2 and 2A). further provide. When failure location determination unit 111A determines that the location of the failure is the host device with which the device internal time is synchronized, failure location determination unit 111A instructs time selection unit 112 to select the host device with which the device internal time is synchronized. let me switch.

Therefore, it is possible to reduce the possibility of synchronizing the internal time of the lower device with an incorrect time.

The Boundary Clock 100A according to the second embodiment can also be configured by a computer having the hardware configuration described with reference to FIG.

Regarding the above embodiments, the following additional remarks are disclosed.

[Appendix 1]
A time synchronizing device for synchronizing the device internal time of its own device with the device internal time of the host device by transmitting and receiving packets to and from a host device, and synchronizing the device internal time of the lower device with the device internal time of the device itself, ,
memory;
a controller connected to the memory;
with
The control unit
calculating an offset, which is the difference between the internal device time of the host device and the internal device time of the own device;
calculating the transmission delay time of packets transmitted and received between the higher-level device and the own device;
determining a variation pattern of the offset;
determining a variation pattern of the transmission delay time;
A time synchronizing device that determines a location of failure in time synchronization with the host device based on the variation pattern of the offset and the variation pattern of the transmission delay time.

[Appendix 2]
In the time synchronization device according to additional item 1,
The time synchronizing device, wherein the control unit stops synchronizing the internal device time of the lower device with the internal device time of the own device when it is determined that the fault has occurred in the higher device.

[Appendix 3]
In the time synchronization device according to additional item 1,
The control unit
select a host device with which to synchronize the internal time of the device from among multiple host devices,
A time synchronizing device that, when determining that the location of the failure is the host device, switches the host device with which the internal time of the self device is to be synchronized from among a plurality of host devices.

[Appendix 4]
In the time synchronization device according to additional item 1,
The control unit
Determining whether the absolute value of the offset is greater than the first threshold, and determining that the absolute value of the offset is greater than the first threshold as the variation pattern of the offset is the second Determine whether it is greater than the threshold,
determining whether or not the transmission delay time is greater than a third threshold, and determining whether or not the transmission delay time is greater than the third threshold as a variation pattern of the transmission delay time; A time synchronization device that determines whether or not it is greater than a threshold.

[Appendix 5]
In the time synchronization device according to additional item 4,
When the time or the number of times that the absolute value of the offset is greater than the first threshold is greater than the second threshold and the transmission delay time is less than or equal to the third threshold Alternatively, when the time or the number of times it is determined that the transmission delay time is greater than the third threshold is less than the fourth threshold, the time synchronization device determines that the fault has occurred in the upper device. .

[Appendix 6]
A time synchronization method for synchronizing the device internal time of a device with the device internal time of the host device and synchronizing the device internal time of a lower device with the device internal time of the device by transmitting and receiving packets to and from a host device, ,
calculating an offset, which is the difference between the internal device time of the host device and the internal device time of the own device;
calculating the transmission delay time of packets transmitted and received between the higher-level device and the own device;
determining a variation pattern of the offset;
determining a variation pattern of the transmission delay time;
A time synchronization method, wherein a location of failure in time synchronization with the host device is determined based on the variation pattern of the offset and the variation pattern of the transmission delay time.

[Appendix 7]
A non-temporary storage medium storing a program executable by a computer, the non-temporary storage medium storing the program for causing the computer to operate as the time synchronization device according to claim 1.

Although the above embodiments have been described as representative examples, it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present disclosure. Therefore, the present invention should not be construed as limited by the embodiments described above, and various modifications and changes are possible without departing from the scope of the claims. For example, it is possible to combine a plurality of configuration blocks described in the configuration diagrams of the embodiments into one, or divide one configuration block.

1

Time synchronization system

2, 2A Grand Master Clock (upper device)
3 Client device (lower device)
11 processor 12 ROM
13 RAM
14 storage 15 input unit 16 display unit 17 communication I/F
19

Bus

100, 100A Boundary Clock (time synchronization device)
101, 101A, 105 packet transmission/reception unit 102 offset calculation unit 103 transmission delay time calculation unit 104 time synchronization processing unit 106 threshold storage unit 107 offset pattern determination unit 108 transmission delay time pattern determination unit 109 count flag unit 110 clock

class rewrite unit

111, 111A Fault point determination unit 112 Time selection unit

Claims

A time synchronizing device for synchronizing the device internal time of its own device with the device internal time of the host device by transmitting and receiving packets to and from a host device, and synchronizing the device internal time of the lower device with the device internal time of the device itself, ,
an offset calculation unit that calculates an offset, which is the difference between the internal device time of the host device and the internal device time of the own device;
a transmission delay time calculation unit that calculates the transmission delay time of packets transmitted and received between the host device and the self device;
an offset pattern determination unit that determines the variation pattern of the offset;
a transmission delay time pattern determination unit that determines a variation pattern of the transmission delay time;
A time synchronizing device comprising: a failure location determination unit that determines a location of failure in time synchronization with the higher-level device based on the variation pattern of the offset and the variation pattern of the transmission delay time.
In the time synchronization device according to claim 1,
The time synchronizing device, wherein the failure location determination unit stops synchronizing the device internal time of the lower device with the device internal time of the own device when it determines that the failure location is the host device.
In the time synchronization device according to claim 1,
further comprising a time selection unit that selects, from among a plurality of higher-level devices, a higher-level device with which the internal time of the device is to be synchronized;
The time synchronizing device, wherein, when the failure location determination unit determines that the location of the failure is the host device, the time selection unit switches the host device with which the device internal time of the own device is to be synchronized.
In the time synchronization device according to any one of claims 1 to 3,
The offset pattern determination unit determines whether or not the absolute value of the offset is greater than a first threshold, and the absolute value of the offset is determined to be greater than the first threshold as the variation pattern of the offset. determining whether the time or number of times is greater than a second threshold;
The transmission delay time pattern determination unit determines whether or not the transmission delay time is greater than a third threshold, and determines that the transmission delay time is greater than the third threshold as the variation pattern of the transmission delay time. time synchronizing device for determining whether the time or number of times set is greater than a fourth threshold.
In the time synchronization device according to claim 4,
The failure point determination unit determines that the time or the number of times that the absolute value of the offset is greater than the first threshold is greater than the second threshold, and the transmission delay time is equal to or less than the third threshold. If there is, or if the time or number of times the transmission delay time is determined to be greater than the third threshold is less than the fourth threshold, determining that the location of the failure is the higher-level device; Synchronizer.
A time synchronization method for synchronizing the device internal time of a device with the device internal time of the host device and synchronizing the device internal time of a lower device with the device internal time of the device by transmitting and receiving packets to and from a host device, ,
a step of calculating an offset, which is the difference between the internal device time of the host device and the internal device time of the own device;
a step of calculating a transmission delay time of packets transmitted and received between the host device and its own device;
determining a variation pattern of the offset;
determining a variation pattern of the transmission delay time;
A time synchronization method, comprising: judging a location where a failure occurs in time synchronization with the host device based on the variation pattern of the offset and the variation pattern of the transmission delay time.
A program that causes a computer to operate as the time synchronization device according to any one of claims 1 to 5.