WO2023095299A1

WO2023095299A1 - Reception device, reception synchronization method, control circuit, and storage medium

Info

Publication number: WO2023095299A1
Application number: PCT/JP2021/043442
Authority: WO
Inventors: 亮介中村
Original assignee: 三菱電機株式会社
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2023-06-01
Also published as: JP7378687B2; JPWO2023095299A1

Abstract

This reception device includes: a correlation value calculation unit (241) that uses a matched filter to calculate a total correlation, which is a cross-correlation between a chirp sequence of a sequence length and a reception signal, a sequence latter-half correlation, which is a cross-correlation between the latter half of the chirp sequence and the reception signal, and a sequence first-half correlation, which is a cross-correlation between the first half of the chirp sequence and the reception signal; a power value calculation unit (242) that calculates the total power value corresponding to the total correlation; a threshold value determination unit (245) that estimates a spread code timing on the basis of the total power value for a one block cycle of a spread code; a power value calculation unit (251A) that calculates a latter-half power value corresponding to the sequence latter-half correlation; a power value calculation unit (251B) that calculates a first-half power value corresponding to the sequence first-half correlation; and an estimation unit (254) that estimates a frequency offset amount on the basis of the spread code timing, the total power value for a one block cycle, the latter-half power value for a one block cycle, and the first-half power value for a one block cycle.

Description

Receiver, Reception Synchronization Method, Control Circuit, and Storage Medium

The present disclosure relates to a receiver, a reception synchronization method, a control circuit, and a storage medium that achieve wide-area communication and long-distance communication with low power consumption.

With the spread of IoT (Internet of Things) and M2M (Machine to Machine), LPWA (Low Power Wide Area) is attracting attention as a communication method that achieves wide-area and long-distance communication with low power consumption. LPWA has a problem of co-channel interference because different systems operate on the same frequency. Therefore, in LPWA, it is effective to apply direct sequence spread spectrum (hereinafter referred to as DS-SS (Direct Sequence Spread Spectrum)) communication that can improve interference resistance, jamming resistance, and confidentiality of communication. LoRa (Long Range), which is one of the LPWA communication methods, is a communication method that utilizes chirp spread spectrum using a chirp signal that is a phase rotation sequence with a constant amplitude. LoRa has a low communication speed, but can realize long-distance communication. Chirp signals are commonly used in radar, sonar, and the like. The chirp signal can reduce the PAPR (Peak-to-Average Power Ratio) of the transmitted signal and has excellent autocorrelation characteristics, so it is also suitable for timing detection of the received signal and is used for DS-SS communication. is also valid.

In DS-SS communication, since the receiving device performs despreading, it is necessary to synchronize with the timing at which the spreading code was multiplied by the transmitting device. Since the receiving device performs despreading processing on the signal spread over a wide frequency band before despreading, it is important to perform timing synchronization with high precision at a low SNR (Signal-to-Noise Ratio). . When there is a frequency offset caused by the frequency deviation of local oscillators between transmitting and receiving apparatuses, the Doppler effect, etc., it is observed that the timing is shifted in DS-SS communication using a chirp signal. In an environment where a large frequency offset exists, the performance of synchronization processing and the performance of demodulation processing in the post-synchronization processing by the receiving device are significantly degraded, so frequency synchronization technology is important.

In response to such a problem, Non-Patent Document 1 discloses that a transmission device uses a modified LoRa chirp signal as a preamble, a PCS (Positive-Chirp Signal) in which the frequency linearly increases from a certain start frequency, and a PCS. A technique for transmitting SCS (Symmetry Chirp Signal), which is two symmetric chirp signals of NCS (Negative-Chirp Signal) whose frequency linearly decreases from the same starting frequency, is disclosed. In Non-Patent Document 1, a receiving device estimates the spread code timing of each of the PCS and NCS, and then estimates the frequency offset and the spread code timing using FFT (Fast Fourier Transform). Non-Patent Document 1 assumes a low-data-rate low-orbit satellite IoT, and enables highly accurate synchronization even when there is a large frequency offset due to the Doppler effect.

However, as in Non-Patent Document 1, in order to process a wideband signal before despreading with a synchronization method using FFT, there was a problem that the circuit scale increased and the processing delay also increased.

The present disclosure has been made in view of the above. An object of the present invention is to obtain a receiving device capable of performing estimation with high accuracy.

In order to solve the above-described problems and achieve the object, the receiving device of the present disclosure provides a timing multiplied by a spreading code in a transmitting device based on a received signal having a preamble spectrum-spread by a chirp signal of a chirp sequence. and a frequency offset estimating unit for estimating the amount of frequency offset from the transmitting device based on the spreading code timing. The timing synchronization unit has overall correlation, which is the cross-correlation between the chirp sequence for the length of the sequence and the received signal, and second-half sequence correlation, which is the cross-correlation between the received signal and the second half of the sequence, which is a continuous sequence including the second half of the chirp sequence. and the first half of the sequence, which is a continuous sequence including the first half of the chirp sequence, and the first half of the sequence correlation, which is the cross-correlation between the received signal and the first half of the sequence, using a matched filter, and the power corresponding to the overall correlation. and a total power value calculation unit for calculating a total power value that is a value. Also, the timing synchronization unit includes an overall correlation power memory that stores the overall power value of each sample timing for one block period of the spreading code, and a determination unit that estimates the spreading code timing based on the overall power value for one block period. and have The frequency offset estimator includes a second half power value calculator that calculates a second half power value that is a power value corresponding to the sequence second half correlation, and a second half correlation power that stores the second half power value of each sampling timing for one block period of the spreading code. a memory; The frequency offset estimator includes a first half power value calculator that calculates a first half power value that is a power value corresponding to sequence first half correlation, and a first half power value calculator that stores the first half power value of each sampling timing for one block period of the spreading code. Estimation for estimating frequency offset amount based on correlation power memory, spreading code timing, total power value for one block period, second half power value for one block period, and first half power value for one block period and

The receiving device according to the present disclosure suppresses processing delay while suppressing an increase in circuit scale, and performs highly accurate spread code timing estimation and frequency offset estimation even in an environment where a large frequency offset exists. It has the effect of being able to

FIG. 1 shows a configuration example of a transmission device included in a communication system according to an embodiment; Flowchart showing the operation of the transmission device according to the embodiment FIG. 4 is a diagram showing an example of a signal framed by the transmitting device according to the embodiment; FIG. 1 shows a configuration example of a receiving device included in a communication system according to an embodiment; Flowchart showing the operation of the receiving device according to the embodiment FIG. 4 shows a configuration example of a timing synchronization section and a frequency offset estimation section included in a receiving apparatus according to an embodiment; Flowchart showing the operation of the timing synchronizer included in the receiver according to the embodiment FIG. 4 is a diagram showing an image of threshold setting in the threshold determination unit of the receiving device according to the embodiment; Flowchart showing the operation of the frequency offset estimator included in the receiver according to the embodiment A diagram showing the relationship between time and frequency in the global correlation A diagram showing the relationship between time and frequency in the partial correlation of the second half of the sequence Diagram showing the relationship between time and frequency in the partial correlation of the first half of the sequence FIG. 4 is a diagram showing a configuration example of a processing circuit provided in a receiving apparatus according to an embodiment when the processing circuit is implemented by a processor and a memory; FIG. 10 is a diagram showing an example of a processing circuit provided in a receiving apparatus according to an embodiment when the processing circuit is composed of dedicated hardware;

The receiving device, reception synchronization method, control circuit, and storage medium according to the embodiments of the present disclosure will be described below in detail with reference to the drawings.

Embodiment.
FIG. 1 is a diagram illustrating a configuration example of a transmission device included in a communication system according to an embodiment. The communication system is a system that performs LPWA communication, which is low power consumption long distance communication. The communication system includes a transmitting device 1 and a receiving device 2 which will be described later.

First, the configuration and operation of the transmission device 1 will be described. The transmitter 1 includes a modulator 11, a chirp spreader 12, a preamble generator 13, a frame generator 14, a transmission filter 15, and a transmission antenna 16, as shown in FIG. FIG. 2 is a flow chart showing the operation of the transmission device according to the embodiment.

The modulation unit 11 modulates information bits consisting of 0 and 1 (step S101). The modulation unit 11 can use, for example, PSK (Phase Shift Keying), FSK (Frequency Shift Keying), etc. as a modulation method. Modulation section 11 outputs the modulated signal to chirp spreading section 12 .

The chirp spreader 12 spreads the spectrum of the modulated signal obtained from the modulator 11 using a chirp signal (step S102). The chirp spreading section 12 can use, for example, a Zadoff-Chu sequence as a sequence used for spectrum spreading. When the sequence length N _c is an even number, the t-th element C(t) of the Zadoff-Chu sequence C is represented by Equation (1) below.

C(t)=exp{jπ(Mt ² -N _c t/2)/N _c } (1)

In Equation (1), M is a series parameter and is coprime to N _c . Also, M is the number of increases from the minimum frequency fmin to the maximum frequency fmax in the sequence length _Nc . When M=1, the frequency increases once from the minimum frequency fmin to the maximum frequency fmax in the sequence length _Nc . When M=2, after the frequency increases from the minimum frequency fmin to the maximum frequency fmax in the first half N _c /2 of the sequence length N _c , the frequency increases from the minimum frequency fmin to the maximum frequency in the second half N _c /2 of the sequence length N _c . The frequency increases up to frequency fmax. That is, when M=2, the frequency increases twice from the minimum frequency fmin to the maximum frequency fmax in the sequence length _Nc . Hereinafter, an example when M=1 will be described, but the value of M is not limited.

The chirp spreading section 12 outputs data generated by spectrum-spreading the modulated signal to the frame generating section 14 . In the following description, the data generated by the chirp spreading section 12 may be called a data block.

The preamble generation unit 13 spectrum-spreads the known signal using a chirp signal. That is, the preamble generator 13 performs spectrum spreading on the known signal to generate a preamble (step S103).

The preamble generation unit 13 outputs the preamble generated by spreading the spectrum to the frame generation unit 14 . In the following description, the preamble generated by the preamble generator 13 may be referred to as a preamble block.

The frame generation unit 14 frames the data block generated by spectrum spreading by the chirp spreading unit 12 and the preamble block generated by spectrum spreading by the preamble generation unit 13 (step S104).

FIG. 3 is a diagram showing an example of a signal framed by the transmission device according to the embodiment. The signal framed by the frame generator 14 has a preamble block in the front stage and a data block in the rear stage. The frame generator 14 outputs the framed signal to the transmission filter 15 .

The transmission filter 15 band-limits the signal framed by the frame generator 14 (step S105). The transmission filter 15 outputs the band-limited spread signal to the transmission antenna 16 .

The transmission antenna 16 transmits the band-limited signal obtained from the transmission filter 15 (step S106).

Next, the configuration and operation of the receiving device 2 will be described. FIG. 4 is a diagram illustrating a configuration example of a receiving device included in the communication system according to the embodiment. The receiving device 2 is a device that performs highly accurate spread code timing estimation and frequency offset estimation with a simple configuration using a single matched filter. The receiving device 2 includes a receiving antenna 21, a frequency offset correction unit 22, a reception filter unit 23, a timing synchronization unit 24, a frequency offset estimation unit 25, a spreading code generation unit 26, a despreading unit 27, and a demodulation unit. a portion 28; FIG. 5 is a flow chart showing the operation of the receiving device according to the embodiment.

The receiving antenna 21 receives the signal transmitted from the transmitting device 1 (step S201). A signal received by the receiving antenna 21, that is, a received signal is a signal transmitted from the transmitting apparatus 1 and having a preamble spread by a chirp signal. The receiving antenna 21 outputs the received signal to the frequency offset correction section 22 .

The frequency offset correction unit 22 corrects the frequency offset of the received signal according to the frequency offset estimation value calculated by the frequency offset estimation unit 25 (step S202). That is, the frequency offset correction unit 22 corrects the frequency offset of the reception signal acquired from the reception antenna 21 with the frequency offset estimation value.

Note that the frequency offset correction unit 22 corrects the frequency offset by feedback after the frequency offset is estimated, so the frequency offset is not corrected when the preamble first passes through. The frequency offset correction unit 22 outputs the received signal after correcting the frequency offset to the reception filter unit 23 .

The reception filter unit 23 performs filter processing using a band-limiting filter on the reception signal acquired from the frequency offset correction unit 22 (step S203). Reception filter section 23 outputs the filtered signal to timing synchronization section 24 and despreading section 27 . In the following description, the signal after receive filter processing may be referred to as a receive filter passing signal.

The timing synchronization unit 24 performs timing synchronization based on the reception filter passing signal acquired from the reception filter unit 23 (step S204). Specifically, the timing synchronization unit 24 synchronizes the timing multiplied by the spreading code in the transmission device 1 in the timing synchronization. That is, the timing synchronization unit 24 estimates the spreading code timing, which is the timing multiplied by the spreading code. The process of estimating the spreading code timing by the timing synchronization unit 24 is timing synchronization. In this way, the timing synchronization unit 24 estimates the spreading code timing, which is the timing multiplied by the spreading code in the transmitting apparatus 1, based on the received signal having the preamble spectrum-spread by the chirp signal of the chirp sequence.

The timing synchronization unit 24 outputs the estimated spread code timing to the frequency offset estimation unit 25 and the spread code generation unit 26 as spread code estimation timing. In addition, the timing synchronization unit 24 outputs calculation information during synchronization processing of timing synchronization to the frequency offset estimation unit 25 as intermediate calculation information. The detailed configuration and operation of the timing synchronizer 24 will be described later.

The frequency offset estimation unit 25 estimates the frequency offset amount (frequency offset estimation value) with the transmission device 1 based on the spreading code timing and the intermediate calculation information acquired from the timing synchronization unit 24 (step S205).

The frequency offset estimation unit 25 feeds back a frequency offset estimation value indicating the estimated frequency offset amount to the frequency offset correction unit 22 . A detailed configuration and operation of the frequency offset estimator 25 will be described later.

The spreading code generation unit 26 generates a spreading code for despreading based on the spreading code timing acquired from the timing synchronization unit 24 . The spreading code generation unit 26 outputs the generated spreading code to the despreading unit 27 .

The spreading code generation unit 26 generates a spreading code for despreading based on the spreading code estimation timing acquired from the timing synchronization unit 24 (step S206). The spreading code generation unit 26 outputs the generated spreading code to the despreading unit 27 .

The despreading section 27 acquires the reception filter passing signal from the reception filter section 23 and acquires the spreading code from the spreading code generation section 26 . The despreading unit 27 despreads the reception filter-passed signal by multiplying the reception filter-passed signal by the complex conjugate of the spreading code (step S207). The despreading section 27 outputs the despread signal to the demodulating section 28 .

The demodulator 28 demodulates the signal acquired from the despreader 27, that is, the signal whose frequency offset has been corrected (step S208).

Next, the configurations and operations of the timing synchronization section 24 and the frequency offset estimation section 25 included in the receiving device 2 will be described in detail. FIG. 6 is a diagram showing a configuration example of a timing synchronization section and a frequency offset estimation section included in the receiving apparatus according to the embodiment. The timing synchronization unit 24 has a correlation value calculation unit 241 , a power value calculation unit 242 , an averaging processing unit 243 , a correlation power memory unit 244 and a threshold determination unit 245 . The averaging processor 243 is the overall averaging processor.

FIG. 7 is a flow chart showing the operation of the timing synchronization section of the receiving device according to the embodiment. Correlation value calculator 241 acquires the reception filter passing signal from reception filter 23 . Correlation value calculator 241 also stores a chirp signal of a chirp sequence that preamble generator 13 uses for spectrum spreading.

Correlation value calculator 241 multiplies the received filter-passed signal by the complex conjugate of the chirp signal using a matched filter, and calculates the cross-correlation function between the received filter-passed signal and the chirp sequence. That is, the correlation value calculator 241 uses a single matched filter to calculate the cross-correlation function between the received filter passing signal and the chirp sequence used for spectrum spreading by the preamble generator 13 (step S301). At this time, the correlation value calculation unit 241 outputs the calculation result of the total correlation for the sequence length _Nc of the chirp sequence to the power value calculation unit 242 in the subsequent stage. Further, the correlation value calculator 241 sets an arbitrary value L to the frequency offset estimator 25 when the sequence number is 0 to _Nc - ₁ for the sequence length Nc of the chirp sequence. , the cross-correlation for the sequence numbers L to N _c -1 and the cross-correlation for the sequence numbers 0 to N _c -L.

In this way, the correlation value calculator 241 uses a matched filter to calculate the overall correlation, which is the cross-correlation between the chirp sequence of sequence length _Nc and the received signal (received filter-passed signal). Correlation value calculation section 241 also uses a matched filter to calculate the late-sequence correlation, which is the cross-correlation between the received signal and the second half of the sequence, which is a continuous sequence including the second half of the chirp sequence. Correlation value calculation section 241 also uses a matched filter to calculate the first half sequence correlation, which is the cross-correlation between the first half of the sequence, which is a continuous sequence including the first half of the chirp sequence, and the received signal.

The power value calculation unit 242 calculates the total power value, which is the power value corresponding to the total correlation. Specifically, the power value calculator 242 squares the absolute value of the cross-correlation function obtained from the correlation value calculator 241 to calculate the power value (step S302). The power value calculator 242 is the total power value calculator. The power value calculator 242 outputs the calculated power value to the averaging processor 243 .

The averaging processor 243 averages the power values acquired from the power value calculator 242 at each sample timing. Specifically, the averaging processing unit 243 performs averaging using the power value acquired from the power value calculation unit 242 and the power value acquired from the power value calculation unit 242 at the same sample timing of the previous block ( step S303). In this embodiment, one block is composed of the spreading code length N _c ×over-sampling number N _ovs , and the sample timing is one element of k=1 to N _c ×N _ovs . The averaging processor 243 causes the correlation power memory 244 to store the power values averaged at each sample timing.

The correlation power memory unit 244 is configured to store the total power value of each sample timing for one block period of the spreading code, that is, the power value of the number corresponding to the spreading code length N _c ×oversampling number N _ovs . there is The correlation power memory unit 244 stores the power sample average value, which is the power value after averaging acquired from the averaging processing unit 243, over the spreading code length N _c ×oversampling number N _ovs (one block period) (step S304). The power sample average value for one block period is the total power value for one block period, and the correlation power memory unit 244 is the total correlation power memory.

The processing up to the averaging processing unit 243 was performed in units of sample time, but the processing after the correlation power memory unit 244 is changed to operation in units of block time. The correlation power memory unit 244 outputs the power sample average value for one block period to the subsequent threshold determination unit 245 and the frequency offset estimation unit 25 .

The threshold determination unit 245 estimates the spreading code timing based on the total power value for one block period. Specifically, the threshold determination unit 245 detects the maximum power sample average value among the power sample average values for one block period acquired from the correlation power memory unit 244, and uses the detected maximum power sample average value. A certain maximum power value is compared with a threshold value (step S305). When the maximum power value exceeds the threshold value, the threshold determination section 245 outputs the spread code estimation timing corresponding to the maximum power value to the frequency offset estimation section 25 and the spread code generation section 26 .

The threshold determination unit 245 uses the following method as a threshold determination method. The threshold determination unit 245 calculates the average value of the power sample average values for one block period (hereinafter referred to as the power block average value) acquired from the correlation power memory unit 244, and calculates the constant α ( 1≦α) times is set as the threshold value. The power block average value is a value obtained by further averaging the power sample average values at each sample timing for one block period.

FIG. 8 is a diagram showing an image of threshold setting in the threshold determining unit of the receiving device according to the embodiment. In FIG. 8, the horizontal axis indicates the sample timing, and the vertical axis indicates the power sample average value. As shown in FIG. 8, the threshold determination unit 245 can reduce false alarms that establish an erroneous synchronization point as the value of the constant α is set larger, but it takes time to detect the timing. On the other hand, as the value of the constant α is set smaller, the threshold determination unit 245 can shorten the timing detection time, but false alarms increase.

Next, the configuration and operation of the frequency offset estimation unit 25 will be described in detail. The frequency offset estimation unit 25 includes power value calculation units 251A and 251B, averaging processing units 252A and 252B, correlation power memory units 253A and 253B, and an estimation unit 254, as shown in FIG. The averaging processing unit 252A is the second half averaging processing unit, and the averaging processing unit 252B is the first half averaging processing unit.

FIG. 9 is a flowchart showing the operation of the frequency offset estimator included in the receiving device according to the embodiment. Power value calculators 251A and 251B acquire partial correlations from correlation value calculator 241 . That is, power value calculation section 251A acquires the partial correlation of the second half of the sequence (second half sequence correlation) from correlation value calculation section 241, and power value calculation section 251B obtains the partial correlation of the first half of the sequence (first half of sequence correlation). The partial correlation of the second half of the series and the partial correlation of the first half of the series are intermediate calculation information. Receiving apparatus 2 obtains the value of the partial correlation of the second half of the sequence and the value of the partial correlation of the first half of the sequence as the intermediate computation information, thereby eliminating the need to provide a separate correlator, thereby reducing the amount of computation.

The power value calculator 251A calculates the power value of the partial correlation in the second half of the sequence (step S401a), and the power value calculator 251B calculates the power value of the partial correlation in the first half of the sequence (step S401b). That is, power value calculation section 251A calculates a second half power value corresponding to the second half sequence correlation, and power value calculation section 251B calculates a first half power value corresponding to the first half sequence correlation. The power value calculator 251A is the latter half power value calculator, and the power value calculator 251B is the first half power value calculator.

The calculations performed by the power value calculation units 251A and 251B to obtain the power values are the same as the calculations performed by the power value calculation unit 242 to obtain the power values. The power value calculator 251A outputs the calculated power value to the averaging processor 252A, and the power value calculator 251B outputs the calculated power value to the averaging processor 252B.

The averaging processing unit 252A averages the power values sent from the power value calculating unit 251A (step S402a), and the averaging processing unit 252B averages the power values sent from the power value calculating unit 251B. conversion is performed (step S402b). The calculations when the averaging processing units 252A and 252B execute the averaging processing are the same as the calculations when the averaging processing unit 243 executes the averaging processing. Averaging processing section 252A outputs the averaged power value to correlation power memory section 253A, and averaging processing section 252B outputs the averaged power value to correlation power memory section 253B.

The correlation power memory units 253A and 253B are memories that store power average values sent from the averaging processing units 252A and 252B. The correlation power memory unit 253A stores the power average value sent from the averaging processing unit 252A over one block period (step S403a). The correlation power memory unit 253B stores the power average value sent from the averaging processing unit 252B over one block period (step S403b).

In this way, the correlation power memory unit 253A stores the power value in the second half of each sampling timing for one block period of the spreading code, and the correlation power memory unit 253B stores the power value in the first half of each sampling timing for one block period of the spreading code. Store the power value. Correlation power memory section 253A is the latter half power value calculation section, and correlation power memory section 253B is the first half power value calculation section.

The processing when the correlation power memory units 253A and 253B store the power average values is the same as the processing when the correlation power memory unit 244 stores the power sample average values. Correlation power memory units 253A and 253B output average power values to estimation unit 254 .

The estimation unit 254 acquires the spread code estimation timing from the threshold determination unit 245 and acquires the power sample average value for one block period from the correlation power memory unit 244 . Estimating section 254 also acquires the power average value of the partial correlation of the second half of the sequence from correlation power memory section 253A, and acquires the power average value of the partial correlation of the first half of the sequence from correlation power memory section 253B.

At the timing of estimating the spreading code, the estimating unit 254 obtains the power average value (power sample average value) of the overall correlation for the sequence (chirp sequence) obtained from the correlation power memory units 244, 253A, and 253B, and the two types of cross-correlations. A frequency offset estimate is estimated based on the power average value, that is, the three types of power average values (step S404).

In this way, the estimator 254 calculates the frequency offset based on the spreading code estimation timing, the total power value for one block period, the power value for the latter half of one block period, and the power value for the first half of one block period. Estimate an estimate. That is, the estimator 254 estimates the frequency offset amount from the power ratio between the total correlation and the partial correlation of the matched filter.

If the partial correlation corresponding to the second half of the chirp sequence is greater than the partial correlation corresponding to the first half of the chirp sequence, the estimating unit 254 estimates the frequency offset using the following equation (2) as the positive frequency offset. Estimate a value.

(Frequency offset estimate)=N _c −(N _c −L)×(square root of average power sample value of overall correlation)/(square root of average power value of partial correlation in latter half of sequence) (2)

In addition, when the partial correlation corresponding to the first half of the chirp sequence is greater than the partial correlation corresponding to the second half of the chirp sequence, estimating section 254 uses the following equation (3) as the frequency offset in the negative direction to determine the frequency Estimate the offset estimate.

(Frequency offset estimate)=(−1)×{N _c −(N _c −L+1)×(square root of power sample mean value of total correlation)/(square root of power mean value of partial correlation in first half of sequence)}・(3)

Note that when the partial correlation corresponding to the first half of the chirp sequence and the partial correlation corresponding to the second half of the chirp sequence have the same magnitude, the estimating unit 254 uses either formula (2) or formula (3) described above. may be used to estimate the frequency offset estimate.

The reason why the estimating unit 254 can accurately estimate the frequency offset estimated value by using the above equations (2) and (3) will be described with reference to FIGS. 10 to 12. FIG.

FIG. 10 is a diagram showing the relationship between time and frequency in the overall correlation. FIG. 11 is a diagram showing the relationship between time and frequency in the partial correlation of the latter half of the sequence, and FIG. 12 is a diagram showing the relationship between time and frequency in the partial correlation of the first half of the sequence. The horizontal axis of the graphs shown in FIGS. 10 to 12 is time, and the vertical axis is frequency.

As shown in FIG. 10, the global correlation varies in frequency from -N _c /2 to N _c /2-1 while time varies from 0 to N _c -1. That is, in the total correlation, the frequency is -N _c /2 when the time is 0, the frequency increases in proportion to the passage of time, and the frequency is N _c /2-1 when the time is N _c -1. Become.

As shown in FIG. 11, in the partial correlation of the second half of the sequence, the frequency changes from -N _c /2+L to N _{c /2-1 while the time changes from L to N c} _-1 . That is, in the partial correlation (second half), the frequency is −N _c /2+L when the time is L, the frequency increases in proportion to the passage of time, and the frequency is N _c /2 when the time is N _c −1. -1.

As shown in FIG. 12, in the partial correlation of the first half of the sequence, the frequency changes from -N _c /2 to N _c /2-L while the time changes from 0 to N _c -L. That is, in the partial correlation (first half), the frequency is −N _c /2 when the time is 0, the frequency increases in proportion to the passage of time, and the frequency is N _c /2 when the time is N _c −L. -L.

Here, if the frequency offset is a positive value A (1<A<L), the waveform shifts in the positive frequency direction as a whole, so the preamble of the received signal is −N _c /2+A to N It changes by _c /2-1. Values greater than N _c /2−1 are cut off by the bandlimiting filter and are therefore not present during synchronization. In this case, the power value obtained by the overall correlation in FIG _. 10 corresponds to the range that overlaps with the frequency components after passing through the filter described above, so the overall correlation in _FIG . , that is, a power value corresponding to the length N _c −A is obtained.

In the partial correlation (second half) of FIG. 11, when A<L, a power value corresponding to the length N _c −L is obtained without being affected by the frequency offset. In the partial correlation (first half) of FIG. 12, the power attenuation corresponding to the frequency offset A gives a power value corresponding to the length N _c -L+1-A. Therefore, since the power value of the partial correlation (second half) is larger than the power value of the partial correlation (first half), it is found that there is a positive frequency offset. The frequency offset estimation value can be obtained from each power value in the second half).

As described above, in the present embodiment, the preamble generator 13 of the transmission device 1 performs chirp spreading with the preamble. Then, the timing synchronization unit 24 of the receiving device 2 calculates the total correlation and the partial correlation by the matched filter of the chirp spreading code. Furthermore, the estimator 254 estimates the frequency offset estimated value using the overall correlation and the partial correlation at the timing estimated from the overall correlation by the timing synchronization unit 24 .

The sequence used in this embodiment is not limited to the M=1 Zadoff-Chu sequence according to equation (1) used by chirp spreading section 12 and preamble generating section 13 of transmitting apparatus 1 . Also, transmitting apparatus 1 may shift the center frequency, and may use other chirp sequences such as CAZAC sequences as spreading codes. In this case as well, the transmitting apparatus 1 can estimate the frequency offset by using a sequence in which the frequency linearly increases and decreases.

Also, in the present embodiment, the timing synchronization unit 24 of the receiving device 2 performs averaging using the power values of the same sample timing of the previous block, but the averaging process is not limited to this. The timing synchronization unit 24 may perform averaging at the same sample timing for all preamble blocks subjected to the same chirp spreading.

As described above, the receiving device 2 calculates the cross-correlation function between the reception filter-passed signal and the chirp sequence used for spectrum spreading. Further, the receiving device 2 calculates the cross-correlation power value, and averages the power value at the same sample timing for each block. The receiving device 2 compares each result after averaging with a threshold, and detects the timing at which the maximum power value of the chirp signal is obtained as the timing for estimating the spreading code.

Also, the receiving device 2 uses a matched filter to find the overall correlation for correlating the length of the chirp sequence and the partial correlation for correlating a part of the sequence. At the timing of estimating the spreading code, the receiver 2 estimates the frequency offset amount from the power ratio of the total correlation and the partial correlation of the matched filter, and corrects the frequency offset for the received signal before passing through the reception filter. As a result, the receiver 2 re-estimates the spreading code timing for the frequency offset-corrected signal, and demodulates the data other than the preamble signal.

As a result, the receiving device 2 can estimate the spread code timing and the frequency offset amount with high accuracy with a simple configuration using a matched filter.

Next, the hardware configuration of the receiving device 2 will be explained. In the receiving device 2, the receiving antenna 21 is realized by an antenna device. The reception filter unit 23 is realized by a filter circuit. The frequency offset corrector 22, the timing synchronizer 24, the frequency offset estimator 25, the spreading code generator 26, the despreader 27, and the demodulator 28 are each implemented by a processing circuit. These processing circuits may be processors and memories that execute programs stored in the memory, or may be dedicated hardware. Processing circuitry is also called control circuitry.

FIG. 13 is a diagram showing a configuration example of a processing circuit when the processing circuit included in the receiving device according to the embodiment is realized by a processor and memory. A processing circuit 90 shown in FIG. 13 is a control circuit and includes a processor 91 and a memory 92 . When the processing circuit 90 is composed of the processor 91 and the memory 92, each function of the processing circuit 90 is implemented by software, firmware, or a combination of software and firmware. Software or firmware is written as a program and stored in memory 92 . In the processing circuit 90, each function is realized by the processor 91 reading and executing the program stored in the memory 92. FIG. That is, the processing circuitry 90 includes a memory 92 for storing programs that result in the processing of the receiving device 2 being executed. This program can also be said to be a program for causing the receiving device 2 to execute each function realized by the processing circuit 90 . This program may be provided by a storage medium storing the program, or may be provided by other means such as a communication medium.

Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor). In addition, the memory 92 is a non-volatile or volatile memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), etc. A semiconductor memory, a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, or a DVD (Digital Versatile Disc) corresponds to this.

FIG. 14 is a diagram showing an example of a processing circuit when the processing circuit included in the receiving device according to the embodiment is configured with dedicated hardware. The processing circuit 93 shown in FIG. 14 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination of these thing applies. The processing circuit may be partly implemented by dedicated hardware and partly implemented by software or firmware. Thus, the processing circuitry may implement each of the functions described above through dedicated hardware, software, firmware, or a combination thereof.

Note that the frequency offset correction unit 22, the timing synchronization unit 24, the frequency offset estimation unit 25, the spreading code generation unit 26, the despreading unit 27, and the demodulation unit 28 may each be configured by separate processing circuits. Also, although the hardware configuration of the receiving device 2 has been described here, the hardware configuration of the transmitting device 1 is the same as that of the receiving device 2 .

As described above, according to the embodiment, the receiving apparatus 2 uses the spread code timing, the total power value for one block period, the second half power value for one block period, and the first half power value for one block period. Based on, the frequency offset amount is estimated. Therefore, the receiving device 2 can suppress processing delay while suppressing an increase in circuit size, and can perform highly accurate estimation of the spreading code timing and the frequency offset even in an environment where a large frequency offset exists. can.

The configuration shown in the above embodiment is an example, and can be combined with another known technique, and part of the configuration can be omitted or changed without departing from the scope of the invention. It is possible.

1 transmission device, 2 reception device, 11 modulation unit, 12 chirp spreading unit, 13 preamble generation unit, 14 frame generation unit, 15 transmission filter, 16 transmission antenna, 21 reception antenna, 22 frequency offset correction unit, 23 reception filter unit, 24 timing synchronization unit, 25 frequency offset estimation unit, 26 spreading code generation unit, 27 despreading unit, 28 demodulation unit, 90, 93 processing circuit, 91 processor, 92 memory, 241 correlation value calculation unit, 242, 251A, 251B power Value calculation unit, 243, 252A, 252B Average processing unit, 244, 253A, 253B Correlation power memory unit, 245 Threshold determination unit, 254 Estimation unit.

Claims

a timing synchronization unit for estimating a spreading code timing, which is a timing at which a spreading code is multiplied by a transmitting device, based on a received signal having a preamble spectrum-spread by a chirp signal of a chirp sequence;
a frequency offset estimating unit that estimates a frequency offset amount with respect to the transmitting device based on the spreading code timing;
with
The timing synchronization unit
total correlation, which is the cross-correlation between the chirp sequence for the length of the sequence and the received signal; and late-sequence correlation, which is the cross-correlation between the received signal and the latter half of the sequence, which is a continuous sequence including the latter part of the chirp sequence. a correlation value calculator that calculates, using a matched filter, a sequence first half correlation that is a cross-correlation between the sequence first half, which is a continuous sequence including the first half of the chirp sequence, and the received signal;
an overall power value calculator that calculates an overall power value that is a power value corresponding to the overall correlation;
an overall correlation power memory for storing the overall power value at each sample timing for one block period of the spreading code;
a determination unit that estimates the spreading code timing based on the total power value for the one block period;
has
The frequency offset estimator,
a second half power value calculation unit that calculates a second half power value that is a power value corresponding to the sequence second half correlation;
a second half correlation power memory that stores the second half power value of each sample timing for the one block period of the spreading code;
a first-half power value calculator that calculates a first-half power value that is a power value corresponding to the series first-half correlation;
a first half correlation power memory that stores the first half power value of each sample timing for the one block period of the spreading code;
The frequency offset amount is calculated based on the spreading code timing, the total power value for one block period, the second half power value for one block period, and the first half power value for one block period. an estimating unit for estimating;
has a
A receiving device characterized by:
The timing synchronization unit
further comprising an overall averaging processing unit that averages the overall power values at each sample timing for the one block period and stores the averaged overall power values in the overall correlation power memory;
The determination unit estimates the spreading code timing based on the averaged overall power value.
2. The receiving apparatus according to claim 1, characterized by:
The frequency offset estimator,
a second-half averaging processor that averages the second-half power values at each sample timing for the one block period and stores the averaged second-half power values in the second-half correlation power memory;
a first-half averaging processing unit that averages the first-half power values at each sample timing for the one block period and stores the averaged first-half power values in the first-half correlation power memory;
further having
The estimation unit
estimating the frequency offset amount based on the averaged overall power value, the averaged second half power value, and the averaged first half power value;
3. The receiving apparatus according to claim 2, characterized by:
The determination unit is
detecting a maximum of the averaged total power values; generating a threshold from the averaged total power values; and based on comparing the maximum of the total power values to the threshold, the diffusion estimating code timing,
3. The receiving apparatus according to claim 2, characterized by:
A receiving synchronization method for a receiving device, comprising:
a first step in which a timing synchronization unit estimates a spreading code timing, which is a timing multiplied by a spreading code in a transmitting device, based on a received signal having a preamble spectrum-spread by a chirp signal of a chirp sequence;
a second step in which a frequency offset estimator estimates a frequency offset amount with respect to the transmitting device based on the spreading code timing;
including
The first step includes
The timing synchronization unit performs overall correlation, which is a cross-correlation between the chirp sequence for a sequence length and the received signal, and cross-correlation between the received signal and the last half of a sequence, which is a continuous sequence including the second half of the chirp sequence. and a first half sequence correlation that is cross-correlation between the received signal and the first half sequence, which is a continuous sequence including the first half of the chirp sequence, using a matched filter. ,
an overall power value calculation step in which the timing synchronization unit calculates an overall power value that is a power value corresponding to the overall correlation;
an overall correlation power storage step in which the timing synchronization unit stores the overall power value of each sample timing for one block period of the spreading code;
a determination step in which the timing synchronization unit estimates the spreading code timing based on the total power value for the one block period;
has
The second step includes
a second half power value calculation step in which the frequency offset estimator calculates a second half power value that is a power value corresponding to the series second half correlation;
a second half correlation power storage step in which the frequency offset estimation unit stores the second half power value of each sample timing for the one block period of the spreading code;
a first half power value calculation step in which the frequency offset estimator calculates a first half power value that is a power value corresponding to the series first half correlation;
a first half correlation power storage step in which the frequency offset estimation unit stores the first half power value of each sample timing for the one block period of the spreading code;
the frequency offset estimating unit based on the spreading code timing, the total power value for one block period, the second half power value for one block period, and the first half power value for one block period; an estimation step of estimating the frequency offset amount;
having
A reception synchronization method characterized by:
A control circuit for controlling a receiving device,
a first process of estimating a spreading code timing, which is a timing at which a spreading code is multiplied by a transmitting device, based on a received signal having a preamble spectrum-spread by a chirp signal of a chirp sequence;
a second process of estimating a frequency offset amount with respect to the transmitting apparatus based on the spreading code timing;
causing the receiving device to perform
In the first process,
total correlation, which is the cross-correlation between the chirp sequence for the length of the sequence and the received signal; and late-sequence correlation, which is the cross-correlation between the received signal and the latter half of the sequence, which is a continuous sequence including the latter part of the chirp sequence. , a correlation value calculation process of calculating, using a matched filter, a sequence first half correlation, which is a cross-correlation between the sequence first half, which is a continuous sequence including the first half of the chirp sequence, and the received signal;
an overall power value calculation process for calculating an overall power value that is a power value corresponding to the overall correlation;
an overall correlation storage process of storing the overall power value at each sample timing for one block period of the spreading code;
a determination process of estimating the spreading code timing based on the total power value for the one block period;
causing the receiving device to perform
In the second processing,
a second half power value calculation process for calculating a second half power value that is a power value corresponding to the series second half correlation;
a second half correlation power storage process of storing the second half power value of each sample timing for the one block period of the spreading code;
a first half power value calculation process for calculating a first half power value that is a power value corresponding to the series first half correlation;
a first half correlation power storage process of storing the first half power value of each sample timing for the one block period of the spreading code;
The frequency offset amount is calculated based on the spreading code timing, the total power value for one block period, the second half power value for one block period, and the first half power value for one block period. an estimation process to estimate;
causing the receiving device to perform
A control circuit characterized by:
A storage medium storing a program for controlling a control circuit for controlling a receiving device,
Said program
A control circuit for controlling a receiving device,
a first process of estimating a spreading code timing, which is a timing at which a spreading code is multiplied by a transmitting device, based on a received signal having a preamble spectrum-spread by a chirp signal of a chirp sequence;
a second process of estimating a frequency offset amount with respect to the transmitting apparatus based on the spreading code timing;
causing the receiving device to perform
In the first process,
total correlation, which is the cross-correlation between the chirp sequence for the length of the sequence and the received signal; and late-sequence correlation, which is the cross-correlation between the received signal and the latter half of the sequence, which is a continuous sequence including the latter part of the chirp sequence. , a correlation value calculation process of calculating, using a matched filter, a sequence first half correlation, which is a cross-correlation between the sequence first half, which is a continuous sequence including the first half of the chirp sequence, and the received signal;
an overall power value calculation process for calculating an overall power value that is a power value corresponding to the overall correlation;
an overall correlation storage process of storing the overall power value at each sample timing for one block period of the spreading code;
a determination process of estimating the spreading code timing based on the total power value for the one block period;
causing the receiving device to perform
In the second processing,
a second half power value calculation process for calculating a second half power value that is a power value corresponding to the series second half correlation;
a second half correlation power storage process of storing the second half power value of each sample timing for the one block period of the spreading code;
a first half power value calculation process for calculating a first half power value that is a power value corresponding to the sequence first half correlation;
a first half correlation power storage process of storing the first half power value of each sample timing for the one block period of the spreading code;
The frequency offset amount is calculated based on the spreading code timing, the total power value for one block period, the second half power value for one block period, and the first half power value for one block period. an estimation process to estimate;
causing the receiving device to perform
A storage medium characterized by: