WO2023092819A1 - Fin semiconductor device and preparation method therefor - Google Patents

Fin semiconductor device and preparation method therefor Download PDF

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WO2023092819A1
WO2023092819A1 PCT/CN2021/143858 CN2021143858W WO2023092819A1 WO 2023092819 A1 WO2023092819 A1 WO 2023092819A1 CN 2021143858 W CN2021143858 W CN 2021143858W WO 2023092819 A1 WO2023092819 A1 WO 2023092819A1
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structures
layer
cavity
multiplication
electrode
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PCT/CN2021/143858
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French (fr)
Chinese (zh)
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康晓旭
蒋宾
陈寿面
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上海集成电路研发中心有限公司
上海集成电路装备材料产业创新中心有限公司
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Priority claimed from CN202111410534.8A external-priority patent/CN114093742B/en
Priority claimed from CN202111410349.9A external-priority patent/CN114093741B/en
Priority claimed from CN202111410564.9A external-priority patent/CN114093743B/en
Application filed by 上海集成电路研发中心有限公司, 上海集成电路装备材料产业创新中心有限公司 filed Critical 上海集成电路研发中心有限公司
Publication of WO2023092819A1 publication Critical patent/WO2023092819A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J43/00Secondary-emission tubes; Electron-multiplier tubes
    • H01J43/04Electron multipliers
    • H01J43/06Electrode arrangements
    • H01J43/18Electrode arrangements using essentially more than one dynode
    • H01J43/24Dynodes having potential gradient along their surfaces

Abstract

Provided in the present invention is a photosensitive sensor, comprising a top electrode, an isolation layer, a bottom electrode, several conductive structures, a support structure, and a multiplication structure array; each multiplication structure is inclined relative to the top electrode and is correspondingly and electrically connected to the conductive structure, such that several accelerating cavity structures are formed between the top electrode and the isolation layer; and an opening facing the top electrode is formed at the top of each accelerating cavity structure, and an emergent through hole is formed at the bottom of each accelerating cavity structure, the emergent through hole being opposite the bottom electrode, and photoelectrons being incident to the accelerating cavity structure, and being formed into secondary photoelectrons through acceleration and multiplication, so as to form amplified signals.

Description

鳍式半导体器件及其制备方法Fin-type semiconductor device and manufacturing method thereof
交叉引用cross reference
本申请要求2021年11月25日提交的申请号为202111410534.8、202111410564.9、202111410349.9的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。This application claims the priority of the Chinese patent applications with application numbers 202111410534.8, 202111410564.9 and 202111410349.9 filed on November 25, 2021. The content of the above application is incorporated herein by reference.
技术领域technical field
本发明涉及集成电路领域,尤其涉及光敏传感器及其制备工艺。The invention relates to the field of integrated circuits, in particular to a photosensitive sensor and a preparation process thereof.
技术背景technical background
常规单光子探测器采用雪崩二极管,其工作电压较高,可集成性差;雪崩二极管击穿电压对工艺的灵敏性,导致其功耗较高,均匀性一致性较差。若应用于高压工作领域,其器件面积较大,而雪崩二极管于衬底内制作,无法与读取电路共享衬底面积,无法大幅度提高感光区域的填充因子。Conventional single-photon detectors use avalanche diodes, which have high operating voltage and poor integration; the breakdown voltage of avalanche diodes is sensitive to the process, resulting in high power consumption and poor uniformity. If it is used in the field of high-voltage work, the device area is large, and the avalanche diode is fabricated in the substrate, which cannot share the substrate area with the readout circuit, and cannot greatly increase the fill factor of the photosensitive area.
因此,有必要提供一种新型的光敏传感器及其制备工艺,以提高集成度并有利于提升对单光子探测的灵敏度。Therefore, it is necessary to provide a new type of photosensitive sensor and its preparation process, so as to improve the integration level and facilitate the improvement of the sensitivity to single photon detection.
发明概要Summary of the invention
本发明的所述光敏传感器,包括:顶电极,用于响应预定波长的光发射光电子;隔离层,与所述顶电极相对设置;底电极,与所述顶电极相对设置且电性相反;若干导电结构,设置于所述隔离层;支撑结构,与所述顶电极和所述底电极围成空腔结构,并与所述顶电极以及所述导电结构电性连接;倍增结构阵列,设置于所述隔离层,包括若干倍增结构,各所述倍增结构相对所述顶电极倾斜,并对应电性连接所述导电结构,以于所述顶电极和所述隔离层之间形成若干加速腔结构,各所述加速腔结构的顶部设有朝向所述顶 电极的开口,并底部开设出射通孔,所述出射通孔相对所述底电极;其中,光电子入射至所述加速腔结构,并经加速和倍增形成二次光电子,所述光电子及所述二次光电子穿过所述出射通孔至所述底电极The photosensitive sensor of the present invention includes: a top electrode, which is used to emit photoelectrons in response to light of a predetermined wavelength; an isolation layer, which is arranged opposite to the top electrode; a bottom electrode, which is arranged opposite to the top electrode and is electrically opposite; The conductive structure is arranged on the isolation layer; the support structure is formed into a cavity structure with the top electrode and the bottom electrode, and is electrically connected with the top electrode and the conductive structure; the multiplication structure array is arranged on The isolation layer includes several multiplication structures, each of the multiplication structures is inclined relative to the top electrode, and correspondingly electrically connected to the conductive structure, so as to form several acceleration cavity structures between the top electrode and the isolation layer , the top of each of the acceleration cavity structures is provided with an opening towards the top electrode, and the bottom is provided with an exit through hole, and the exit through hole is opposite to the bottom electrode; Accelerate and multiply to form secondary photoelectrons, and the photoelectrons and the secondary photoelectrons pass through the exit through hole to the bottom electrode
本发明还提供一种光敏传感器的制备工艺,包括以下步骤:S1:提供衬底,在所述衬底顶面形成底电极,使所述底电极的顶面露出,然后在所述底电极上形成隔离层,所述隔离层具有若干初始通孔;S2:使用导电材料填充所述若干初始通孔,形成若干导电结构,图形化所述隔离层,使所述初始通孔与所述导电结构间隔分布,且和所述底电极相对应设置;S3:形成第一牺牲层,所述第一牺牲层覆盖所述隔离层顶面并填充所述初始通孔,去除部分第一牺牲层形成若干倾斜结构,各所述倾斜结构朝向相同方向延伸,并使所述隔离层顶面和至少部分所述导电结构顶面露出,然后沉积倍增电极材料形成倍增结构阵列,所述倍增结构阵列包括若干倍增结构,各所述倍增结构电性连接对应的所述导电结构;S4:形成第二牺牲层,所述第二牺牲层填充相邻倍增结构之间的空间并覆盖所述若干倍增结构顶面,在所述第二牺牲层上形成相对的沟槽结构,填充支撑材料至所述沟槽结构,形成支撑结构;S5:沉积顶电极材料形成初始顶电极,所述初始顶电极覆盖所述支撑结构顶面和所述第二牺牲层顶面,并图形化所述初始顶电极以形成释放通孔,通过所述释放通孔去除所述第一/第二牺牲层,使用密封介质填充所述释放通孔,形成顶电极。The present invention also provides a process for preparing a photosensitive sensor, which includes the following steps: S1: providing a substrate, forming a bottom electrode on the top surface of the substrate, exposing the top surface of the bottom electrode, and then forming a substrate on the bottom electrode Forming an isolation layer, the isolation layer has a number of initial through holes; S2: using conductive material to fill the number of initial through holes, forming a number of conductive structures, patterning the isolation layer, making the initial through holes and the conductive structure distributed at intervals, and arranged correspondingly to the bottom electrodes; S3: forming a first sacrificial layer, the first sacrificial layer covering the top surface of the isolation layer and filling the initial through holes, removing part of the first sacrificial layer to form several inclined structures, each of the inclined structures extends towards the same direction, and exposes the top surface of the isolation layer and at least part of the top surface of the conductive structure, and then deposits a dynode material to form a multiplication structure array, and the multiplication structure array includes several multiplication structures. structure, each of the multiplication structures is electrically connected to the corresponding conductive structure; S4: forming a second sacrificial layer, the second sacrificial layer fills the space between adjacent multiplication structures and covers the top surfaces of the plurality of multiplication structures, Forming an opposite groove structure on the second sacrificial layer, filling the groove structure with a support material to form a support structure; S5: depositing a top electrode material to form an initial top electrode, and the initial top electrode covers the support structure top surface and the top surface of the second sacrificial layer, and pattern the initial top electrode to form a release via hole, remove the first/second sacrificial layer through the release via hole, fill the release via with a sealing medium via holes to form the top electrode.
本发明的有益效果在于:于加速腔结构中形成加速电场,光电子经加速并撞击形成二次光电子,从而放大信号,提升对单光子探测的灵敏度,且提高集成度,尺寸较小,不需要施加高电压,且功耗可控。The beneficial effect of the present invention is that: an accelerating electric field is formed in the accelerating cavity structure, photoelectrons are accelerated and collided to form secondary photoelectrons, thereby amplifying the signal, improving the sensitivity of single photon detection, and improving the integration degree, the size is small, and no need to apply High voltage with controllable power consumption.
附图说明Description of drawings
图1为本发明实施例的一种光敏传感器的剖视图;Fig. 1 is the sectional view of a kind of photosensitive sensor of the embodiment of the present invention;
图2为本发明实施例一的一种光敏传感器的剖视图;2 is a cross-sectional view of a photosensitive sensor according to Embodiment 1 of the present invention;
图3为本发明实施例一的正V型倍增电极和倒V型倍增电极的排布情况示意图;3 is a schematic diagram of the arrangement of positive V-shaped dynodes and inverted V-shaped dynodes in Embodiment 1 of the present invention;
图4~图11为本发明实施例一的一种光敏传感器的制备工艺的结构示意图;4 to 11 are structural schematic diagrams of a preparation process of a photosensitive sensor according to Embodiment 1 of the present invention;
图12是本发明实施例一的一种光敏传感器的顶电极的结构示意图;12 is a schematic structural view of a top electrode of a photosensitive sensor according to Embodiment 1 of the present invention;
图13是本发明实施例一的另一种光敏传感器的结构示意图;Fig. 13 is a schematic structural diagram of another photosensitive sensor according to Embodiment 1 of the present invention;
图14~图18为本发明实施例一的另一种光敏传感器在图5所示结构基础上的制备工艺的结构示意图;14 to 18 are structural schematic diagrams of the preparation process of another photosensitive sensor according to Embodiment 1 of the present invention based on the structure shown in FIG. 5 ;
图19为本发明实施例二的光敏传感器的结构示意图;19 is a schematic structural diagram of a photosensitive sensor according to Embodiment 2 of the present invention;
图20为本发明实施例二的若干空腔结构的俯视图;Fig. 20 is a top view of several cavity structures in Embodiment 2 of the present invention;
图21为同一子空腔阵列层的结构示意图;Fig. 21 is a schematic structural diagram of the same sub-cavity array layer;
图22~图30为本发明实施例二的光敏传感器的制备工艺的结构示意图;22 to 30 are structural schematic diagrams of the preparation process of the photosensitive sensor according to Embodiment 2 of the present invention;
图31为本发明实施例三的一种光敏传感器的结构示意图;31 is a schematic structural diagram of a photosensitive sensor according to Embodiment 3 of the present invention;
图32~图40为本发明实施例三的一种光敏传感器的制备工艺的结构示意图;32 to 40 are structural schematic diagrams of a preparation process of a photosensitive sensor according to Embodiment 3 of the present invention;
图41为本发明实施例三的另一种光敏传感器的结构示意图。FIG. 41 is a schematic structural diagram of another photosensitive sensor according to Embodiment 3 of the present invention.
发明内容Contents of the invention
为使本发明实施例的目的、技术方案和优点更加清楚,下面将对本发明 实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. the embodiment.
本发明提供了一种光敏传感器,包括顶电极、底电极、隔离层、若干导电结构、支撑结构和若干倍增结构。基于集成度高,及对单光子的探测灵敏度高,无需施加高电压,实现对光电子的加速和级联倍增。The invention provides a photosensitive sensor, which includes a top electrode, a bottom electrode, an isolation layer, several conductive structures, a supporting structure and several multiplying structures. Based on high integration and high detection sensitivity to single photons, it does not need to apply high voltage to realize the acceleration and cascade multiplication of photoelectrons.
如图1所示,顶电极11响应预定波长的光发射光电子;隔离层12与顶电极11相对设置;底电极13设置于隔离层12,且与顶电极11相对设置且电性相反;若干导电结构14设置于隔离层12;支撑结构15、顶电极11和隔离层12围成空腔结构16,支撑结构15与顶电极11电性连接;倍增结构阵列设置于隔离层12,并包括若干倍增结构17,各倍增结构17相对顶电极11倾斜,并对应电性连接导电结构14,以于顶电极11和隔离层12之间形成若干加速腔结构(未标示),各所述加速腔结构的顶部设有朝向所述顶电极的开口,并底部开设出射通孔,所述出射通孔相对所述底电极。As shown in Figure 1, the top electrode 11 responds to the light of predetermined wavelength to emit photoelectrons; The isolation layer 12 is arranged opposite to the top electrode 11; The bottom electrode 13 is arranged on the isolation layer 12, and is arranged opposite to the top electrode 11 and is electrically opposite; The structure 14 is arranged on the isolation layer 12; the support structure 15, the top electrode 11 and the isolation layer 12 form a cavity structure 16, and the support structure 15 is electrically connected to the top electrode 11; the multiplication structure array is arranged on the isolation layer 12, and includes several multiplying Structure 17, each multiplication structure 17 is inclined relative to the top electrode 11, and correspondingly electrically connected to the conductive structure 14, so as to form a number of acceleration cavity structures (not shown) between the top electrode 11 and the isolation layer 12, each of the acceleration cavity structures The top is provided with an opening facing the top electrode, and the bottom is provided with an exit through hole, and the exit through hole is opposite to the bottom electrode.
各倍增结构17倾斜于顶电极11和底电极13,并垂直于所述底电极设置。所述顶电极倾斜于所述底电极。所述顶电极由若干顶电极单元连接而成,每个所述顶电极单元均倾斜于所述底电极。所述顶电极使用具有光电效应的材料制备,以响应于预定波长的光出射光电子。所述具有光电效应的材料为AgOCs和SbCs 3的任意一种。 Each multiplication structure 17 is inclined to the top electrode 11 and the bottom electrode 13 and arranged perpendicularly to said bottom electrode. The top electrode is inclined to the bottom electrode. The top electrode is formed by connecting several top electrode units, and each of the top electrode units is inclined to the bottom electrode. The top electrode is prepared using a material having a photoelectric effect to emit photoelectrons in response to light of a predetermined wavelength. The material with photoelectric effect is any one of AgOCs and SbCs 3 .
倍增结构17朝向顶电极11的延伸线与顶电极11相交的锐角为20°~65°,有利于光电子传输到倍增结构17上,并经加速腔结构加速,并撞击形成二次光电子,从而放大信号,提升对单光子探测的灵敏度。倍增电极使用的材料为GaP(Cs)。相对顶电极11,若干倍增结构17朝同一方向倾斜设置,提高集成度。相邻倍增结构17的间距小于电子传输的自由程,避免光电子在传输过程中的能量损耗。The acute angle between the extension line of the multiplication structure 17 towards the top electrode 11 and the top electrode 11 is 20°-65°, which is conducive to the transmission of photoelectrons to the multiplication structure 17, and accelerates through the acceleration cavity structure, and collides to form secondary photoelectrons, thereby amplifying signal, improving the sensitivity of single-photon detection. The material used for the dynode is GaP(Cs). Relative to the top electrode 11, several multiplication structures 17 are arranged obliquely towards the same direction to improve integration. The distance between adjacent multiplication structures 17 is smaller than the free path of electron transmission, so as to avoid energy loss of photoelectrons during transmission.
参考图1,所述光敏传感器(未标示)还包括释放通孔18,释放通孔18与空腔结构16内相通,通过释放通孔18排出制备过程中的副产物。光敏传感器能够在非真空条件下使用,释放通孔18设置在顶电极11的边缘,以降 低对顶电极11产生光电子的影响。Referring to FIG. 1 , the photosensitive sensor (not marked) also includes a release through hole 18 , which communicates with the cavity structure 16 , and discharges by-products during the preparation process through the release through hole 18 . The photosensitive sensor can be used under non-vacuum conditions, and the release through hole 18 is arranged on the edge of the top electrode 11 to reduce the influence of photoelectrons generated on the top electrode 11.
本发明还提供一种光敏传感器的制备工艺,包括:The present invention also provides a preparation process of a photosensitive sensor, comprising:
S1:提供衬底,在所述衬底顶面形成底电极,使所述底电极的顶面露出,然后在所述底电极上形成隔离层,所述隔离层具有若干初始通孔;S1: providing a substrate, forming a bottom electrode on the top surface of the substrate, exposing the top surface of the bottom electrode, and then forming an isolation layer on the bottom electrode, the isolation layer having a number of initial through holes;
S2:使用导电材料填充所述若干初始通孔,形成若干导电结构,图形化所述隔离层,使所述初始通孔与所述导电结构间隔分布,且和所述底电极相对应设置;S2: filling the plurality of initial through holes with a conductive material to form a plurality of conductive structures, patterning the isolation layer, so that the initial through holes are spaced apart from the conductive structures, and arranged corresponding to the bottom electrodes;
S3:形成第一牺牲层,所述第一牺牲层覆盖所述隔离层顶面并填充所述初始通孔,去除部分第一牺牲层形成若干倾斜结构,各所述倾斜结构朝向相同方向延伸,并使所述隔离层顶面和至少部分所述导电结构顶面露出,然后沉积倍增电极材料形成倍增结构阵列,所述倍增结构阵列包括若干倍增结构,各所述倍增结构电性连接对应的所述导电结构;S3: forming a first sacrificial layer, the first sacrificial layer covering the top surface of the isolation layer and filling the initial through hole, removing part of the first sacrificial layer to form several inclined structures, each of which extends toward the same direction, And exposing the top surface of the isolation layer and at least part of the top surface of the conductive structure, and then depositing a dynode material to form a multiplication structure array, the multiplication structure array includes several multiplication structures, each of the multiplication structures is electrically connected to the corresponding the conductive structure;
S4:形成第二牺牲层,所述第二牺牲层填充相邻倍增结构之间的空间并覆盖所述若干倍增结构顶面,在所述第二牺牲层上形成相对的沟槽结构,填充支撑材料至所述沟槽结构,形成支撑结构;S4: Form a second sacrificial layer, the second sacrificial layer fills the space between adjacent multiplication structures and covers the top surfaces of the plurality of multiplication structures, and forms opposite trench structures on the second sacrificial layer to fill the support material to the trench structure to form a support structure;
S5:沉积顶电极材料形成初始顶电极,所述初始顶电极覆盖所述支撑结构顶面和所述第二牺牲层顶面,并图形化所述初始顶电极以形成释放通孔,通过所述释放通孔去除所述第一/第二牺牲层,使用密封介质填充所述释放通孔,形成顶电极。S5: Deposit top electrode material to form an initial top electrode, the initial top electrode covers the top surface of the support structure and the top surface of the second sacrificial layer, and pattern the initial top electrode to form a release via hole, through the The first/second sacrificial layer is removed for the release via hole, and the release via hole is filled with a sealing medium to form a top electrode.
实施例一Embodiment one
图2为本发明实施例一的一种光敏传感器的剖视图。图2与图1所示的光敏传感器的区别在于:图2还包括密封介质层19,密封介质层19封闭所述释放通孔(未标示),使空腔结构16形成真空状态,能够应用于真空条件。FIG. 2 is a cross-sectional view of a photosensitive sensor according to Embodiment 1 of the present invention. The difference between Fig. 2 and the photosensitive sensor shown in Fig. 1 is: Fig. 2 also includes a sealing medium layer 19, and the sealing medium layer 19 closes the release through hole (not marked), so that the cavity structure 16 forms a vacuum state, which can be applied to vacuum condition.
参考图2和图3,各倍增结构17包括若干正V型倍增电极171和若干倒 V型倍增电极172,正V型倍增电极171和倒V型倍增电极172均由两个倾斜倍增电极170相接而成,各所述倾斜电极170相对顶电极11倾斜设置。正V型倍增电极171和倒V型倍增电极172交替设置且电性相反,相邻的正V型倍增电极171和倒V型倍增电极172之间围成加速腔结构173。使得正V型倍增电极171和倒V型倍增电极172的两侧都可以使用,有利于提高电子的倍增效果,并使倍增结构17的设置更为紧凑,集成度更高,减小了整个器件的尺寸。Referring to Fig. 2 and Fig. 3, each multiplication structure 17 comprises several positive V-shaped dynodes 171 and several inverted V-shaped dynodes 172, and both positive V-shaped dynodes 171 and inverted V-shaped dynodes 172 are phased by two inclined dynodes 170. Each of the inclined electrodes 170 is arranged obliquely relative to the top electrode 11 . Positive V-shaped dynodes 171 and inverted V-shaped dynodes 172 are arranged alternately with opposite electrical properties, and adjacent positive V-shaped dynodes 171 and inverted V-shaped dynodes 172 form an acceleration cavity structure 173 . Both sides of the positive V-shaped dynode 171 and the inverted V-shaped dynode 172 can be used, which is conducive to improving the multiplication effect of electrons, and makes the setting of the multiplication structure 17 more compact and highly integrated, reducing the size of the entire device. size of.
正V型倍增电极171为负电压型倍增电极,倒V型倍增电极172为正电压型倍增电极,在加速腔结构173内形成了加速电场,光电子碰撞倾斜倍增电极170后,倍增得到二次光电子并实现加速。相邻的倾斜倍增电极170电性相反,从而不需要高压,以实现电子倍增。The positive V-shaped dynode 171 is a negative voltage dynode, and the inverted V-shaped dynode 172 is a positive voltage dynode. An accelerating electric field is formed in the accelerating cavity structure 173. After photoelectrons collide with the inclined dynode 170, they are multiplied to obtain secondary photoelectrons and achieve acceleration. Adjacent slanted dynodes 170 are electrically opposite so that no high voltage is required to achieve electron multiplication.
参照图4至图6,所述底电极包括若干阳极。衬底21形成顶面暴露的若干阳极22,阳极22的顶面和衬底21的顶面沉积覆盖隔离层12,在隔离层12中形成若干填充导电材料的导电结构14。Referring to FIGS. 4 to 6 , the bottom electrode includes several anodes. The substrate 21 forms a plurality of anodes 22 with exposed top surfaces. The top surfaces of the anodes 22 and the top surface of the substrate 21 are deposited to cover the isolation layer 12 , and a plurality of conductive structures 14 filled with conductive materials are formed in the isolation layer 12 .
在相邻阳极22之间形成金属互连结构23,金属互连结构23与所述导电结构14电性连接。在初始衬底上形成第一导电金属层,并图形化形成下层互连结构33,在下层互连结构33顶部沉积介质材料形成底部介质层,然后通过光刻刻蚀形成互连通孔,使用互连金属材料沉积并进行CMP磨平后形成填充所述互连通孔的互连导电结构32。A metal interconnection structure 23 is formed between adjacent anodes 22 , and the metal interconnection structure 23 is electrically connected to the conductive structure 14 . Form a first conductive metal layer on the initial substrate, and pattern it to form a lower interconnection structure 33, deposit a dielectric material on the top of the lower interconnection structure 33 to form a bottom dielectric layer, and then form interconnection vias by photolithography etching, using The interconnection conductive structure 32 filling the interconnection via hole is formed after the interconnection metal material is deposited and subjected to CMP grinding.
沉积介质材料形成顶部介质层,所述顶部介质层覆盖互连导电结构32顶面和所述底部介质层顶面,在所述顶部介质层上沉积形成阳极22以及上层互连结构31,通过互连导电结构32,上层互连结构31与下层互连结构33电接触。下层互连结构33、互连导电结构32和上层互连结构31构成金属互连结构23,金属互连结构23连接处理电路。所述初始衬底、所述顶部介质层和所述底部介质层构成衬底21。A dielectric material is deposited to form a top dielectric layer, the top dielectric layer covers the top surface of the interconnection conductive structure 32 and the top surface of the bottom dielectric layer, and the anode 22 and the upper interconnection structure 31 are formed by depositing on the top dielectric layer. The upper layer interconnection structure 31 is in electrical contact with the lower layer interconnection structure 33 . The lower interconnection structure 33 , the interconnection conductive structure 32 and the upper interconnection structure 31 form a metal interconnection structure 23 , and the metal interconnection structure 23 is connected to a processing circuit. The initial substrate, the top dielectric layer and the bottom dielectric layer constitute a substrate 21 .
沉积隔离介质于阳极22顶面和衬底21顶面,并CMP磨平后形成初始隔离层,然后图形化所述初始隔离层,形成具有若干初始通孔的隔离层12。所 述沉积和填充的方法包括化学气相沉积工艺、电子束蒸发工艺、原子层沉积工艺和溅射工艺中的任意一种。An isolation medium is deposited on the top surface of the anode 22 and the top surface of the substrate 21 , and the initial isolation layer is formed after CMP grinding, and then the initial isolation layer is patterned to form the isolation layer 12 with several initial through holes. The deposition and filling methods include any one of chemical vapor deposition process, electron beam evaporation process, atomic layer deposition process and sputtering process.
参照图5,使用导电材料填充所述若干初始通孔形成若干导电结构14,再图形化隔离层12形成若干出射通孔26,并使若干出射通孔26与若干导电结构14间隔分布。出射通孔26与阳极22相对,使阳极22的顶面露出;导电结构14与金属互连结构23电接触。Referring to FIG. 5 , the initial through-holes are filled with conductive material to form a number of conductive structures 14 , and then the isolation layer 12 is patterned to form a number of outgoing through-holes 26 , and the several outgoing through-holes 26 are spaced apart from the several conductive structures 14 . The exit through hole 26 is opposite to the anode 22 , exposing the top surface of the anode 22 ; the conductive structure 14 is in electrical contact with the metal interconnection structure 23 .
参照图6,若干倾斜结构27朝向同一方向倾斜,沉积倍增电极材料形成的初始倍增电极层28覆盖倾斜结构27的表面、隔离层12的顶面以及导电结构14的顶面,牺牲材料还填充了隔离层12上设置的若干出射通孔26。Referring to Fig. 6, several inclined structures 27 are inclined toward the same direction, and the initial dynode layer 28 formed by depositing the dynode material covers the surface of the inclined structures 27, the top surface of the isolation layer 12 and the top surface of the conductive structure 14, and the sacrificial material also fills the Several outgoing through holes 26 are provided on the isolation layer 12 .
S3包括:S31:形成第一牺牲层,所述第一牺牲层覆盖所述隔离层顶面并填充所述初始通孔;S32:将所述衬底倾斜,刻蚀形成包括若干空腔结构的空腔阵列,然后将所述衬底复位后,沉积倍增电极材料形成初始倍增电极层,所述初始倍增电极层填充所述空腔阵列,再将所述衬底倾斜,去除部分所述初始倍增电极层,得到倍增结构阵列,所述倍增结构阵列设置于所述空腔结构侧壁,并与所述导电结构电接触。S3 includes: S31: forming a first sacrificial layer, the first sacrificial layer covering the top surface of the isolation layer and filling the initial through hole; S32: tilting the substrate, etching to form a cavity structure Cavity array, and then after the substrate is reset, the dynode material is deposited to form an initial dynode layer, and the initial dynode layer fills the cavity array, and then the substrate is tilted to remove part of the initial dynode The electrode layer obtains a multiplication structure array, and the multiplication structure array is arranged on the side wall of the cavity structure and is in electrical contact with the conductive structure.
另一实施例,S3将所述衬底倾斜设置后,形成第一牺牲层之前,沉积辅助牺牲材料,形成若干辅助倾斜结构;形成第一牺牲层之后,去除所述辅助倾斜结构同侧的第一牺牲层,去除所述辅助牺牲材料,形成若干倾斜结构。参照图6,初始倍增电极层28覆盖倾斜结构27的侧壁和顶面,还覆盖隔离层12顶面,使导电结构14的顶面被覆盖。In another embodiment, in S3, after setting the substrate at an inclination, before forming the first sacrificial layer, deposit an auxiliary sacrificial material to form several auxiliary inclined structures; after forming the first sacrificial layer, remove the second A sacrificial layer, the auxiliary sacrificial material is removed to form several inclined structures. Referring to FIG. 6 , the initial dynode layer 28 covers the sidewall and top surface of the inclined structure 27 , and also covers the top surface of the isolation layer 12 , so that the top surface of the conductive structure 14 is covered.
如图7所示,通过包层刻蚀(Blanket etch),去除覆盖导电结构14的顶面以及覆盖隔离层12顶面的初始倍增电极层28,露出导电结构14的顶面以及隔离层12的顶面,然后再刻蚀倾斜结构27及其表面的初始倍增电极层28,倾斜结构27的相对侧面上的初始倍增电极层28保留,用于倾斜倍增电极,形成倍增结构17,相邻倍增结构17之间的空间通过出射通孔26与阳极22相对。去除牺牲层后,所述倍增结构与所述导电结构电性连接且朝向相同, 以提高集成度。所述倾斜倍增电极倾斜于所述顶电极,并设置于所述隔离层。所述隔离层对应的倾斜倍增电极之间具有相同或不同的高度。As shown in FIG. 7 , by cladding etching (Blanket etch), the top surface covering the conductive structure 14 and the initial dynode layer 28 covering the top surface of the isolation layer 12 are removed, exposing the top surface of the conductive structure 14 and the top surface of the isolation layer 12. top surface, and then etch the initial dynode layer 28 on the inclined structure 27 and its surface, the initial dynode layer 28 on the opposite side of the inclined structure 27 is reserved for tilting the dynode to form the multiplication structure 17, adjacent multiplication structures The space between 17 is opposite to the anode 22 through the exit through hole 26 . After removing the sacrificial layer, the multiplication structure is electrically connected to the conductive structure with the same orientation to improve integration. The inclined dynode is inclined to the top electrode and disposed on the isolation layer. The inclined dynodes corresponding to the isolation layers have the same or different heights.
参照图8,S4中,沉积所述牺牲材料形成第二牺牲层41,第二牺牲层41填充相邻倍增结构之间的空间,并覆盖所述若干倍增结构顶面及隔离层12的顶面。参照图9,在所述第二牺牲层41上形成相对的沟槽结构42。Referring to FIG. 8, in S4, the sacrificial material is deposited to form a second sacrificial layer 41, and the second sacrificial layer 41 fills the space between adjacent multiplication structures and covers the top surfaces of the plurality of multiplication structures and the top surface of the isolation layer 12. . Referring to FIG. 9 , an opposite trench structure 42 is formed on the second sacrificial layer 41 .
参照图1、图9和图10,S4中,沉积支撑材料以形成初始支撑结构,所述初始支撑结构填充沟槽结构42,并覆盖第二牺牲层41,去除部分所述初始支撑结构,并使第二牺牲层41的顶面露出,形成支撑结构15,支撑结构15包括第一支撑结构44和第二支撑结构45。Referring to FIG. 1, FIG. 9 and FIG. 10, in S4, a support material is deposited to form an initial support structure, the initial support structure fills the trench structure 42, and covers the second sacrificial layer 41, part of the initial support structure is removed, and The top surface of the second sacrificial layer 41 is exposed to form a support structure 15 , and the support structure 15 includes a first support structure 44 and a second support structure 45 .
参照图1、图10和图11,S5中,沉积顶电极材料形成初始顶电极43,初始顶电极43覆盖第二牺牲层41顶面、第一支撑结构44和第二支撑结构45。图形化初始顶电极43以形成释放通孔18,通过释放通孔18去除第二牺牲层41,形成顶电极11。参考图2,S5之后还包括:使用密封介质19密封释放通孔18,并去除初始顶电极43顶面的密封介质,形成顶电极11。Referring to FIG. 1 , FIG. 10 and FIG. 11 , in S5 , the top electrode material is deposited to form the initial top electrode 43 , and the initial top electrode 43 covers the top surface of the second sacrificial layer 41 , the first support structure 44 and the second support structure 45 . The initial top electrode 43 is patterned to form the release via hole 18 , and the second sacrificial layer 41 is removed through the release via hole 18 to form the top electrode 11 . Referring to FIG. 2 , after S5 , it also includes: using the sealing medium 19 to seal the release through hole 18 , and removing the sealing medium on the top surface of the initial top electrode 43 to form the top electrode 11 .
在高真空的成膜设备中,使用介质沉积工艺,在释放通孔18内填充密封介质19,以封堵释放通孔18;再通过blanket刻蚀去除初始顶电极43表面的密封介质。参照图12,顶电极11包括不同顶电极单元51,每个顶电极单元51均倾斜于底电极13设置。参照图13,若干倍增结构17垂直于底电极13设置,顶电极11呈锥形结构。各顶电极单元51之间串联连接以实现电接触。使用灰阶掩膜进行光刻,形成从边缘到中间逐渐增厚的锥形结构,在所述锥形结构顶面沉积阴极材料,形成初始顶电极。In the high-vacuum film forming equipment, a dielectric deposition process is used to fill the release through hole 18 with a sealing medium 19 to block the release through hole 18; then the sealing medium on the surface of the initial top electrode 43 is removed by blanket etching. Referring to FIG. 12 , the top electrode 11 includes different top electrode units 51 , and each top electrode unit 51 is disposed obliquely to the bottom electrode 13 . Referring to FIG. 13 , several multiplication structures 17 are arranged perpendicular to the bottom electrode 13 , and the top electrode 11 has a tapered structure. The top electrode units 51 are connected in series to realize electrical contact. Photolithography is performed using a grayscale mask to form a tapered structure that gradually thickens from the edge to the middle, and a cathode material is deposited on the top surface of the tapered structure to form an initial top electrode.
参考图14~图18,另一实施例,S3包括:Referring to Figures 14 to 18, another embodiment, S3 includes:
S301:部分隔离层12的顶面形成第一牺牲层201;S301: forming a first sacrificial layer 201 on a top surface of part of the isolation layer 12;
S302:倾斜刻蚀第一牺牲层201至露出导电结构14,以形成倾斜的且朝向相同方向的第一倾斜窗口图形202,如图14所示;S302: Obliquely etch the first sacrificial layer 201 to expose the conductive structure 14, so as to form a first inclined window pattern 202 that is inclined and faces the same direction, as shown in FIG. 14 ;
S303:反向倾斜刻蚀第一牺牲层201至露出导电结构14,以形成倾斜的且朝向与第一倾斜窗口图形202的方向相反的第二倾斜窗口图形203,如图 15所示;S303: reverse obliquely etch the first sacrificial layer 201 to expose the conductive structure 14, so as to form a second inclined window pattern 203 that is inclined and oriented opposite to the direction of the first inclined window pattern 202, as shown in FIG. 15 ;
S304:在第一牺牲层201和导电结构14的表面沉积倍增电极材料,通过刻蚀工艺去除第一牺牲层201上表面的倍增电极材料至露出第一牺牲层201,使第一倾斜窗口图形202和第二倾斜窗口图形203内形成初始倍增电极204,如图16所示;S304: Deposit the dynode material on the surface of the first sacrificial layer 201 and the conductive structure 14, remove the dynode material on the upper surface of the first sacrificial layer 201 through an etching process to expose the first sacrificial layer 201, and make the first inclined window pattern 202 and an initial dynode 204 is formed in the second inclined window pattern 203, as shown in FIG. 16;
S305:去除部分所述倍增电极材料,以形成倍增结构17,并使倍增结构17与所述导电结构电连接,如图17所示;S305: removing part of the dynode material to form a dynode structure 17, and electrically connecting the dynode structure 17 to the conductive structure, as shown in FIG. 17 ;
S306:去除第一牺牲层201和部分所述隔离层,以使相邻的倍增结构17形成正V型倍增电极171和倒V型倍增电极172,并围成加速腔结构173,如图18所示。S306: remove the first sacrificial layer 201 and part of the isolation layer, so that the adjacent multiplication structure 17 forms a positive V-shaped dynode 171 and an inverted V-shaped dynode 172, and encloses an acceleration cavity structure 173, as shown in FIG. 18 Show.
实施例二Embodiment two
参照图19,上层空腔阵列13和下层空腔阵列14组成加速腔阵列,所述加速腔阵列设置于顶电极11和底电极12之间,所述加速腔阵列的顶面开口朝向顶电极11,底面开口朝向底电极12,形成若干加速腔17供所述光电子以及二次电子通过,并使所述二次光电子到达底电极12。参照图20,以第一加速腔结构131为例,沿顶电极11设置方向,各所述加速腔结构的截面呈等边六边形。Referring to Fig. 19, the upper layer cavity array 13 and the lower layer cavity array 14 form an accelerating cavity array, the accelerating cavity array is arranged between the top electrode 11 and the bottom electrode 12, and the top surface opening of the accelerating cavity array faces the top electrode 11 , the opening of the bottom surface faces the bottom electrode 12 , forming a number of acceleration cavities 17 for the passage of the photoelectrons and secondary electrons, and allowing the secondary photoelectrons to reach the bottom electrode 12 . Referring to FIG. 20 , taking the first acceleration chamber structure 131 as an example, along the direction in which the top electrode 11 is arranged, the cross-section of each acceleration chamber structure is an equilateral hexagon.
倍增电极15之间两两相对,设置于每个加速腔17内,光电子经倍增电极15加速和倍增,形成所述二次光电子,提高集成度,并有利于提升弱光探测的灵敏度。The dynodes 15 face each other in pairs and are arranged in each acceleration cavity 17. The photoelectrons are accelerated and multiplied by the dynodes 15 to form the secondary photoelectrons, which improves the integration and is beneficial to improve the sensitivity of weak light detection.
参照图19,若干加速腔17沿倾斜于顶电极11的方向排布。Referring to FIG. 19 , several accelerating chambers 17 are arranged in a direction oblique to the top electrode 11 .
所述倍增结构包括倍增电极对,所述倍增电极对相对设置于每个加速腔结构,使得同一空腔结构内的相邻倍增电极之间形成加速电场。The multiplication structure includes a pair of dynodes, and the pair of dynodes is arranged opposite to each acceleration cavity structure, so that an accelerating electric field is formed between adjacent dynodes in the same cavity structure.
沿倾斜于所述顶电极的方向,所述倍增结构阵列包含若干子空腔阵列层,各所述子空腔阵列层倾斜于所述顶电极,相邻子空腔阵列层的加速腔结构相对且连通设置,同一子空腔阵列层的空腔结构顶面开口朝向所述顶电极,底面开口朝向所述底电极。Along the direction inclined to the top electrode, the multiplication structure array includes several sub-cavity array layers, each of the sub-cavity array layers is inclined to the top electrode, and the accelerating cavity structures of adjacent sub-cavity array layers are opposite to each other. In addition, the cavity structures of the same sub-cavity array layer have top openings facing the top electrode and bottom openings facing the bottom electrode.
图19所示的8个空腔结构中,4个加速腔结构排布形成上层空腔阵列层13,上层空腔阵列层13作为一个子空腔阵列层,另外4个加速腔结构排布形成下层空腔阵列层14,下层空腔阵列层14作为另一个子空腔阵列层。上层空腔阵列层13和下层空腔阵列层14设置于顶电极11和底电极12之间。上层空腔阵列层13的每个加速腔结构和下层空腔阵列层14的每个加速腔结构一一对应设置。加速腔结构的个数可以根据需求灵活调整。Among the 8 cavity structures shown in Figure 19, 4 accelerating cavity structures are arranged to form the upper cavity array layer 13, and the upper cavity array layer 13 is used as a sub-cavity array layer, and the other 4 accelerating cavity structures are arranged to form The lower cavity array layer 14, the lower cavity array layer 14 serves as another sub-cavity array layer. The upper cavity array layer 13 and the lower cavity array layer 14 are disposed between the top electrode 11 and the bottom electrode 12 . Each accelerating cavity structure of the upper cavity array layer 13 and each accelerating cavity structure of the lower cavity array layer 14 are provided in a one-to-one correspondence. The number of accelerating cavity structures can be flexibly adjusted according to requirements.
不同子空腔阵列层的相邻加速腔结构中,靠近所述顶电极的加速腔结构出射通孔与靠近所述底电极的加速腔结构的开口一一对应,以允许所述光电子及二次光电子通过。参照图19,相邻的第一加速腔结构131的出射通孔和第二加速腔结构141的开口相接,使得第一加速腔结构131和第二加速腔结构141内部相通。In the adjacent accelerating cavity structures of different sub-cavity array layers, the exit through hole of the accelerating cavity structure close to the top electrode corresponds to the opening of the accelerating cavity structure close to the bottom electrode, so as to allow the photoelectron and secondary Photoelectrons pass through. Referring to FIG. 19 , the exit holes of adjacent first accelerating cavity structures 131 are connected to the openings of the second accelerating cavity structures 141 , so that the first accelerating cavity structures 131 and the second accelerating cavity structures 141 communicate with each other.
参照图19和图21,所述光敏传感器还包括层间隔离层。上层空腔阵列层13和下层空腔阵列层14之间具有层间隔离层16,层间隔离层16包括若干层间导电结构161,以及若干位于沿水平方向相对的层间导电结构161之间的层间通孔结构(未标示),以供光电子通过。Referring to FIG. 19 and FIG. 21 , the photosensitive sensor further includes an interlayer isolation layer. There is an interlayer isolation layer 16 between the upper cavity array layer 13 and the lower cavity array layer 14, and the interlayer isolation layer 16 includes several interlayer conductive structures 161, and several interlayer conductive structures 161 located opposite along the horizontal direction. An interlayer via structure (not shown) for photoelectrons to pass through.
层间导电结构161电接触相邻所述子空腔阵列层中的至少一层的若干倍增结构。参照图21,层间导电结构161电接触第一倍增电极151和第二倍增电极152,第一倍增电极151和第二倍增电极152属于同一子空腔阵列层。每个空腔结构的底部设置有加速薄膜,所述加速薄膜具有通道孔,所述通道孔作为所述空腔结构的底面开口,并加强对所述空腔结构出射的二次光电子的加速作用。所述加速薄膜由还原石墨烯和氧化石墨烯层的至少一层组成。The interlayer conductive structure 161 is in electrical contact with several multiplication structures of at least one layer adjacent to the sub-cavity array layers. Referring to FIG. 21 , the interlayer conductive structure 161 electrically contacts the first dynode 151 and the second dynode 152 , and the first dynode 151 and the second dynode 152 belong to the same sub-cavity array layer. The bottom of each cavity structure is provided with an accelerating film, the accelerating film has a channel hole, the channel hole is used as the bottom opening of the cavity structure, and strengthens the acceleration of the secondary photoelectrons emitted by the cavity structure . The accelerating film is composed of at least one of reduced graphene and graphene oxide layers.
参照图21,除若干层间导电结构161外,层间隔离层16的其他部分以及加速电极162构成所述加速薄膜。加速电极162为多孔结构,以允许光电子及二次光电子通过,用于加速。层间隔离层16中除若干层间导电结构161外的其他部分由氧化石墨烯组成,加速电极162由还原石墨烯组成。所述加速薄膜与相邻的加速腔结构内的倍增电极相互隔离,以不发生电连接。相邻的加速腔结构内,倍增电极包括第一倍增电极151、第二倍增电极152。Referring to FIG. 21 , except for several interlayer conductive structures 161 , other parts of the interlayer isolation layer 16 and the accelerating electrodes 162 constitute the accelerating film. The accelerating electrode 162 has a porous structure to allow photoelectrons and secondary photoelectrons to pass through for acceleration. Other parts of the interlayer isolation layer 16 except for some interlayer conductive structures 161 are composed of graphene oxide, and the accelerating electrode 162 is composed of reduced graphene. The accelerating film is isolated from the dynodes in the adjacent accelerating cavity structure so as not to be electrically connected. In adjacent accelerating cavity structures, the dynodes include a first dynode 151 and a second dynode 152 .
不同子空腔阵列层的相邻加速腔结构形成的运动通道呈V型。请参见图19,不同子空腔阵列层的相邻加速腔结构,以第一加速腔结构131和第二加速腔结构141为例,第一加速腔结构131和第二加速腔结构141形成的结构呈V型。同一子空腔阵列层的倍增电极对朝向同一方向设置。所述底电极包括若干相互隔离的阳极,所述若干阳极与最接近所述底电极的加速腔结构一一对应设置。The motion channel formed by the adjacent accelerating cavity structures of different sub-cavity array layers is V-shaped. Please refer to FIG. 19, the adjacent accelerating cavity structures of different sub-cavity array layers, taking the first accelerating cavity structure 131 and the second accelerating cavity structure 141 as an example, the first accelerating cavity structure 131 and the second accelerating cavity structure 141 form The structure is V-shaped. The dynode pairs of the same sub-cavity array layer are arranged facing the same direction. The bottom electrode includes a number of anodes isolated from each other, and the anodes are arranged in one-to-one correspondence with the acceleration chamber structure closest to the bottom electrode.
本发明实施例二的所述光敏传感器,参照图22和图23,所述底电极包括若干阳极。衬底21形成有顶面暴露的若干阳极22,阳极22的顶面和衬底21的顶面沉积覆盖有隔离层24,隔离层24形成有若干填充导电材料的导电结构25。Referring to Fig. 22 and Fig. 23 for the photosensitive sensor according to the second embodiment of the present invention, the bottom electrode includes several anodes. The substrate 21 is formed with a number of anodes 22 with exposed top surfaces, and the top surfaces of the anodes 22 and the top surface of the substrate 21 are deposited and covered with an isolation layer 24, and the isolation layer 24 is formed with a number of conductive structures 25 filled with conductive materials.
相邻阳极22之间形成有金属互连结构23以便于外接处理电路,金属互连结构23与导电结构25电性连接。互连导电结构32和下层互连结构33组成了金属互连结构23。具体的,在初始衬底上形成第一导电金属层,并图形化形成下层互连结构33,在下层互连结构33顶部沉积牺牲材料形成第一牺牲层,然后通过光刻刻蚀形成互连通孔,使用互连金属材料沉积并进行CMP磨平后形成填充所述互连通孔的互连导电结构32。A metal interconnection structure 23 is formed between adjacent anodes 22 for external processing circuit, and the metal interconnection structure 23 is electrically connected with the conductive structure 25 . The interconnection conductive structure 32 and the underlying interconnection structure 33 constitute the metal interconnection structure 23 . Specifically, a first conductive metal layer is formed on the initial substrate, and the underlying interconnection structure 33 is patterned, a sacrificial material is deposited on the top of the underlying interconnection structure 33 to form a first sacrificial layer, and then the interconnection is formed by photolithography. The through holes are deposited by interconnecting metal materials and smoothed by CMP to form the interconnected conductive structures 32 filling the interconnected through holes.
使用牺牲材料沉积形成第二牺牲层,所述第二牺牲层覆盖互连导电结构32顶面和所述第一牺牲层,在所述第二牺牲层上形成阳极22以及上层互连结构31,使上层互连结构31通过互连导电结构32与下层互连结构33电接触。所述初始衬底、所述第二牺牲层和所述第一牺牲层构成了衬底21。Depositing a sacrificial material to form a second sacrificial layer, the second sacrificial layer covering the top surface of the interconnection conductive structure 32 and the first sacrificial layer, forming the anode 22 and the upper interconnection structure 31 on the second sacrificial layer, The upper interconnection structure 31 is electrically contacted with the lower interconnection structure 33 through the interconnection conductive structure 32 . The initial substrate, the second sacrificial layer and the first sacrificial layer constitute a substrate 21 .
具体的,阳极22的顶面露出,在阳极22顶面和衬底21顶面沉积一层初始隔离层(未标示)后,图形化所述初始隔离层(未标示)以形成若干初始通孔。Specifically, the top surface of the anode 22 is exposed, and after depositing an initial isolation layer (not indicated) on the top surface of the anode 22 and the top surface of the substrate 21, the initial isolation layer (not indicated) is patterned to form several initial through holes .
参见图23,使用导电材料填充所述若干初始通孔,形成若干导电结构,再图形化初始隔离层,并通过刻蚀使在所述初始隔离层中形成若干出射通孔,并使若干所述出射通孔与若干所述导电结构间隔分布。隔离层24中,导电结构25和出射通孔26间隔分布,出射通孔26与阳极22相对,使至少 部分阳极22的顶面露出;导电结构25与金属互连结构23电接触。Referring to FIG. 23 , the initial through holes are filled with conductive material to form a number of conductive structures, and then the initial isolation layer is patterned, and several outgoing through holes are formed in the initial isolation layer by etching, and several of the The exit through holes are distributed at intervals with several conductive structures. In the isolation layer 24, the conductive structure 25 and the exit through hole 26 are distributed at intervals, and the exit through hole 26 is opposite to the anode 22, exposing at least part of the top surface of the anode 22; the conductive structure 25 is in electrical contact with the metal interconnection structure 23.
在实施例二,S3包括:将所述衬底倾斜,刻蚀形成包括若干空腔结构的空腔阵列,然后将所述衬底复位后,沉积倍增电极材料形成初始倍增电极层,所述初始倍增电极层填充所述空腔阵列,再将所述衬底倾斜,去除部分所述初始倍增电极层,得到设置于所述空腔结构侧壁,并与所述导电结构电接触的倍增结构。In the second embodiment, S3 includes: tilting the substrate, etching to form a cavity array including several cavity structures, and then resetting the substrate, depositing a dynode material to form an initial dynode layer, the initial The dynode layer fills the cavity array, and then the substrate is tilted to remove part of the initial dynode layer to obtain a multiplication structure disposed on the sidewall of the cavity structure and in electrical contact with the conductive structure.
参照图23和图24,通过刻蚀去除了覆盖隔离层24顶面以及填充所述若干出射通孔26的牺牲材料,还去除了覆盖导电结构25的一部分牺牲材料,形成若干倾斜结构61,倾斜结构61与导电结构25相接,相互平行且均倾斜于衬底21,相邻的倾斜结构61组成1个顶部开口的空腔,每个空腔的顶部开口与阳极22相对。具体的,所述牺牲材料为绝缘材料。Referring to FIGS. 23 and 24 , the sacrificial material covering the top surface of the isolation layer 24 and filling the exit holes 26 is removed by etching, and a part of the sacrificial material covering the conductive structure 25 is also removed to form several inclined structures 61. The structures 61 are in contact with the conductive structures 25 , are parallel to each other and are inclined to the substrate 21 , adjacent inclined structures 61 form a cavity with a top opening, and the top opening of each cavity is opposite to the anode 22 . Specifically, the sacrificial material is an insulating material.
沉积倍增电极材料,形成初始倍增电极层(未标示),所述初始倍增电极层覆盖隔离层24和若干导电结构25,填充出射通孔26并覆盖每个倾斜结构61。参照图25,采用各向异性刻蚀,去除部分所述初始倍增电极层后,得到图7所示的若干倍增电极71,相邻的倾斜结构61的相对侧壁形成有倍增电极71,每个倍增电极71与导电结构25电连接。The dynode material is deposited to form an initial dynode layer (not shown). The initial dynode layer covers the isolation layer 24 and several conductive structures 25 , fills the emission via hole 26 and covers each inclined structure 61 . Referring to FIG. 25, after removing part of the initial dynode layer by anisotropic etching, several dynodes 71 as shown in FIG. The dynode 71 is electrically connected to the conductive structure 25 .
所述空腔阵列包括若干子空腔阵列层,已形成的所述子空腔阵列层经S3形成之后,执行以下步骤:The cavity array includes several sub-cavity array layers, and after the formed sub-cavity array layers are formed in S3, the following steps are performed:
S331:使用牺牲材料填充所述已形成的子空腔阵列层内部,使所述已形成的子空腔阵列层的顶面露出;S331: Fill the inside of the formed sub-cavity array layer with a sacrificial material, exposing the top surface of the formed sub-cavity array layer;
S332:使用层间材料形成层间隔离层,所述层间隔离层覆盖所述已形成的子空腔阵列层,并包括若干层间导电结构和若干层间通孔结构,各所述层间通孔结构相对所述已形成的子空腔阵列层对应的加速腔结构设置,所述层间导电结构的至少部分表面露出;其中,重复执行S3、S331及S332,直至形成若干层子空腔阵列层,相邻所述子空腔阵列层之间设有所述层间隔离 层,并至少一所述子空腔阵列层的倍增结构电接触所述层间导电结构。S332: Use an interlayer material to form an interlayer isolation layer, the interlayer isolation layer covers the formed sub-cavity array layer, and includes several interlayer conductive structures and several interlayer via structures, each of the interlayer The through-hole structure is arranged relative to the corresponding acceleration cavity structure of the formed sub-cavity array layer, and at least part of the surface of the interlayer conductive structure is exposed; wherein, S3, S331 and S332 are repeatedly executed until several layers of sub-cavities are formed Array layer, the interlayer isolation layer is provided between adjacent sub-cavity array layers, and at least one multiplication structure of the sub-cavity array layer is in electrical contact with the interlayer conductive structure.
层间隔离层16的形成过程,请参见导电结构25和出射通孔26的形成过程,区别在于,参照图21和图26,通过图形化和刻蚀、沉积工艺,在每个层间隔离层16形成层间导电结构161,然后将分散液旋涂于每个层间隔离层16的顶面以及相邻层间隔离层16顶面之间,以实现对相邻的空腔阵列之间通道的密封。所述分散液为包含氧化石墨烯和有机溶剂的分散液。S332之后,将所述分散液旋涂于所述加速腔结构的开口,所述氧化石墨烯层覆盖至少一个所述开口,并与所述层间导电结构相接触。For the formation process of the interlayer isolation layer 16, please refer to the formation process of the conductive structure 25 and the exit through hole 26. The difference is that, referring to FIG. 21 and FIG. 26, each interlayer isolation layer is 16 to form an interlayer conductive structure 161, and then spin-coat the dispersion on the top surface of each interlayer isolation layer 16 and between the top surfaces of adjacent interlayer isolation layers 16, so as to realize the channel between adjacent cavity arrays. of the seal. The dispersion liquid is a dispersion liquid containing graphene oxide and an organic solvent. After S332, the dispersion liquid is spin-coated on openings of the acceleration chamber structure, and the graphene oxide layer covers at least one of the openings and is in contact with the interlayer conductive structure.
参照图27,于第一层空腔阵列91的顶部沉积形成第二层空腔阵列92。第二层空腔阵列92的各倾斜结构相互平行,且与沿垂直方向相接的倾斜结构形成的夹角相同。第二层空腔阵列92设置的若干倍增电极的形成方式请参见前述,在此不做赘述。Referring to FIG. 27 , a second layer cavity array 92 is deposited on top of the first layer cavity array 91 . The inclined structures of the cavity array 92 on the second layer are parallel to each other, and form the same angle with the inclined structures connected along the vertical direction. For the formation method of the several dynodes provided in the cavity array 92 on the second layer, please refer to the above, and details will not be repeated here.
参照图27至图30,牺牲材料填充形成第二牺牲层101,在第二牺牲层101上形成相对的沟槽结构,即第一沟槽结构102和第二沟槽结构103后,使用支撑材料填充两个沟槽结构,形成第一支撑结构111和第二支撑结构112。沉积顶电极材料,所述顶电极材料覆盖第一支撑结构111和第二支撑结构112的顶面,以及第二牺牲层101顶面,形成初始顶电极113,图形化初始顶电极113以形成释放通孔114。27 to 30, the sacrificial material is filled to form the second sacrificial layer 101, and after forming the opposite trench structures on the second sacrificial layer 101, that is, the first trench structure 102 and the second trench structure 103, a supporting material is used The two trench structures are filled to form a first support structure 111 and a second support structure 112 . Deposit top electrode material, the top electrode material covers the top surface of the first support structure 111 and the second support structure 112, and the top surface of the second sacrificial layer 101 to form the initial top electrode 113, patterning the initial top electrode 113 to form a release through hole 114 .
通过释放通孔114去除所述牺牲材料后,使用密封介质密封所述释放通孔,并去除初始顶电极113顶面的密封介质,形成顶电极。并保留释放通孔114以与所述空腔结构相通。再去除部分所述氧化石墨烯层,使沿纵向方向相对的加速腔结构相通,再使用密封介质,密封所述释放通孔,并去除所述初始顶电极顶面的密封介质。After the sacrificial material is removed through the release via hole 114 , a sealing medium is used to seal the release via hole, and the sealing medium on the top surface of the initial top electrode 113 is removed to form a top electrode. And the release through hole 114 is reserved to communicate with the cavity structure. Removing a portion of the graphene oxide layer, so that the structures of the relative acceleration chambers along the longitudinal direction are communicated, and then using a sealing medium to seal the release through hole, and removing the sealing medium on the top surface of the initial top electrode.
S5中,去除部分所述氧化石墨烯层包括,通过光刻刻蚀在每个所述氧化石墨烯层形成通道孔,使沿纵向方向相对的加速腔结构相通。再还原剩余的氧化石墨烯层,得到加速电极。In S5, removing part of the graphene oxide layer includes forming a channel hole in each graphene oxide layer by photolithography, so as to communicate with the opposing acceleration cavity structures along the longitudinal direction. Then reduce the remaining graphene oxide layer to obtain an accelerating electrode.
实施例三Embodiment three
图31所示的光敏传感器,若干隔离层14设置于所述空腔结构内,并将所述空腔结构分隔形成若干子空腔结构18,各隔离层14对应设置有若干导电结构(未标示)及若干倍增结构阵列,各所述导电结构与所述支撑结构电性连接;相邻所述隔离层之间,靠近所述顶电极的倍增结构阵列的出射通孔作为靠近所述底电极的另一个倍增结构阵列的开口,参照图31,一个加速腔结构底部的通孔161与另一个加速腔底部的通孔162相对设置,提高集成度,减少光电子的运动路程和能量损耗。各所述倍增结构朝向同一方向倾斜,提高集成度。顶电极11和底电极12沿同一方向设置,若干倍增结构15倾斜于顶电极11和底电极12。In the photosensitive sensor shown in Figure 31, several isolation layers 14 are arranged in the cavity structure, and the cavity structure is separated to form several sub-cavity structures 18, and each isolation layer 14 is correspondingly provided with some conductive structures (not marked). ) and a plurality of multiplication structure arrays, each of the conductive structures is electrically connected to the support structure; between adjacent isolation layers, the exit through hole of the multiplication structure array near the top electrode is used as a hole near the bottom electrode For the opening of another multiplication structure array, referring to FIG. 31 , the through hole 161 at the bottom of one accelerating cavity structure is opposite to the through hole 162 at the bottom of the other accelerating cavity to improve integration and reduce the movement distance and energy loss of photoelectrons. Each of the multiplication structures is inclined towards the same direction to improve integration. The top electrode 11 and the bottom electrode 12 are arranged along the same direction, and several multiplication structures 15 are inclined to the top electrode 11 and the bottom electrode 12 .
若干倍增结构15相对顶电极11倾斜设置于每层隔离层14并与所述导电结构(未标示)一一对应电性连接,将每个子空腔结构18分隔形成顶部朝向顶电极11开口的加速腔结构(未标示),以接收入射的光电子并对所述入射的光电子进行加速和倍增形成二次光电子。每个加速腔结构底部开设允许所述二次光电子通过通孔16,还包含相对的两个倍增结构15。相邻倍增结构15之间形成加速电场,利用加速电场使光电子在相邻倍增结构15之间加速并撞击形成更多光电子,形成放大的光电子信号。每个子空腔结构18中的加速腔结构的数目大于1。相邻倍增结构15之间的距离小于光电子传输的自由程,最大限度避免光电子在传输过程中的能量损耗。A plurality of multiplication structures 15 are arranged obliquely on each isolation layer 14 relative to the top electrode 11 and are electrically connected to the conductive structures (not shown) in one-to-one correspondence, separating each sub-cavity structure 18 to form an acceleration whose top opens toward the top electrode 11. The cavity structure (not shown) is used to receive incident photoelectrons and accelerate and multiply the incident photoelectrons to form secondary photoelectrons. The bottom of each accelerating cavity structure is opened to allow the secondary photoelectrons to pass through holes 16 , and also includes two opposite multiplication structures 15 . An accelerating electric field is formed between adjacent multiplication structures 15 , and photoelectrons are accelerated between adjacent multiplication structures 15 by using the accelerating electric field and collide to form more photoelectrons to form amplified photoelectron signals. The number of accelerating cavity structures in each sub-cavity structure 18 is greater than one. The distance between adjacent multiplication structures 15 is smaller than the free path of photoelectron transmission, so as to avoid the energy loss of photoelectrons in the transmission process to the greatest extent.
不同隔离层14的相邻加速腔结构中,靠近顶电极11的一个加速腔结构的通孔作为靠近底电极12的另一个加速腔结构的光电子入射口,使所述二次光电子实现连续加速和级联倍增并由所述底电极接收,提高集成度并提升对单光子或弱光探测的灵敏度。In the adjacent accelerating cavity structures of different isolation layers 14, the through hole of one accelerating cavity structure close to the top electrode 11 is used as the photoelectron entrance of another accelerating cavity structure close to the bottom electrode 12, so that the secondary photoelectrons can be continuously accelerated and accelerated. Cascaded multiplication and receiving by the bottom electrode, the integration degree is improved and the sensitivity to single photon or weak light detection is improved.
所述光敏传感器还包括加速电极。所述加速电极通过吸引并加速电子,所述电子通过加速电极到达倍增结构15。参照图31,加速电极17靠近顶电极11设置,以对所述光电子进行加速并使至少部分所述光电子到达由相邻倍增结构15围成且底部具有通孔16的加速腔结构。加速电极17设置于顶 电极11的底面,并形成于所述顶部空腔结构的加速腔结构的顶面之间,且开设有若干加速通孔。The photosensitive sensor also includes an accelerating electrode. The accelerating electrode attracts and accelerates electrons, and the electrons reach the multiplication structure 15 through the accelerating electrode. Referring to FIG. 31 , the accelerating electrode 17 is arranged close to the top electrode 11 to accelerate the photoelectrons and make at least part of the photoelectrons reach the accelerating cavity structure surrounded by adjacent multiplication structures 15 and having a through hole 16 at the bottom. The accelerating electrode 17 is arranged on the bottom surface of the top electrode 11, and is formed between the top surfaces of the accelerating cavity structures of the top cavity structure, and has several accelerating through holes.
所述加速电极设置于所述顶电极的底面和所述顶部加速腔结构的顶面之间,并开设有若干加速通孔,至少一部分所述加速通孔对应各所述顶部加速腔结构,光电子穿过所述加速通孔至所述顶部加速腔结构,提高集成度,减少光电子的运动路程。相邻隔离层的对应的加速腔结构中,位于同一侧的倍增结构共轴,进一步提高集成度。而且,沿垂直方向,光电子依次穿过各所述子空腔结构,进一步加速和级联倍增,不占用更多的衬底投影面积,降低加工成本。不同层所述隔离层的相邻加速腔结构具有相同的结构,能够共享衬底的投影面积,提高集成度。The accelerating electrode is arranged between the bottom surface of the top electrode and the top surface of the top accelerating cavity structure, and is provided with a number of accelerating through holes, at least a part of the accelerating through holes correspond to each of the top accelerating cavity structures, and the optoelectronic Through the acceleration through hole to the top acceleration cavity structure, the degree of integration is improved and the movement distance of photoelectrons is reduced. In the corresponding acceleration cavity structures of the adjacent isolation layers, the multiplication structures located on the same side are coaxial, which further improves the degree of integration. Moreover, along the vertical direction, the photoelectrons sequentially pass through each of the sub-cavity structures, further accelerating and cascading multiplication, without occupying more projected area of the substrate, and reducing the processing cost. The adjacent accelerating cavity structures of the isolation layers of different layers have the same structure, which can share the projected area of the substrate and improve the integration degree.
在所述衬底顶面形成底电极,使所述底电极的顶面露出,然后在所述底电极上形成具有若干初始通孔的第一隔离层。参照图32至图34,所述底电极包括若干阳极,衬底21形成有顶面暴露的若干阳极22,阳极22的顶面和衬底21的顶面沉积覆盖有第一隔离层24,第一隔离层24中形成有若干填充导电材料的导电结构25。A bottom electrode is formed on the top surface of the substrate to expose the top surface of the bottom electrode, and then a first isolation layer with several initial through holes is formed on the bottom electrode. 32 to 34, the bottom electrode includes a number of anodes, the substrate 21 is formed with a number of anodes 22 exposed on the top surface, the top surface of the anode 22 and the top surface of the substrate 21 are deposited and covered with a first isolation layer 24, the first A number of conductive structures 25 filled with conductive material are formed in an isolation layer 24 .
相邻阳极22之间形成有金属互连结构23,金属互连结构23与导电结构25电性连接。在初始衬底上形成第一导电金属层,所述第一导电金属层图形化形成下层互连结构33,在下层互连结构33顶部沉积介质材料形成底部介质层,然后通过光刻刻蚀形成互连通孔,使用互连金属材料沉积,并进行CMP磨平,形成填充所述互连通孔的互连导电结构32。A metal interconnection structure 23 is formed between adjacent anodes 22 , and the metal interconnection structure 23 is electrically connected to the conductive structure 25 . A first conductive metal layer is formed on the initial substrate, the first conductive metal layer is patterned to form a lower interconnection structure 33, a dielectric material is deposited on the top of the lower interconnection structure 33 to form a bottom dielectric layer, and then formed by photolithography The interconnection vias are deposited using interconnection metal material and smoothed by CMP to form the interconnection conductive structures 32 filling the interconnection vias.
沉积介质材料,形成覆盖互连导电结构32顶面和所述底部介质层顶面的顶部介质层后,在所述顶部介质层上沉积形成阳极22以及上层互连结构31,使上层互连结构31通过互连导电结构32与下层互连结构33电接触。下层互连结构33、互连导电结构32和上层互连结构31构成了金属互连结构23,以外接处理电路。所述初始衬底、所述顶部介质层和所述底部介质层构成了衬底21。阳极22的顶面露出,在阳极22顶面和衬底21顶面沉积一层初始隔离层(未标示)后,图形化所述隔离层,形成具有若干初始通孔(未 标示)的第一隔离层24。After depositing a dielectric material to form a top dielectric layer covering the top surface of the interconnection conductive structure 32 and the top surface of the bottom dielectric layer, deposit and form the anode 22 and the upper interconnection structure 31 on the top dielectric layer, so that the upper interconnection structure 31 is in electrical contact with an underlying interconnection structure 33 through an interconnection conductive structure 32 . The lower interconnection structure 33 , the interconnection conductive structure 32 and the upper interconnection structure 31 constitute the metal interconnection structure 23 , which is externally connected to the processing circuit. The initial substrate, the top dielectric layer and the bottom dielectric layer constitute a substrate 21 . The top surface of the anode 22 is exposed. After depositing an initial isolation layer (not marked) on the top surface of the anode 22 and the top surface of the substrate 21, the isolation layer is patterned to form a first through hole (not indicated) with several initial Isolation layer 24.
参见图34,本实施例中,使用导电材料填充所述若干初始通孔,形成若干导电结构,图形化所述第一隔离层使所述第一隔离层形成的若干通孔与若干所述导电结构间隔分布。第一隔离层24中,导电结构25和出射通孔26间隔分布,出射通孔26与阳极22相对,使阳极22的顶面露出;导电结构25与金属互连结构23电接触。Referring to FIG. 34 , in this embodiment, conductive materials are used to fill the initial via holes to form several conductive structures, and the first isolation layer is patterned so that the plurality of via holes formed by the first isolation layer are connected to the plurality of conductive structures. Structural interval distribution. In the first isolation layer 24 , conductive structures 25 and outgoing through holes 26 are distributed at intervals, and the outgoing through holes 26 are opposite to the anode 22 , exposing the top surface of the anode 22 ; the conductive structure 25 is in electrical contact with the metal interconnection structure 23 .
参照图32,使用牺牲材料沉积形成覆盖所述第一隔离层顶面并填充所述若干通孔的第一牺牲层后,去除部分牺牲材料形成朝向相同方向延伸的若干倾斜结构,并使所述第一隔离层顶面和至少部分所述导电结构顶面露出,然后沉积倍增电极材料,形成与所述导电结构电性连接的若干倍增结构。若干倾斜结构27朝向同一方向倾斜,沉积倍增电极材料形成的初始倍增电极层覆盖倾斜结构27的表面、第一隔离层24的顶面以及导电结构25的顶面,牺牲材料还填充了的第一隔离层24上设置的若干出射通孔26。Referring to FIG. 32 , after depositing a sacrificial material to form a first sacrificial layer covering the top surface of the first isolation layer and filling the through holes, part of the sacrificial material is removed to form several inclined structures extending in the same direction, and the The top surface of the first isolation layer and at least part of the top surface of the conductive structure are exposed, and then the dynode material is deposited to form several dynode structures electrically connected to the conductive structure. Several inclined structures 27 are inclined towards the same direction, and the initial dynode layer formed by depositing the dynode material covers the surface of the inclined structures 27, the top surface of the first isolation layer 24 and the top surface of the conductive structure 25, and the sacrificial material also fills the first dynode layer. Several outgoing through holes 26 are provided on the isolation layer 24 .
本实施例,形成第一牺牲层后,将所述衬底倾斜设置,然后刻蚀去除部分所述第一牺牲层形成若干倾斜结构,并使所述隔离层顶面和至少部分所述导电结构顶面露出。In this embodiment, after the first sacrificial layer is formed, the substrate is tilted, and then part of the first sacrificial layer is etched away to form several tilted structures, and the top surface of the isolation layer and at least part of the conductive structure The top surface is exposed.
另一实施例,将所述衬底倾斜设置后,首先使用辅助牺牲材料沉积形成若干辅助倾斜结构,然后使用牺牲材料沉积形成覆盖所述辅助倾斜结构顶面的第一牺牲层,再刻蚀去除所述若干辅助倾斜结构同一侧的牺牲材料后去除所述辅助牺牲材料,形成若干倾斜结构,并使所述隔离层顶面和至少部分所述导电结构顶面露出。In another embodiment, after the substrate is tilted, first use auxiliary sacrificial material deposition to form several auxiliary tilting structures, then use sacrificial material deposition to form a first sacrificial layer covering the top surface of the auxiliary tilting structures, and then etch to remove After the sacrificial material on the same side of the plurality of auxiliary inclined structures is removed, the auxiliary sacrificial material is formed to form several inclined structures, and the top surface of the isolation layer and at least part of the top surface of the conductive structure are exposed.
参照图32,初始倍增电极层28覆盖倾斜结构27的侧壁和顶面,还覆盖了第一隔离层24顶面,使导电结构25的顶面被覆盖。通过包层刻蚀(Blanket etch),去除覆盖导电结构25的顶面以及覆盖第一隔离层24顶面的初始倍增电极层28,使导电结构25的顶面以及第一隔离层24顶面露出,然后去除倾斜结构27顶面的初始倍增电极层,然后保留相对侧面覆盖有初始倍增电极层作为倾斜倍增电极,倾斜结构27提供了支撑作用。Referring to FIG. 32 , the initial dynode layer 28 covers the sidewall and top surface of the inclined structure 27 , and also covers the top surface of the first isolation layer 24 , so that the top surface of the conductive structure 25 is covered. The initial dynode layer 28 covering the top surface of the conductive structure 25 and the top surface of the first isolation layer 24 is removed by cladding etching (Blanket etch), so that the top surface of the conductive structure 25 and the top surface of the first isolation layer 24 are exposed , and then remove the initial dynode layer on the top surface of the inclined structure 27, and then keep the opposite side covered with the initial dynode layer as an inclined dynode, and the inclined structure 27 provides a supporting function.
然后,去除牺牲层,倾斜倍增电极与所述导电结构电性连接且朝向相同,以提高集成度。参照图35,本实施中,使用所述牺牲材料沉积形成填充相邻倍增结构之间的空间并覆盖所述若干倍增结构顶面的第二牺牲层。第二牺牲层52填充了相邻倍增电极51之间的空间,并覆盖了第一隔离层24的顶面。Then, the sacrificial layer is removed, and the inclined dynode is electrically connected to the conductive structure with the same orientation, so as to improve integration. Referring to FIG. 35 , in this implementation, the sacrificial material is deposited to form a second sacrificial layer that fills the space between adjacent multiplication structures and covers the top surfaces of the several multiplication structures. The second sacrificial layer 52 fills the space between adjacent dynodes 51 and covers the top surface of the first isolation layer 24 .
参照图36,重复执行S2和S3,直至形成若干层隔离层,在每层所述隔离层形成若干倍增结构15,相邻所述隔离层的导电结构相对设置,并使所述牺牲材料填充相邻倍增结构15之间的空间形成完整牺牲层61。Referring to FIG. 36 , S2 and S3 are repeated until several isolation layers are formed, and several multiplication structures 15 are formed in each isolation layer, and the conductive structures adjacent to the isolation layers are arranged oppositely, and the sacrificial material is filled phase The space between adjacent multiplication structures 15 forms a complete sacrificial layer 61 .
参照图36至图38,S5中,在完整牺牲层61上形成相对的沟槽结构,即第一沟槽结构711和第二沟槽结构712后,使用支撑材料填充两个沟槽结构形成第一支撑结构131和第二支撑结构132。36 to 38, in S5, after forming opposite trench structures on the complete sacrificial layer 61, that is, the first trench structure 711 and the second trench structure 712, the support material is used to fill the two trench structures to form the second trench structure. A support structure 131 and a second support structure 132 .
参照图36、图39和图40,S6中,使用顶电极材料在所述支撑结构顶面,即第一支撑结构131和第二支撑结构132的顶面,以及完整牺牲层61顶面沉积形成初始顶电极91。图形化初始顶电极91以形成释放通孔101。通过所述释放通孔去除所述牺牲材料后,使用密封介质密封所述释放通孔并去除初始顶电极91顶面的密封介质,形成顶电极。并保留所述释放通孔以与所述空腔结构内相通。Referring to Figure 36, Figure 39 and Figure 40, in S6, the top electrode material is used to deposit and form the top surface of the support structure, that is, the top surface of the first support structure 131 and the second support structure 132, and the top surface of the complete sacrificial layer 61 Initial top electrode 91 . The initial top electrode 91 is patterned to form a release via 101 . After the sacrificial material is removed through the release via hole, a sealing medium is used to seal the release via hole and the sealing medium on the top surface of the initial top electrode 91 is removed to form a top electrode. And retain the release through hole to communicate with the cavity structure.
所述光敏传感器还包括若干水平倍增电极,至少一个所述加速腔结构底部靠近开设的所述通孔相对设置两个所述水平倍增电极,以增强对二次光电子的加速作用。所述水平倍增电极设置于所述隔离层的至少部分暴露表面。The photosensitive sensor also includes several horizontal dynodes, and at least one of the bottom of the acceleration cavity structure is adjacent to the through hole opened and two of the horizontal dynodes are oppositely arranged to enhance the acceleration of secondary photoelectrons. The horizontal dynode is disposed on at least part of the exposed surface of the isolation layer.
图41为本发明实施例三的另一种光敏传感器的结构示意图。若干倍增结构15垂直于底电极12设置,顶电极111呈锥形结构。若干倍增结构15垂直于每层所述隔离层,并与所述导电结构(未标示)一一对应电性连接,将每个子空腔结构分隔形成顶部朝向顶电极111开口的加速腔结构(未标示),以接收入射的光电子并对所述入射的光电子进行加速和倍增形成二次光电子。FIG. 41 is a schematic structural diagram of another photosensitive sensor according to Embodiment 3 of the present invention. Several multiplication structures 15 are arranged perpendicular to the bottom electrode 12 , and the top electrode 111 is in a tapered structure. A plurality of multiplication structures 15 are perpendicular to each layer of the isolation layer, and are electrically connected to the conductive structures (not shown) one by one, and each sub-cavity structure is separated to form an acceleration chamber structure (not shown) whose top is opened toward the top electrode 111. marked) to receive incident photoelectrons and accelerate and multiply the incident photoelectrons to form secondary photoelectrons.
以上所述仅为本发明的优选实施例,所述实施例并非用于限制本发明的专利保护范围,因此凡是运用本发明的说明书及附图内容所作的等同结构变 化,同理均应包含在本发明所附权利要求的保护范围内。The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of patent protection of the present invention, so all equivalent structural changes made by using the description and drawings of the present invention should be included in the same reason Within the protection scope of the appended claims of the present invention.

Claims (36)

  1. 一种光敏传感器,其特征在于,包括:A photosensitive sensor is characterized in that, comprising:
    顶电极,用于响应预定波长的光发射光电子;a top electrode for emitting photoelectrons in response to light of a predetermined wavelength;
    隔离层,与所述顶电极相对设置;an isolation layer disposed opposite to the top electrode;
    底电极,与所述顶电极相对设置且电性相反;a bottom electrode disposed opposite to the top electrode and electrically opposite;
    若干导电结构,设置于所述隔离层;a plurality of conductive structures disposed on the isolation layer;
    支撑结构,与所述顶电极和所述底电极围成空腔结构,并与所述顶电极以及所述导电结构电性连接;a supporting structure, forming a cavity structure with the top electrode and the bottom electrode, and electrically connected with the top electrode and the conductive structure;
    倍增结构阵列,设置于所述隔离层,包括若干倍增结构,各所述倍增结构相对所述顶电极倾斜,并对应电性连接所述导电结构,以于所述顶电极和所述隔离层之间形成若干加速腔结构,各所述加速腔结构的顶部设有朝向所述顶电极的开口,并底部开设出射通孔,所述出射通孔相对所述底电极;The multiplication structure array is arranged on the isolation layer, including a plurality of multiplication structures, each of the multiplication structures is inclined relative to the top electrode, and correspondingly electrically connected to the conductive structure, so as to be between the top electrode and the isolation layer A number of acceleration chamber structures are formed between them, the top of each acceleration chamber structure is provided with an opening facing the top electrode, and the bottom is provided with an exit hole, and the exit through hole is opposite to the bottom electrode;
    其中,光电子入射至所述加速腔结构,并经加速和倍增形成二次光电子,所述光电子及所述二次光电子穿过所述出射通孔至所述底电极。Wherein, photoelectrons are incident to the accelerating cavity structure, and are accelerated and multiplied to form secondary photoelectrons, and the photoelectrons and the secondary photoelectrons pass through the exit through hole to the bottom electrode.
  2. 根据权利要求1所述的光敏传感器,其特征在于,所述倍增结构朝向所述顶电极的延伸线与所述顶电极相交的锐角为20°~65°。The photosensitive sensor according to claim 1, wherein an acute angle at which an extension line of the multiplication structure toward the top electrode intersects the top electrode is 20°-65°.
  3. 根据权利要求1所述的光敏传感器,其特征在于,相邻所述倍增结构的间距小于电子传输的自由程。The photosensitive sensor according to claim 1, wherein the distance between adjacent multiplication structures is smaller than the free path of electron transmission.
  4. 根据权利要求1所述的光敏传感器,其特征在于,相对所述顶电极,各所述倍增结构朝同一方向倾斜设置。The photosensitive sensor according to claim 1, characterized in that, relative to the top electrode, each of the multiplication structures is inclined in the same direction.
  5. 根据权利要求1所述的光敏传感器,其特征在于,各所述倍增结构包括若干倾斜倍增电极,相邻所述倾斜倍增电极的电性相反,各所述倾斜倍 增电极相对所述顶电极倾斜设置。The photosensitive sensor according to claim 1, wherein each of the multiplication structures includes a plurality of inclined dynodes, the electrical properties of adjacent inclined dynodes are opposite, and each of the inclined dynodes is arranged obliquely relative to the top electrode .
  6. 根据权利要求1所述的光敏传感器,其特征在于,各所述倍增结构包括若干正V型倍增电极和若干倒V型倍增电极,所述正V型倍增电极和所述倒V型倍增电极交替设置且电性相反,各所述正V型倍增电极和各所述倒V型倍增电极均由两个倾斜倍增电极相接形成,各所述倾斜倍增电极相对所述顶电极倾斜设置。The photosensitive sensor according to claim 1, wherein each of the multiplication structures comprises several positive V-type dynodes and several inverted V-type dynodes, and the positive V-type dynodes and the inverted V-type dynodes alternate Each of the positive V-shaped dynodes and each of the inverted V-shaped dynodes are formed by connecting two inclined dynodes, and each of the inclined dynodes is arranged obliquely relative to the top electrode.
  7. 根据权利要求1所述的光敏传感器,其特征在于,还包括释放通孔以及密封介质层,所述释放通孔开设于所述空腔结构顶面边缘,所述密封介质层封闭所述释放通孔。The photosensitive sensor according to claim 1, further comprising a release through hole and a sealing medium layer, the release through hole is opened on the edge of the top surface of the cavity structure, and the sealing medium layer seals the release through hole hole.
  8. 根据权利要求1所述的光敏传感器,其特征在于,所述若干倍增结构倾斜于所述底电极,或,所述若干倍增结构垂直于所述底电极,并所述顶电极倾斜于所述底电极。The photosensitive sensor according to claim 1, wherein the plurality of multiplication structures are inclined to the bottom electrode, or the plurality of multiplication structures are perpendicular to the bottom electrode, and the top electrode is inclined to the bottom electrode electrode.
  9. 根据权利要求1所述的光敏传感器,其特征在于,所述顶电极呈锥形结构。The photosensitive sensor according to claim 1, wherein the top electrode is in a cone-shaped structure.
  10. 根据权利要求1所述的光敏传感器,其特征在于,还包括金属互连结构,所述金属互连结构与所述底电极电接触,以电连接处理电路。The photosensitive sensor according to claim 1, further comprising a metal interconnection structure, the metal interconnection structure is in electrical contact with the bottom electrode to electrically connect a processing circuit.
  11. 根据权利要求1所述的光敏传感器,其特征在于,各所述加速腔结构沿所述顶电极设置方向的截面呈等边六边形。The photosensitive sensor according to claim 1, characterized in that, the cross-section of each of the accelerating cavity structures along the direction in which the top electrodes are arranged is an equilateral hexagon.
  12. 根据权利要求11所述的光敏传感器,其特征在于,至少一个所述加速腔结构的底部设置有加速薄膜,以加速所述二次光电子。The photosensitive sensor according to claim 11, characterized in that an accelerating thin film is arranged at the bottom of at least one of the accelerating cavity structures to accelerate the secondary photoelectrons.
  13. 根据权利要求12所述的光敏传感器,其特征在于,所述加速薄膜包括还原石墨烯和氧化石墨烯中的一种或两种组合。The photosensitive sensor according to claim 12, wherein the accelerating film comprises one or a combination of reduced graphene and graphene oxide.
  14. 根据权利要求12所述的光敏传感器,其特征在于,所述加速薄膜具有至少一个通道孔作为所述出射通孔。The photosensitive sensor according to claim 12, wherein the accelerating film has at least one channel hole as the exit through hole.
  15. 根据权利要求11所述的光敏传感器,其特征在于,所述倍增结构阵列包含若干子空腔阵列层,各所述子空腔阵列层倾斜于所述顶电极,相邻子空腔阵列层的加速腔结构相对且连通设置。The photosensitive sensor according to claim 11, wherein the multiplication structure array comprises several sub-cavity array layers, each of the sub-cavity array layers is inclined to the top electrode, and the adjacent sub-cavity array layers are The acceleration chamber structures are opposite and communicated with each other.
  16. 根据权利要求15所述的光敏传感器,其特征在于,还包括:若干层间隔离层、若干层间导电结构和若干层间通孔结构,相邻所述子空腔阵列层之间设有所述层间隔离层,并至少一所述子空腔阵列层的倍增结构电接触所述层间导电结构,且任一所述子空腔阵列层的加速腔结构相对所述层间通孔结构,所述光电子通过所述层间通孔结构。The photosensitive sensor according to claim 15, further comprising: several interlayer isolation layers, several interlayer conductive structures, and several interlayer through hole structures, the adjacent sub-cavity array layers are provided with the The interlayer isolation layer, and at least one multiplication structure of the sub-cavity array layer electrically contacts the interlayer conductive structure, and the accelerating cavity structure of any one of the sub-cavity array layers is opposite to the interlayer via structure , the photoelectrons pass through the interlayer via structure.
  17. 根据权利要求11所述的光敏传感器,其特征在于,所述倍增结构包括倍增电极对,所述倍增电极对相对设置于每个加速腔结构内壁。The photosensitive sensor according to claim 11, characterized in that, the multiplication structure includes a pair of dynodes, and the pair of dynodes is arranged opposite to the inner wall of each acceleration cavity structure.
  18. 根据权利要求17所述的光敏传感器,其特征在于,不同所述子空腔阵列层之间,相邻加速腔结构形成的运动通道呈V型。The photosensitive sensor according to claim 17, characterized in that, between different said sub-cavity array layers, the motion channels formed by adjacent accelerating cavity structures are V-shaped.
  19. 根据权利要求1所述的光敏传感器,其特征在于,若干所述隔离层设置于所述空腔结构内,并将所述空腔结构分隔形成若干子空腔结构,各隔离层对应设置有若干导电结构及若干倍增结构阵列,各所述导电结构与所述支撑结构电性连接;The photosensitive sensor according to claim 1, wherein a plurality of isolation layers are arranged in the cavity structure, and the cavity structure is separated to form a plurality of sub-cavity structures, and each isolation layer is correspondingly provided with a plurality of sub-cavity structures. a conductive structure and a plurality of multiplication structure arrays, each of the conductive structures is electrically connected to the support structure;
    其中,相邻所述隔离层之间,靠近所述顶电极的倍增结构阵列的出射通孔作为靠近所述底电极的另一个倍增结构阵列的开口。Wherein, between the adjacent isolation layers, the exit through hole of the multiplication structure array close to the top electrode serves as an opening of another multiplication structure array close to the bottom electrode.
  20. 根据权利要求19所述的光敏传感器,其特征在于,顶部加速腔结构为距离所述顶电极最近的倍增结构阵列对应的加速腔结构,还包括:加速 电极,设置于顶部加速腔结构,以加速所述光电子,并使至少部分所述光电子到达所述顶部加速腔结构。The photosensitive sensor according to claim 19, wherein the top accelerating cavity structure is an accelerating cavity structure corresponding to the multiplication structure array closest to the top electrode, further comprising: an accelerating electrode, arranged on the top accelerating cavity structure, to accelerate the photoelectrons, and make at least part of the photoelectrons reach the top accelerating cavity structure.
  21. 根据权利要求19所述的光敏传感器,其特征在于,所述加速电极设置于所述顶电极的底面和所述顶部加速腔结构的顶面之间,并开设有若干加速通孔,至少一部分所述加速通孔对应各所述顶部加速腔结构,光电子穿过所述加速通孔至所述顶部加速腔结构。The photosensitive sensor according to claim 19, wherein the accelerating electrode is arranged between the bottom surface of the top electrode and the top surface of the top accelerating cavity structure, and is provided with a number of accelerating through holes, at least a part of which is The acceleration through holes correspond to the top accelerating cavity structures, and the photoelectrons pass through the accelerating through holes to the top accelerating cavity structures.
  22. 根据权利要求19所述的光敏传感器,其特征在于,各所述倍增结构朝向同一方向倾斜。The photosensitive sensor according to claim 19, wherein each of said multiplication structures is inclined towards the same direction.
  23. 根据权利要求21所述的光敏传感器,其特征在于,不同所述隔离层对应同侧的加速腔结构共轴。The photosensitive sensor according to claim 21, characterized in that the acceleration cavity structures corresponding to the same side of different isolation layers are coaxial.
  24. 根据权利要求19所述的光敏传感器,其特征在于,所述倍增结构包括倾斜倍增电极,各倾斜倍增电极倾斜于所述顶电极,设置于各所述隔离层,并与所述导电结构电性连接且倾斜角度相同;同层所述隔离层对应的倾斜倍增电极之间具有相同或不同的高度。The photosensitive sensor according to claim 19, wherein the multiplication structure includes inclined dynodes, each inclined dynode is inclined to the top electrode, is arranged on each of the isolation layers, and is electrically connected to the conductive structure connected and have the same inclination angle; the inclination dynodes corresponding to the isolation layers in the same layer have the same or different heights.
  25. 根据权利要求19所述的光敏传感器,其特征在于,还包括若干水平倍增电极,至少一个所述子空腔结构的底部对应的各出射通孔邻设有相对的两个所述水平倍增电极,以加速所述二次光电子。The photosensitive sensor according to claim 19, further comprising a plurality of horizontal dynodes, at least one of the sub-cavity structures corresponding to each exit through-hole adjacent to two of the horizontal dynodes, to accelerate the secondary photoelectrons.
  26. 一种光敏传感器的制备工艺方法,其特征在于,包括:A method for preparing a photosensitive sensor, characterized in that it comprises:
    S1:提供衬底,在所述衬底顶面形成底电极,使所述底电极的顶面露出,然后在所述底电极上形成隔离层,所述隔离层具有若干初始通孔;S1: providing a substrate, forming a bottom electrode on the top surface of the substrate, exposing the top surface of the bottom electrode, and then forming an isolation layer on the bottom electrode, the isolation layer having a number of initial through holes;
    S2:使用导电材料填充所述若干初始通孔,形成若干导电结构,图形化所述隔离层,使所述初始通孔与所述导电结构间隔分布,且和所述底电极相 对应设置;S2: Filling the plurality of initial through holes with a conductive material to form a plurality of conductive structures, patterning the isolation layer, so that the initial through holes are spaced apart from the conductive structures, and arranged corresponding to the bottom electrodes;
    S3:形成第一牺牲层,所述第一牺牲层覆盖所述隔离层顶面并填充所述初始通孔,去除部分第一牺牲层形成若干倾斜结构,各所述倾斜结构朝向相同方向延伸,并使所述隔离层顶面和至少部分所述导电结构顶面露出,然后沉积倍增电极材料形成倍增结构阵列,所述倍增结构阵列包括若干倍增结构,各所述倍增结构电性连接对应的所述导电结构;S3: forming a first sacrificial layer, the first sacrificial layer covering the top surface of the isolation layer and filling the initial through hole, removing part of the first sacrificial layer to form several inclined structures, each of which extends toward the same direction, And exposing the top surface of the isolation layer and at least part of the top surface of the conductive structure, and then depositing a dynode material to form a multiplication structure array, the multiplication structure array includes several multiplication structures, each of the multiplication structures is electrically connected to the corresponding the conductive structure;
    S4:形成第二牺牲层,所述第二牺牲层填充相邻倍增结构之间的空间并覆盖所述若干倍增结构顶面,在所述第二牺牲层上形成相对的沟槽结构,填充支撑材料至所述沟槽结构,形成支撑结构;S4: Form a second sacrificial layer, the second sacrificial layer fills the space between adjacent multiplication structures and covers the top surfaces of the plurality of multiplication structures, and forms opposite trench structures on the second sacrificial layer to fill the support material to the trench structure to form a support structure;
    S5:沉积顶电极材料形成初始顶电极,所述初始顶电极覆盖所述支撑结构顶面和所述第二牺牲层顶面,并图形化所述初始顶电极以形成释放通孔,通过所述释放通孔去除所述第一/第二牺牲层,使用密封介质填充所述释放通孔,形成顶电极。S5: Deposit top electrode material to form an initial top electrode, the initial top electrode covers the top surface of the support structure and the top surface of the second sacrificial layer, and pattern the initial top electrode to form a release via hole, through the The first/second sacrificial layer is removed for the release via hole, and the release via hole is filled with a sealing medium to form a top electrode.
  27. 根据权利要求26所述的方法,其特征在于,S3包括:The method according to claim 26, wherein S3 comprises:
    S31:形成第一牺牲层,所述第一牺牲层覆盖所述隔离层顶面并填充所述初始通孔;S31: forming a first sacrificial layer, the first sacrificial layer covering the top surface of the isolation layer and filling the initial through hole;
    S32:将所述衬底倾斜,刻蚀形成包括若干空腔结构的空腔阵列,然后将所述衬底复位后,沉积倍增电极材料形成初始倍增电极层,所述初始倍增电极层填充所述空腔阵列,再将所述衬底倾斜,去除部分所述初始倍增电极层,得到倍增结构阵列,所述倍增结构阵列设置于所述空腔结构侧壁,并与所述导电结构电接触。S32: Tilt the substrate, etch to form a cavity array including several cavity structures, then reset the substrate, deposit a dynode material to form an initial dynode layer, and the initial dynode layer fills the A cavity array, and then tilting the substrate to remove part of the initial dynode layer to obtain a multiplication structure array, the multiplication structure array is arranged on the side wall of the cavity structure and is in electrical contact with the conductive structure.
  28. 根据权利要求27所述的方法,其特征在于,所述空腔阵列包括若 干子空腔阵列层,S3之后,还包括:The method according to claim 27, wherein the cavity array comprises several sub-cavity array layers, after S3, further comprising:
    S331:使用牺牲材料填充所述已形成的子空腔阵列层内部,使所述已形成的子空腔阵列层的顶面露出;S331: Fill the inside of the formed sub-cavity array layer with a sacrificial material, exposing the top surface of the formed sub-cavity array layer;
    S332:使用层间材料形成层间隔离层,所述层间隔离层覆盖所述已形成的子空腔阵列层,并包括若干层间导电结构和若干层间通孔结构,各所述层间通孔结构相对所述已形成的子空腔阵列层对应的加速腔结构设置,所述层间导电结构的至少部分表面露出;其中,S332: Use an interlayer material to form an interlayer isolation layer, the interlayer isolation layer covers the formed sub-cavity array layer, and includes several interlayer conductive structures and several interlayer via structures, each of the interlayer The through-hole structure is arranged relative to the acceleration cavity structure corresponding to the formed sub-cavity array layer, and at least part of the surface of the interlayer conductive structure is exposed; wherein,
    重复执行S3、S331及S332,直至形成若干层子空腔阵列层,相邻所述子空腔阵列层之间设有所述层间隔离层,并至少一所述子空腔阵列层的倍增结构电接触所述层间导电结构。Repeat S3, S331, and S332 until several layers of sub-cavity array layers are formed, the interlayer isolation layer is provided between adjacent sub-cavity array layers, and at least one sub-cavity array layer is multiplied A structure electrically contacts the interlayer conductive structure.
  29. 根据权利要求28所述的方法,其特征在于,所述层间材料还包括分散液,所述分散液含有氧化石墨烯和有机溶剂,S332之后,将所述分散液旋涂于所述加速腔结构的开口,所述氧化石墨烯层覆盖至少一个所述开口,并与所述层间导电结构相接触。The method according to claim 28, wherein the interlayer material further comprises a dispersion liquid, the dispersion liquid contains graphene oxide and an organic solvent, and after S332, the dispersion liquid is spin-coated on the acceleration chamber The opening of the structure, the graphene oxide layer covers at least one of the openings and is in contact with the interlayer conductive structure.
  30. 根据权利要求29所述的方法,其特征在于,通过所述释放通孔去除所述第一/第二牺牲层之后,去除部分所述氧化石墨烯层。The method according to claim 29, characterized in that after removing the first/second sacrificial layer through the release via hole, part of the graphene oxide layer is removed.
  31. 根据权利要求30所述的方法,其特征在于,去除部分所述氧化石墨烯层包括,通过光刻刻蚀在每个所述氧化石墨烯层形成通道孔。The method according to claim 30, wherein removing part of the graphene oxide layer comprises forming channel holes in each of the graphene oxide layers by photolithography.
  32. 根据权利要求31所述的方法,其特征在于,通过光刻刻蚀在每个所述氧化石墨烯层形成通道孔之后,还原剩余的氧化石墨烯层,得到加速电极。The method according to claim 31, characterized in that, after forming a channel hole in each graphene oxide layer by photolithography, reducing the remaining graphene oxide layer to obtain an accelerating electrode.
  33. 根据权利要求26所述的方法,其特征在于,形成第二牺牲层,所 述第二牺牲层填充相邻倍增结构之间的空间并覆盖所述若干倍增结构顶面之后,重复执行S2和S3,直至形成若干层隔离层,在每层所述隔离层形成若干倍增结构,相邻所述隔离层的导电结构相对设置,并使所述牺牲材料填充相邻倍增结构之间的空间形成完整牺牲层。The method according to claim 26, characterized in that, after forming a second sacrificial layer, after the second sacrificial layer fills the space between adjacent multiplication structures and covers the top surfaces of the several multiplication structures, repeating S2 and S3 , until several layers of isolation layers are formed, several multiplication structures are formed in each layer of isolation layers, the conductive structures of adjacent isolation layers are arranged oppositely, and the sacrificial material fills the space between adjacent multiplication structures to form a complete sacrificial layer.
  34. 根据权利要求26所述的方法,其特征在于,S3中,去除部分第一牺牲层形成若干倾斜结构,包括:The method according to claim 26, characterized in that, in S3, removing part of the first sacrificial layer to form several inclined structures, including:
    将所述衬底倾斜设置,然后刻蚀去除部分所述第一牺牲层形成若干倾斜结构。The substrate is arranged obliquely, and then part of the first sacrificial layer is removed by etching to form several oblique structures.
  35. 根据权利要求26所述的方法,其特征在于,形成第一牺牲层之前,沉积辅助牺牲材料,形成若干辅助倾斜结构;形成第一牺牲层之后,去除所述辅助倾斜结构同侧的第一牺牲层,去除所述辅助牺牲材料,形成若干倾斜结构。The method according to claim 26, characterized in that before forming the first sacrificial layer, an auxiliary sacrificial material is deposited to form several auxiliary inclined structures; after forming the first sacrificial layer, the first sacrificial material on the same side as the auxiliary inclined structures is removed layer, removing the auxiliary sacrificial material to form several inclined structures.
  36. 根据权利要求26所述的方法,其特征在于,形成顶电极的步骤包括:The method according to claim 26, wherein the step of forming the top electrode comprises:
    使用灰阶掩膜进行光刻,形成从边缘到中间逐渐增厚的锥形结构,然后沉积阴极材料,在所述锥形结构顶面形成初始顶电极。Photolithography is performed using a grayscale mask to form a tapered structure that gradually thickens from the edge to the middle, and then a cathode material is deposited to form an initial top electrode on the top surface of the tapered structure.
PCT/CN2021/143858 2021-11-25 2021-12-31 Fin semiconductor device and preparation method therefor WO2023092819A1 (en)

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CN202111410349.9 2021-11-25
CN202111410534.8 2021-11-25
CN202111410534.8A CN114093742B (en) 2021-11-25 2021-11-25 Photosensitive sensor and preparation process thereof
CN202111410564.9 2021-11-25
CN202111410349.9A CN114093741B (en) 2021-11-25 2021-11-25 Photosensitive sensor and preparation process thereof
CN202111410564.9A CN114093743B (en) 2021-11-25 2021-11-25 Photosensitive sensor and preparation method thereof

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6258536A (en) * 1985-09-06 1987-03-14 Hamamatsu Photonics Kk Electron multiplying element
US5180943A (en) * 1989-11-10 1993-01-19 Hamamatsu Photonics K.K. Photomultiplier tube with dynode array having venetian-blind structure
JPH0817389A (en) * 1994-06-28 1996-01-19 Hamamatsu Photonics Kk Electron tube
CN110416056A (en) * 2019-07-11 2019-11-05 西北核技术研究院 A kind of high-gain mixed type photomultiplier tube based on microchannel plate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6258536A (en) * 1985-09-06 1987-03-14 Hamamatsu Photonics Kk Electron multiplying element
US5180943A (en) * 1989-11-10 1993-01-19 Hamamatsu Photonics K.K. Photomultiplier tube with dynode array having venetian-blind structure
JPH0817389A (en) * 1994-06-28 1996-01-19 Hamamatsu Photonics Kk Electron tube
CN110416056A (en) * 2019-07-11 2019-11-05 西北核技术研究院 A kind of high-gain mixed type photomultiplier tube based on microchannel plate

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