Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
  • H05K1/144—Stacked arrangements of planar printed circuit boards
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
  • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
  • H10W70/616—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips
  • H10W70/618—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips the bridge chips being embedded in the package substrates, interposers or redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/688—Flexible insulating substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/20—Configurations of stacked chips
  • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/04—Assemblies of printed circuits
  • H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10378—Interposers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W44/00—Electrical arrangements for controlling or matching impedance
  • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
  • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
  • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• FIG. 4 illustrates an exemplary cross sectional profile view of a package that includes channel interconnects.
• the second package 103 includes a second substrate 104, a second integrated device 107, a third integrated device 109 and a plurality of channel interconnections 108.
• the second integrated device 107 is coupled to a first surface (e.g., top surface) of the second substrate 104, through a plurality of solder interconnects 170.
• the third integrated device 109 is coupled to the first surface (e.g., top surface) of the second substrate 104, through a plurality of solder interconnects 190.
• the second integrated device 107 is located between the second substrate 104 and the third integrated device 109.
• SUBSTITUTE SHEET (RULE 26) includes at least one second dielectric layer 140 and a second plurality of interconnects 142.
• the second substrate 104 may be an interposer. In some implementations, the second substrate 104 may have 2 metal layers or less.
• the third integrated device 109 is coupled to the second plurality of interconnects 142 of the second substrate 104, through the plurality of solder interconnects 190.
• the second integrated device 107 is coupled to the second plurality of interconnects 142 of the second substrate 104, through the plurality of solder interconnects 170.
• the second package 103 is coupled to the first package 101 through the plurality of solder interconnects 112.
• the second substrate 104 is coupled to the first substrate 102 through the plurality of solder interconnects 112.
• the plurality of solder interconnects 112 may be considered part of the first package 101 and/or the second package 103.
• FIG. 3 illustrates possible electrical paths in the package 100.
• FIG. 3 illustrates an electrical path 305, an electrical path 306 and an electrical path 307.
• the electrical path 305 may represent a possible electrical path for one or more signals to and/or from the second integrated device 107.
• the electrical path 306 may represent a possible electrical path for one or more signals to and/or from the second integrated device 107.
• the electrical path 307 may represent a possible electrical path for one or more signals to and/or from the first integrated device 105.
• solder interconnects 112 that are located along the periphery of the substrate 102 and/or the substrate 104 may include the two rows of solder interconnects that are closest to one or more edges of the substrate 102 and/or the substrate 104.
• a row of solder interconnects may include rows along the X direction and/or along the Y direction of a substrate.
• the electrical path 305 may be extended to be coupled to the board 106.
• the electrical path 305 may also include at least one solder interconnect from the plurality of solder interconnects 110 and at least one board interconnect from the plurality of board interconnects 162.
• one or more signals between the board 106 and the second integrated device 107 may travel through the electrical path 305 as described above.
• At least one dielectric layer may be located over the plurality of interconnects 408.
• the at least one dielectric layer may include a polymer (e.g., pure polymer).
• the dielectric layer that is located over the plurality of interconnects 408 is different than the at least one dielectric layer 140 of the second substrate 104.
• a first plurality of channel interconnects faces a first side of the integrated device 107
• a second plurality of channel interconnects faces a second side of the integrated device 107
• a third plurality of channel interconnects faces a third side of the integrated device 107
• a fourth plurality of channel interconnects faces a fourth side of the integrated device 107.
• the plurality of channel interconnects may face less than all four sides of the integrated device 107 (e.g., face one or more sides of the integrated device).
• the plurality of channel substrates 608 may laterally surround the second integrated device 107.
• the electrical path 306 implemented in the package 800 may include (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from the plurality of channel interconnects 408 from the plurality of flexible cables 808 (may
• the integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filters, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, power management processor, and/or combinations thereof.
• An integrated device (e.g., 105, 107, 109) may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc. . .).
• An integrated device may include transistors.
• An integrated device may be an example of an electrical component and/or electrical device.
• Stage 5 illustrates a state after a second integrated device 107 is coupled to the first surface (e.g., top surface) of the substrate 104.
• the second integrated device 107 may be coupled to the substrate 104 through the plurality of solder interconnects 170.
• a solder reflow process may be used to couple the second integrated device 107 to the substrate 104.
• fabricating a package includes several processes.
• FIGS. 12A-12C illustrate an exemplary sequence for providing or fabricating a package that includes channel interconnects.
• the sequence of FIGS. 12A-12C may be used to provide or fabricate the package 600.
• the process of FIGS. 12A-12C may be used to fabricate any of the packages (e.g., 800, 1000) described in the disclosure.
• SUBSTITUTE SHEET (RULE 26) may be fabricated one at a time or may be fabricated together in part or as a whole as part of one or more strips or panels and then assembled or singulated into individual packages.
• the method couples (at 1320) a second integrated device (e.g., 107) to the first surface of the second substrate (e.g., 104) through a plurality of solder interconnects (e.g., 170).
• a solder reflow process may be used to couple the second integrated device to the first surface of the second substrate 104.
• Stage 5 of FIG. 1 IB illustrates and describes an example of a second integrated device coupled to a second substrate.
• Stage 5 of FIG. 12B illustrates and describes an example of a second integrated device coupled to a second substrate.
• the plurality of channel interconnects 408 from the plurality of channel substrates 608 may be located between solder interconnects from the plurality of solder interconnects 190.
• the plurality of channel interconnects 408 from the plurality of flexible cables 808 may be located between solder interconnects from the plurality of solder interconnects 190.
• the plurality of solder interconnects 190 may laterally surround the second integrated device 107.
• the method may singulate (at 1330) the package (e.g., 100, 400, 600, 800, 1000). In other cases, singulation happens before substrates are couple to each other.
• fabricating a substrate includes several processes.
• FIGS. 14A-14B illustrate an exemplary sequence for providing or fabricating a substrate.
• the sequence of FIGS. 14A-14B may be used to provide or fabricate the substrate 102.
• the process of FIGS. 14A-14B may be used to fabricate any of the substrates described in the disclosure, such as the substrate 104 and/or the channel substrate 608.
• FIGS. 14A-14B may combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating a substrate.
• the order of the processes may be changed or modified.
• one or more of processes may be replaced or substituted without departing from the scope of the disclosure.
• Stage 1 illustrates a state after a carrier 1400 is provided.
• a seed layer 1401 and interconnects 1402 may be located over the carrier 1400.
• the interconnects 1402 may be located over the seed layer 1401.
• a plating process and etching process may be used to form the interconnects 1402.
• the carrier 1400 may be provided with the seed layer 1401 and a metal layer that is patterned to form the interconnects 1402.
• the interconnects 1402 may represent at least some of the interconnects from the plurality of interconnects 122.
• Stage 2 illustrates a state after a dielectric layer 1420 is formed over the carrier 1400, the seed layer 1401 and the interconnects 1402.
• a deposition and/or lamination process may be used to form the dielectric layer 1420.
• the dielectric layer 1420 may include prepreg and/or polyimide.
• the dielectric layer 1420 may include a photo- imageable dielectric. However, different implementations may use different materials for the dielectric layer.
• Stage 3 illustrates a state after a plurality of cavities 1410 is formed in the dielectric layer 1420.
• the plurality of cavities 1410 may be formed using an etching process (e.g., photo etching process) or laser process.
• Stage 5 illustrates a state after a dielectric layer 1422 is formed over the dielectric layer 1420 and the interconnects 1412.
• a deposition and/or lamination process may be used to form the dielectric layer 1422.
• the dielectric layer 1422 may include
• the dielectric layer 1422 may include a photo-imageable dielectric. However, different implementations may use different materials for the dielectric layer.
• Stage 8 illustrates a state after the carrier 1400 is decoupled (e.g., detached, removed, grinded out) from at least one dielectric layer 120 and the seed layer 1401, portions of the seed layer 1401 are removed (e.g., etched out), leaving the substrate 102 that includes at least one dielectric layer 120 and the plurality of interconnects 122.
• the method provides (at 1505) a carrier (e.g., 1400).
• a carrier e.g., 1400
• the carrier 1400 may include a seed layer (e.g., 1401).
• the seed layer 1401 may include a metal (e.g., copper).
• the carrier may include a substrate, glass, quartz and/or carrier tape.
• Stage 1 of FIG. 14A illustrates and describes an example of a carrier with a seed layer that is provided.
• the method forms (at 1515) a dielectric layer 1420 over the seed layer 1401, the carrier 1400 and the interconnects 1402.
• a deposition and/or lamination process may be used to form the dielectric layer 1420.
• the dielectric layer 1420 may include prepreg and/or polyimide.
• the dielectric layer 1420 may include a photo-imageable dielectric.
• Forming the dielectric layer 1420 may also include forming a plurality of cavities (e.g., 1410) in the dielectric layer 1420.
• the plurality of cavities may be formed using an etching process (e.g., photo etching) or laser process.
• Stages 2-3 of FIG. 14A illustrate and describe an example of forming a dielectric layer and cavities in the dielectric layer.
• the method decouples (at 1535) the carrier (e.g., 1400) from the seed layer (e.g., 1401).
• the carrier 1400 may be detached and/or grinded off.
• the method may also remove (at 1535) portions of the seed layer (e.g., 1401).
• An etching process may be used to remove portions of the seed layer 1401.
• Stage 8 of FIG. 14B illustrates and describes an example of decoupling a carrier and seed layer removal.
• a chemical vapor deposition (CVD) process may be used to form the metal layer(s).
• CVD chemical vapor deposition
• PVD physical vapor deposition
• a sputtering process may be used to form the metal layer(s).
• a spray coating process may be used to form the metal layer(s).
• FIGS. 1-10, 11A-11C, 12A-12C, 13, 14A-14B and 15-16 may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be noted FIGS. 1-10, 11A-11C, 12A-12C, 13, 14A-14B and 15-16 and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations, FIGS.
• the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be
• the second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects; a second integrated device coupled to a first surface of the second substrate; a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects; and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.
• Aspect 4 The device of aspects 1 through 3, further comprising a flexible cable coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is part of the flexible cable.
• Aspect 12 The apparatus of aspect 11, wherein the second integrated device is located between the third integrated device and the second substrate.
• Aspect 17 The apparatus of aspects 11 through 16, wherein a first electrical path between the second integrated device and the first substrate comprises at least one first solder interconnect coupling the second integrated device to the second substrate; at least one first interconnect from the second plurality of interconnects of the second substrate; the means for channel interconnection; at least one second interconnect from the second plurality of interconnects of the second substrate; at least one second solder
• SUBSTITUTE SHEET (RULE 26) interconnect from the first plurality of solder interconnects coupling the second substrate and the first substrate; and at least one interconnect from the first plurality of interconnects of the first substrate.
• Aspect 24 The method of aspects 21 through 23, wherein providing the first plurality of channel interconnects comprises coupling a flexible cable comprising the first plurality of channel interconnects, to the first surface of the second substrate.
• Aspect 31 The device of aspects 26 through 30, further comprising a second plurality of channel interconnects coupled to a second surface of the substrate.
• SUBSTITUTE SHEET (RULE 26) can be readily applied to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Combinations Of Printed Boards (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Geometry (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

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Citations (4)

• 2021
  • 2021-11-22 US US17/532,754 patent/US12243855B2/en active Active
• 2022
  • 2022-10-28 KR KR1020247013807A patent/KR20240104099A/ko active Pending
  • 2022-10-28 TW TW111141117A patent/TW202324621A/zh unknown
  • 2022-10-28 WO PCT/US2022/048192 patent/WO2023091285A1/en not_active Ceased
  • 2022-10-28 EP EP22822236.0A patent/EP4437587A1/en active Pending
  • 2022-10-28 CN CN202280074189.1A patent/CN118215998A/zh active Pending
  • 2022-10-28 JP JP2024527687A patent/JP2024540436A/ja active Pending

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